1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 struct psp_fw_legacy_bin_desc { 75 uint32_t fw_version; 76 uint32_t offset_bytes; 77 uint32_t size_bytes; 78 }; 79 80 /* version_major=1, version_minor=0 */ 81 struct psp_firmware_header_v1_0 { 82 struct common_firmware_header header; 83 struct psp_fw_legacy_bin_desc sos; 84 }; 85 86 /* version_major=1, version_minor=1 */ 87 struct psp_firmware_header_v1_1 { 88 struct psp_firmware_header_v1_0 v1_0; 89 struct psp_fw_legacy_bin_desc toc; 90 struct psp_fw_legacy_bin_desc kdb; 91 }; 92 93 /* version_major=1, version_minor=2 */ 94 struct psp_firmware_header_v1_2 { 95 struct psp_firmware_header_v1_0 v1_0; 96 struct psp_fw_legacy_bin_desc res; 97 struct psp_fw_legacy_bin_desc kdb; 98 }; 99 100 /* version_major=1, version_minor=3 */ 101 struct psp_firmware_header_v1_3 { 102 struct psp_firmware_header_v1_1 v1_1; 103 struct psp_fw_legacy_bin_desc spl; 104 struct psp_fw_legacy_bin_desc rl; 105 struct psp_fw_legacy_bin_desc sys_drv_aux; 106 struct psp_fw_legacy_bin_desc sos_aux; 107 }; 108 109 struct psp_fw_bin_desc { 110 uint32_t fw_type; 111 uint32_t fw_version; 112 uint32_t offset_bytes; 113 uint32_t size_bytes; 114 }; 115 116 enum psp_fw_type { 117 PSP_FW_TYPE_UNKOWN, 118 PSP_FW_TYPE_PSP_SOS, 119 PSP_FW_TYPE_PSP_SYS_DRV, 120 PSP_FW_TYPE_PSP_KDB, 121 PSP_FW_TYPE_PSP_TOC, 122 PSP_FW_TYPE_PSP_SPL, 123 PSP_FW_TYPE_PSP_RL, 124 PSP_FW_TYPE_PSP_SOC_DRV, 125 PSP_FW_TYPE_PSP_INTF_DRV, 126 PSP_FW_TYPE_PSP_DBG_DRV, 127 }; 128 129 /* version_major=2, version_minor=0 */ 130 struct psp_firmware_header_v2_0 { 131 struct common_firmware_header header; 132 uint32_t psp_fw_bin_count; 133 struct psp_fw_bin_desc psp_fw_bin[]; 134 }; 135 136 /* version_major=1, version_minor=0 */ 137 struct ta_firmware_header_v1_0 { 138 struct common_firmware_header header; 139 struct psp_fw_legacy_bin_desc xgmi; 140 struct psp_fw_legacy_bin_desc ras; 141 struct psp_fw_legacy_bin_desc hdcp; 142 struct psp_fw_legacy_bin_desc dtm; 143 struct psp_fw_legacy_bin_desc securedisplay; 144 }; 145 146 enum ta_fw_type { 147 TA_FW_TYPE_UNKOWN, 148 TA_FW_TYPE_PSP_ASD, 149 TA_FW_TYPE_PSP_XGMI, 150 TA_FW_TYPE_PSP_RAS, 151 TA_FW_TYPE_PSP_HDCP, 152 TA_FW_TYPE_PSP_DTM, 153 TA_FW_TYPE_PSP_RAP, 154 TA_FW_TYPE_PSP_SECUREDISPLAY, 155 TA_FW_TYPE_MAX_INDEX, 156 }; 157 158 /* version_major=2, version_minor=0 */ 159 struct ta_firmware_header_v2_0 { 160 struct common_firmware_header header; 161 uint32_t ta_fw_bin_count; 162 struct psp_fw_bin_desc ta_fw_bin[]; 163 }; 164 165 /* version_major=1, version_minor=0 */ 166 struct gfx_firmware_header_v1_0 { 167 struct common_firmware_header header; 168 uint32_t ucode_feature_version; 169 uint32_t jt_offset; /* jt location */ 170 uint32_t jt_size; /* size of jt */ 171 }; 172 173 /* version_major=2, version_minor=0 */ 174 struct gfx_firmware_header_v2_0 { 175 struct common_firmware_header header; 176 uint32_t ucode_feature_version; 177 uint32_t ucode_size_bytes; 178 uint32_t ucode_offset_bytes; 179 uint32_t data_size_bytes; 180 uint32_t data_offset_bytes; 181 uint32_t ucode_start_addr_lo; 182 uint32_t ucode_start_addr_hi; 183 }; 184 185 /* version_major=1, version_minor=0 */ 186 struct mes_firmware_header_v1_0 { 187 struct common_firmware_header header; 188 uint32_t mes_ucode_version; 189 uint32_t mes_ucode_size_bytes; 190 uint32_t mes_ucode_offset_bytes; 191 uint32_t mes_ucode_data_version; 192 uint32_t mes_ucode_data_size_bytes; 193 uint32_t mes_ucode_data_offset_bytes; 194 uint32_t mes_uc_start_addr_lo; 195 uint32_t mes_uc_start_addr_hi; 196 uint32_t mes_data_start_addr_lo; 197 uint32_t mes_data_start_addr_hi; 198 }; 199 200 /* version_major=1, version_minor=0 */ 201 struct rlc_firmware_header_v1_0 { 202 struct common_firmware_header header; 203 uint32_t ucode_feature_version; 204 uint32_t save_and_restore_offset; 205 uint32_t clear_state_descriptor_offset; 206 uint32_t avail_scratch_ram_locations; 207 uint32_t master_pkt_description_offset; 208 }; 209 210 /* version_major=2, version_minor=0 */ 211 struct rlc_firmware_header_v2_0 { 212 struct common_firmware_header header; 213 uint32_t ucode_feature_version; 214 uint32_t jt_offset; /* jt location */ 215 uint32_t jt_size; /* size of jt */ 216 uint32_t save_and_restore_offset; 217 uint32_t clear_state_descriptor_offset; 218 uint32_t avail_scratch_ram_locations; 219 uint32_t reg_restore_list_size; 220 uint32_t reg_list_format_start; 221 uint32_t reg_list_format_separate_start; 222 uint32_t starting_offsets_start; 223 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 224 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 225 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 226 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 227 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 228 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 229 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 230 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 231 }; 232 233 /* version_major=2, version_minor=1 */ 234 struct rlc_firmware_header_v2_1 { 235 struct rlc_firmware_header_v2_0 v2_0; 236 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 237 uint32_t save_restore_list_cntl_ucode_ver; 238 uint32_t save_restore_list_cntl_feature_ver; 239 uint32_t save_restore_list_cntl_size_bytes; 240 uint32_t save_restore_list_cntl_offset_bytes; 241 uint32_t save_restore_list_gpm_ucode_ver; 242 uint32_t save_restore_list_gpm_feature_ver; 243 uint32_t save_restore_list_gpm_size_bytes; 244 uint32_t save_restore_list_gpm_offset_bytes; 245 uint32_t save_restore_list_srm_ucode_ver; 246 uint32_t save_restore_list_srm_feature_ver; 247 uint32_t save_restore_list_srm_size_bytes; 248 uint32_t save_restore_list_srm_offset_bytes; 249 }; 250 251 /* version_major=2, version_minor=2 */ 252 struct rlc_firmware_header_v2_2 { 253 struct rlc_firmware_header_v2_1 v2_1; 254 uint32_t rlc_iram_ucode_size_bytes; 255 uint32_t rlc_iram_ucode_offset_bytes; 256 uint32_t rlc_dram_ucode_size_bytes; 257 uint32_t rlc_dram_ucode_offset_bytes; 258 }; 259 260 /* version_major=2, version_minor=3 */ 261 struct rlc_firmware_header_v2_3 { 262 struct rlc_firmware_header_v2_2 v2_2; 263 uint32_t rlcp_ucode_size_bytes; 264 uint32_t rlcp_ucode_offset_bytes; 265 uint32_t rlcv_ucode_size_bytes; 266 uint32_t rlcv_ucode_offset_bytes; 267 }; 268 269 /* version_major=1, version_minor=0 */ 270 struct sdma_firmware_header_v1_0 { 271 struct common_firmware_header header; 272 uint32_t ucode_feature_version; 273 uint32_t ucode_change_version; 274 uint32_t jt_offset; /* jt location */ 275 uint32_t jt_size; /* size of jt */ 276 }; 277 278 /* version_major=1, version_minor=1 */ 279 struct sdma_firmware_header_v1_1 { 280 struct sdma_firmware_header_v1_0 v1_0; 281 uint32_t digest_size; 282 }; 283 284 /* version_major=2, version_minor=0 */ 285 struct sdma_firmware_header_v2_0 { 286 struct common_firmware_header header; 287 uint32_t ucode_feature_version; 288 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 289 uint32_t ctx_jt_offset; /* context thread jt location */ 290 uint32_t ctx_jt_size; /* context thread size of jt */ 291 uint32_t ctl_ucode_offset; 292 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 293 uint32_t ctl_jt_offset; /* control thread jt location */ 294 uint32_t ctl_jt_size; /* control thread size of jt */ 295 }; 296 297 /* gpu info payload */ 298 struct gpu_info_firmware_v1_0 { 299 uint32_t gc_num_se; 300 uint32_t gc_num_cu_per_sh; 301 uint32_t gc_num_sh_per_se; 302 uint32_t gc_num_rb_per_se; 303 uint32_t gc_num_tccs; 304 uint32_t gc_num_gprs; 305 uint32_t gc_num_max_gs_thds; 306 uint32_t gc_gs_table_depth; 307 uint32_t gc_gsprim_buff_depth; 308 uint32_t gc_parameter_cache_depth; 309 uint32_t gc_double_offchip_lds_buffer; 310 uint32_t gc_wave_size; 311 uint32_t gc_max_waves_per_simd; 312 uint32_t gc_max_scratch_slots_per_cu; 313 uint32_t gc_lds_size; 314 }; 315 316 struct gpu_info_firmware_v1_1 { 317 struct gpu_info_firmware_v1_0 v1_0; 318 uint32_t num_sc_per_sh; 319 uint32_t num_packer_per_sc; 320 }; 321 322 /* gpu info payload 323 * version_major=1, version_minor=1 */ 324 struct gpu_info_firmware_v1_2 { 325 struct gpu_info_firmware_v1_1 v1_1; 326 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 327 }; 328 329 /* version_major=1, version_minor=0 */ 330 struct gpu_info_firmware_header_v1_0 { 331 struct common_firmware_header header; 332 uint16_t version_major; /* version */ 333 uint16_t version_minor; /* version */ 334 }; 335 336 /* version_major=1, version_minor=0 */ 337 struct dmcu_firmware_header_v1_0 { 338 struct common_firmware_header header; 339 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 340 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 341 }; 342 343 /* version_major=1, version_minor=0 */ 344 struct dmcub_firmware_header_v1_0 { 345 struct common_firmware_header header; 346 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 347 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 348 }; 349 350 /* version_major=1, version_minor=0 */ 351 struct imu_firmware_header_v1_0 { 352 struct common_firmware_header header; 353 uint32_t imu_iram_ucode_size_bytes; 354 uint32_t imu_iram_ucode_offset_bytes; 355 uint32_t imu_dram_ucode_size_bytes; 356 uint32_t imu_dram_ucode_offset_bytes; 357 }; 358 359 /* header is fixed size */ 360 union amdgpu_firmware_header { 361 struct common_firmware_header common; 362 struct mc_firmware_header_v1_0 mc; 363 struct smc_firmware_header_v1_0 smc; 364 struct smc_firmware_header_v2_0 smc_v2_0; 365 struct psp_firmware_header_v1_0 psp; 366 struct psp_firmware_header_v1_1 psp_v1_1; 367 struct psp_firmware_header_v1_3 psp_v1_3; 368 struct psp_firmware_header_v2_0 psp_v2_0; 369 struct ta_firmware_header_v1_0 ta; 370 struct ta_firmware_header_v2_0 ta_v2_0; 371 struct gfx_firmware_header_v1_0 gfx; 372 struct gfx_firmware_header_v2_0 gfx_v2_0; 373 struct rlc_firmware_header_v1_0 rlc; 374 struct rlc_firmware_header_v2_0 rlc_v2_0; 375 struct rlc_firmware_header_v2_1 rlc_v2_1; 376 struct rlc_firmware_header_v2_2 rlc_v2_2; 377 struct rlc_firmware_header_v2_3 rlc_v2_3; 378 struct sdma_firmware_header_v1_0 sdma; 379 struct sdma_firmware_header_v1_1 sdma_v1_1; 380 struct sdma_firmware_header_v2_0 sdma_v2_0; 381 struct gpu_info_firmware_header_v1_0 gpu_info; 382 struct dmcu_firmware_header_v1_0 dmcu; 383 struct dmcub_firmware_header_v1_0 dmcub; 384 struct imu_firmware_header_v1_0 imu; 385 uint8_t raw[0x100]; 386 }; 387 388 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) 389 390 /* 391 * fw loading support 392 */ 393 enum AMDGPU_UCODE_ID { 394 AMDGPU_UCODE_ID_CAP = 0, 395 AMDGPU_UCODE_ID_SDMA0, 396 AMDGPU_UCODE_ID_SDMA1, 397 AMDGPU_UCODE_ID_SDMA2, 398 AMDGPU_UCODE_ID_SDMA3, 399 AMDGPU_UCODE_ID_SDMA4, 400 AMDGPU_UCODE_ID_SDMA5, 401 AMDGPU_UCODE_ID_SDMA6, 402 AMDGPU_UCODE_ID_SDMA7, 403 AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 404 AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 405 AMDGPU_UCODE_ID_CP_CE, 406 AMDGPU_UCODE_ID_CP_PFP, 407 AMDGPU_UCODE_ID_CP_ME, 408 AMDGPU_UCODE_ID_CP_RS64_PFP, 409 AMDGPU_UCODE_ID_CP_RS64_ME, 410 AMDGPU_UCODE_ID_CP_RS64_MEC, 411 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 412 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 413 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 414 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 415 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 416 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 417 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 418 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 419 AMDGPU_UCODE_ID_CP_MEC1, 420 AMDGPU_UCODE_ID_CP_MEC1_JT, 421 AMDGPU_UCODE_ID_CP_MEC2, 422 AMDGPU_UCODE_ID_CP_MEC2_JT, 423 AMDGPU_UCODE_ID_CP_MES, 424 AMDGPU_UCODE_ID_CP_MES_DATA, 425 AMDGPU_UCODE_ID_CP_MES1, 426 AMDGPU_UCODE_ID_CP_MES1_DATA, 427 AMDGPU_UCODE_ID_IMU_I, 428 AMDGPU_UCODE_ID_IMU_D, 429 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 430 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 431 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 432 AMDGPU_UCODE_ID_RLC_IRAM, 433 AMDGPU_UCODE_ID_RLC_DRAM, 434 AMDGPU_UCODE_ID_RLC_P, 435 AMDGPU_UCODE_ID_RLC_V, 436 AMDGPU_UCODE_ID_RLC_G, 437 AMDGPU_UCODE_ID_STORAGE, 438 AMDGPU_UCODE_ID_SMC, 439 AMDGPU_UCODE_ID_PPTABLE, 440 AMDGPU_UCODE_ID_UVD, 441 AMDGPU_UCODE_ID_UVD1, 442 AMDGPU_UCODE_ID_VCE, 443 AMDGPU_UCODE_ID_VCN, 444 AMDGPU_UCODE_ID_VCN1, 445 AMDGPU_UCODE_ID_DMCU_ERAM, 446 AMDGPU_UCODE_ID_DMCU_INTV, 447 AMDGPU_UCODE_ID_VCN0_RAM, 448 AMDGPU_UCODE_ID_VCN1_RAM, 449 AMDGPU_UCODE_ID_DMCUB, 450 AMDGPU_UCODE_ID_MAXIMUM, 451 }; 452 453 /* engine firmware status */ 454 enum AMDGPU_UCODE_STATUS { 455 AMDGPU_UCODE_STATUS_INVALID, 456 AMDGPU_UCODE_STATUS_NOT_LOADED, 457 AMDGPU_UCODE_STATUS_LOADED, 458 }; 459 460 enum amdgpu_firmware_load_type { 461 AMDGPU_FW_LOAD_DIRECT = 0, 462 AMDGPU_FW_LOAD_PSP, 463 AMDGPU_FW_LOAD_SMU, 464 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 465 }; 466 467 /* conform to smu_ucode_xfer_cz.h */ 468 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 469 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 470 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 471 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 472 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 473 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 474 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 475 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 476 477 /* amdgpu firmware info */ 478 struct amdgpu_firmware_info { 479 /* ucode ID */ 480 enum AMDGPU_UCODE_ID ucode_id; 481 /* request_firmware */ 482 const struct firmware *fw; 483 /* starting mc address */ 484 uint64_t mc_addr; 485 /* kernel linear address */ 486 void *kaddr; 487 /* ucode_size_bytes */ 488 uint32_t ucode_size; 489 /* starting tmr mc address */ 490 uint32_t tmr_mc_addr_lo; 491 uint32_t tmr_mc_addr_hi; 492 }; 493 494 struct amdgpu_firmware { 495 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 496 enum amdgpu_firmware_load_type load_type; 497 struct amdgpu_bo *fw_buf; 498 unsigned int fw_size; 499 unsigned int max_ucodes; 500 /* firmwares are loaded by psp instead of smu from vega10 */ 501 const struct amdgpu_psp_funcs *funcs; 502 struct amdgpu_bo *rbuf; 503 struct mutex mutex; 504 505 /* gpu info firmware data pointer */ 506 const struct firmware *gpu_info_fw; 507 508 void *fw_buf_ptr; 509 uint64_t fw_buf_mc; 510 }; 511 512 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 513 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 514 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 515 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 516 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 517 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 518 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 519 int amdgpu_ucode_validate(const struct firmware *fw); 520 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 521 uint16_t hdr_major, uint16_t hdr_minor); 522 523 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 524 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 525 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 526 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 527 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 528 529 enum amdgpu_firmware_load_type 530 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 531 532 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 533 534 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 535 536 #endif 537