1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=2, version_minor=0 */ 55 struct smc_firmware_header_v2_0 { 56 struct smc_firmware_header_v1_0 v1_0; 57 uint32_t ppt_offset_bytes; /* soft pptable offset */ 58 uint32_t ppt_size_bytes; /* soft pptable size */ 59 }; 60 61 struct smc_soft_pptable_entry { 62 uint32_t id; 63 uint32_t ppt_offset_bytes; 64 uint32_t ppt_size_bytes; 65 }; 66 67 /* version_major=2, version_minor=1 */ 68 struct smc_firmware_header_v2_1 { 69 struct smc_firmware_header_v1_0 v1_0; 70 uint32_t pptable_count; 71 uint32_t pptable_entry_offset; 72 }; 73 74 struct psp_fw_legacy_bin_desc { 75 uint32_t fw_version; 76 uint32_t offset_bytes; 77 uint32_t size_bytes; 78 }; 79 80 /* version_major=1, version_minor=0 */ 81 struct psp_firmware_header_v1_0 { 82 struct common_firmware_header header; 83 struct psp_fw_legacy_bin_desc sos; 84 }; 85 86 /* version_major=1, version_minor=1 */ 87 struct psp_firmware_header_v1_1 { 88 struct psp_firmware_header_v1_0 v1_0; 89 struct psp_fw_legacy_bin_desc toc; 90 struct psp_fw_legacy_bin_desc kdb; 91 }; 92 93 /* version_major=1, version_minor=2 */ 94 struct psp_firmware_header_v1_2 { 95 struct psp_firmware_header_v1_0 v1_0; 96 struct psp_fw_legacy_bin_desc res; 97 struct psp_fw_legacy_bin_desc kdb; 98 }; 99 100 /* version_major=1, version_minor=3 */ 101 struct psp_firmware_header_v1_3 { 102 struct psp_firmware_header_v1_1 v1_1; 103 struct psp_fw_legacy_bin_desc spl; 104 struct psp_fw_legacy_bin_desc rl; 105 struct psp_fw_legacy_bin_desc sys_drv_aux; 106 struct psp_fw_legacy_bin_desc sos_aux; 107 }; 108 109 struct psp_fw_bin_desc { 110 uint32_t fw_type; 111 uint32_t fw_version; 112 uint32_t offset_bytes; 113 uint32_t size_bytes; 114 }; 115 116 enum psp_fw_type { 117 PSP_FW_TYPE_UNKOWN, 118 PSP_FW_TYPE_PSP_SOS, 119 PSP_FW_TYPE_PSP_SYS_DRV, 120 PSP_FW_TYPE_PSP_KDB, 121 PSP_FW_TYPE_PSP_TOC, 122 PSP_FW_TYPE_PSP_SPL, 123 PSP_FW_TYPE_PSP_RL, 124 PSP_FW_TYPE_PSP_SOC_DRV, 125 PSP_FW_TYPE_PSP_INTF_DRV, 126 PSP_FW_TYPE_PSP_DBG_DRV, 127 PSP_FW_TYPE_PSP_RAS_DRV, 128 PSP_FW_TYPE_PSP_IPKEYMGR_DRV, 129 PSP_FW_TYPE_MAX_INDEX, 130 }; 131 132 /* version_major=2, version_minor=0 */ 133 struct psp_firmware_header_v2_0 { 134 struct common_firmware_header header; 135 uint32_t psp_fw_bin_count; 136 struct psp_fw_bin_desc psp_fw_bin[]; 137 }; 138 139 /* version_major=1, version_minor=0 */ 140 struct ta_firmware_header_v1_0 { 141 struct common_firmware_header header; 142 struct psp_fw_legacy_bin_desc xgmi; 143 struct psp_fw_legacy_bin_desc ras; 144 struct psp_fw_legacy_bin_desc hdcp; 145 struct psp_fw_legacy_bin_desc dtm; 146 struct psp_fw_legacy_bin_desc securedisplay; 147 }; 148 149 enum ta_fw_type { 150 TA_FW_TYPE_UNKOWN, 151 TA_FW_TYPE_PSP_ASD, 152 TA_FW_TYPE_PSP_XGMI, 153 TA_FW_TYPE_PSP_RAS, 154 TA_FW_TYPE_PSP_HDCP, 155 TA_FW_TYPE_PSP_DTM, 156 TA_FW_TYPE_PSP_RAP, 157 TA_FW_TYPE_PSP_SECUREDISPLAY, 158 TA_FW_TYPE_MAX_INDEX, 159 }; 160 161 /* version_major=2, version_minor=0 */ 162 struct ta_firmware_header_v2_0 { 163 struct common_firmware_header header; 164 uint32_t ta_fw_bin_count; 165 struct psp_fw_bin_desc ta_fw_bin[]; 166 }; 167 168 /* version_major=1, version_minor=0 */ 169 struct gfx_firmware_header_v1_0 { 170 struct common_firmware_header header; 171 uint32_t ucode_feature_version; 172 uint32_t jt_offset; /* jt location */ 173 uint32_t jt_size; /* size of jt */ 174 }; 175 176 /* version_major=2, version_minor=0 */ 177 struct gfx_firmware_header_v2_0 { 178 struct common_firmware_header header; 179 uint32_t ucode_feature_version; 180 uint32_t ucode_size_bytes; 181 uint32_t ucode_offset_bytes; 182 uint32_t data_size_bytes; 183 uint32_t data_offset_bytes; 184 uint32_t ucode_start_addr_lo; 185 uint32_t ucode_start_addr_hi; 186 }; 187 188 /* version_major=1, version_minor=0 */ 189 struct mes_firmware_header_v1_0 { 190 struct common_firmware_header header; 191 uint32_t mes_ucode_version; 192 uint32_t mes_ucode_size_bytes; 193 uint32_t mes_ucode_offset_bytes; 194 uint32_t mes_ucode_data_version; 195 uint32_t mes_ucode_data_size_bytes; 196 uint32_t mes_ucode_data_offset_bytes; 197 uint32_t mes_uc_start_addr_lo; 198 uint32_t mes_uc_start_addr_hi; 199 uint32_t mes_data_start_addr_lo; 200 uint32_t mes_data_start_addr_hi; 201 }; 202 203 /* version_major=1, version_minor=0 */ 204 struct rlc_firmware_header_v1_0 { 205 struct common_firmware_header header; 206 uint32_t ucode_feature_version; 207 uint32_t save_and_restore_offset; 208 uint32_t clear_state_descriptor_offset; 209 uint32_t avail_scratch_ram_locations; 210 uint32_t master_pkt_description_offset; 211 }; 212 213 /* version_major=2, version_minor=0 */ 214 struct rlc_firmware_header_v2_0 { 215 struct common_firmware_header header; 216 uint32_t ucode_feature_version; 217 uint32_t jt_offset; /* jt location */ 218 uint32_t jt_size; /* size of jt */ 219 uint32_t save_and_restore_offset; 220 uint32_t clear_state_descriptor_offset; 221 uint32_t avail_scratch_ram_locations; 222 uint32_t reg_restore_list_size; 223 uint32_t reg_list_format_start; 224 uint32_t reg_list_format_separate_start; 225 uint32_t starting_offsets_start; 226 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 227 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 228 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 229 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 230 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 231 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 232 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 233 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 234 }; 235 236 /* version_major=2, version_minor=1 */ 237 struct rlc_firmware_header_v2_1 { 238 struct rlc_firmware_header_v2_0 v2_0; 239 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 240 uint32_t save_restore_list_cntl_ucode_ver; 241 uint32_t save_restore_list_cntl_feature_ver; 242 uint32_t save_restore_list_cntl_size_bytes; 243 uint32_t save_restore_list_cntl_offset_bytes; 244 uint32_t save_restore_list_gpm_ucode_ver; 245 uint32_t save_restore_list_gpm_feature_ver; 246 uint32_t save_restore_list_gpm_size_bytes; 247 uint32_t save_restore_list_gpm_offset_bytes; 248 uint32_t save_restore_list_srm_ucode_ver; 249 uint32_t save_restore_list_srm_feature_ver; 250 uint32_t save_restore_list_srm_size_bytes; 251 uint32_t save_restore_list_srm_offset_bytes; 252 }; 253 254 /* version_major=2, version_minor=2 */ 255 struct rlc_firmware_header_v2_2 { 256 struct rlc_firmware_header_v2_1 v2_1; 257 uint32_t rlc_iram_ucode_size_bytes; 258 uint32_t rlc_iram_ucode_offset_bytes; 259 uint32_t rlc_dram_ucode_size_bytes; 260 uint32_t rlc_dram_ucode_offset_bytes; 261 }; 262 263 /* version_major=2, version_minor=3 */ 264 struct rlc_firmware_header_v2_3 { 265 struct rlc_firmware_header_v2_2 v2_2; 266 uint32_t rlcp_ucode_version; 267 uint32_t rlcp_ucode_feature_version; 268 uint32_t rlcp_ucode_size_bytes; 269 uint32_t rlcp_ucode_offset_bytes; 270 uint32_t rlcv_ucode_version; 271 uint32_t rlcv_ucode_feature_version; 272 uint32_t rlcv_ucode_size_bytes; 273 uint32_t rlcv_ucode_offset_bytes; 274 }; 275 276 /* version_major=2, version_minor=4 */ 277 struct rlc_firmware_header_v2_4 { 278 struct rlc_firmware_header_v2_3 v2_3; 279 uint32_t global_tap_delays_ucode_size_bytes; 280 uint32_t global_tap_delays_ucode_offset_bytes; 281 uint32_t se0_tap_delays_ucode_size_bytes; 282 uint32_t se0_tap_delays_ucode_offset_bytes; 283 uint32_t se1_tap_delays_ucode_size_bytes; 284 uint32_t se1_tap_delays_ucode_offset_bytes; 285 uint32_t se2_tap_delays_ucode_size_bytes; 286 uint32_t se2_tap_delays_ucode_offset_bytes; 287 uint32_t se3_tap_delays_ucode_size_bytes; 288 uint32_t se3_tap_delays_ucode_offset_bytes; 289 }; 290 291 /* version_major=1, version_minor=0 */ 292 struct sdma_firmware_header_v1_0 { 293 struct common_firmware_header header; 294 uint32_t ucode_feature_version; 295 uint32_t ucode_change_version; 296 uint32_t jt_offset; /* jt location */ 297 uint32_t jt_size; /* size of jt */ 298 }; 299 300 /* version_major=1, version_minor=1 */ 301 struct sdma_firmware_header_v1_1 { 302 struct sdma_firmware_header_v1_0 v1_0; 303 uint32_t digest_size; 304 }; 305 306 /* version_major=2, version_minor=0 */ 307 struct sdma_firmware_header_v2_0 { 308 struct common_firmware_header header; 309 uint32_t ucode_feature_version; 310 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 311 uint32_t ctx_jt_offset; /* context thread jt location */ 312 uint32_t ctx_jt_size; /* context thread size of jt */ 313 uint32_t ctl_ucode_offset; 314 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 315 uint32_t ctl_jt_offset; /* control thread jt location */ 316 uint32_t ctl_jt_size; /* control thread size of jt */ 317 }; 318 319 /* version_major=1, version_minor=0 */ 320 struct vpe_firmware_header_v1_0 { 321 struct common_firmware_header header; 322 uint32_t ucode_feature_version; 323 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 324 uint32_t ctx_jt_offset; /* context thread jt location */ 325 uint32_t ctx_jt_size; /* context thread size of jt */ 326 uint32_t ctl_ucode_offset; 327 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 328 uint32_t ctl_jt_offset; /* control thread jt location */ 329 uint32_t ctl_jt_size; /* control thread size of jt */ 330 }; 331 332 /* version_major=1, version_minor=0 */ 333 struct umsch_mm_firmware_header_v1_0 { 334 struct common_firmware_header header; 335 uint32_t umsch_mm_ucode_version; 336 uint32_t umsch_mm_ucode_size_bytes; 337 uint32_t umsch_mm_ucode_offset_bytes; 338 uint32_t umsch_mm_ucode_data_version; 339 uint32_t umsch_mm_ucode_data_size_bytes; 340 uint32_t umsch_mm_ucode_data_offset_bytes; 341 uint32_t umsch_mm_irq_start_addr_lo; 342 uint32_t umsch_mm_irq_start_addr_hi; 343 uint32_t umsch_mm_uc_start_addr_lo; 344 uint32_t umsch_mm_uc_start_addr_hi; 345 uint32_t umsch_mm_data_start_addr_lo; 346 uint32_t umsch_mm_data_start_addr_hi; 347 }; 348 349 /* version_major=3, version_minor=0 */ 350 struct sdma_firmware_header_v3_0 { 351 struct common_firmware_header header; 352 uint32_t ucode_feature_version; 353 uint32_t ucode_offset_bytes; 354 uint32_t ucode_size_bytes; 355 }; 356 357 /* gpu info payload */ 358 struct gpu_info_firmware_v1_0 { 359 uint32_t gc_num_se; 360 uint32_t gc_num_cu_per_sh; 361 uint32_t gc_num_sh_per_se; 362 uint32_t gc_num_rb_per_se; 363 uint32_t gc_num_tccs; 364 uint32_t gc_num_gprs; 365 uint32_t gc_num_max_gs_thds; 366 uint32_t gc_gs_table_depth; 367 uint32_t gc_gsprim_buff_depth; 368 uint32_t gc_parameter_cache_depth; 369 uint32_t gc_double_offchip_lds_buffer; 370 uint32_t gc_wave_size; 371 uint32_t gc_max_waves_per_simd; 372 uint32_t gc_max_scratch_slots_per_cu; 373 uint32_t gc_lds_size; 374 }; 375 376 struct gpu_info_firmware_v1_1 { 377 struct gpu_info_firmware_v1_0 v1_0; 378 uint32_t num_sc_per_sh; 379 uint32_t num_packer_per_sc; 380 }; 381 382 /* gpu info payload 383 * version_major=1, version_minor=1 */ 384 struct gpu_info_firmware_v1_2 { 385 struct gpu_info_firmware_v1_1 v1_1; 386 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 387 }; 388 389 /* version_major=1, version_minor=0 */ 390 struct gpu_info_firmware_header_v1_0 { 391 struct common_firmware_header header; 392 uint16_t version_major; /* version */ 393 uint16_t version_minor; /* version */ 394 }; 395 396 /* version_major=1, version_minor=0 */ 397 struct dmcu_firmware_header_v1_0 { 398 struct common_firmware_header header; 399 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 400 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 401 }; 402 403 /* version_major=1, version_minor=0 */ 404 struct dmcub_firmware_header_v1_0 { 405 struct common_firmware_header header; 406 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 407 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 408 }; 409 410 /* version_major=1, version_minor=0 */ 411 struct imu_firmware_header_v1_0 { 412 struct common_firmware_header header; 413 uint32_t imu_iram_ucode_size_bytes; 414 uint32_t imu_iram_ucode_offset_bytes; 415 uint32_t imu_dram_ucode_size_bytes; 416 uint32_t imu_dram_ucode_offset_bytes; 417 }; 418 419 /* header is fixed size */ 420 union amdgpu_firmware_header { 421 struct common_firmware_header common; 422 struct mc_firmware_header_v1_0 mc; 423 struct smc_firmware_header_v1_0 smc; 424 struct smc_firmware_header_v2_0 smc_v2_0; 425 struct psp_firmware_header_v1_0 psp; 426 struct psp_firmware_header_v1_1 psp_v1_1; 427 struct psp_firmware_header_v1_3 psp_v1_3; 428 struct psp_firmware_header_v2_0 psp_v2_0; 429 struct ta_firmware_header_v1_0 ta; 430 struct ta_firmware_header_v2_0 ta_v2_0; 431 struct gfx_firmware_header_v1_0 gfx; 432 struct gfx_firmware_header_v2_0 gfx_v2_0; 433 struct rlc_firmware_header_v1_0 rlc; 434 struct rlc_firmware_header_v2_0 rlc_v2_0; 435 struct rlc_firmware_header_v2_1 rlc_v2_1; 436 struct rlc_firmware_header_v2_2 rlc_v2_2; 437 struct rlc_firmware_header_v2_3 rlc_v2_3; 438 struct rlc_firmware_header_v2_4 rlc_v2_4; 439 struct sdma_firmware_header_v1_0 sdma; 440 struct sdma_firmware_header_v1_1 sdma_v1_1; 441 struct sdma_firmware_header_v2_0 sdma_v2_0; 442 struct sdma_firmware_header_v3_0 sdma_v3_0; 443 struct gpu_info_firmware_header_v1_0 gpu_info; 444 struct dmcu_firmware_header_v1_0 dmcu; 445 struct dmcub_firmware_header_v1_0 dmcub; 446 struct imu_firmware_header_v1_0 imu; 447 uint8_t raw[0x100]; 448 }; 449 450 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) 451 452 /* 453 * fw loading support 454 */ 455 enum AMDGPU_UCODE_ID { 456 AMDGPU_UCODE_ID_CAP = 0, 457 AMDGPU_UCODE_ID_SDMA0, 458 AMDGPU_UCODE_ID_SDMA1, 459 AMDGPU_UCODE_ID_SDMA2, 460 AMDGPU_UCODE_ID_SDMA3, 461 AMDGPU_UCODE_ID_SDMA4, 462 AMDGPU_UCODE_ID_SDMA5, 463 AMDGPU_UCODE_ID_SDMA6, 464 AMDGPU_UCODE_ID_SDMA7, 465 AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 466 AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 467 AMDGPU_UCODE_ID_SDMA_RS64, 468 AMDGPU_UCODE_ID_CP_CE, 469 AMDGPU_UCODE_ID_CP_PFP, 470 AMDGPU_UCODE_ID_CP_ME, 471 AMDGPU_UCODE_ID_CP_RS64_PFP, 472 AMDGPU_UCODE_ID_CP_RS64_ME, 473 AMDGPU_UCODE_ID_CP_RS64_MEC, 474 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 475 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 476 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 477 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 478 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 479 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 480 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 481 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 482 AMDGPU_UCODE_ID_CP_MEC1, 483 AMDGPU_UCODE_ID_CP_MEC1_JT, 484 AMDGPU_UCODE_ID_CP_MEC2, 485 AMDGPU_UCODE_ID_CP_MEC2_JT, 486 AMDGPU_UCODE_ID_CP_MES, 487 AMDGPU_UCODE_ID_CP_MES_DATA, 488 AMDGPU_UCODE_ID_CP_MES1, 489 AMDGPU_UCODE_ID_CP_MES1_DATA, 490 AMDGPU_UCODE_ID_IMU_I, 491 AMDGPU_UCODE_ID_IMU_D, 492 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, 493 AMDGPU_UCODE_ID_SE0_TAP_DELAYS, 494 AMDGPU_UCODE_ID_SE1_TAP_DELAYS, 495 AMDGPU_UCODE_ID_SE2_TAP_DELAYS, 496 AMDGPU_UCODE_ID_SE3_TAP_DELAYS, 497 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 498 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 499 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 500 AMDGPU_UCODE_ID_RLC_IRAM, 501 AMDGPU_UCODE_ID_RLC_DRAM, 502 AMDGPU_UCODE_ID_RLC_P, 503 AMDGPU_UCODE_ID_RLC_V, 504 AMDGPU_UCODE_ID_RLC_G, 505 AMDGPU_UCODE_ID_STORAGE, 506 AMDGPU_UCODE_ID_SMC, 507 AMDGPU_UCODE_ID_PPTABLE, 508 AMDGPU_UCODE_ID_UVD, 509 AMDGPU_UCODE_ID_UVD1, 510 AMDGPU_UCODE_ID_VCE, 511 AMDGPU_UCODE_ID_VCN, 512 AMDGPU_UCODE_ID_VCN1, 513 AMDGPU_UCODE_ID_DMCU_ERAM, 514 AMDGPU_UCODE_ID_DMCU_INTV, 515 AMDGPU_UCODE_ID_VCN0_RAM, 516 AMDGPU_UCODE_ID_VCN1_RAM, 517 AMDGPU_UCODE_ID_DMCUB, 518 AMDGPU_UCODE_ID_VPE_CTX, 519 AMDGPU_UCODE_ID_VPE_CTL, 520 AMDGPU_UCODE_ID_VPE, 521 AMDGPU_UCODE_ID_UMSCH_MM_UCODE, 522 AMDGPU_UCODE_ID_UMSCH_MM_DATA, 523 AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER, 524 AMDGPU_UCODE_ID_P2S_TABLE, 525 AMDGPU_UCODE_ID_JPEG_RAM, 526 AMDGPU_UCODE_ID_ISP, 527 AMDGPU_UCODE_ID_MAXIMUM, 528 }; 529 530 /* engine firmware status */ 531 enum AMDGPU_UCODE_STATUS { 532 AMDGPU_UCODE_STATUS_INVALID, 533 AMDGPU_UCODE_STATUS_NOT_LOADED, 534 AMDGPU_UCODE_STATUS_LOADED, 535 }; 536 537 enum amdgpu_firmware_load_type { 538 AMDGPU_FW_LOAD_DIRECT = 0, 539 AMDGPU_FW_LOAD_PSP, 540 AMDGPU_FW_LOAD_SMU, 541 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 542 }; 543 544 /* conform to smu_ucode_xfer_cz.h */ 545 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 546 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 547 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 548 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 549 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 550 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 551 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 552 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 553 554 /* amdgpu firmware info */ 555 struct amdgpu_firmware_info { 556 /* ucode ID */ 557 enum AMDGPU_UCODE_ID ucode_id; 558 /* request_firmware */ 559 const struct firmware *fw; 560 /* starting mc address */ 561 uint64_t mc_addr; 562 /* kernel linear address */ 563 void *kaddr; 564 /* ucode_size_bytes */ 565 uint32_t ucode_size; 566 /* starting tmr mc address */ 567 uint32_t tmr_mc_addr_lo; 568 uint32_t tmr_mc_addr_hi; 569 }; 570 571 struct amdgpu_firmware { 572 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 573 enum amdgpu_firmware_load_type load_type; 574 struct amdgpu_bo *fw_buf; 575 unsigned int fw_size; 576 unsigned int max_ucodes; 577 /* firmwares are loaded by psp instead of smu from vega10 */ 578 const struct amdgpu_psp_funcs *funcs; 579 struct amdgpu_bo *rbuf; 580 struct mutex mutex; 581 582 /* gpu info firmware data pointer */ 583 const struct firmware *gpu_info_fw; 584 585 void *fw_buf_ptr; 586 uint64_t fw_buf_mc; 587 }; 588 589 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 590 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 591 void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); 592 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 593 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 594 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 595 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 596 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 597 __printf(3, 4) 598 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 599 const char *fmt, ...); 600 void amdgpu_ucode_release(const struct firmware **fw); 601 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 602 uint16_t hdr_major, uint16_t hdr_minor); 603 604 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 605 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 606 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 607 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 608 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 609 610 enum amdgpu_firmware_load_type 611 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 612 613 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 614 615 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 616 617 #endif 618