1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 #define AMDGPU_UCODE_NAME_MAX (128) 32 33 static const struct kicker_device kicker_device_list[] = { 34 {0x744B, 0x00}, 35 {0x7551, 0xC8} 36 }; 37 38 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 39 { 40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 42 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 43 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 44 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 45 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 48 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 49 le32_to_cpu(hdr->ucode_array_offset_bytes)); 50 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 51 } 52 53 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 54 { 55 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 56 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 57 58 DRM_DEBUG("MC\n"); 59 amdgpu_ucode_print_common_hdr(hdr); 60 61 if (version_major == 1) { 62 const struct mc_firmware_header_v1_0 *mc_hdr = 63 container_of(hdr, struct mc_firmware_header_v1_0, header); 64 65 DRM_DEBUG("io_debug_size_bytes: %u\n", 66 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 67 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 68 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 69 } else { 70 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 71 } 72 } 73 74 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 75 { 76 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 77 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 78 const struct smc_firmware_header_v1_0 *v1_0_hdr; 79 const struct smc_firmware_header_v2_0 *v2_0_hdr; 80 const struct smc_firmware_header_v2_1 *v2_1_hdr; 81 82 DRM_DEBUG("SMC\n"); 83 amdgpu_ucode_print_common_hdr(hdr); 84 85 if (version_major == 1) { 86 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 87 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 88 } else if (version_major == 2) { 89 switch (version_minor) { 90 case 0: 91 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 92 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 93 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 94 break; 95 case 1: 96 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 97 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 98 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 99 break; 100 default: 101 break; 102 } 103 104 } else { 105 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 106 } 107 } 108 109 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 110 { 111 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 112 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 113 114 DRM_DEBUG("GFX\n"); 115 amdgpu_ucode_print_common_hdr(hdr); 116 117 if (version_major == 1) { 118 const struct gfx_firmware_header_v1_0 *gfx_hdr = 119 container_of(hdr, struct gfx_firmware_header_v1_0, header); 120 121 DRM_DEBUG("ucode_feature_version: %u\n", 122 le32_to_cpu(gfx_hdr->ucode_feature_version)); 123 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 124 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 125 } else if (version_major == 2) { 126 const struct gfx_firmware_header_v2_0 *gfx_hdr = 127 container_of(hdr, struct gfx_firmware_header_v2_0, header); 128 129 DRM_DEBUG("ucode_feature_version: %u\n", 130 le32_to_cpu(gfx_hdr->ucode_feature_version)); 131 } else { 132 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 133 } 134 } 135 136 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 137 { 138 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 139 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 140 141 DRM_DEBUG("RLC\n"); 142 amdgpu_ucode_print_common_hdr(hdr); 143 144 if (version_major == 1) { 145 const struct rlc_firmware_header_v1_0 *rlc_hdr = 146 container_of(hdr, struct rlc_firmware_header_v1_0, header); 147 148 DRM_DEBUG("ucode_feature_version: %u\n", 149 le32_to_cpu(rlc_hdr->ucode_feature_version)); 150 DRM_DEBUG("save_and_restore_offset: %u\n", 151 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 152 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 153 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 154 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 155 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 156 DRM_DEBUG("master_pkt_description_offset: %u\n", 157 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 158 } else if (version_major == 2) { 159 const struct rlc_firmware_header_v2_0 *rlc_hdr = 160 container_of(hdr, struct rlc_firmware_header_v2_0, header); 161 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = 162 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 163 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = 164 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); 165 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = 166 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); 167 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = 168 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); 169 170 switch (version_minor) { 171 case 0: 172 /* rlc_hdr v2_0 */ 173 DRM_DEBUG("ucode_feature_version: %u\n", 174 le32_to_cpu(rlc_hdr->ucode_feature_version)); 175 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 176 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 177 DRM_DEBUG("save_and_restore_offset: %u\n", 178 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 179 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 180 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 181 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 182 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 183 DRM_DEBUG("reg_restore_list_size: %u\n", 184 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 185 DRM_DEBUG("reg_list_format_start: %u\n", 186 le32_to_cpu(rlc_hdr->reg_list_format_start)); 187 DRM_DEBUG("reg_list_format_separate_start: %u\n", 188 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 189 DRM_DEBUG("starting_offsets_start: %u\n", 190 le32_to_cpu(rlc_hdr->starting_offsets_start)); 191 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 192 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 193 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 194 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 195 DRM_DEBUG("reg_list_size_bytes: %u\n", 196 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 197 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 198 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 199 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 200 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 201 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 202 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 203 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 204 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 205 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 206 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 207 break; 208 case 1: 209 /* rlc_hdr v2_1 */ 210 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 211 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); 212 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 213 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); 214 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 215 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); 216 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 217 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); 218 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 219 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); 220 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 221 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); 222 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 223 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); 224 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 225 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); 226 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 227 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); 228 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 229 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); 230 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 231 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); 232 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 233 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); 234 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 235 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); 236 break; 237 case 2: 238 /* rlc_hdr v2_2 */ 239 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", 240 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); 241 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", 242 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); 243 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", 244 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); 245 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", 246 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); 247 break; 248 case 3: 249 /* rlc_hdr v2_3 */ 250 DRM_DEBUG("rlcp_ucode_version: %u\n", 251 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); 252 DRM_DEBUG("rlcp_ucode_feature_version: %u\n", 253 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); 254 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", 255 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); 256 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", 257 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); 258 DRM_DEBUG("rlcv_ucode_version: %u\n", 259 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); 260 DRM_DEBUG("rlcv_ucode_feature_version: %u\n", 261 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); 262 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", 263 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); 264 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", 265 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); 266 break; 267 case 4: 268 /* rlc_hdr v2_4 */ 269 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", 270 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); 271 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", 272 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); 273 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", 274 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); 275 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", 276 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); 277 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", 278 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); 279 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", 280 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); 281 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", 282 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); 283 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", 284 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); 285 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", 286 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); 287 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", 288 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); 289 break; 290 default: 291 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); 292 break; 293 } 294 } else { 295 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 296 } 297 } 298 299 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 300 { 301 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 302 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 303 304 DRM_DEBUG("SDMA\n"); 305 amdgpu_ucode_print_common_hdr(hdr); 306 307 if (version_major == 1) { 308 const struct sdma_firmware_header_v1_0 *sdma_hdr = 309 container_of(hdr, struct sdma_firmware_header_v1_0, header); 310 311 DRM_DEBUG("ucode_feature_version: %u\n", 312 le32_to_cpu(sdma_hdr->ucode_feature_version)); 313 DRM_DEBUG("ucode_change_version: %u\n", 314 le32_to_cpu(sdma_hdr->ucode_change_version)); 315 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 316 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 317 if (version_minor >= 1) { 318 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 319 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 320 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 321 } 322 } else if (version_major == 2) { 323 const struct sdma_firmware_header_v2_0 *sdma_hdr = 324 container_of(hdr, struct sdma_firmware_header_v2_0, header); 325 326 DRM_DEBUG("ucode_feature_version: %u\n", 327 le32_to_cpu(sdma_hdr->ucode_feature_version)); 328 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); 329 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); 330 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 331 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); 332 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); 333 } else if (version_major == 3) { 334 const struct sdma_firmware_header_v3_0 *sdma_hdr = 335 container_of(hdr, struct sdma_firmware_header_v3_0, header); 336 337 DRM_DEBUG("ucode_reversion: %u\n", 338 le32_to_cpu(sdma_hdr->ucode_feature_version)); 339 } else { 340 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 341 version_major, version_minor); 342 } 343 } 344 345 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 346 { 347 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 348 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 349 uint32_t fw_index; 350 const struct psp_fw_bin_desc *desc; 351 352 DRM_DEBUG("PSP\n"); 353 amdgpu_ucode_print_common_hdr(hdr); 354 355 if (version_major == 1) { 356 const struct psp_firmware_header_v1_0 *psp_hdr = 357 container_of(hdr, struct psp_firmware_header_v1_0, header); 358 359 DRM_DEBUG("ucode_feature_version: %u\n", 360 le32_to_cpu(psp_hdr->sos.fw_version)); 361 DRM_DEBUG("sos_offset_bytes: %u\n", 362 le32_to_cpu(psp_hdr->sos.offset_bytes)); 363 DRM_DEBUG("sos_size_bytes: %u\n", 364 le32_to_cpu(psp_hdr->sos.size_bytes)); 365 if (version_minor == 1) { 366 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 367 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 368 DRM_DEBUG("toc_header_version: %u\n", 369 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 370 DRM_DEBUG("toc_offset_bytes: %u\n", 371 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 372 DRM_DEBUG("toc_size_bytes: %u\n", 373 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 374 DRM_DEBUG("kdb_header_version: %u\n", 375 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 376 DRM_DEBUG("kdb_offset_bytes: %u\n", 377 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 378 DRM_DEBUG("kdb_size_bytes: %u\n", 379 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 380 } 381 if (version_minor == 2) { 382 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 383 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 384 DRM_DEBUG("kdb_header_version: %u\n", 385 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 386 DRM_DEBUG("kdb_offset_bytes: %u\n", 387 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 388 DRM_DEBUG("kdb_size_bytes: %u\n", 389 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 390 } 391 if (version_minor == 3) { 392 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 393 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 394 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 395 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 396 DRM_DEBUG("toc_header_version: %u\n", 397 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 398 DRM_DEBUG("toc_offset_bytes: %u\n", 399 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 400 DRM_DEBUG("toc_size_bytes: %u\n", 401 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 402 DRM_DEBUG("kdb_header_version: %u\n", 403 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 404 DRM_DEBUG("kdb_offset_bytes: %u\n", 405 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 406 DRM_DEBUG("kdb_size_bytes: %u\n", 407 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 408 DRM_DEBUG("spl_header_version: %u\n", 409 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 410 DRM_DEBUG("spl_offset_bytes: %u\n", 411 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 412 DRM_DEBUG("spl_size_bytes: %u\n", 413 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 414 } 415 } else if (version_major == 2) { 416 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = 417 container_of(hdr, struct psp_firmware_header_v2_0, header); 418 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { 419 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); 420 switch (desc->fw_type) { 421 case PSP_FW_TYPE_PSP_SOS: 422 DRM_DEBUG("psp_sos_version: %u\n", 423 le32_to_cpu(desc->fw_version)); 424 DRM_DEBUG("psp_sos_size_bytes: %u\n", 425 le32_to_cpu(desc->size_bytes)); 426 break; 427 case PSP_FW_TYPE_PSP_SYS_DRV: 428 DRM_DEBUG("psp_sys_drv_version: %u\n", 429 le32_to_cpu(desc->fw_version)); 430 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", 431 le32_to_cpu(desc->size_bytes)); 432 break; 433 case PSP_FW_TYPE_PSP_KDB: 434 DRM_DEBUG("psp_kdb_version: %u\n", 435 le32_to_cpu(desc->fw_version)); 436 DRM_DEBUG("psp_kdb_size_bytes: %u\n", 437 le32_to_cpu(desc->size_bytes)); 438 break; 439 case PSP_FW_TYPE_PSP_TOC: 440 DRM_DEBUG("psp_toc_version: %u\n", 441 le32_to_cpu(desc->fw_version)); 442 DRM_DEBUG("psp_toc_size_bytes: %u\n", 443 le32_to_cpu(desc->size_bytes)); 444 break; 445 case PSP_FW_TYPE_PSP_SPL: 446 DRM_DEBUG("psp_spl_version: %u\n", 447 le32_to_cpu(desc->fw_version)); 448 DRM_DEBUG("psp_spl_size_bytes: %u\n", 449 le32_to_cpu(desc->size_bytes)); 450 break; 451 case PSP_FW_TYPE_PSP_RL: 452 DRM_DEBUG("psp_rl_version: %u\n", 453 le32_to_cpu(desc->fw_version)); 454 DRM_DEBUG("psp_rl_size_bytes: %u\n", 455 le32_to_cpu(desc->size_bytes)); 456 break; 457 case PSP_FW_TYPE_PSP_SOC_DRV: 458 DRM_DEBUG("psp_soc_drv_version: %u\n", 459 le32_to_cpu(desc->fw_version)); 460 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", 461 le32_to_cpu(desc->size_bytes)); 462 break; 463 case PSP_FW_TYPE_PSP_INTF_DRV: 464 DRM_DEBUG("psp_intf_drv_version: %u\n", 465 le32_to_cpu(desc->fw_version)); 466 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", 467 le32_to_cpu(desc->size_bytes)); 468 break; 469 case PSP_FW_TYPE_PSP_DBG_DRV: 470 DRM_DEBUG("psp_dbg_drv_version: %u\n", 471 le32_to_cpu(desc->fw_version)); 472 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", 473 le32_to_cpu(desc->size_bytes)); 474 break; 475 case PSP_FW_TYPE_PSP_RAS_DRV: 476 DRM_DEBUG("psp_ras_drv_version: %u\n", 477 le32_to_cpu(desc->fw_version)); 478 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n", 479 le32_to_cpu(desc->size_bytes)); 480 break; 481 default: 482 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); 483 break; 484 } 485 } 486 } else { 487 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 488 version_major, version_minor); 489 } 490 } 491 492 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 493 { 494 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 495 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 496 497 DRM_DEBUG("GPU_INFO\n"); 498 amdgpu_ucode_print_common_hdr(hdr); 499 500 if (version_major == 1) { 501 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 502 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 503 504 DRM_DEBUG("version_major: %u\n", 505 le16_to_cpu(gpu_info_hdr->version_major)); 506 DRM_DEBUG("version_minor: %u\n", 507 le16_to_cpu(gpu_info_hdr->version_minor)); 508 } else { 509 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 510 } 511 } 512 513 static int amdgpu_ucode_validate(const struct firmware *fw) 514 { 515 const struct common_firmware_header *hdr = 516 (const struct common_firmware_header *)fw->data; 517 518 if (fw->size == le32_to_cpu(hdr->size_bytes)) 519 return 0; 520 521 return -EINVAL; 522 } 523 524 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 525 uint16_t hdr_major, uint16_t hdr_minor) 526 { 527 if ((hdr->common.header_version_major == hdr_major) && 528 (hdr->common.header_version_minor == hdr_minor)) 529 return true; 530 return false; 531 } 532 533 enum amdgpu_firmware_load_type 534 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 535 { 536 switch (adev->asic_type) { 537 #ifdef CONFIG_DRM_AMDGPU_SI 538 case CHIP_TAHITI: 539 case CHIP_PITCAIRN: 540 case CHIP_VERDE: 541 case CHIP_OLAND: 542 case CHIP_HAINAN: 543 return AMDGPU_FW_LOAD_DIRECT; 544 #endif 545 #ifdef CONFIG_DRM_AMDGPU_CIK 546 case CHIP_BONAIRE: 547 case CHIP_KAVERI: 548 case CHIP_KABINI: 549 case CHIP_HAWAII: 550 case CHIP_MULLINS: 551 return AMDGPU_FW_LOAD_DIRECT; 552 #endif 553 case CHIP_TOPAZ: 554 case CHIP_TONGA: 555 case CHIP_FIJI: 556 case CHIP_CARRIZO: 557 case CHIP_STONEY: 558 case CHIP_POLARIS10: 559 case CHIP_POLARIS11: 560 case CHIP_POLARIS12: 561 case CHIP_VEGAM: 562 return AMDGPU_FW_LOAD_SMU; 563 case CHIP_CYAN_SKILLFISH: 564 if (!(load_type && 565 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) 566 return AMDGPU_FW_LOAD_DIRECT; 567 else 568 return AMDGPU_FW_LOAD_PSP; 569 default: 570 if (!load_type) 571 return AMDGPU_FW_LOAD_DIRECT; 572 else if (load_type == 3) 573 return AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO; 574 else 575 return AMDGPU_FW_LOAD_PSP; 576 } 577 } 578 579 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 580 { 581 switch (ucode_id) { 582 case AMDGPU_UCODE_ID_SDMA0: 583 return "SDMA0"; 584 case AMDGPU_UCODE_ID_SDMA1: 585 return "SDMA1"; 586 case AMDGPU_UCODE_ID_SDMA2: 587 return "SDMA2"; 588 case AMDGPU_UCODE_ID_SDMA3: 589 return "SDMA3"; 590 case AMDGPU_UCODE_ID_SDMA4: 591 return "SDMA4"; 592 case AMDGPU_UCODE_ID_SDMA5: 593 return "SDMA5"; 594 case AMDGPU_UCODE_ID_SDMA6: 595 return "SDMA6"; 596 case AMDGPU_UCODE_ID_SDMA7: 597 return "SDMA7"; 598 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 599 return "SDMA_CTX"; 600 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 601 return "SDMA_CTL"; 602 case AMDGPU_UCODE_ID_CP_CE: 603 return "CP_CE"; 604 case AMDGPU_UCODE_ID_CP_PFP: 605 return "CP_PFP"; 606 case AMDGPU_UCODE_ID_CP_ME: 607 return "CP_ME"; 608 case AMDGPU_UCODE_ID_CP_MEC1: 609 return "CP_MEC1"; 610 case AMDGPU_UCODE_ID_CP_MEC1_JT: 611 return "CP_MEC1_JT"; 612 case AMDGPU_UCODE_ID_CP_MEC2: 613 return "CP_MEC2"; 614 case AMDGPU_UCODE_ID_CP_MEC2_JT: 615 return "CP_MEC2_JT"; 616 case AMDGPU_UCODE_ID_CP_MES: 617 return "CP_MES"; 618 case AMDGPU_UCODE_ID_CP_MES_DATA: 619 return "CP_MES_DATA"; 620 case AMDGPU_UCODE_ID_CP_MES1: 621 return "CP_MES_KIQ"; 622 case AMDGPU_UCODE_ID_CP_MES1_DATA: 623 return "CP_MES_KIQ_DATA"; 624 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 625 return "RLC_RESTORE_LIST_CNTL"; 626 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 627 return "RLC_RESTORE_LIST_GPM_MEM"; 628 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 629 return "RLC_RESTORE_LIST_SRM_MEM"; 630 case AMDGPU_UCODE_ID_RLC_IRAM: 631 return "RLC_IRAM"; 632 case AMDGPU_UCODE_ID_RLC_DRAM: 633 return "RLC_DRAM"; 634 case AMDGPU_UCODE_ID_RLC_G: 635 return "RLC_G"; 636 case AMDGPU_UCODE_ID_RLC_P: 637 return "RLC_P"; 638 case AMDGPU_UCODE_ID_RLC_V: 639 return "RLC_V"; 640 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 641 return "GLOBAL_TAP_DELAYS"; 642 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 643 return "SE0_TAP_DELAYS"; 644 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 645 return "SE1_TAP_DELAYS"; 646 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 647 return "SE2_TAP_DELAYS"; 648 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 649 return "SE3_TAP_DELAYS"; 650 case AMDGPU_UCODE_ID_IMU_I: 651 return "IMU_I"; 652 case AMDGPU_UCODE_ID_IMU_D: 653 return "IMU_D"; 654 case AMDGPU_UCODE_ID_STORAGE: 655 return "STORAGE"; 656 case AMDGPU_UCODE_ID_SMC: 657 return "SMC"; 658 case AMDGPU_UCODE_ID_PPTABLE: 659 return "PPTABLE"; 660 case AMDGPU_UCODE_ID_P2S_TABLE: 661 return "P2STABLE"; 662 case AMDGPU_UCODE_ID_UVD: 663 return "UVD"; 664 case AMDGPU_UCODE_ID_UVD1: 665 return "UVD1"; 666 case AMDGPU_UCODE_ID_VCE: 667 return "VCE"; 668 case AMDGPU_UCODE_ID_VCN: 669 return "VCN"; 670 case AMDGPU_UCODE_ID_VCN1: 671 return "VCN1"; 672 case AMDGPU_UCODE_ID_DMCU_ERAM: 673 return "DMCU_ERAM"; 674 case AMDGPU_UCODE_ID_DMCU_INTV: 675 return "DMCU_INTV"; 676 case AMDGPU_UCODE_ID_VCN0_RAM: 677 return "VCN0_RAM"; 678 case AMDGPU_UCODE_ID_VCN1_RAM: 679 return "VCN1_RAM"; 680 case AMDGPU_UCODE_ID_DMCUB: 681 return "DMCUB"; 682 case AMDGPU_UCODE_ID_CAP: 683 return "CAP"; 684 case AMDGPU_UCODE_ID_VPE_CTX: 685 return "VPE_CTX"; 686 case AMDGPU_UCODE_ID_VPE_CTL: 687 return "VPE_CTL"; 688 case AMDGPU_UCODE_ID_VPE: 689 return "VPE"; 690 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 691 return "UMSCH_MM_UCODE"; 692 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 693 return "UMSCH_MM_DATA"; 694 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 695 return "UMSCH_MM_CMD_BUFFER"; 696 case AMDGPU_UCODE_ID_JPEG_RAM: 697 return "JPEG"; 698 case AMDGPU_UCODE_ID_SDMA_RS64: 699 return "RS64_SDMA"; 700 case AMDGPU_UCODE_ID_CP_RS64_PFP: 701 return "RS64_PFP"; 702 case AMDGPU_UCODE_ID_CP_RS64_ME: 703 return "RS64_ME"; 704 case AMDGPU_UCODE_ID_CP_RS64_MEC: 705 return "RS64_MEC"; 706 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 707 return "RS64_PFP_P0_STACK"; 708 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 709 return "RS64_PFP_P1_STACK"; 710 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 711 return "RS64_ME_P0_STACK"; 712 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 713 return "RS64_ME_P1_STACK"; 714 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 715 return "RS64_MEC_P0_STACK"; 716 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 717 return "RS64_MEC_P1_STACK"; 718 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 719 return "RS64_MEC_P2_STACK"; 720 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 721 return "RS64_MEC_P3_STACK"; 722 case AMDGPU_UCODE_ID_ISP: 723 return "ISP"; 724 default: 725 return "UNKNOWN UCODE"; 726 } 727 } 728 729 static inline int amdgpu_ucode_is_valid(uint32_t fw_version) 730 { 731 if (!fw_version) 732 return -EINVAL; 733 734 return 0; 735 } 736 737 #define FW_VERSION_ATTR(name, mode, field) \ 738 static ssize_t show_##name(struct device *dev, \ 739 struct device_attribute *attr, char *buf) \ 740 { \ 741 struct drm_device *ddev = dev_get_drvdata(dev); \ 742 struct amdgpu_device *adev = drm_to_adev(ddev); \ 743 \ 744 if (!buf) \ 745 return amdgpu_ucode_is_valid(adev->field); \ 746 \ 747 return sysfs_emit(buf, "0x%08x\n", adev->field); \ 748 } \ 749 static DEVICE_ATTR(name, mode, show_##name, NULL) 750 751 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 752 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 753 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 754 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 755 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 756 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 757 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 758 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 759 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 760 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 761 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 762 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 763 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version); 764 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 765 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); 766 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); 767 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); 768 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 769 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 770 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 771 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 772 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 773 FW_VERSION_ATTR(dmcub_fw_version, 0444, dm.dmcub_fw_version); 774 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK); 775 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK); 776 FW_VERSION_ATTR(pldm_fw_version, 0444, firmware.pldm_version); 777 778 static struct attribute *fw_attrs[] = { 779 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 780 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 781 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 782 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 783 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 784 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 785 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 786 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 787 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 788 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 789 &dev_attr_dmcu_fw_version.attr, &dev_attr_dmcub_fw_version.attr, 790 &dev_attr_imu_fw_version.attr, &dev_attr_mes_fw_version.attr, 791 &dev_attr_mes_kiq_fw_version.attr, &dev_attr_pldm_fw_version.attr, 792 NULL 793 }; 794 795 #define to_dev_attr(x) container_of(x, struct device_attribute, attr) 796 797 static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj, 798 struct attribute *attr, int idx) 799 { 800 struct device_attribute *dev_attr = to_dev_attr(attr); 801 struct device *dev = kobj_to_dev(kobj); 802 803 if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL) 804 return 0; 805 806 return attr->mode; 807 } 808 809 static const struct attribute_group fw_attr_group = { 810 .name = "fw_version", 811 .attrs = fw_attrs, 812 .is_visible = amdgpu_ucode_sys_visible 813 }; 814 815 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 816 { 817 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 818 } 819 820 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 821 { 822 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 823 } 824 825 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 826 struct amdgpu_firmware_info *ucode, 827 uint64_t mc_addr, void *kptr) 828 { 829 const struct common_firmware_header *header = NULL; 830 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 831 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; 832 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 833 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 834 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 835 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; 836 const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL; 837 const struct imu_firmware_header_v1_0 *imu_hdr = NULL; 838 const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL; 839 const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL; 840 u8 *ucode_addr; 841 842 if (!ucode->fw) 843 return 0; 844 845 ucode->mc_addr = mc_addr; 846 ucode->kaddr = kptr; 847 848 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 849 return 0; 850 851 header = (const struct common_firmware_header *)ucode->fw->data; 852 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 853 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; 854 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 855 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 856 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 857 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; 858 sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data; 859 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; 860 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data; 861 umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data; 862 863 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 864 switch (ucode->ucode_id) { 865 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 866 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 867 ucode_addr = (u8 *)ucode->fw->data + 868 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes); 869 break; 870 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 871 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 872 ucode_addr = (u8 *)ucode->fw->data + 873 le32_to_cpu(sdma_hdr->ctl_ucode_offset); 874 break; 875 case AMDGPU_UCODE_ID_SDMA_RS64: 876 ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes); 877 ucode_addr = (u8 *)ucode->fw->data + 878 le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes); 879 break; 880 case AMDGPU_UCODE_ID_CP_MEC1: 881 case AMDGPU_UCODE_ID_CP_MEC2: 882 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 883 le32_to_cpu(cp_hdr->jt_size) * 4; 884 ucode_addr = (u8 *)ucode->fw->data + 885 le32_to_cpu(header->ucode_array_offset_bytes); 886 break; 887 case AMDGPU_UCODE_ID_CP_MEC1_JT: 888 case AMDGPU_UCODE_ID_CP_MEC2_JT: 889 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 890 ucode_addr = (u8 *)ucode->fw->data + 891 le32_to_cpu(header->ucode_array_offset_bytes) + 892 le32_to_cpu(cp_hdr->jt_offset) * 4; 893 break; 894 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 895 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 896 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; 897 break; 898 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 899 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 900 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; 901 break; 902 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 903 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 904 ucode_addr = adev->gfx.rlc.save_restore_list_srm; 905 break; 906 case AMDGPU_UCODE_ID_RLC_IRAM: 907 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 908 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; 909 break; 910 case AMDGPU_UCODE_ID_RLC_DRAM: 911 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 912 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; 913 break; 914 case AMDGPU_UCODE_ID_RLC_P: 915 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; 916 ucode_addr = adev->gfx.rlc.rlcp_ucode; 917 break; 918 case AMDGPU_UCODE_ID_RLC_V: 919 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes; 920 ucode_addr = adev->gfx.rlc.rlcv_ucode; 921 break; 922 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 923 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes; 924 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode; 925 break; 926 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 927 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes; 928 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; 929 break; 930 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 931 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes; 932 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; 933 break; 934 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 935 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes; 936 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; 937 break; 938 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 939 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes; 940 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode; 941 break; 942 case AMDGPU_UCODE_ID_CP_MES: 943 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 944 ucode_addr = (u8 *)ucode->fw->data + 945 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 946 break; 947 case AMDGPU_UCODE_ID_CP_MES_DATA: 948 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 949 ucode_addr = (u8 *)ucode->fw->data + 950 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 951 break; 952 case AMDGPU_UCODE_ID_CP_MES1: 953 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 954 ucode_addr = (u8 *)ucode->fw->data + 955 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 956 break; 957 case AMDGPU_UCODE_ID_CP_MES1_DATA: 958 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 959 ucode_addr = (u8 *)ucode->fw->data + 960 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 961 break; 962 case AMDGPU_UCODE_ID_DMCU_ERAM: 963 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 964 le32_to_cpu(dmcu_hdr->intv_size_bytes); 965 ucode_addr = (u8 *)ucode->fw->data + 966 le32_to_cpu(header->ucode_array_offset_bytes); 967 break; 968 case AMDGPU_UCODE_ID_DMCU_INTV: 969 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 970 ucode_addr = (u8 *)ucode->fw->data + 971 le32_to_cpu(header->ucode_array_offset_bytes) + 972 le32_to_cpu(dmcu_hdr->intv_offset_bytes); 973 break; 974 case AMDGPU_UCODE_ID_DMCUB: 975 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 976 ucode_addr = (u8 *)ucode->fw->data + 977 le32_to_cpu(header->ucode_array_offset_bytes); 978 break; 979 case AMDGPU_UCODE_ID_PPTABLE: 980 ucode->ucode_size = ucode->fw->size; 981 ucode_addr = (u8 *)ucode->fw->data; 982 break; 983 case AMDGPU_UCODE_ID_P2S_TABLE: 984 ucode->ucode_size = ucode->fw->size; 985 ucode_addr = (u8 *)ucode->fw->data; 986 break; 987 case AMDGPU_UCODE_ID_IMU_I: 988 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 989 ucode_addr = (u8 *)ucode->fw->data + 990 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes); 991 break; 992 case AMDGPU_UCODE_ID_IMU_D: 993 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes); 994 ucode_addr = (u8 *)ucode->fw->data + 995 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + 996 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 997 break; 998 case AMDGPU_UCODE_ID_CP_RS64_PFP: 999 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1000 ucode_addr = (u8 *)ucode->fw->data + 1001 le32_to_cpu(header->ucode_array_offset_bytes); 1002 break; 1003 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 1004 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1005 ucode_addr = (u8 *)ucode->fw->data + 1006 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1007 break; 1008 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 1009 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1010 ucode_addr = (u8 *)ucode->fw->data + 1011 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1012 break; 1013 case AMDGPU_UCODE_ID_CP_RS64_ME: 1014 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1015 ucode_addr = (u8 *)ucode->fw->data + 1016 le32_to_cpu(header->ucode_array_offset_bytes); 1017 break; 1018 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 1019 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1020 ucode_addr = (u8 *)ucode->fw->data + 1021 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1022 break; 1023 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 1024 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1025 ucode_addr = (u8 *)ucode->fw->data + 1026 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1027 break; 1028 case AMDGPU_UCODE_ID_CP_RS64_MEC: 1029 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1030 ucode_addr = (u8 *)ucode->fw->data + 1031 le32_to_cpu(header->ucode_array_offset_bytes); 1032 break; 1033 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 1034 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1035 ucode_addr = (u8 *)ucode->fw->data + 1036 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1037 break; 1038 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 1039 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1040 ucode_addr = (u8 *)ucode->fw->data + 1041 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1042 break; 1043 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 1044 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1045 ucode_addr = (u8 *)ucode->fw->data + 1046 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1047 break; 1048 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 1049 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1050 ucode_addr = (u8 *)ucode->fw->data + 1051 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1052 break; 1053 case AMDGPU_UCODE_ID_VPE_CTX: 1054 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); 1055 ucode_addr = (u8 *)ucode->fw->data + 1056 le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); 1057 break; 1058 case AMDGPU_UCODE_ID_VPE_CTL: 1059 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); 1060 ucode_addr = (u8 *)ucode->fw->data + 1061 le32_to_cpu(vpe_hdr->ctl_ucode_offset); 1062 break; 1063 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 1064 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes); 1065 ucode_addr = (u8 *)ucode->fw->data + 1066 le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes); 1067 break; 1068 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 1069 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes); 1070 ucode_addr = (u8 *)ucode->fw->data + 1071 le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes); 1072 break; 1073 default: 1074 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1075 ucode_addr = (u8 *)ucode->fw->data + 1076 le32_to_cpu(header->ucode_array_offset_bytes); 1077 break; 1078 } 1079 } else { 1080 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1081 ucode_addr = (u8 *)ucode->fw->data + 1082 le32_to_cpu(header->ucode_array_offset_bytes); 1083 } 1084 1085 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); 1086 1087 return 0; 1088 } 1089 1090 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 1091 uint64_t mc_addr, void *kptr) 1092 { 1093 const struct gfx_firmware_header_v1_0 *header = NULL; 1094 const struct common_firmware_header *comm_hdr = NULL; 1095 uint8_t *src_addr = NULL; 1096 uint8_t *dst_addr = NULL; 1097 1098 if (!ucode->fw) 1099 return 0; 1100 1101 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 1102 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1103 dst_addr = ucode->kaddr + 1104 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 1105 PAGE_SIZE); 1106 src_addr = (uint8_t *)ucode->fw->data + 1107 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 1108 (le32_to_cpu(header->jt_offset) * 4); 1109 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 1110 1111 return 0; 1112 } 1113 1114 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 1115 { 1116 if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && 1117 (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { 1118 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 1119 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 1120 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 1121 &adev->firmware.fw_buf, 1122 &adev->firmware.fw_buf_mc, 1123 &adev->firmware.fw_buf_ptr); 1124 if (!adev->firmware.fw_buf) { 1125 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 1126 return -ENOMEM; 1127 } else if (amdgpu_sriov_vf(adev)) { 1128 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 1129 } 1130 } 1131 return 0; 1132 } 1133 1134 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 1135 { 1136 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 1137 &adev->firmware.fw_buf_mc, 1138 &adev->firmware.fw_buf_ptr); 1139 } 1140 1141 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 1142 { 1143 uint64_t fw_offset = 0; 1144 int i; 1145 struct amdgpu_firmware_info *ucode = NULL; 1146 1147 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 1148 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 1149 return 0; 1150 /* 1151 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 1152 * ucode info here 1153 */ 1154 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1155 if (amdgpu_sriov_vf(adev)) 1156 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 1157 else 1158 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 1159 } else { 1160 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 1161 } 1162 1163 if (amdgpu_virt_xgmi_migrate_enabled(adev) && adev->firmware.fw_buf) 1164 adev->firmware.fw_buf_mc = amdgpu_bo_fb_aper_addr(adev->firmware.fw_buf); 1165 1166 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1167 ucode = &adev->firmware.ucode[i]; 1168 if (ucode->fw) { 1169 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 1170 adev->firmware.fw_buf_ptr + fw_offset); 1171 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 1172 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1173 const struct gfx_firmware_header_v1_0 *cp_hdr; 1174 1175 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1176 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 1177 adev->firmware.fw_buf_ptr + fw_offset); 1178 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1179 } 1180 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 1181 } 1182 } 1183 return 0; 1184 } 1185 1186 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) 1187 { 1188 if (block_type == MP0_HWIP) { 1189 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1190 case IP_VERSION(9, 0, 0): 1191 switch (adev->asic_type) { 1192 case CHIP_VEGA10: 1193 return "vega10"; 1194 case CHIP_VEGA12: 1195 return "vega12"; 1196 default: 1197 return NULL; 1198 } 1199 case IP_VERSION(10, 0, 0): 1200 case IP_VERSION(10, 0, 1): 1201 if (adev->asic_type == CHIP_RAVEN) { 1202 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1203 return "raven2"; 1204 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1205 return "picasso"; 1206 return "raven"; 1207 } 1208 break; 1209 case IP_VERSION(11, 0, 0): 1210 return "navi10"; 1211 case IP_VERSION(11, 0, 2): 1212 return "vega20"; 1213 case IP_VERSION(11, 0, 3): 1214 return "renoir"; 1215 case IP_VERSION(11, 0, 4): 1216 return "arcturus"; 1217 case IP_VERSION(11, 0, 5): 1218 return "navi14"; 1219 case IP_VERSION(11, 0, 7): 1220 return "sienna_cichlid"; 1221 case IP_VERSION(11, 0, 9): 1222 return "navi12"; 1223 case IP_VERSION(11, 0, 11): 1224 return "navy_flounder"; 1225 case IP_VERSION(11, 0, 12): 1226 return "dimgrey_cavefish"; 1227 case IP_VERSION(11, 0, 13): 1228 return "beige_goby"; 1229 case IP_VERSION(11, 5, 0): 1230 case IP_VERSION(11, 5, 2): 1231 return "vangogh"; 1232 case IP_VERSION(12, 0, 1): 1233 return "green_sardine"; 1234 case IP_VERSION(13, 0, 2): 1235 return "aldebaran"; 1236 case IP_VERSION(13, 0, 1): 1237 case IP_VERSION(13, 0, 3): 1238 return "yellow_carp"; 1239 } 1240 } else if (block_type == MP1_HWIP) { 1241 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1242 case IP_VERSION(9, 0, 0): 1243 case IP_VERSION(10, 0, 0): 1244 case IP_VERSION(10, 0, 1): 1245 case IP_VERSION(11, 0, 2): 1246 if (adev->asic_type == CHIP_ARCTURUS) 1247 return "arcturus_smc"; 1248 return NULL; 1249 case IP_VERSION(11, 0, 0): 1250 return "navi10_smc"; 1251 case IP_VERSION(11, 0, 5): 1252 return "navi14_smc"; 1253 case IP_VERSION(11, 0, 9): 1254 return "navi12_smc"; 1255 case IP_VERSION(11, 0, 7): 1256 return "sienna_cichlid_smc"; 1257 case IP_VERSION(11, 0, 11): 1258 return "navy_flounder_smc"; 1259 case IP_VERSION(11, 0, 12): 1260 return "dimgrey_cavefish_smc"; 1261 case IP_VERSION(11, 0, 13): 1262 return "beige_goby_smc"; 1263 case IP_VERSION(13, 0, 2): 1264 return "aldebaran_smc"; 1265 } 1266 } else if (block_type == SDMA0_HWIP) { 1267 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1268 case IP_VERSION(4, 0, 0): 1269 return "vega10_sdma"; 1270 case IP_VERSION(4, 0, 1): 1271 return "vega12_sdma"; 1272 case IP_VERSION(4, 1, 0): 1273 case IP_VERSION(4, 1, 1): 1274 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1275 return "raven2_sdma"; 1276 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1277 return "picasso_sdma"; 1278 return "raven_sdma"; 1279 case IP_VERSION(4, 1, 2): 1280 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1281 return "renoir_sdma"; 1282 return "green_sardine_sdma"; 1283 case IP_VERSION(4, 2, 0): 1284 return "vega20_sdma"; 1285 case IP_VERSION(4, 2, 2): 1286 return "arcturus_sdma"; 1287 case IP_VERSION(4, 4, 0): 1288 return "aldebaran_sdma"; 1289 case IP_VERSION(5, 0, 0): 1290 return "navi10_sdma"; 1291 case IP_VERSION(5, 0, 1): 1292 return "cyan_skillfish2_sdma"; 1293 case IP_VERSION(5, 0, 2): 1294 return "navi14_sdma"; 1295 case IP_VERSION(5, 0, 5): 1296 return "navi12_sdma"; 1297 case IP_VERSION(5, 2, 0): 1298 return "sienna_cichlid_sdma"; 1299 case IP_VERSION(5, 2, 2): 1300 return "navy_flounder_sdma"; 1301 case IP_VERSION(5, 2, 4): 1302 return "dimgrey_cavefish_sdma"; 1303 case IP_VERSION(5, 2, 5): 1304 return "beige_goby_sdma"; 1305 case IP_VERSION(5, 2, 3): 1306 return "yellow_carp_sdma"; 1307 case IP_VERSION(5, 2, 1): 1308 return "vangogh_sdma"; 1309 } 1310 } else if (block_type == UVD_HWIP) { 1311 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 1312 case IP_VERSION(1, 0, 0): 1313 case IP_VERSION(1, 0, 1): 1314 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1315 return "raven2_vcn"; 1316 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1317 return "picasso_vcn"; 1318 return "raven_vcn"; 1319 case IP_VERSION(2, 5, 0): 1320 return "arcturus_vcn"; 1321 case IP_VERSION(2, 2, 0): 1322 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1323 return "renoir_vcn"; 1324 return "green_sardine_vcn"; 1325 case IP_VERSION(2, 6, 0): 1326 return "aldebaran_vcn"; 1327 case IP_VERSION(2, 0, 0): 1328 return "navi10_vcn"; 1329 case IP_VERSION(2, 0, 2): 1330 if (adev->asic_type == CHIP_NAVI12) 1331 return "navi12_vcn"; 1332 return "navi14_vcn"; 1333 case IP_VERSION(3, 0, 0): 1334 case IP_VERSION(3, 0, 64): 1335 case IP_VERSION(3, 0, 192): 1336 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 1337 IP_VERSION(10, 3, 0)) 1338 return "sienna_cichlid_vcn"; 1339 return "navy_flounder_vcn"; 1340 case IP_VERSION(3, 0, 2): 1341 return "vangogh_vcn"; 1342 case IP_VERSION(3, 0, 16): 1343 return "dimgrey_cavefish_vcn"; 1344 case IP_VERSION(3, 0, 33): 1345 return "beige_goby_vcn"; 1346 case IP_VERSION(3, 1, 1): 1347 return "yellow_carp_vcn"; 1348 } 1349 } else if (block_type == GC_HWIP) { 1350 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1351 case IP_VERSION(9, 0, 1): 1352 return "vega10"; 1353 case IP_VERSION(9, 2, 1): 1354 return "vega12"; 1355 case IP_VERSION(9, 4, 0): 1356 return "vega20"; 1357 case IP_VERSION(9, 2, 2): 1358 case IP_VERSION(9, 1, 0): 1359 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1360 return "raven2"; 1361 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1362 return "picasso"; 1363 return "raven"; 1364 case IP_VERSION(9, 4, 1): 1365 return "arcturus"; 1366 case IP_VERSION(9, 3, 0): 1367 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1368 return "renoir"; 1369 return "green_sardine"; 1370 case IP_VERSION(9, 4, 2): 1371 return "aldebaran"; 1372 case IP_VERSION(10, 1, 10): 1373 return "navi10"; 1374 case IP_VERSION(10, 1, 1): 1375 return "navi14"; 1376 case IP_VERSION(10, 1, 2): 1377 return "navi12"; 1378 case IP_VERSION(10, 3, 0): 1379 return "sienna_cichlid"; 1380 case IP_VERSION(10, 3, 2): 1381 return "navy_flounder"; 1382 case IP_VERSION(10, 3, 1): 1383 return "vangogh"; 1384 case IP_VERSION(10, 3, 4): 1385 return "dimgrey_cavefish"; 1386 case IP_VERSION(10, 3, 5): 1387 return "beige_goby"; 1388 case IP_VERSION(10, 3, 3): 1389 return "yellow_carp"; 1390 case IP_VERSION(10, 1, 3): 1391 case IP_VERSION(10, 1, 4): 1392 return "cyan_skillfish2"; 1393 } 1394 } 1395 return NULL; 1396 } 1397 1398 bool amdgpu_is_kicker_fw(struct amdgpu_device *adev) 1399 { 1400 int i; 1401 1402 for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) { 1403 if (adev->pdev->device == kicker_device_list[i].device && 1404 adev->pdev->revision == kicker_device_list[i].revision) 1405 return true; 1406 } 1407 1408 return false; 1409 } 1410 1411 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) 1412 { 1413 int maj, min, rev; 1414 char *ip_name; 1415 const char *legacy; 1416 uint32_t version = amdgpu_ip_version(adev, block_type, 0); 1417 1418 legacy = amdgpu_ucode_legacy_naming(adev, block_type); 1419 if (legacy) { 1420 snprintf(ucode_prefix, len, "%s", legacy); 1421 return; 1422 } 1423 1424 switch (block_type) { 1425 case GC_HWIP: 1426 ip_name = "gc"; 1427 break; 1428 case SDMA0_HWIP: 1429 ip_name = "sdma"; 1430 break; 1431 case MP0_HWIP: 1432 ip_name = "psp"; 1433 break; 1434 case MP1_HWIP: 1435 ip_name = "smu"; 1436 break; 1437 case UVD_HWIP: 1438 ip_name = "vcn"; 1439 break; 1440 case VPE_HWIP: 1441 ip_name = "vpe"; 1442 break; 1443 case ISP_HWIP: 1444 ip_name = "isp"; 1445 break; 1446 default: 1447 BUG(); 1448 } 1449 1450 maj = IP_VERSION_MAJ(version); 1451 min = IP_VERSION_MIN(version); 1452 rev = IP_VERSION_REV(version); 1453 1454 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); 1455 } 1456 1457 /* 1458 * amdgpu_ucode_request - Fetch and validate amdgpu microcode 1459 * 1460 * @adev: amdgpu device 1461 * @fw: pointer to load firmware to 1462 * @required: whether the firmware is required 1463 * @fmt: firmware name format string 1464 * @...: variable arguments 1465 * 1466 * This is a helper that will use request_firmware and amdgpu_ucode_validate 1467 * to load and run basic validation on firmware. If the load fails, remap 1468 * the error code to -ENODEV, so that early_init functions will fail to load. 1469 */ 1470 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 1471 enum amdgpu_ucode_required required, const char *fmt, ...) 1472 { 1473 char fname[AMDGPU_UCODE_NAME_MAX]; 1474 va_list ap; 1475 int r; 1476 1477 va_start(ap, fmt); 1478 r = vsnprintf(fname, sizeof(fname), fmt, ap); 1479 va_end(ap); 1480 if (r == sizeof(fname)) { 1481 dev_warn(adev->dev, "amdgpu firmware name buffer overflow\n"); 1482 return -EOVERFLOW; 1483 } 1484 1485 if (required == AMDGPU_UCODE_REQUIRED) 1486 r = request_firmware(fw, fname, adev->dev); 1487 else { 1488 r = firmware_request_nowarn(fw, fname, adev->dev); 1489 if (r) 1490 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fname); 1491 } 1492 if (r) 1493 return -ENODEV; 1494 1495 r = amdgpu_ucode_validate(*fw); 1496 if (r) 1497 /* 1498 * The amdgpu_ucode_request() should be paired with amdgpu_ucode_release() 1499 * regardless of success/failure, and the amdgpu_ucode_release() takes care of 1500 * firmware release and need to avoid redundant release FW operation here. 1501 */ 1502 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fname); 1503 1504 return r; 1505 } 1506 1507 /* 1508 * amdgpu_ucode_release - Release firmware microcode 1509 * 1510 * @fw: pointer to firmware to release 1511 */ 1512 void amdgpu_ucode_release(const struct firmware **fw) 1513 { 1514 release_firmware(*fw); 1515 *fw = NULL; 1516 } 1517