1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 #define AMDGPU_UCODE_NAME_MAX (128) 32 33 static const struct kicker_device kicker_device_list[] = { 34 {0x744B, 0x00}, 35 {0x7551, 0xC8} 36 }; 37 38 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 39 { 40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 42 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 43 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 44 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 45 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 48 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 49 le32_to_cpu(hdr->ucode_array_offset_bytes)); 50 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 51 } 52 53 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 54 { 55 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 56 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 57 58 DRM_DEBUG("MC\n"); 59 amdgpu_ucode_print_common_hdr(hdr); 60 61 if (version_major == 1) { 62 const struct mc_firmware_header_v1_0 *mc_hdr = 63 container_of(hdr, struct mc_firmware_header_v1_0, header); 64 65 DRM_DEBUG("io_debug_size_bytes: %u\n", 66 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 67 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 68 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 69 } else { 70 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 71 } 72 } 73 74 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 75 { 76 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 77 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 78 const struct smc_firmware_header_v1_0 *v1_0_hdr; 79 const struct smc_firmware_header_v2_0 *v2_0_hdr; 80 const struct smc_firmware_header_v2_1 *v2_1_hdr; 81 82 DRM_DEBUG("SMC\n"); 83 amdgpu_ucode_print_common_hdr(hdr); 84 85 if (version_major == 1) { 86 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 87 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 88 } else if (version_major == 2) { 89 switch (version_minor) { 90 case 0: 91 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 92 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 93 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 94 break; 95 case 1: 96 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 97 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 98 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 99 break; 100 default: 101 break; 102 } 103 104 } else { 105 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 106 } 107 } 108 109 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 110 { 111 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 112 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 113 114 DRM_DEBUG("GFX\n"); 115 amdgpu_ucode_print_common_hdr(hdr); 116 117 if (version_major == 1) { 118 const struct gfx_firmware_header_v1_0 *gfx_hdr = 119 container_of(hdr, struct gfx_firmware_header_v1_0, header); 120 121 DRM_DEBUG("ucode_feature_version: %u\n", 122 le32_to_cpu(gfx_hdr->ucode_feature_version)); 123 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 124 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 125 } else if (version_major == 2) { 126 const struct gfx_firmware_header_v2_0 *gfx_hdr = 127 container_of(hdr, struct gfx_firmware_header_v2_0, header); 128 129 DRM_DEBUG("ucode_feature_version: %u\n", 130 le32_to_cpu(gfx_hdr->ucode_feature_version)); 131 } else { 132 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 133 } 134 } 135 136 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 137 { 138 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 139 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 140 141 DRM_DEBUG("RLC\n"); 142 amdgpu_ucode_print_common_hdr(hdr); 143 144 if (version_major == 1) { 145 const struct rlc_firmware_header_v1_0 *rlc_hdr = 146 container_of(hdr, struct rlc_firmware_header_v1_0, header); 147 148 DRM_DEBUG("ucode_feature_version: %u\n", 149 le32_to_cpu(rlc_hdr->ucode_feature_version)); 150 DRM_DEBUG("save_and_restore_offset: %u\n", 151 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 152 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 153 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 154 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 155 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 156 DRM_DEBUG("master_pkt_description_offset: %u\n", 157 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 158 } else if (version_major == 2) { 159 const struct rlc_firmware_header_v2_0 *rlc_hdr = 160 container_of(hdr, struct rlc_firmware_header_v2_0, header); 161 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = 162 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 163 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = 164 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); 165 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = 166 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); 167 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = 168 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); 169 const struct rlc_firmware_header_v2_5 *rlc_hdr_v2_5 = 170 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_5, v2_2); 171 172 switch (version_minor) { 173 case 0: 174 /* rlc_hdr v2_0 */ 175 DRM_DEBUG("ucode_feature_version: %u\n", 176 le32_to_cpu(rlc_hdr->ucode_feature_version)); 177 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 178 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 179 DRM_DEBUG("save_and_restore_offset: %u\n", 180 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 181 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 182 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 183 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 184 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 185 DRM_DEBUG("reg_restore_list_size: %u\n", 186 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 187 DRM_DEBUG("reg_list_format_start: %u\n", 188 le32_to_cpu(rlc_hdr->reg_list_format_start)); 189 DRM_DEBUG("reg_list_format_separate_start: %u\n", 190 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 191 DRM_DEBUG("starting_offsets_start: %u\n", 192 le32_to_cpu(rlc_hdr->starting_offsets_start)); 193 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 194 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 195 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 196 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 197 DRM_DEBUG("reg_list_size_bytes: %u\n", 198 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 199 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 200 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 201 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 202 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 203 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 204 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 205 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 206 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 207 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 208 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 209 break; 210 case 1: 211 /* rlc_hdr v2_1 */ 212 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 213 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); 214 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 215 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); 216 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 217 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); 218 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 219 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); 220 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 221 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); 222 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 223 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); 224 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 225 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); 226 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 227 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); 228 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 229 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); 230 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 231 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); 232 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 233 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); 234 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 235 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); 236 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 237 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); 238 break; 239 case 2: 240 /* rlc_hdr v2_2 */ 241 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", 242 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); 243 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", 244 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); 245 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", 246 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); 247 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", 248 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); 249 break; 250 case 3: 251 /* rlc_hdr v2_3 */ 252 DRM_DEBUG("rlcp_ucode_version: %u\n", 253 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); 254 DRM_DEBUG("rlcp_ucode_feature_version: %u\n", 255 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); 256 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", 257 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); 258 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", 259 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); 260 DRM_DEBUG("rlcv_ucode_version: %u\n", 261 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); 262 DRM_DEBUG("rlcv_ucode_feature_version: %u\n", 263 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); 264 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", 265 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); 266 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", 267 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); 268 break; 269 case 4: 270 /* rlc_hdr v2_4 */ 271 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", 272 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); 273 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", 274 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); 275 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", 276 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); 277 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", 278 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); 279 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", 280 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); 281 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", 282 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); 283 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", 284 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); 285 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", 286 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); 287 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", 288 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); 289 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", 290 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); 291 break; 292 case 5: 293 /* rlc_hdr v2_5 */ 294 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", 295 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_size_bytes)); 296 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", 297 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_offset_bytes)); 298 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", 299 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_size_bytes)); 300 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", 301 le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_offset_bytes)); 302 /* rlc_hdr v2_5 */ 303 DRM_DEBUG("rlc_1_iram_ucode_size_bytes: %u\n", 304 le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_size_bytes)); 305 DRM_DEBUG("rlc_1_iram_ucode_offset_bytes: %u\n", 306 le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_offset_bytes)); 307 DRM_DEBUG("rlc_1_dram_ucode_size_bytes: %u\n", 308 le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_size_bytes)); 309 DRM_DEBUG("rlc_1_dram_ucode_offset_bytes: %u\n", 310 le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_offset_bytes)); 311 break; 312 default: 313 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); 314 break; 315 } 316 } else { 317 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 318 } 319 } 320 321 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 322 { 323 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 324 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 325 326 DRM_DEBUG("SDMA\n"); 327 amdgpu_ucode_print_common_hdr(hdr); 328 329 if (version_major == 1) { 330 const struct sdma_firmware_header_v1_0 *sdma_hdr = 331 container_of(hdr, struct sdma_firmware_header_v1_0, header); 332 333 DRM_DEBUG("ucode_feature_version: %u\n", 334 le32_to_cpu(sdma_hdr->ucode_feature_version)); 335 DRM_DEBUG("ucode_change_version: %u\n", 336 le32_to_cpu(sdma_hdr->ucode_change_version)); 337 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 338 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 339 if (version_minor >= 1) { 340 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 341 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 342 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 343 } 344 } else if (version_major == 2) { 345 const struct sdma_firmware_header_v2_0 *sdma_hdr = 346 container_of(hdr, struct sdma_firmware_header_v2_0, header); 347 348 DRM_DEBUG("ucode_feature_version: %u\n", 349 le32_to_cpu(sdma_hdr->ucode_feature_version)); 350 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); 351 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); 352 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 353 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); 354 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); 355 } else if (version_major == 3) { 356 const struct sdma_firmware_header_v3_0 *sdma_hdr = 357 container_of(hdr, struct sdma_firmware_header_v3_0, header); 358 359 DRM_DEBUG("ucode_reversion: %u\n", 360 le32_to_cpu(sdma_hdr->ucode_feature_version)); 361 } else { 362 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 363 version_major, version_minor); 364 } 365 } 366 367 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 368 { 369 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 370 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 371 uint32_t fw_index; 372 const struct psp_fw_bin_desc *desc; 373 374 DRM_DEBUG("PSP\n"); 375 amdgpu_ucode_print_common_hdr(hdr); 376 377 if (version_major == 1) { 378 const struct psp_firmware_header_v1_0 *psp_hdr = 379 container_of(hdr, struct psp_firmware_header_v1_0, header); 380 381 DRM_DEBUG("ucode_feature_version: %u\n", 382 le32_to_cpu(psp_hdr->sos.fw_version)); 383 DRM_DEBUG("sos_offset_bytes: %u\n", 384 le32_to_cpu(psp_hdr->sos.offset_bytes)); 385 DRM_DEBUG("sos_size_bytes: %u\n", 386 le32_to_cpu(psp_hdr->sos.size_bytes)); 387 if (version_minor == 1) { 388 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 389 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 390 DRM_DEBUG("toc_header_version: %u\n", 391 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 392 DRM_DEBUG("toc_offset_bytes: %u\n", 393 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 394 DRM_DEBUG("toc_size_bytes: %u\n", 395 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 396 DRM_DEBUG("kdb_header_version: %u\n", 397 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 398 DRM_DEBUG("kdb_offset_bytes: %u\n", 399 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 400 DRM_DEBUG("kdb_size_bytes: %u\n", 401 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 402 } 403 if (version_minor == 2) { 404 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 405 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 406 DRM_DEBUG("kdb_header_version: %u\n", 407 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 408 DRM_DEBUG("kdb_offset_bytes: %u\n", 409 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 410 DRM_DEBUG("kdb_size_bytes: %u\n", 411 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 412 } 413 if (version_minor == 3) { 414 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 415 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 416 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 417 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 418 DRM_DEBUG("toc_header_version: %u\n", 419 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 420 DRM_DEBUG("toc_offset_bytes: %u\n", 421 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 422 DRM_DEBUG("toc_size_bytes: %u\n", 423 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 424 DRM_DEBUG("kdb_header_version: %u\n", 425 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 426 DRM_DEBUG("kdb_offset_bytes: %u\n", 427 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 428 DRM_DEBUG("kdb_size_bytes: %u\n", 429 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 430 DRM_DEBUG("spl_header_version: %u\n", 431 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 432 DRM_DEBUG("spl_offset_bytes: %u\n", 433 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 434 DRM_DEBUG("spl_size_bytes: %u\n", 435 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 436 } 437 } else if (version_major == 2) { 438 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = 439 container_of(hdr, struct psp_firmware_header_v2_0, header); 440 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { 441 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); 442 switch (desc->fw_type) { 443 case PSP_FW_TYPE_PSP_SOS: 444 DRM_DEBUG("psp_sos_version: %u\n", 445 le32_to_cpu(desc->fw_version)); 446 DRM_DEBUG("psp_sos_size_bytes: %u\n", 447 le32_to_cpu(desc->size_bytes)); 448 break; 449 case PSP_FW_TYPE_PSP_SYS_DRV: 450 DRM_DEBUG("psp_sys_drv_version: %u\n", 451 le32_to_cpu(desc->fw_version)); 452 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", 453 le32_to_cpu(desc->size_bytes)); 454 break; 455 case PSP_FW_TYPE_PSP_KDB: 456 DRM_DEBUG("psp_kdb_version: %u\n", 457 le32_to_cpu(desc->fw_version)); 458 DRM_DEBUG("psp_kdb_size_bytes: %u\n", 459 le32_to_cpu(desc->size_bytes)); 460 break; 461 case PSP_FW_TYPE_PSP_TOC: 462 DRM_DEBUG("psp_toc_version: %u\n", 463 le32_to_cpu(desc->fw_version)); 464 DRM_DEBUG("psp_toc_size_bytes: %u\n", 465 le32_to_cpu(desc->size_bytes)); 466 break; 467 case PSP_FW_TYPE_PSP_SPL: 468 DRM_DEBUG("psp_spl_version: %u\n", 469 le32_to_cpu(desc->fw_version)); 470 DRM_DEBUG("psp_spl_size_bytes: %u\n", 471 le32_to_cpu(desc->size_bytes)); 472 break; 473 case PSP_FW_TYPE_PSP_RL: 474 DRM_DEBUG("psp_rl_version: %u\n", 475 le32_to_cpu(desc->fw_version)); 476 DRM_DEBUG("psp_rl_size_bytes: %u\n", 477 le32_to_cpu(desc->size_bytes)); 478 break; 479 case PSP_FW_TYPE_PSP_SOC_DRV: 480 DRM_DEBUG("psp_soc_drv_version: %u\n", 481 le32_to_cpu(desc->fw_version)); 482 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", 483 le32_to_cpu(desc->size_bytes)); 484 break; 485 case PSP_FW_TYPE_PSP_INTF_DRV: 486 DRM_DEBUG("psp_intf_drv_version: %u\n", 487 le32_to_cpu(desc->fw_version)); 488 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", 489 le32_to_cpu(desc->size_bytes)); 490 break; 491 case PSP_FW_TYPE_PSP_DBG_DRV: 492 DRM_DEBUG("psp_dbg_drv_version: %u\n", 493 le32_to_cpu(desc->fw_version)); 494 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", 495 le32_to_cpu(desc->size_bytes)); 496 break; 497 case PSP_FW_TYPE_PSP_RAS_DRV: 498 DRM_DEBUG("psp_ras_drv_version: %u\n", 499 le32_to_cpu(desc->fw_version)); 500 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n", 501 le32_to_cpu(desc->size_bytes)); 502 break; 503 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 504 DRM_DEBUG("psp_ipkeymgr_drv_version: %u\n", 505 le32_to_cpu(desc->fw_version)); 506 DRM_DEBUG("psp_ipkeymgr_drv_size_bytes: %u\n", 507 le32_to_cpu(desc->size_bytes)); 508 break; 509 default: 510 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); 511 break; 512 } 513 } 514 } else { 515 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 516 version_major, version_minor); 517 } 518 } 519 520 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 521 { 522 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 523 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 524 525 DRM_DEBUG("GPU_INFO\n"); 526 amdgpu_ucode_print_common_hdr(hdr); 527 528 if (version_major == 1) { 529 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 530 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 531 532 DRM_DEBUG("version_major: %u\n", 533 le16_to_cpu(gpu_info_hdr->version_major)); 534 DRM_DEBUG("version_minor: %u\n", 535 le16_to_cpu(gpu_info_hdr->version_minor)); 536 } else { 537 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 538 } 539 } 540 541 static int amdgpu_ucode_validate(const struct firmware *fw) 542 { 543 const struct common_firmware_header *hdr = 544 (const struct common_firmware_header *)fw->data; 545 546 if (fw->size == le32_to_cpu(hdr->size_bytes)) 547 return 0; 548 549 return -EINVAL; 550 } 551 552 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 553 uint16_t hdr_major, uint16_t hdr_minor) 554 { 555 if ((hdr->common.header_version_major == hdr_major) && 556 (hdr->common.header_version_minor == hdr_minor)) 557 return true; 558 return false; 559 } 560 561 enum amdgpu_firmware_load_type 562 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 563 { 564 switch (adev->asic_type) { 565 #ifdef CONFIG_DRM_AMDGPU_SI 566 case CHIP_TAHITI: 567 case CHIP_PITCAIRN: 568 case CHIP_VERDE: 569 case CHIP_OLAND: 570 case CHIP_HAINAN: 571 return AMDGPU_FW_LOAD_DIRECT; 572 #endif 573 #ifdef CONFIG_DRM_AMDGPU_CIK 574 case CHIP_BONAIRE: 575 case CHIP_KAVERI: 576 case CHIP_KABINI: 577 case CHIP_HAWAII: 578 case CHIP_MULLINS: 579 return AMDGPU_FW_LOAD_DIRECT; 580 #endif 581 case CHIP_TOPAZ: 582 case CHIP_TONGA: 583 case CHIP_FIJI: 584 case CHIP_CARRIZO: 585 case CHIP_STONEY: 586 case CHIP_POLARIS10: 587 case CHIP_POLARIS11: 588 case CHIP_POLARIS12: 589 case CHIP_VEGAM: 590 return AMDGPU_FW_LOAD_SMU; 591 case CHIP_CYAN_SKILLFISH: 592 if (!(load_type && 593 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) 594 return AMDGPU_FW_LOAD_DIRECT; 595 else 596 return AMDGPU_FW_LOAD_PSP; 597 default: 598 if (!load_type) 599 return AMDGPU_FW_LOAD_DIRECT; 600 else if (load_type == 3) 601 return AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO; 602 else 603 return AMDGPU_FW_LOAD_PSP; 604 } 605 } 606 607 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 608 { 609 switch (ucode_id) { 610 case AMDGPU_UCODE_ID_SDMA0: 611 return "SDMA0"; 612 case AMDGPU_UCODE_ID_SDMA1: 613 return "SDMA1"; 614 case AMDGPU_UCODE_ID_SDMA2: 615 return "SDMA2"; 616 case AMDGPU_UCODE_ID_SDMA3: 617 return "SDMA3"; 618 case AMDGPU_UCODE_ID_SDMA4: 619 return "SDMA4"; 620 case AMDGPU_UCODE_ID_SDMA5: 621 return "SDMA5"; 622 case AMDGPU_UCODE_ID_SDMA6: 623 return "SDMA6"; 624 case AMDGPU_UCODE_ID_SDMA7: 625 return "SDMA7"; 626 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 627 return "SDMA_CTX"; 628 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 629 return "SDMA_CTL"; 630 case AMDGPU_UCODE_ID_CP_CE: 631 return "CP_CE"; 632 case AMDGPU_UCODE_ID_CP_PFP: 633 return "CP_PFP"; 634 case AMDGPU_UCODE_ID_CP_ME: 635 return "CP_ME"; 636 case AMDGPU_UCODE_ID_CP_MEC1: 637 return "CP_MEC1"; 638 case AMDGPU_UCODE_ID_CP_MEC1_JT: 639 return "CP_MEC1_JT"; 640 case AMDGPU_UCODE_ID_CP_MEC2: 641 return "CP_MEC2"; 642 case AMDGPU_UCODE_ID_CP_MEC2_JT: 643 return "CP_MEC2_JT"; 644 case AMDGPU_UCODE_ID_CP_MES: 645 return "CP_MES"; 646 case AMDGPU_UCODE_ID_CP_MES_DATA: 647 return "CP_MES_DATA"; 648 case AMDGPU_UCODE_ID_CP_MES1: 649 return "CP_MES_KIQ"; 650 case AMDGPU_UCODE_ID_CP_MES1_DATA: 651 return "CP_MES_KIQ_DATA"; 652 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 653 return "RLC_RESTORE_LIST_CNTL"; 654 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 655 return "RLC_RESTORE_LIST_GPM_MEM"; 656 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 657 return "RLC_RESTORE_LIST_SRM_MEM"; 658 case AMDGPU_UCODE_ID_RLC_IRAM: 659 return "RLC_IRAM"; 660 case AMDGPU_UCODE_ID_RLC_DRAM: 661 return "RLC_DRAM"; 662 case AMDGPU_UCODE_ID_RLC_IRAM_1: 663 return "RLC_IRAM_1"; 664 case AMDGPU_UCODE_ID_RLC_DRAM_1: 665 return "RLC_DRAM_1"; 666 case AMDGPU_UCODE_ID_RLC_G: 667 return "RLC_G"; 668 case AMDGPU_UCODE_ID_RLC_P: 669 return "RLC_P"; 670 case AMDGPU_UCODE_ID_RLC_V: 671 return "RLC_V"; 672 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 673 return "GLOBAL_TAP_DELAYS"; 674 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 675 return "SE0_TAP_DELAYS"; 676 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 677 return "SE1_TAP_DELAYS"; 678 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 679 return "SE2_TAP_DELAYS"; 680 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 681 return "SE3_TAP_DELAYS"; 682 case AMDGPU_UCODE_ID_IMU_I: 683 return "IMU_I"; 684 case AMDGPU_UCODE_ID_IMU_D: 685 return "IMU_D"; 686 case AMDGPU_UCODE_ID_STORAGE: 687 return "STORAGE"; 688 case AMDGPU_UCODE_ID_SMC: 689 return "SMC"; 690 case AMDGPU_UCODE_ID_PPTABLE: 691 return "PPTABLE"; 692 case AMDGPU_UCODE_ID_P2S_TABLE: 693 return "P2STABLE"; 694 case AMDGPU_UCODE_ID_UVD: 695 return "UVD"; 696 case AMDGPU_UCODE_ID_UVD1: 697 return "UVD1"; 698 case AMDGPU_UCODE_ID_VCE: 699 return "VCE"; 700 case AMDGPU_UCODE_ID_VCN: 701 return "VCN"; 702 case AMDGPU_UCODE_ID_VCN1: 703 return "VCN1"; 704 case AMDGPU_UCODE_ID_DMCU_ERAM: 705 return "DMCU_ERAM"; 706 case AMDGPU_UCODE_ID_DMCU_INTV: 707 return "DMCU_INTV"; 708 case AMDGPU_UCODE_ID_VCN0_RAM: 709 return "VCN0_RAM"; 710 case AMDGPU_UCODE_ID_VCN1_RAM: 711 return "VCN1_RAM"; 712 case AMDGPU_UCODE_ID_DMCUB: 713 return "DMCUB"; 714 case AMDGPU_UCODE_ID_CAP: 715 return "CAP"; 716 case AMDGPU_UCODE_ID_VPE_CTX: 717 return "VPE_CTX"; 718 case AMDGPU_UCODE_ID_VPE_CTL: 719 return "VPE_CTL"; 720 case AMDGPU_UCODE_ID_VPE: 721 return "VPE"; 722 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 723 return "UMSCH_MM_UCODE"; 724 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 725 return "UMSCH_MM_DATA"; 726 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 727 return "UMSCH_MM_CMD_BUFFER"; 728 case AMDGPU_UCODE_ID_JPEG_RAM: 729 return "JPEG"; 730 case AMDGPU_UCODE_ID_SDMA_RS64: 731 return "RS64_SDMA"; 732 case AMDGPU_UCODE_ID_CP_RS64_PFP: 733 return "RS64_PFP"; 734 case AMDGPU_UCODE_ID_CP_RS64_ME: 735 return "RS64_ME"; 736 case AMDGPU_UCODE_ID_CP_RS64_MEC: 737 return "RS64_MEC"; 738 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 739 return "RS64_PFP_P0_STACK"; 740 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 741 return "RS64_PFP_P1_STACK"; 742 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 743 return "RS64_ME_P0_STACK"; 744 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 745 return "RS64_ME_P1_STACK"; 746 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 747 return "RS64_MEC_P0_STACK"; 748 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 749 return "RS64_MEC_P1_STACK"; 750 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 751 return "RS64_MEC_P2_STACK"; 752 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 753 return "RS64_MEC_P3_STACK"; 754 case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: 755 return "RS64_MEC_P4_STACK"; 756 case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: 757 return "RS64_MEC_P5_STACK"; 758 case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: 759 return "RS64_MEC_P6_STACK"; 760 case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: 761 return "RS64_MEC_P7_STACK"; 762 case AMDGPU_UCODE_ID_ISP: 763 return "ISP"; 764 case AMDGPU_UCODE_ID_MP5: 765 return "MP5"; 766 default: 767 return "UNKNOWN UCODE"; 768 } 769 } 770 771 static inline int amdgpu_ucode_is_valid(uint32_t fw_version) 772 { 773 if (!fw_version) 774 return -EINVAL; 775 776 return 0; 777 } 778 779 #define FW_VERSION_ATTR(name, mode, field) \ 780 static ssize_t show_##name(struct device *dev, \ 781 struct device_attribute *attr, char *buf) \ 782 { \ 783 struct drm_device *ddev = dev_get_drvdata(dev); \ 784 struct amdgpu_device *adev = drm_to_adev(ddev); \ 785 \ 786 if (!buf) \ 787 return amdgpu_ucode_is_valid(adev->field); \ 788 \ 789 return sysfs_emit(buf, "0x%08x\n", adev->field); \ 790 } \ 791 static DEVICE_ATTR(name, mode, show_##name, NULL) 792 793 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 794 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 795 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 796 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 797 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 798 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 799 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 800 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 801 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 802 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 803 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 804 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 805 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version); 806 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 807 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); 808 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); 809 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); 810 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 811 FW_VERSION_ATTR(mp5_fw_version, 0444, pm.mp5_fw_version); 812 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 813 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 814 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 815 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 816 FW_VERSION_ATTR(dmcub_fw_version, 0444, dm.dmcub_fw_version); 817 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK); 818 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK); 819 FW_VERSION_ATTR(pldm_fw_version, 0444, firmware.pldm_version); 820 821 static struct attribute *fw_attrs[] = { 822 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 823 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 824 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 825 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 826 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 827 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 828 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 829 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 830 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 831 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 832 &dev_attr_dmcu_fw_version.attr, &dev_attr_dmcub_fw_version.attr, 833 &dev_attr_imu_fw_version.attr, &dev_attr_mes_fw_version.attr, 834 &dev_attr_mes_kiq_fw_version.attr, &dev_attr_pldm_fw_version.attr, 835 &dev_attr_mp5_fw_version.attr, 836 NULL 837 }; 838 839 #define to_dev_attr(x) container_of(x, struct device_attribute, attr) 840 841 static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj, 842 struct attribute *attr, int idx) 843 { 844 struct device_attribute *dev_attr = to_dev_attr(attr); 845 struct device *dev = kobj_to_dev(kobj); 846 847 if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL) 848 return 0; 849 850 return attr->mode; 851 } 852 853 static const struct attribute_group fw_attr_group = { 854 .name = "fw_version", 855 .attrs = fw_attrs, 856 .is_visible = amdgpu_ucode_sys_visible 857 }; 858 859 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 860 { 861 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 862 } 863 864 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 865 { 866 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 867 } 868 869 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 870 struct amdgpu_firmware_info *ucode, 871 uint64_t mc_addr, void *kptr) 872 { 873 const struct common_firmware_header *header = NULL; 874 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 875 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; 876 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 877 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 878 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 879 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; 880 const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL; 881 const struct imu_firmware_header_v1_0 *imu_hdr = NULL; 882 const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL; 883 const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL; 884 u8 *ucode_addr; 885 886 if (!ucode->fw) 887 return 0; 888 889 ucode->mc_addr = mc_addr; 890 ucode->kaddr = kptr; 891 892 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 893 return 0; 894 895 header = (const struct common_firmware_header *)ucode->fw->data; 896 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 897 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; 898 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 899 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 900 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 901 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; 902 sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data; 903 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; 904 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data; 905 umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data; 906 907 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 908 switch (ucode->ucode_id) { 909 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 910 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 911 ucode_addr = (u8 *)ucode->fw->data + 912 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes); 913 break; 914 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 915 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 916 ucode_addr = (u8 *)ucode->fw->data + 917 le32_to_cpu(sdma_hdr->ctl_ucode_offset); 918 break; 919 case AMDGPU_UCODE_ID_SDMA_RS64: 920 ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes); 921 ucode_addr = (u8 *)ucode->fw->data + 922 le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes); 923 break; 924 case AMDGPU_UCODE_ID_CP_MEC1: 925 case AMDGPU_UCODE_ID_CP_MEC2: 926 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 927 le32_to_cpu(cp_hdr->jt_size) * 4; 928 ucode_addr = (u8 *)ucode->fw->data + 929 le32_to_cpu(header->ucode_array_offset_bytes); 930 break; 931 case AMDGPU_UCODE_ID_CP_MEC1_JT: 932 case AMDGPU_UCODE_ID_CP_MEC2_JT: 933 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 934 ucode_addr = (u8 *)ucode->fw->data + 935 le32_to_cpu(header->ucode_array_offset_bytes) + 936 le32_to_cpu(cp_hdr->jt_offset) * 4; 937 break; 938 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 939 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 940 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; 941 break; 942 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 943 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 944 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; 945 break; 946 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 947 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 948 ucode_addr = adev->gfx.rlc.save_restore_list_srm; 949 break; 950 case AMDGPU_UCODE_ID_RLC_IRAM: 951 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 952 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; 953 break; 954 case AMDGPU_UCODE_ID_RLC_DRAM: 955 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 956 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; 957 break; 958 case AMDGPU_UCODE_ID_RLC_IRAM_1: 959 ucode->ucode_size = adev->gfx.rlc.rlc_1_iram_ucode_size_bytes; 960 ucode_addr = adev->gfx.rlc.rlc_1_iram_ucode; 961 break; 962 case AMDGPU_UCODE_ID_RLC_DRAM_1: 963 ucode->ucode_size = adev->gfx.rlc.rlc_1_dram_ucode_size_bytes; 964 ucode_addr = adev->gfx.rlc.rlc_1_dram_ucode; 965 break; 966 case AMDGPU_UCODE_ID_RLC_P: 967 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; 968 ucode_addr = adev->gfx.rlc.rlcp_ucode; 969 break; 970 case AMDGPU_UCODE_ID_RLC_V: 971 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes; 972 ucode_addr = adev->gfx.rlc.rlcv_ucode; 973 break; 974 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 975 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes; 976 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode; 977 break; 978 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 979 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes; 980 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; 981 break; 982 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 983 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes; 984 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; 985 break; 986 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 987 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes; 988 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; 989 break; 990 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 991 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes; 992 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode; 993 break; 994 case AMDGPU_UCODE_ID_CP_MES: 995 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 996 ucode_addr = (u8 *)ucode->fw->data + 997 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 998 break; 999 case AMDGPU_UCODE_ID_CP_MES_DATA: 1000 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1001 ucode_addr = (u8 *)ucode->fw->data + 1002 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 1003 break; 1004 case AMDGPU_UCODE_ID_CP_MES1: 1005 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1006 ucode_addr = (u8 *)ucode->fw->data + 1007 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 1008 break; 1009 case AMDGPU_UCODE_ID_CP_MES1_DATA: 1010 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1011 ucode_addr = (u8 *)ucode->fw->data + 1012 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 1013 break; 1014 case AMDGPU_UCODE_ID_DMCU_ERAM: 1015 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 1016 le32_to_cpu(dmcu_hdr->intv_size_bytes); 1017 ucode_addr = (u8 *)ucode->fw->data + 1018 le32_to_cpu(header->ucode_array_offset_bytes); 1019 break; 1020 case AMDGPU_UCODE_ID_DMCU_INTV: 1021 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 1022 ucode_addr = (u8 *)ucode->fw->data + 1023 le32_to_cpu(header->ucode_array_offset_bytes) + 1024 le32_to_cpu(dmcu_hdr->intv_offset_bytes); 1025 break; 1026 case AMDGPU_UCODE_ID_DMCUB: 1027 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 1028 ucode_addr = (u8 *)ucode->fw->data + 1029 le32_to_cpu(header->ucode_array_offset_bytes); 1030 break; 1031 case AMDGPU_UCODE_ID_PPTABLE: 1032 ucode->ucode_size = ucode->fw->size; 1033 ucode_addr = (u8 *)ucode->fw->data; 1034 break; 1035 case AMDGPU_UCODE_ID_P2S_TABLE: 1036 ucode->ucode_size = ucode->fw->size; 1037 ucode_addr = (u8 *)ucode->fw->data; 1038 break; 1039 case AMDGPU_UCODE_ID_IMU_I: 1040 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 1041 ucode_addr = (u8 *)ucode->fw->data + 1042 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes); 1043 break; 1044 case AMDGPU_UCODE_ID_IMU_D: 1045 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes); 1046 ucode_addr = (u8 *)ucode->fw->data + 1047 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + 1048 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 1049 break; 1050 case AMDGPU_UCODE_ID_CP_RS64_PFP: 1051 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1052 ucode_addr = (u8 *)ucode->fw->data + 1053 le32_to_cpu(header->ucode_array_offset_bytes); 1054 break; 1055 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 1056 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1057 ucode_addr = (u8 *)ucode->fw->data + 1058 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1059 break; 1060 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 1061 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1062 ucode_addr = (u8 *)ucode->fw->data + 1063 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1064 break; 1065 case AMDGPU_UCODE_ID_CP_RS64_ME: 1066 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1067 ucode_addr = (u8 *)ucode->fw->data + 1068 le32_to_cpu(header->ucode_array_offset_bytes); 1069 break; 1070 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 1071 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1072 ucode_addr = (u8 *)ucode->fw->data + 1073 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1074 break; 1075 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 1076 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1077 ucode_addr = (u8 *)ucode->fw->data + 1078 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1079 break; 1080 case AMDGPU_UCODE_ID_CP_RS64_MEC: 1081 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1082 ucode_addr = (u8 *)ucode->fw->data + 1083 le32_to_cpu(header->ucode_array_offset_bytes); 1084 break; 1085 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 1086 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1087 ucode_addr = (u8 *)ucode->fw->data + 1088 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1089 break; 1090 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 1091 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1092 ucode_addr = (u8 *)ucode->fw->data + 1093 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1094 break; 1095 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 1096 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1097 ucode_addr = (u8 *)ucode->fw->data + 1098 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1099 break; 1100 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 1101 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1102 ucode_addr = (u8 *)ucode->fw->data + 1103 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1104 break; 1105 case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: 1106 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1107 ucode_addr = (u8 *)ucode->fw->data + 1108 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1109 break; 1110 case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: 1111 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1112 ucode_addr = (u8 *)ucode->fw->data + 1113 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1114 break; 1115 case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: 1116 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1117 ucode_addr = (u8 *)ucode->fw->data + 1118 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1119 break; 1120 case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: 1121 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1122 ucode_addr = (u8 *)ucode->fw->data + 1123 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1124 break; 1125 case AMDGPU_UCODE_ID_VPE_CTX: 1126 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); 1127 ucode_addr = (u8 *)ucode->fw->data + 1128 le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); 1129 break; 1130 case AMDGPU_UCODE_ID_VPE_CTL: 1131 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); 1132 ucode_addr = (u8 *)ucode->fw->data + 1133 le32_to_cpu(vpe_hdr->ctl_ucode_offset); 1134 break; 1135 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 1136 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes); 1137 ucode_addr = (u8 *)ucode->fw->data + 1138 le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes); 1139 break; 1140 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 1141 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes); 1142 ucode_addr = (u8 *)ucode->fw->data + 1143 le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes); 1144 break; 1145 default: 1146 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1147 ucode_addr = (u8 *)ucode->fw->data + 1148 le32_to_cpu(header->ucode_array_offset_bytes); 1149 break; 1150 } 1151 } else { 1152 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1153 ucode_addr = (u8 *)ucode->fw->data + 1154 le32_to_cpu(header->ucode_array_offset_bytes); 1155 } 1156 1157 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); 1158 1159 return 0; 1160 } 1161 1162 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 1163 uint64_t mc_addr, void *kptr) 1164 { 1165 const struct gfx_firmware_header_v1_0 *header = NULL; 1166 const struct common_firmware_header *comm_hdr = NULL; 1167 uint8_t *src_addr = NULL; 1168 uint8_t *dst_addr = NULL; 1169 1170 if (!ucode->fw) 1171 return 0; 1172 1173 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 1174 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1175 dst_addr = ucode->kaddr + 1176 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 1177 PAGE_SIZE); 1178 src_addr = (uint8_t *)ucode->fw->data + 1179 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 1180 (le32_to_cpu(header->jt_offset) * 4); 1181 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 1182 1183 return 0; 1184 } 1185 1186 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 1187 { 1188 if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && 1189 (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { 1190 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 1191 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 1192 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 1193 &adev->firmware.fw_buf, 1194 &adev->firmware.fw_buf_mc, 1195 &adev->firmware.fw_buf_ptr); 1196 if (!adev->firmware.fw_buf) { 1197 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 1198 return -ENOMEM; 1199 } else if (amdgpu_sriov_vf(adev)) { 1200 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 1201 } 1202 } 1203 return 0; 1204 } 1205 1206 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 1207 { 1208 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 1209 &adev->firmware.fw_buf_mc, 1210 &adev->firmware.fw_buf_ptr); 1211 } 1212 1213 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 1214 { 1215 uint64_t fw_offset = 0; 1216 int i; 1217 struct amdgpu_firmware_info *ucode = NULL; 1218 1219 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 1220 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 1221 return 0; 1222 /* 1223 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 1224 * ucode info here 1225 */ 1226 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1227 if (amdgpu_sriov_vf(adev)) 1228 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 1229 else 1230 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 1231 } else { 1232 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 1233 } 1234 1235 if (amdgpu_virt_xgmi_migrate_enabled(adev) && adev->firmware.fw_buf) 1236 adev->firmware.fw_buf_mc = amdgpu_bo_fb_aper_addr(adev->firmware.fw_buf); 1237 1238 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1239 ucode = &adev->firmware.ucode[i]; 1240 if (ucode->fw) { 1241 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 1242 adev->firmware.fw_buf_ptr + fw_offset); 1243 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 1244 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1245 const struct gfx_firmware_header_v1_0 *cp_hdr; 1246 1247 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1248 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 1249 adev->firmware.fw_buf_ptr + fw_offset); 1250 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1251 } 1252 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 1253 } 1254 } 1255 return 0; 1256 } 1257 1258 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) 1259 { 1260 if (block_type == MP0_HWIP) { 1261 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1262 case IP_VERSION(9, 0, 0): 1263 switch (adev->asic_type) { 1264 case CHIP_VEGA10: 1265 return "vega10"; 1266 case CHIP_VEGA12: 1267 return "vega12"; 1268 default: 1269 return NULL; 1270 } 1271 case IP_VERSION(10, 0, 0): 1272 case IP_VERSION(10, 0, 1): 1273 if (adev->asic_type == CHIP_RAVEN) { 1274 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1275 return "raven2"; 1276 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1277 return "picasso"; 1278 return "raven"; 1279 } 1280 break; 1281 case IP_VERSION(11, 0, 0): 1282 return "navi10"; 1283 case IP_VERSION(11, 0, 2): 1284 return "vega20"; 1285 case IP_VERSION(11, 0, 3): 1286 return "renoir"; 1287 case IP_VERSION(11, 0, 4): 1288 return "arcturus"; 1289 case IP_VERSION(11, 0, 5): 1290 return "navi14"; 1291 case IP_VERSION(11, 0, 7): 1292 return "sienna_cichlid"; 1293 case IP_VERSION(11, 0, 9): 1294 return "navi12"; 1295 case IP_VERSION(11, 0, 11): 1296 return "navy_flounder"; 1297 case IP_VERSION(11, 0, 12): 1298 return "dimgrey_cavefish"; 1299 case IP_VERSION(11, 0, 13): 1300 return "beige_goby"; 1301 case IP_VERSION(11, 5, 0): 1302 case IP_VERSION(11, 5, 2): 1303 return "vangogh"; 1304 case IP_VERSION(12, 0, 1): 1305 return "green_sardine"; 1306 case IP_VERSION(13, 0, 2): 1307 return "aldebaran"; 1308 case IP_VERSION(13, 0, 1): 1309 case IP_VERSION(13, 0, 3): 1310 return "yellow_carp"; 1311 } 1312 } else if (block_type == MP1_HWIP) { 1313 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1314 case IP_VERSION(9, 0, 0): 1315 case IP_VERSION(10, 0, 0): 1316 case IP_VERSION(10, 0, 1): 1317 case IP_VERSION(11, 0, 2): 1318 if (adev->asic_type == CHIP_ARCTURUS) 1319 return "arcturus_smc"; 1320 return NULL; 1321 case IP_VERSION(11, 0, 0): 1322 return "navi10_smc"; 1323 case IP_VERSION(11, 0, 5): 1324 return "navi14_smc"; 1325 case IP_VERSION(11, 0, 9): 1326 return "navi12_smc"; 1327 case IP_VERSION(11, 0, 7): 1328 return "sienna_cichlid_smc"; 1329 case IP_VERSION(11, 0, 11): 1330 return "navy_flounder_smc"; 1331 case IP_VERSION(11, 0, 12): 1332 return "dimgrey_cavefish_smc"; 1333 case IP_VERSION(11, 0, 13): 1334 return "beige_goby_smc"; 1335 case IP_VERSION(13, 0, 2): 1336 return "aldebaran_smc"; 1337 } 1338 } else if (block_type == SDMA0_HWIP) { 1339 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1340 case IP_VERSION(4, 0, 0): 1341 return "vega10_sdma"; 1342 case IP_VERSION(4, 0, 1): 1343 return "vega12_sdma"; 1344 case IP_VERSION(4, 1, 0): 1345 case IP_VERSION(4, 1, 1): 1346 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1347 return "raven2_sdma"; 1348 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1349 return "picasso_sdma"; 1350 return "raven_sdma"; 1351 case IP_VERSION(4, 1, 2): 1352 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1353 return "renoir_sdma"; 1354 return "green_sardine_sdma"; 1355 case IP_VERSION(4, 2, 0): 1356 return "vega20_sdma"; 1357 case IP_VERSION(4, 2, 2): 1358 return "arcturus_sdma"; 1359 case IP_VERSION(4, 4, 0): 1360 return "aldebaran_sdma"; 1361 case IP_VERSION(5, 0, 0): 1362 return "navi10_sdma"; 1363 case IP_VERSION(5, 0, 1): 1364 return "cyan_skillfish2_sdma"; 1365 case IP_VERSION(5, 0, 2): 1366 return "navi14_sdma"; 1367 case IP_VERSION(5, 0, 5): 1368 return "navi12_sdma"; 1369 case IP_VERSION(5, 2, 0): 1370 return "sienna_cichlid_sdma"; 1371 case IP_VERSION(5, 2, 2): 1372 return "navy_flounder_sdma"; 1373 case IP_VERSION(5, 2, 4): 1374 return "dimgrey_cavefish_sdma"; 1375 case IP_VERSION(5, 2, 5): 1376 return "beige_goby_sdma"; 1377 case IP_VERSION(5, 2, 3): 1378 return "yellow_carp_sdma"; 1379 case IP_VERSION(5, 2, 1): 1380 return "vangogh_sdma"; 1381 } 1382 } else if (block_type == UVD_HWIP) { 1383 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 1384 case IP_VERSION(1, 0, 0): 1385 case IP_VERSION(1, 0, 1): 1386 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1387 return "raven2_vcn"; 1388 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1389 return "picasso_vcn"; 1390 return "raven_vcn"; 1391 case IP_VERSION(2, 5, 0): 1392 return "arcturus_vcn"; 1393 case IP_VERSION(2, 2, 0): 1394 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1395 return "renoir_vcn"; 1396 return "green_sardine_vcn"; 1397 case IP_VERSION(2, 6, 0): 1398 return "aldebaran_vcn"; 1399 case IP_VERSION(2, 0, 0): 1400 return "navi10_vcn"; 1401 case IP_VERSION(2, 0, 2): 1402 if (adev->asic_type == CHIP_NAVI12) 1403 return "navi12_vcn"; 1404 return "navi14_vcn"; 1405 case IP_VERSION(3, 0, 0): 1406 case IP_VERSION(3, 0, 64): 1407 case IP_VERSION(3, 0, 192): 1408 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 1409 IP_VERSION(10, 3, 0)) 1410 return "sienna_cichlid_vcn"; 1411 return "navy_flounder_vcn"; 1412 case IP_VERSION(3, 0, 2): 1413 return "vangogh_vcn"; 1414 case IP_VERSION(3, 0, 16): 1415 return "dimgrey_cavefish_vcn"; 1416 case IP_VERSION(3, 0, 33): 1417 return "beige_goby_vcn"; 1418 case IP_VERSION(3, 1, 1): 1419 return "yellow_carp_vcn"; 1420 } 1421 } else if (block_type == GC_HWIP) { 1422 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1423 case IP_VERSION(9, 0, 1): 1424 return "vega10"; 1425 case IP_VERSION(9, 2, 1): 1426 return "vega12"; 1427 case IP_VERSION(9, 4, 0): 1428 return "vega20"; 1429 case IP_VERSION(9, 2, 2): 1430 case IP_VERSION(9, 1, 0): 1431 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1432 return "raven2"; 1433 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1434 return "picasso"; 1435 return "raven"; 1436 case IP_VERSION(9, 4, 1): 1437 return "arcturus"; 1438 case IP_VERSION(9, 3, 0): 1439 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1440 return "renoir"; 1441 return "green_sardine"; 1442 case IP_VERSION(9, 4, 2): 1443 return "aldebaran"; 1444 case IP_VERSION(10, 1, 10): 1445 return "navi10"; 1446 case IP_VERSION(10, 1, 1): 1447 return "navi14"; 1448 case IP_VERSION(10, 1, 2): 1449 return "navi12"; 1450 case IP_VERSION(10, 3, 0): 1451 return "sienna_cichlid"; 1452 case IP_VERSION(10, 3, 2): 1453 return "navy_flounder"; 1454 case IP_VERSION(10, 3, 1): 1455 return "vangogh"; 1456 case IP_VERSION(10, 3, 4): 1457 return "dimgrey_cavefish"; 1458 case IP_VERSION(10, 3, 5): 1459 return "beige_goby"; 1460 case IP_VERSION(10, 3, 3): 1461 return "yellow_carp"; 1462 case IP_VERSION(10, 1, 3): 1463 case IP_VERSION(10, 1, 4): 1464 return "cyan_skillfish2"; 1465 } 1466 } 1467 return NULL; 1468 } 1469 1470 bool amdgpu_is_kicker_fw(struct amdgpu_device *adev) 1471 { 1472 int i; 1473 1474 for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) { 1475 if (adev->pdev->device == kicker_device_list[i].device && 1476 adev->pdev->revision == kicker_device_list[i].revision) 1477 return true; 1478 } 1479 1480 return false; 1481 } 1482 1483 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) 1484 { 1485 int maj, min, rev; 1486 char *ip_name; 1487 const char *legacy; 1488 uint32_t version = amdgpu_ip_version(adev, block_type, 0); 1489 1490 legacy = amdgpu_ucode_legacy_naming(adev, block_type); 1491 if (legacy) { 1492 snprintf(ucode_prefix, len, "%s", legacy); 1493 return; 1494 } 1495 1496 switch (block_type) { 1497 case GC_HWIP: 1498 ip_name = "gc"; 1499 break; 1500 case SDMA0_HWIP: 1501 ip_name = "sdma"; 1502 break; 1503 case MP0_HWIP: 1504 ip_name = "psp"; 1505 break; 1506 case MP1_HWIP: 1507 ip_name = "smu"; 1508 break; 1509 case UVD_HWIP: 1510 ip_name = "vcn"; 1511 break; 1512 case VPE_HWIP: 1513 ip_name = "vpe"; 1514 break; 1515 case ISP_HWIP: 1516 ip_name = "isp"; 1517 break; 1518 default: 1519 WARN(1, "invalid HWIP %d\n", block_type); 1520 return; 1521 } 1522 1523 maj = IP_VERSION_MAJ(version); 1524 min = IP_VERSION_MIN(version); 1525 rev = IP_VERSION_REV(version); 1526 1527 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); 1528 } 1529 1530 /* 1531 * amdgpu_ucode_request - Fetch and validate amdgpu microcode 1532 * 1533 * @adev: amdgpu device 1534 * @fw: pointer to load firmware to 1535 * @required: whether the firmware is required 1536 * @fmt: firmware name format string 1537 * @...: variable arguments 1538 * 1539 * This is a helper that will use request_firmware and amdgpu_ucode_validate 1540 * to load and run basic validation on firmware. If the load fails, remap 1541 * the error code to -ENODEV, so that early_init functions will fail to load. 1542 */ 1543 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 1544 enum amdgpu_ucode_required required, const char *fmt, ...) 1545 { 1546 char fname[AMDGPU_UCODE_NAME_MAX]; 1547 va_list ap; 1548 int r; 1549 1550 va_start(ap, fmt); 1551 r = vsnprintf(fname, sizeof(fname), fmt, ap); 1552 va_end(ap); 1553 if (r == sizeof(fname)) { 1554 dev_warn(adev->dev, "amdgpu firmware name buffer overflow\n"); 1555 return -EOVERFLOW; 1556 } 1557 1558 if (required == AMDGPU_UCODE_REQUIRED) 1559 r = request_firmware(fw, fname, adev->dev); 1560 else { 1561 r = firmware_request_nowarn(fw, fname, adev->dev); 1562 if (r) 1563 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fname); 1564 } 1565 if (r) 1566 return -ENODEV; 1567 1568 r = amdgpu_ucode_validate(*fw); 1569 if (r) 1570 /* 1571 * The amdgpu_ucode_request() should be paired with amdgpu_ucode_release() 1572 * regardless of success/failure, and the amdgpu_ucode_release() takes care of 1573 * firmware release and need to avoid redundant release FW operation here. 1574 */ 1575 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fname); 1576 1577 return r; 1578 } 1579 1580 /* 1581 * amdgpu_ucode_release - Release firmware microcode 1582 * 1583 * @fw: pointer to firmware to release 1584 */ 1585 void amdgpu_ucode_release(const struct firmware **fw) 1586 { 1587 release_firmware(*fw); 1588 *fw = NULL; 1589 } 1590