1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 31 #define AMDGPU_UCODE_NAME_MAX (128) 32 33 static const struct kicker_device kicker_device_list[] = { 34 {0x744B, 0x00}, 35 }; 36 37 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 38 { 39 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 40 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 41 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 42 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 43 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 44 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 45 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 46 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 47 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 48 le32_to_cpu(hdr->ucode_array_offset_bytes)); 49 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 50 } 51 52 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 53 { 54 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 55 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 56 57 DRM_DEBUG("MC\n"); 58 amdgpu_ucode_print_common_hdr(hdr); 59 60 if (version_major == 1) { 61 const struct mc_firmware_header_v1_0 *mc_hdr = 62 container_of(hdr, struct mc_firmware_header_v1_0, header); 63 64 DRM_DEBUG("io_debug_size_bytes: %u\n", 65 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 66 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 67 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 68 } else { 69 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 70 } 71 } 72 73 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 74 { 75 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 76 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 77 const struct smc_firmware_header_v1_0 *v1_0_hdr; 78 const struct smc_firmware_header_v2_0 *v2_0_hdr; 79 const struct smc_firmware_header_v2_1 *v2_1_hdr; 80 81 DRM_DEBUG("SMC\n"); 82 amdgpu_ucode_print_common_hdr(hdr); 83 84 if (version_major == 1) { 85 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); 86 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); 87 } else if (version_major == 2) { 88 switch (version_minor) { 89 case 0: 90 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); 91 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); 92 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); 93 break; 94 case 1: 95 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); 96 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); 97 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); 98 break; 99 default: 100 break; 101 } 102 103 } else { 104 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 105 } 106 } 107 108 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 109 { 110 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 111 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 112 113 DRM_DEBUG("GFX\n"); 114 amdgpu_ucode_print_common_hdr(hdr); 115 116 if (version_major == 1) { 117 const struct gfx_firmware_header_v1_0 *gfx_hdr = 118 container_of(hdr, struct gfx_firmware_header_v1_0, header); 119 120 DRM_DEBUG("ucode_feature_version: %u\n", 121 le32_to_cpu(gfx_hdr->ucode_feature_version)); 122 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 123 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 124 } else if (version_major == 2) { 125 const struct gfx_firmware_header_v2_0 *gfx_hdr = 126 container_of(hdr, struct gfx_firmware_header_v2_0, header); 127 128 DRM_DEBUG("ucode_feature_version: %u\n", 129 le32_to_cpu(gfx_hdr->ucode_feature_version)); 130 } else { 131 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 132 } 133 } 134 135 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 136 { 137 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 138 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 139 140 DRM_DEBUG("RLC\n"); 141 amdgpu_ucode_print_common_hdr(hdr); 142 143 if (version_major == 1) { 144 const struct rlc_firmware_header_v1_0 *rlc_hdr = 145 container_of(hdr, struct rlc_firmware_header_v1_0, header); 146 147 DRM_DEBUG("ucode_feature_version: %u\n", 148 le32_to_cpu(rlc_hdr->ucode_feature_version)); 149 DRM_DEBUG("save_and_restore_offset: %u\n", 150 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 151 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 152 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 153 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 154 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 155 DRM_DEBUG("master_pkt_description_offset: %u\n", 156 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 157 } else if (version_major == 2) { 158 const struct rlc_firmware_header_v2_0 *rlc_hdr = 159 container_of(hdr, struct rlc_firmware_header_v2_0, header); 160 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = 161 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 162 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = 163 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); 164 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = 165 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); 166 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = 167 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); 168 169 switch (version_minor) { 170 case 0: 171 /* rlc_hdr v2_0 */ 172 DRM_DEBUG("ucode_feature_version: %u\n", 173 le32_to_cpu(rlc_hdr->ucode_feature_version)); 174 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 175 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 176 DRM_DEBUG("save_and_restore_offset: %u\n", 177 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 178 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 179 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 180 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 181 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 182 DRM_DEBUG("reg_restore_list_size: %u\n", 183 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 184 DRM_DEBUG("reg_list_format_start: %u\n", 185 le32_to_cpu(rlc_hdr->reg_list_format_start)); 186 DRM_DEBUG("reg_list_format_separate_start: %u\n", 187 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 188 DRM_DEBUG("starting_offsets_start: %u\n", 189 le32_to_cpu(rlc_hdr->starting_offsets_start)); 190 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 191 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 192 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 193 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 194 DRM_DEBUG("reg_list_size_bytes: %u\n", 195 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 196 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 197 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 198 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 199 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 200 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 201 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 202 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 203 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 204 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 205 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 206 break; 207 case 1: 208 /* rlc_hdr v2_1 */ 209 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 210 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); 211 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 212 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); 213 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 214 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); 215 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 216 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); 217 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 218 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); 219 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 220 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); 221 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 222 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); 223 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 224 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); 225 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 226 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); 227 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 228 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); 229 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 230 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); 231 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 232 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); 233 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 234 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); 235 break; 236 case 2: 237 /* rlc_hdr v2_2 */ 238 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", 239 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); 240 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", 241 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); 242 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", 243 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); 244 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", 245 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); 246 break; 247 case 3: 248 /* rlc_hdr v2_3 */ 249 DRM_DEBUG("rlcp_ucode_version: %u\n", 250 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); 251 DRM_DEBUG("rlcp_ucode_feature_version: %u\n", 252 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); 253 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", 254 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); 255 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", 256 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); 257 DRM_DEBUG("rlcv_ucode_version: %u\n", 258 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); 259 DRM_DEBUG("rlcv_ucode_feature_version: %u\n", 260 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); 261 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", 262 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); 263 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", 264 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); 265 break; 266 case 4: 267 /* rlc_hdr v2_4 */ 268 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", 269 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); 270 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", 271 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); 272 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", 273 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); 274 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", 275 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); 276 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", 277 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); 278 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", 279 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); 280 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", 281 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); 282 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", 283 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); 284 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", 285 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); 286 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", 287 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); 288 break; 289 default: 290 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); 291 break; 292 } 293 } else { 294 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 295 } 296 } 297 298 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 299 { 300 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 301 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 302 303 DRM_DEBUG("SDMA\n"); 304 amdgpu_ucode_print_common_hdr(hdr); 305 306 if (version_major == 1) { 307 const struct sdma_firmware_header_v1_0 *sdma_hdr = 308 container_of(hdr, struct sdma_firmware_header_v1_0, header); 309 310 DRM_DEBUG("ucode_feature_version: %u\n", 311 le32_to_cpu(sdma_hdr->ucode_feature_version)); 312 DRM_DEBUG("ucode_change_version: %u\n", 313 le32_to_cpu(sdma_hdr->ucode_change_version)); 314 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 315 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 316 if (version_minor >= 1) { 317 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 318 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 319 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 320 } 321 } else if (version_major == 2) { 322 const struct sdma_firmware_header_v2_0 *sdma_hdr = 323 container_of(hdr, struct sdma_firmware_header_v2_0, header); 324 325 DRM_DEBUG("ucode_feature_version: %u\n", 326 le32_to_cpu(sdma_hdr->ucode_feature_version)); 327 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); 328 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); 329 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 330 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); 331 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); 332 } else if (version_major == 3) { 333 const struct sdma_firmware_header_v3_0 *sdma_hdr = 334 container_of(hdr, struct sdma_firmware_header_v3_0, header); 335 336 DRM_DEBUG("ucode_reversion: %u\n", 337 le32_to_cpu(sdma_hdr->ucode_feature_version)); 338 } else { 339 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 340 version_major, version_minor); 341 } 342 } 343 344 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 345 { 346 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 347 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 348 uint32_t fw_index; 349 const struct psp_fw_bin_desc *desc; 350 351 DRM_DEBUG("PSP\n"); 352 amdgpu_ucode_print_common_hdr(hdr); 353 354 if (version_major == 1) { 355 const struct psp_firmware_header_v1_0 *psp_hdr = 356 container_of(hdr, struct psp_firmware_header_v1_0, header); 357 358 DRM_DEBUG("ucode_feature_version: %u\n", 359 le32_to_cpu(psp_hdr->sos.fw_version)); 360 DRM_DEBUG("sos_offset_bytes: %u\n", 361 le32_to_cpu(psp_hdr->sos.offset_bytes)); 362 DRM_DEBUG("sos_size_bytes: %u\n", 363 le32_to_cpu(psp_hdr->sos.size_bytes)); 364 if (version_minor == 1) { 365 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 366 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 367 DRM_DEBUG("toc_header_version: %u\n", 368 le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); 369 DRM_DEBUG("toc_offset_bytes: %u\n", 370 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); 371 DRM_DEBUG("toc_size_bytes: %u\n", 372 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); 373 DRM_DEBUG("kdb_header_version: %u\n", 374 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); 375 DRM_DEBUG("kdb_offset_bytes: %u\n", 376 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); 377 DRM_DEBUG("kdb_size_bytes: %u\n", 378 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); 379 } 380 if (version_minor == 2) { 381 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 382 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 383 DRM_DEBUG("kdb_header_version: %u\n", 384 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); 385 DRM_DEBUG("kdb_offset_bytes: %u\n", 386 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); 387 DRM_DEBUG("kdb_size_bytes: %u\n", 388 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); 389 } 390 if (version_minor == 3) { 391 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 392 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 393 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = 394 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); 395 DRM_DEBUG("toc_header_version: %u\n", 396 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); 397 DRM_DEBUG("toc_offset_bytes: %u\n", 398 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); 399 DRM_DEBUG("toc_size_bytes: %u\n", 400 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); 401 DRM_DEBUG("kdb_header_version: %u\n", 402 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); 403 DRM_DEBUG("kdb_offset_bytes: %u\n", 404 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); 405 DRM_DEBUG("kdb_size_bytes: %u\n", 406 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); 407 DRM_DEBUG("spl_header_version: %u\n", 408 le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); 409 DRM_DEBUG("spl_offset_bytes: %u\n", 410 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); 411 DRM_DEBUG("spl_size_bytes: %u\n", 412 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); 413 } 414 } else if (version_major == 2) { 415 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = 416 container_of(hdr, struct psp_firmware_header_v2_0, header); 417 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { 418 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); 419 switch (desc->fw_type) { 420 case PSP_FW_TYPE_PSP_SOS: 421 DRM_DEBUG("psp_sos_version: %u\n", 422 le32_to_cpu(desc->fw_version)); 423 DRM_DEBUG("psp_sos_size_bytes: %u\n", 424 le32_to_cpu(desc->size_bytes)); 425 break; 426 case PSP_FW_TYPE_PSP_SYS_DRV: 427 DRM_DEBUG("psp_sys_drv_version: %u\n", 428 le32_to_cpu(desc->fw_version)); 429 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", 430 le32_to_cpu(desc->size_bytes)); 431 break; 432 case PSP_FW_TYPE_PSP_KDB: 433 DRM_DEBUG("psp_kdb_version: %u\n", 434 le32_to_cpu(desc->fw_version)); 435 DRM_DEBUG("psp_kdb_size_bytes: %u\n", 436 le32_to_cpu(desc->size_bytes)); 437 break; 438 case PSP_FW_TYPE_PSP_TOC: 439 DRM_DEBUG("psp_toc_version: %u\n", 440 le32_to_cpu(desc->fw_version)); 441 DRM_DEBUG("psp_toc_size_bytes: %u\n", 442 le32_to_cpu(desc->size_bytes)); 443 break; 444 case PSP_FW_TYPE_PSP_SPL: 445 DRM_DEBUG("psp_spl_version: %u\n", 446 le32_to_cpu(desc->fw_version)); 447 DRM_DEBUG("psp_spl_size_bytes: %u\n", 448 le32_to_cpu(desc->size_bytes)); 449 break; 450 case PSP_FW_TYPE_PSP_RL: 451 DRM_DEBUG("psp_rl_version: %u\n", 452 le32_to_cpu(desc->fw_version)); 453 DRM_DEBUG("psp_rl_size_bytes: %u\n", 454 le32_to_cpu(desc->size_bytes)); 455 break; 456 case PSP_FW_TYPE_PSP_SOC_DRV: 457 DRM_DEBUG("psp_soc_drv_version: %u\n", 458 le32_to_cpu(desc->fw_version)); 459 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", 460 le32_to_cpu(desc->size_bytes)); 461 break; 462 case PSP_FW_TYPE_PSP_INTF_DRV: 463 DRM_DEBUG("psp_intf_drv_version: %u\n", 464 le32_to_cpu(desc->fw_version)); 465 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", 466 le32_to_cpu(desc->size_bytes)); 467 break; 468 case PSP_FW_TYPE_PSP_DBG_DRV: 469 DRM_DEBUG("psp_dbg_drv_version: %u\n", 470 le32_to_cpu(desc->fw_version)); 471 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", 472 le32_to_cpu(desc->size_bytes)); 473 break; 474 case PSP_FW_TYPE_PSP_RAS_DRV: 475 DRM_DEBUG("psp_ras_drv_version: %u\n", 476 le32_to_cpu(desc->fw_version)); 477 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n", 478 le32_to_cpu(desc->size_bytes)); 479 break; 480 default: 481 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); 482 break; 483 } 484 } 485 } else { 486 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 487 version_major, version_minor); 488 } 489 } 490 491 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 492 { 493 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 494 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 495 496 DRM_DEBUG("GPU_INFO\n"); 497 amdgpu_ucode_print_common_hdr(hdr); 498 499 if (version_major == 1) { 500 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 501 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 502 503 DRM_DEBUG("version_major: %u\n", 504 le16_to_cpu(gpu_info_hdr->version_major)); 505 DRM_DEBUG("version_minor: %u\n", 506 le16_to_cpu(gpu_info_hdr->version_minor)); 507 } else { 508 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 509 } 510 } 511 512 static int amdgpu_ucode_validate(const struct firmware *fw) 513 { 514 const struct common_firmware_header *hdr = 515 (const struct common_firmware_header *)fw->data; 516 517 if (fw->size == le32_to_cpu(hdr->size_bytes)) 518 return 0; 519 520 return -EINVAL; 521 } 522 523 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 524 uint16_t hdr_major, uint16_t hdr_minor) 525 { 526 if ((hdr->common.header_version_major == hdr_major) && 527 (hdr->common.header_version_minor == hdr_minor)) 528 return true; 529 return false; 530 } 531 532 enum amdgpu_firmware_load_type 533 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 534 { 535 switch (adev->asic_type) { 536 #ifdef CONFIG_DRM_AMDGPU_SI 537 case CHIP_TAHITI: 538 case CHIP_PITCAIRN: 539 case CHIP_VERDE: 540 case CHIP_OLAND: 541 case CHIP_HAINAN: 542 return AMDGPU_FW_LOAD_DIRECT; 543 #endif 544 #ifdef CONFIG_DRM_AMDGPU_CIK 545 case CHIP_BONAIRE: 546 case CHIP_KAVERI: 547 case CHIP_KABINI: 548 case CHIP_HAWAII: 549 case CHIP_MULLINS: 550 return AMDGPU_FW_LOAD_DIRECT; 551 #endif 552 case CHIP_TOPAZ: 553 case CHIP_TONGA: 554 case CHIP_FIJI: 555 case CHIP_CARRIZO: 556 case CHIP_STONEY: 557 case CHIP_POLARIS10: 558 case CHIP_POLARIS11: 559 case CHIP_POLARIS12: 560 case CHIP_VEGAM: 561 return AMDGPU_FW_LOAD_SMU; 562 case CHIP_CYAN_SKILLFISH: 563 if (!(load_type && 564 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) 565 return AMDGPU_FW_LOAD_DIRECT; 566 else 567 return AMDGPU_FW_LOAD_PSP; 568 default: 569 if (!load_type) 570 return AMDGPU_FW_LOAD_DIRECT; 571 else if (load_type == 3) 572 return AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO; 573 else 574 return AMDGPU_FW_LOAD_PSP; 575 } 576 } 577 578 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) 579 { 580 switch (ucode_id) { 581 case AMDGPU_UCODE_ID_SDMA0: 582 return "SDMA0"; 583 case AMDGPU_UCODE_ID_SDMA1: 584 return "SDMA1"; 585 case AMDGPU_UCODE_ID_SDMA2: 586 return "SDMA2"; 587 case AMDGPU_UCODE_ID_SDMA3: 588 return "SDMA3"; 589 case AMDGPU_UCODE_ID_SDMA4: 590 return "SDMA4"; 591 case AMDGPU_UCODE_ID_SDMA5: 592 return "SDMA5"; 593 case AMDGPU_UCODE_ID_SDMA6: 594 return "SDMA6"; 595 case AMDGPU_UCODE_ID_SDMA7: 596 return "SDMA7"; 597 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 598 return "SDMA_CTX"; 599 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 600 return "SDMA_CTL"; 601 case AMDGPU_UCODE_ID_CP_CE: 602 return "CP_CE"; 603 case AMDGPU_UCODE_ID_CP_PFP: 604 return "CP_PFP"; 605 case AMDGPU_UCODE_ID_CP_ME: 606 return "CP_ME"; 607 case AMDGPU_UCODE_ID_CP_MEC1: 608 return "CP_MEC1"; 609 case AMDGPU_UCODE_ID_CP_MEC1_JT: 610 return "CP_MEC1_JT"; 611 case AMDGPU_UCODE_ID_CP_MEC2: 612 return "CP_MEC2"; 613 case AMDGPU_UCODE_ID_CP_MEC2_JT: 614 return "CP_MEC2_JT"; 615 case AMDGPU_UCODE_ID_CP_MES: 616 return "CP_MES"; 617 case AMDGPU_UCODE_ID_CP_MES_DATA: 618 return "CP_MES_DATA"; 619 case AMDGPU_UCODE_ID_CP_MES1: 620 return "CP_MES_KIQ"; 621 case AMDGPU_UCODE_ID_CP_MES1_DATA: 622 return "CP_MES_KIQ_DATA"; 623 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 624 return "RLC_RESTORE_LIST_CNTL"; 625 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 626 return "RLC_RESTORE_LIST_GPM_MEM"; 627 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 628 return "RLC_RESTORE_LIST_SRM_MEM"; 629 case AMDGPU_UCODE_ID_RLC_IRAM: 630 return "RLC_IRAM"; 631 case AMDGPU_UCODE_ID_RLC_DRAM: 632 return "RLC_DRAM"; 633 case AMDGPU_UCODE_ID_RLC_G: 634 return "RLC_G"; 635 case AMDGPU_UCODE_ID_RLC_P: 636 return "RLC_P"; 637 case AMDGPU_UCODE_ID_RLC_V: 638 return "RLC_V"; 639 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 640 return "GLOBAL_TAP_DELAYS"; 641 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 642 return "SE0_TAP_DELAYS"; 643 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 644 return "SE1_TAP_DELAYS"; 645 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 646 return "SE2_TAP_DELAYS"; 647 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 648 return "SE3_TAP_DELAYS"; 649 case AMDGPU_UCODE_ID_IMU_I: 650 return "IMU_I"; 651 case AMDGPU_UCODE_ID_IMU_D: 652 return "IMU_D"; 653 case AMDGPU_UCODE_ID_STORAGE: 654 return "STORAGE"; 655 case AMDGPU_UCODE_ID_SMC: 656 return "SMC"; 657 case AMDGPU_UCODE_ID_PPTABLE: 658 return "PPTABLE"; 659 case AMDGPU_UCODE_ID_P2S_TABLE: 660 return "P2STABLE"; 661 case AMDGPU_UCODE_ID_UVD: 662 return "UVD"; 663 case AMDGPU_UCODE_ID_UVD1: 664 return "UVD1"; 665 case AMDGPU_UCODE_ID_VCE: 666 return "VCE"; 667 case AMDGPU_UCODE_ID_VCN: 668 return "VCN"; 669 case AMDGPU_UCODE_ID_VCN1: 670 return "VCN1"; 671 case AMDGPU_UCODE_ID_DMCU_ERAM: 672 return "DMCU_ERAM"; 673 case AMDGPU_UCODE_ID_DMCU_INTV: 674 return "DMCU_INTV"; 675 case AMDGPU_UCODE_ID_VCN0_RAM: 676 return "VCN0_RAM"; 677 case AMDGPU_UCODE_ID_VCN1_RAM: 678 return "VCN1_RAM"; 679 case AMDGPU_UCODE_ID_DMCUB: 680 return "DMCUB"; 681 case AMDGPU_UCODE_ID_CAP: 682 return "CAP"; 683 case AMDGPU_UCODE_ID_VPE_CTX: 684 return "VPE_CTX"; 685 case AMDGPU_UCODE_ID_VPE_CTL: 686 return "VPE_CTL"; 687 case AMDGPU_UCODE_ID_VPE: 688 return "VPE"; 689 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 690 return "UMSCH_MM_UCODE"; 691 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 692 return "UMSCH_MM_DATA"; 693 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 694 return "UMSCH_MM_CMD_BUFFER"; 695 case AMDGPU_UCODE_ID_JPEG_RAM: 696 return "JPEG"; 697 case AMDGPU_UCODE_ID_SDMA_RS64: 698 return "RS64_SDMA"; 699 case AMDGPU_UCODE_ID_CP_RS64_PFP: 700 return "RS64_PFP"; 701 case AMDGPU_UCODE_ID_CP_RS64_ME: 702 return "RS64_ME"; 703 case AMDGPU_UCODE_ID_CP_RS64_MEC: 704 return "RS64_MEC"; 705 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 706 return "RS64_PFP_P0_STACK"; 707 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 708 return "RS64_PFP_P1_STACK"; 709 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 710 return "RS64_ME_P0_STACK"; 711 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 712 return "RS64_ME_P1_STACK"; 713 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 714 return "RS64_MEC_P0_STACK"; 715 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 716 return "RS64_MEC_P1_STACK"; 717 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 718 return "RS64_MEC_P2_STACK"; 719 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 720 return "RS64_MEC_P3_STACK"; 721 case AMDGPU_UCODE_ID_ISP: 722 return "ISP"; 723 default: 724 return "UNKNOWN UCODE"; 725 } 726 } 727 728 static inline int amdgpu_ucode_is_valid(uint32_t fw_version) 729 { 730 if (!fw_version) 731 return -EINVAL; 732 733 return 0; 734 } 735 736 #define FW_VERSION_ATTR(name, mode, field) \ 737 static ssize_t show_##name(struct device *dev, \ 738 struct device_attribute *attr, char *buf) \ 739 { \ 740 struct drm_device *ddev = dev_get_drvdata(dev); \ 741 struct amdgpu_device *adev = drm_to_adev(ddev); \ 742 \ 743 if (!buf) \ 744 return amdgpu_ucode_is_valid(adev->field); \ 745 \ 746 return sysfs_emit(buf, "0x%08x\n", adev->field); \ 747 } \ 748 static DEVICE_ATTR(name, mode, show_##name, NULL) 749 750 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 751 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 752 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 753 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 754 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 755 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 756 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 757 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 758 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 759 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 760 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 761 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 762 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version); 763 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); 764 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); 765 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); 766 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); 767 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 768 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 769 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 770 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 771 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 772 FW_VERSION_ATTR(dmcub_fw_version, 0444, dm.dmcub_fw_version); 773 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK); 774 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK); 775 FW_VERSION_ATTR(pldm_fw_version, 0444, firmware.pldm_version); 776 777 static struct attribute *fw_attrs[] = { 778 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 779 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 780 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 781 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 782 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 783 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 784 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 785 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 786 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 787 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 788 &dev_attr_dmcu_fw_version.attr, &dev_attr_dmcub_fw_version.attr, 789 &dev_attr_imu_fw_version.attr, &dev_attr_mes_fw_version.attr, 790 &dev_attr_mes_kiq_fw_version.attr, &dev_attr_pldm_fw_version.attr, 791 NULL 792 }; 793 794 #define to_dev_attr(x) container_of(x, struct device_attribute, attr) 795 796 static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj, 797 struct attribute *attr, int idx) 798 { 799 struct device_attribute *dev_attr = to_dev_attr(attr); 800 struct device *dev = kobj_to_dev(kobj); 801 802 if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL) 803 return 0; 804 805 return attr->mode; 806 } 807 808 static const struct attribute_group fw_attr_group = { 809 .name = "fw_version", 810 .attrs = fw_attrs, 811 .is_visible = amdgpu_ucode_sys_visible 812 }; 813 814 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 815 { 816 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 817 } 818 819 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 820 { 821 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 822 } 823 824 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 825 struct amdgpu_firmware_info *ucode, 826 uint64_t mc_addr, void *kptr) 827 { 828 const struct common_firmware_header *header = NULL; 829 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 830 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; 831 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 832 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 833 const struct mes_firmware_header_v1_0 *mes_hdr = NULL; 834 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; 835 const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL; 836 const struct imu_firmware_header_v1_0 *imu_hdr = NULL; 837 const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL; 838 const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL; 839 u8 *ucode_addr; 840 841 if (!ucode->fw) 842 return 0; 843 844 ucode->mc_addr = mc_addr; 845 ucode->kaddr = kptr; 846 847 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 848 return 0; 849 850 header = (const struct common_firmware_header *)ucode->fw->data; 851 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 852 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; 853 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 854 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 855 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; 856 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; 857 sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data; 858 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; 859 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data; 860 umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data; 861 862 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 863 switch (ucode->ucode_id) { 864 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 865 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 866 ucode_addr = (u8 *)ucode->fw->data + 867 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes); 868 break; 869 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 870 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 871 ucode_addr = (u8 *)ucode->fw->data + 872 le32_to_cpu(sdma_hdr->ctl_ucode_offset); 873 break; 874 case AMDGPU_UCODE_ID_SDMA_RS64: 875 ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes); 876 ucode_addr = (u8 *)ucode->fw->data + 877 le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes); 878 break; 879 case AMDGPU_UCODE_ID_CP_MEC1: 880 case AMDGPU_UCODE_ID_CP_MEC2: 881 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 882 le32_to_cpu(cp_hdr->jt_size) * 4; 883 ucode_addr = (u8 *)ucode->fw->data + 884 le32_to_cpu(header->ucode_array_offset_bytes); 885 break; 886 case AMDGPU_UCODE_ID_CP_MEC1_JT: 887 case AMDGPU_UCODE_ID_CP_MEC2_JT: 888 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 889 ucode_addr = (u8 *)ucode->fw->data + 890 le32_to_cpu(header->ucode_array_offset_bytes) + 891 le32_to_cpu(cp_hdr->jt_offset) * 4; 892 break; 893 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 894 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 895 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; 896 break; 897 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 898 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 899 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; 900 break; 901 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 902 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 903 ucode_addr = adev->gfx.rlc.save_restore_list_srm; 904 break; 905 case AMDGPU_UCODE_ID_RLC_IRAM: 906 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; 907 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; 908 break; 909 case AMDGPU_UCODE_ID_RLC_DRAM: 910 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; 911 ucode_addr = adev->gfx.rlc.rlc_dram_ucode; 912 break; 913 case AMDGPU_UCODE_ID_RLC_P: 914 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; 915 ucode_addr = adev->gfx.rlc.rlcp_ucode; 916 break; 917 case AMDGPU_UCODE_ID_RLC_V: 918 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes; 919 ucode_addr = adev->gfx.rlc.rlcv_ucode; 920 break; 921 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 922 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes; 923 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode; 924 break; 925 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 926 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes; 927 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; 928 break; 929 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 930 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes; 931 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; 932 break; 933 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 934 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes; 935 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; 936 break; 937 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 938 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes; 939 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode; 940 break; 941 case AMDGPU_UCODE_ID_CP_MES: 942 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 943 ucode_addr = (u8 *)ucode->fw->data + 944 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 945 break; 946 case AMDGPU_UCODE_ID_CP_MES_DATA: 947 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 948 ucode_addr = (u8 *)ucode->fw->data + 949 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 950 break; 951 case AMDGPU_UCODE_ID_CP_MES1: 952 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 953 ucode_addr = (u8 *)ucode->fw->data + 954 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); 955 break; 956 case AMDGPU_UCODE_ID_CP_MES1_DATA: 957 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 958 ucode_addr = (u8 *)ucode->fw->data + 959 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); 960 break; 961 case AMDGPU_UCODE_ID_DMCU_ERAM: 962 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 963 le32_to_cpu(dmcu_hdr->intv_size_bytes); 964 ucode_addr = (u8 *)ucode->fw->data + 965 le32_to_cpu(header->ucode_array_offset_bytes); 966 break; 967 case AMDGPU_UCODE_ID_DMCU_INTV: 968 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 969 ucode_addr = (u8 *)ucode->fw->data + 970 le32_to_cpu(header->ucode_array_offset_bytes) + 971 le32_to_cpu(dmcu_hdr->intv_offset_bytes); 972 break; 973 case AMDGPU_UCODE_ID_DMCUB: 974 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 975 ucode_addr = (u8 *)ucode->fw->data + 976 le32_to_cpu(header->ucode_array_offset_bytes); 977 break; 978 case AMDGPU_UCODE_ID_PPTABLE: 979 ucode->ucode_size = ucode->fw->size; 980 ucode_addr = (u8 *)ucode->fw->data; 981 break; 982 case AMDGPU_UCODE_ID_P2S_TABLE: 983 ucode->ucode_size = ucode->fw->size; 984 ucode_addr = (u8 *)ucode->fw->data; 985 break; 986 case AMDGPU_UCODE_ID_IMU_I: 987 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 988 ucode_addr = (u8 *)ucode->fw->data + 989 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes); 990 break; 991 case AMDGPU_UCODE_ID_IMU_D: 992 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes); 993 ucode_addr = (u8 *)ucode->fw->data + 994 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + 995 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); 996 break; 997 case AMDGPU_UCODE_ID_CP_RS64_PFP: 998 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 999 ucode_addr = (u8 *)ucode->fw->data + 1000 le32_to_cpu(header->ucode_array_offset_bytes); 1001 break; 1002 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 1003 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1004 ucode_addr = (u8 *)ucode->fw->data + 1005 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1006 break; 1007 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 1008 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1009 ucode_addr = (u8 *)ucode->fw->data + 1010 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1011 break; 1012 case AMDGPU_UCODE_ID_CP_RS64_ME: 1013 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1014 ucode_addr = (u8 *)ucode->fw->data + 1015 le32_to_cpu(header->ucode_array_offset_bytes); 1016 break; 1017 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 1018 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1019 ucode_addr = (u8 *)ucode->fw->data + 1020 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1021 break; 1022 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 1023 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1024 ucode_addr = (u8 *)ucode->fw->data + 1025 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1026 break; 1027 case AMDGPU_UCODE_ID_CP_RS64_MEC: 1028 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1029 ucode_addr = (u8 *)ucode->fw->data + 1030 le32_to_cpu(header->ucode_array_offset_bytes); 1031 break; 1032 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 1033 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1034 ucode_addr = (u8 *)ucode->fw->data + 1035 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1036 break; 1037 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 1038 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1039 ucode_addr = (u8 *)ucode->fw->data + 1040 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1041 break; 1042 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 1043 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1044 ucode_addr = (u8 *)ucode->fw->data + 1045 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1046 break; 1047 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 1048 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1049 ucode_addr = (u8 *)ucode->fw->data + 1050 le32_to_cpu(cpv2_hdr->data_offset_bytes); 1051 break; 1052 case AMDGPU_UCODE_ID_VPE_CTX: 1053 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); 1054 ucode_addr = (u8 *)ucode->fw->data + 1055 le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); 1056 break; 1057 case AMDGPU_UCODE_ID_VPE_CTL: 1058 ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); 1059 ucode_addr = (u8 *)ucode->fw->data + 1060 le32_to_cpu(vpe_hdr->ctl_ucode_offset); 1061 break; 1062 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 1063 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes); 1064 ucode_addr = (u8 *)ucode->fw->data + 1065 le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes); 1066 break; 1067 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 1068 ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes); 1069 ucode_addr = (u8 *)ucode->fw->data + 1070 le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes); 1071 break; 1072 default: 1073 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1074 ucode_addr = (u8 *)ucode->fw->data + 1075 le32_to_cpu(header->ucode_array_offset_bytes); 1076 break; 1077 } 1078 } else { 1079 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 1080 ucode_addr = (u8 *)ucode->fw->data + 1081 le32_to_cpu(header->ucode_array_offset_bytes); 1082 } 1083 1084 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); 1085 1086 return 0; 1087 } 1088 1089 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 1090 uint64_t mc_addr, void *kptr) 1091 { 1092 const struct gfx_firmware_header_v1_0 *header = NULL; 1093 const struct common_firmware_header *comm_hdr = NULL; 1094 uint8_t *src_addr = NULL; 1095 uint8_t *dst_addr = NULL; 1096 1097 if (!ucode->fw) 1098 return 0; 1099 1100 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 1101 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1102 dst_addr = ucode->kaddr + 1103 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 1104 PAGE_SIZE); 1105 src_addr = (uint8_t *)ucode->fw->data + 1106 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 1107 (le32_to_cpu(header->jt_offset) * 4); 1108 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 1109 1110 return 0; 1111 } 1112 1113 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 1114 { 1115 if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && 1116 (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { 1117 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 1118 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 1119 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 1120 &adev->firmware.fw_buf, 1121 &adev->firmware.fw_buf_mc, 1122 &adev->firmware.fw_buf_ptr); 1123 if (!adev->firmware.fw_buf) { 1124 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 1125 return -ENOMEM; 1126 } else if (amdgpu_sriov_vf(adev)) { 1127 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 1128 } 1129 } 1130 return 0; 1131 } 1132 1133 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 1134 { 1135 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 1136 &adev->firmware.fw_buf_mc, 1137 &adev->firmware.fw_buf_ptr); 1138 } 1139 1140 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 1141 { 1142 uint64_t fw_offset = 0; 1143 int i; 1144 struct amdgpu_firmware_info *ucode = NULL; 1145 1146 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 1147 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) 1148 return 0; 1149 /* 1150 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 1151 * ucode info here 1152 */ 1153 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1154 if (amdgpu_sriov_vf(adev)) 1155 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 1156 else 1157 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 1158 } else { 1159 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 1160 } 1161 1162 if (amdgpu_virt_xgmi_migrate_enabled(adev) && adev->firmware.fw_buf) 1163 adev->firmware.fw_buf_mc = amdgpu_bo_fb_aper_addr(adev->firmware.fw_buf); 1164 1165 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1166 ucode = &adev->firmware.ucode[i]; 1167 if (ucode->fw) { 1168 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 1169 adev->firmware.fw_buf_ptr + fw_offset); 1170 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 1171 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1172 const struct gfx_firmware_header_v1_0 *cp_hdr; 1173 1174 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 1175 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 1176 adev->firmware.fw_buf_ptr + fw_offset); 1177 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1178 } 1179 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 1180 } 1181 } 1182 return 0; 1183 } 1184 1185 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) 1186 { 1187 if (block_type == MP0_HWIP) { 1188 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1189 case IP_VERSION(9, 0, 0): 1190 switch (adev->asic_type) { 1191 case CHIP_VEGA10: 1192 return "vega10"; 1193 case CHIP_VEGA12: 1194 return "vega12"; 1195 default: 1196 return NULL; 1197 } 1198 case IP_VERSION(10, 0, 0): 1199 case IP_VERSION(10, 0, 1): 1200 if (adev->asic_type == CHIP_RAVEN) { 1201 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1202 return "raven2"; 1203 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1204 return "picasso"; 1205 return "raven"; 1206 } 1207 break; 1208 case IP_VERSION(11, 0, 0): 1209 return "navi10"; 1210 case IP_VERSION(11, 0, 2): 1211 return "vega20"; 1212 case IP_VERSION(11, 0, 3): 1213 return "renoir"; 1214 case IP_VERSION(11, 0, 4): 1215 return "arcturus"; 1216 case IP_VERSION(11, 0, 5): 1217 return "navi14"; 1218 case IP_VERSION(11, 0, 7): 1219 return "sienna_cichlid"; 1220 case IP_VERSION(11, 0, 9): 1221 return "navi12"; 1222 case IP_VERSION(11, 0, 11): 1223 return "navy_flounder"; 1224 case IP_VERSION(11, 0, 12): 1225 return "dimgrey_cavefish"; 1226 case IP_VERSION(11, 0, 13): 1227 return "beige_goby"; 1228 case IP_VERSION(11, 5, 0): 1229 case IP_VERSION(11, 5, 2): 1230 return "vangogh"; 1231 case IP_VERSION(12, 0, 1): 1232 return "green_sardine"; 1233 case IP_VERSION(13, 0, 2): 1234 return "aldebaran"; 1235 case IP_VERSION(13, 0, 1): 1236 case IP_VERSION(13, 0, 3): 1237 return "yellow_carp"; 1238 } 1239 } else if (block_type == MP1_HWIP) { 1240 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1241 case IP_VERSION(9, 0, 0): 1242 case IP_VERSION(10, 0, 0): 1243 case IP_VERSION(10, 0, 1): 1244 case IP_VERSION(11, 0, 2): 1245 if (adev->asic_type == CHIP_ARCTURUS) 1246 return "arcturus_smc"; 1247 return NULL; 1248 case IP_VERSION(11, 0, 0): 1249 return "navi10_smc"; 1250 case IP_VERSION(11, 0, 5): 1251 return "navi14_smc"; 1252 case IP_VERSION(11, 0, 9): 1253 return "navi12_smc"; 1254 case IP_VERSION(11, 0, 7): 1255 return "sienna_cichlid_smc"; 1256 case IP_VERSION(11, 0, 11): 1257 return "navy_flounder_smc"; 1258 case IP_VERSION(11, 0, 12): 1259 return "dimgrey_cavefish_smc"; 1260 case IP_VERSION(11, 0, 13): 1261 return "beige_goby_smc"; 1262 case IP_VERSION(13, 0, 2): 1263 return "aldebaran_smc"; 1264 } 1265 } else if (block_type == SDMA0_HWIP) { 1266 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1267 case IP_VERSION(4, 0, 0): 1268 return "vega10_sdma"; 1269 case IP_VERSION(4, 0, 1): 1270 return "vega12_sdma"; 1271 case IP_VERSION(4, 1, 0): 1272 case IP_VERSION(4, 1, 1): 1273 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1274 return "raven2_sdma"; 1275 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1276 return "picasso_sdma"; 1277 return "raven_sdma"; 1278 case IP_VERSION(4, 1, 2): 1279 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1280 return "renoir_sdma"; 1281 return "green_sardine_sdma"; 1282 case IP_VERSION(4, 2, 0): 1283 return "vega20_sdma"; 1284 case IP_VERSION(4, 2, 2): 1285 return "arcturus_sdma"; 1286 case IP_VERSION(4, 4, 0): 1287 return "aldebaran_sdma"; 1288 case IP_VERSION(5, 0, 0): 1289 return "navi10_sdma"; 1290 case IP_VERSION(5, 0, 1): 1291 return "cyan_skillfish2_sdma"; 1292 case IP_VERSION(5, 0, 2): 1293 return "navi14_sdma"; 1294 case IP_VERSION(5, 0, 5): 1295 return "navi12_sdma"; 1296 case IP_VERSION(5, 2, 0): 1297 return "sienna_cichlid_sdma"; 1298 case IP_VERSION(5, 2, 2): 1299 return "navy_flounder_sdma"; 1300 case IP_VERSION(5, 2, 4): 1301 return "dimgrey_cavefish_sdma"; 1302 case IP_VERSION(5, 2, 5): 1303 return "beige_goby_sdma"; 1304 case IP_VERSION(5, 2, 3): 1305 return "yellow_carp_sdma"; 1306 case IP_VERSION(5, 2, 1): 1307 return "vangogh_sdma"; 1308 } 1309 } else if (block_type == UVD_HWIP) { 1310 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 1311 case IP_VERSION(1, 0, 0): 1312 case IP_VERSION(1, 0, 1): 1313 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1314 return "raven2_vcn"; 1315 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1316 return "picasso_vcn"; 1317 return "raven_vcn"; 1318 case IP_VERSION(2, 5, 0): 1319 return "arcturus_vcn"; 1320 case IP_VERSION(2, 2, 0): 1321 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1322 return "renoir_vcn"; 1323 return "green_sardine_vcn"; 1324 case IP_VERSION(2, 6, 0): 1325 return "aldebaran_vcn"; 1326 case IP_VERSION(2, 0, 0): 1327 return "navi10_vcn"; 1328 case IP_VERSION(2, 0, 2): 1329 if (adev->asic_type == CHIP_NAVI12) 1330 return "navi12_vcn"; 1331 return "navi14_vcn"; 1332 case IP_VERSION(3, 0, 0): 1333 case IP_VERSION(3, 0, 64): 1334 case IP_VERSION(3, 0, 192): 1335 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 1336 IP_VERSION(10, 3, 0)) 1337 return "sienna_cichlid_vcn"; 1338 return "navy_flounder_vcn"; 1339 case IP_VERSION(3, 0, 2): 1340 return "vangogh_vcn"; 1341 case IP_VERSION(3, 0, 16): 1342 return "dimgrey_cavefish_vcn"; 1343 case IP_VERSION(3, 0, 33): 1344 return "beige_goby_vcn"; 1345 case IP_VERSION(3, 1, 1): 1346 return "yellow_carp_vcn"; 1347 } 1348 } else if (block_type == GC_HWIP) { 1349 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1350 case IP_VERSION(9, 0, 1): 1351 return "vega10"; 1352 case IP_VERSION(9, 2, 1): 1353 return "vega12"; 1354 case IP_VERSION(9, 4, 0): 1355 return "vega20"; 1356 case IP_VERSION(9, 2, 2): 1357 case IP_VERSION(9, 1, 0): 1358 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1359 return "raven2"; 1360 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1361 return "picasso"; 1362 return "raven"; 1363 case IP_VERSION(9, 4, 1): 1364 return "arcturus"; 1365 case IP_VERSION(9, 3, 0): 1366 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1367 return "renoir"; 1368 return "green_sardine"; 1369 case IP_VERSION(9, 4, 2): 1370 return "aldebaran"; 1371 case IP_VERSION(10, 1, 10): 1372 return "navi10"; 1373 case IP_VERSION(10, 1, 1): 1374 return "navi14"; 1375 case IP_VERSION(10, 1, 2): 1376 return "navi12"; 1377 case IP_VERSION(10, 3, 0): 1378 return "sienna_cichlid"; 1379 case IP_VERSION(10, 3, 2): 1380 return "navy_flounder"; 1381 case IP_VERSION(10, 3, 1): 1382 return "vangogh"; 1383 case IP_VERSION(10, 3, 4): 1384 return "dimgrey_cavefish"; 1385 case IP_VERSION(10, 3, 5): 1386 return "beige_goby"; 1387 case IP_VERSION(10, 3, 3): 1388 return "yellow_carp"; 1389 case IP_VERSION(10, 1, 3): 1390 case IP_VERSION(10, 1, 4): 1391 return "cyan_skillfish2"; 1392 } 1393 } 1394 return NULL; 1395 } 1396 1397 bool amdgpu_is_kicker_fw(struct amdgpu_device *adev) 1398 { 1399 int i; 1400 1401 for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) { 1402 if (adev->pdev->device == kicker_device_list[i].device && 1403 adev->pdev->revision == kicker_device_list[i].revision) 1404 return true; 1405 } 1406 1407 return false; 1408 } 1409 1410 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) 1411 { 1412 int maj, min, rev; 1413 char *ip_name; 1414 const char *legacy; 1415 uint32_t version = amdgpu_ip_version(adev, block_type, 0); 1416 1417 legacy = amdgpu_ucode_legacy_naming(adev, block_type); 1418 if (legacy) { 1419 snprintf(ucode_prefix, len, "%s", legacy); 1420 return; 1421 } 1422 1423 switch (block_type) { 1424 case GC_HWIP: 1425 ip_name = "gc"; 1426 break; 1427 case SDMA0_HWIP: 1428 ip_name = "sdma"; 1429 break; 1430 case MP0_HWIP: 1431 ip_name = "psp"; 1432 break; 1433 case MP1_HWIP: 1434 ip_name = "smu"; 1435 break; 1436 case UVD_HWIP: 1437 ip_name = "vcn"; 1438 break; 1439 case VPE_HWIP: 1440 ip_name = "vpe"; 1441 break; 1442 case ISP_HWIP: 1443 ip_name = "isp"; 1444 break; 1445 default: 1446 BUG(); 1447 } 1448 1449 maj = IP_VERSION_MAJ(version); 1450 min = IP_VERSION_MIN(version); 1451 rev = IP_VERSION_REV(version); 1452 1453 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); 1454 } 1455 1456 /* 1457 * amdgpu_ucode_request - Fetch and validate amdgpu microcode 1458 * 1459 * @adev: amdgpu device 1460 * @fw: pointer to load firmware to 1461 * @required: whether the firmware is required 1462 * @fmt: firmware name format string 1463 * @...: variable arguments 1464 * 1465 * This is a helper that will use request_firmware and amdgpu_ucode_validate 1466 * to load and run basic validation on firmware. If the load fails, remap 1467 * the error code to -ENODEV, so that early_init functions will fail to load. 1468 */ 1469 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 1470 enum amdgpu_ucode_required required, const char *fmt, ...) 1471 { 1472 char fname[AMDGPU_UCODE_NAME_MAX]; 1473 va_list ap; 1474 int r; 1475 1476 va_start(ap, fmt); 1477 r = vsnprintf(fname, sizeof(fname), fmt, ap); 1478 va_end(ap); 1479 if (r == sizeof(fname)) { 1480 dev_warn(adev->dev, "amdgpu firmware name buffer overflow\n"); 1481 return -EOVERFLOW; 1482 } 1483 1484 if (required == AMDGPU_UCODE_REQUIRED) 1485 r = request_firmware(fw, fname, adev->dev); 1486 else { 1487 r = firmware_request_nowarn(fw, fname, adev->dev); 1488 if (r) 1489 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fname); 1490 } 1491 if (r) 1492 return -ENODEV; 1493 1494 r = amdgpu_ucode_validate(*fw); 1495 if (r) 1496 /* 1497 * The amdgpu_ucode_request() should be paired with amdgpu_ucode_release() 1498 * regardless of success/failure, and the amdgpu_ucode_release() takes care of 1499 * firmware release and need to avoid redundant release FW operation here. 1500 */ 1501 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fname); 1502 1503 return r; 1504 } 1505 1506 /* 1507 * amdgpu_ucode_release - Release firmware microcode 1508 * 1509 * @fw: pointer to firmware to release 1510 */ 1511 void amdgpu_ucode_release(const struct firmware **fw) 1512 { 1513 release_firmware(*fw); 1514 *fw = NULL; 1515 } 1516