1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include "amdgpu_vram_mgr.h" 30 #include "amdgpu.h" 31 32 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 33 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 34 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 35 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 36 37 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 38 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 39 40 #define AMDGPU_POISON 0xd0bed0be 41 42 struct amdgpu_gtt_mgr { 43 struct ttm_resource_manager manager; 44 struct drm_mm mm; 45 spinlock_t lock; 46 }; 47 48 struct amdgpu_mman { 49 struct ttm_device bdev; 50 bool initialized; 51 void __iomem *aper_base_kaddr; 52 53 /* buffer handling */ 54 const struct amdgpu_buffer_funcs *buffer_funcs; 55 struct amdgpu_ring *buffer_funcs_ring; 56 bool buffer_funcs_enabled; 57 58 struct mutex gtt_window_lock; 59 /* Scheduler entity for buffer moves */ 60 struct drm_sched_entity entity; 61 62 struct amdgpu_vram_mgr vram_mgr; 63 struct amdgpu_gtt_mgr gtt_mgr; 64 struct ttm_resource_manager preempt_mgr; 65 66 uint64_t stolen_vga_size; 67 struct amdgpu_bo *stolen_vga_memory; 68 uint64_t stolen_extended_size; 69 struct amdgpu_bo *stolen_extended_memory; 70 bool keep_stolen_vga_memory; 71 72 struct amdgpu_bo *stolen_reserved_memory; 73 uint64_t stolen_reserved_offset; 74 uint64_t stolen_reserved_size; 75 76 /* discovery */ 77 uint8_t *discovery_bin; 78 uint32_t discovery_tmr_size; 79 struct amdgpu_bo *discovery_memory; 80 81 /* firmware VRAM reservation */ 82 u64 fw_vram_usage_start_offset; 83 u64 fw_vram_usage_size; 84 struct amdgpu_bo *fw_vram_usage_reserved_bo; 85 void *fw_vram_usage_va; 86 87 /* driver VRAM reservation */ 88 u64 drv_vram_usage_start_offset; 89 u64 drv_vram_usage_size; 90 struct amdgpu_bo *drv_vram_usage_reserved_bo; 91 92 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 93 struct amdgpu_bo *sdma_access_bo; 94 void *sdma_access_ptr; 95 }; 96 97 struct amdgpu_copy_mem { 98 struct ttm_buffer_object *bo; 99 struct ttm_resource *mem; 100 unsigned long offset; 101 }; 102 103 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 104 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 105 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 106 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 107 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 108 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 109 110 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 111 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 112 113 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 114 115 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 116 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 117 struct ttm_resource *mem, 118 u64 offset, u64 size, 119 struct device *dev, 120 enum dma_data_direction dir, 121 struct sg_table **sgt); 122 void amdgpu_vram_mgr_free_sgt(struct device *dev, 123 enum dma_data_direction dir, 124 struct sg_table *sgt); 125 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 126 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 127 uint64_t start, uint64_t size); 128 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 129 uint64_t start); 130 131 int amdgpu_ttm_init(struct amdgpu_device *adev); 132 void amdgpu_ttm_fini(struct amdgpu_device *adev); 133 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 134 bool enable); 135 136 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 137 uint64_t dst_offset, uint32_t byte_count, 138 struct dma_resv *resv, 139 struct dma_fence **fence, bool direct_submit, 140 bool vm_needs_flush, bool tmz); 141 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 142 const struct amdgpu_copy_mem *src, 143 const struct amdgpu_copy_mem *dst, 144 uint64_t size, bool tmz, 145 struct dma_resv *resv, 146 struct dma_fence **f); 147 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 148 uint32_t src_data, 149 struct dma_resv *resv, 150 struct dma_fence **fence); 151 152 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 153 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 154 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 155 156 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 157 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); 158 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm); 159 #else 160 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 161 struct page **pages) 162 { 163 return -EPERM; 164 } 165 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 166 { 167 return false; 168 } 169 #endif 170 171 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); 172 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 173 uint64_t *user_addr); 174 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 175 uint64_t addr, uint32_t flags); 176 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 177 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 178 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 179 unsigned long end, unsigned long *userptr); 180 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 181 int *last_invalidated); 182 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 183 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 184 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 185 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 186 struct ttm_resource *mem); 187 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 188 189 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 190 191 #endif 192