1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/ttm/ttm_placement.h> 30 #include "amdgpu_vram_mgr.h" 31 #include "amdgpu_hmm.h" 32 33 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 34 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 35 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 36 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 37 #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) 38 #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) 39 #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) 40 41 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 42 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 43 44 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 45 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 46 47 struct hmm_range; 48 49 struct amdgpu_gtt_mgr { 50 struct ttm_resource_manager manager; 51 struct drm_mm mm; 52 spinlock_t lock; 53 }; 54 55 struct amdgpu_ttm_buffer_entity { 56 struct drm_sched_entity base; 57 }; 58 59 struct amdgpu_mman { 60 struct ttm_device bdev; 61 struct ttm_pool *ttm_pools; 62 bool initialized; 63 void __iomem *aper_base_kaddr; 64 65 /* buffer handling */ 66 const struct amdgpu_buffer_funcs *buffer_funcs; 67 struct amdgpu_ring *buffer_funcs_ring; 68 bool buffer_funcs_enabled; 69 70 struct mutex gtt_window_lock; 71 72 struct amdgpu_ttm_buffer_entity default_entity; 73 struct amdgpu_ttm_buffer_entity clear_entity; 74 struct amdgpu_ttm_buffer_entity move_entity; 75 76 struct amdgpu_vram_mgr vram_mgr; 77 struct amdgpu_gtt_mgr gtt_mgr; 78 struct ttm_resource_manager preempt_mgr; 79 80 uint64_t stolen_vga_size; 81 struct amdgpu_bo *stolen_vga_memory; 82 uint64_t stolen_extended_size; 83 struct amdgpu_bo *stolen_extended_memory; 84 bool keep_stolen_vga_memory; 85 86 struct amdgpu_bo *stolen_reserved_memory; 87 uint64_t stolen_reserved_offset; 88 uint64_t stolen_reserved_size; 89 90 /* fw reserved memory */ 91 struct amdgpu_bo *fw_reserved_memory; 92 struct amdgpu_bo *fw_reserved_memory_extend; 93 94 /* firmware VRAM reservation */ 95 u64 fw_vram_usage_start_offset; 96 u64 fw_vram_usage_size; 97 struct amdgpu_bo *fw_vram_usage_reserved_bo; 98 void *fw_vram_usage_va; 99 100 /* driver VRAM reservation */ 101 u64 drv_vram_usage_start_offset; 102 u64 drv_vram_usage_size; 103 struct amdgpu_bo *drv_vram_usage_reserved_bo; 104 void *drv_vram_usage_va; 105 106 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 107 struct amdgpu_bo *sdma_access_bo; 108 void *sdma_access_ptr; 109 }; 110 111 struct amdgpu_copy_mem { 112 struct ttm_buffer_object *bo; 113 struct ttm_resource *mem; 114 unsigned long offset; 115 }; 116 117 #define AMDGPU_COPY_FLAGS_TMZ (1 << 0) 118 #define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1) 119 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2) 120 #define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3 121 #define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03 122 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT 5 123 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07 124 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8 125 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f 126 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14 127 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1 128 129 #define AMDGPU_COPY_FLAGS_SET(field, value) \ 130 (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT) 131 #define AMDGPU_COPY_FLAGS_GET(value, field) \ 132 (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK) 133 134 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 135 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 136 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 137 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 138 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 139 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 140 141 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 142 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 143 144 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 145 146 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 147 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 148 struct ttm_resource *mem, 149 u64 offset, u64 size, 150 struct device *dev, 151 enum dma_data_direction dir, 152 struct sg_table **sgt); 153 void amdgpu_vram_mgr_free_sgt(struct device *dev, 154 enum dma_data_direction dir, 155 struct sg_table *sgt); 156 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 157 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 158 uint64_t start, uint64_t size); 159 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 160 uint64_t start); 161 void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev); 162 163 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 164 struct ttm_resource *res); 165 166 int amdgpu_ttm_init(struct amdgpu_device *adev); 167 void amdgpu_ttm_fini(struct amdgpu_device *adev); 168 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 169 bool enable); 170 int amdgpu_copy_buffer(struct amdgpu_device *adev, 171 struct amdgpu_ttm_buffer_entity *entity, 172 uint64_t src_offset, 173 uint64_t dst_offset, uint32_t byte_count, 174 struct dma_resv *resv, 175 struct dma_fence **fence, 176 bool vm_needs_flush, uint32_t copy_flags); 177 int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, 178 struct dma_resv *resv, 179 struct dma_fence **fence); 180 int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, 181 struct amdgpu_bo *bo, 182 uint32_t src_data, 183 struct dma_resv *resv, 184 struct dma_fence **f, 185 u64 k_job_id); 186 187 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 188 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 189 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 190 191 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 192 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 193 struct amdgpu_hmm_range *range); 194 #else 195 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 196 struct amdgpu_hmm_range *range) 197 { 198 return -EPERM; 199 } 200 #endif 201 202 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); 203 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 204 uint64_t *user_addr); 205 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 206 uint64_t addr, uint32_t flags); 207 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 208 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 209 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 210 unsigned long end, unsigned long *userptr); 211 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 212 int *last_invalidated); 213 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 214 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 215 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 216 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 217 struct ttm_resource *mem); 218 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 219 220 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 221 222 int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev, 223 struct ttm_resource *res, 224 struct device *dev, 225 enum dma_data_direction dir, 226 struct sg_table **sgt); 227 void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev, 228 enum dma_data_direction dir, 229 struct sg_table *sgt); 230 231 #endif 232