1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/ttm/ttm_placement.h> 30 #include "amdgpu_vram_mgr.h" 31 32 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 33 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 34 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 35 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 36 #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) 37 #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) 38 #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) 39 40 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 41 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 42 43 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 44 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 45 46 struct hmm_range; 47 48 struct amdgpu_gtt_mgr { 49 struct ttm_resource_manager manager; 50 struct drm_mm mm; 51 spinlock_t lock; 52 }; 53 54 struct amdgpu_mman { 55 struct ttm_device bdev; 56 struct ttm_pool *ttm_pools; 57 bool initialized; 58 void __iomem *aper_base_kaddr; 59 60 /* buffer handling */ 61 const struct amdgpu_buffer_funcs *buffer_funcs; 62 struct amdgpu_ring *buffer_funcs_ring; 63 bool buffer_funcs_enabled; 64 65 struct mutex gtt_window_lock; 66 /* High priority scheduler entity for buffer moves */ 67 struct drm_sched_entity high_pr; 68 /* Low priority scheduler entity for VRAM clearing */ 69 struct drm_sched_entity low_pr; 70 71 struct amdgpu_vram_mgr vram_mgr; 72 struct amdgpu_gtt_mgr gtt_mgr; 73 struct ttm_resource_manager preempt_mgr; 74 75 uint64_t stolen_vga_size; 76 struct amdgpu_bo *stolen_vga_memory; 77 uint64_t stolen_extended_size; 78 struct amdgpu_bo *stolen_extended_memory; 79 bool keep_stolen_vga_memory; 80 81 struct amdgpu_bo *stolen_reserved_memory; 82 uint64_t stolen_reserved_offset; 83 uint64_t stolen_reserved_size; 84 85 /* discovery */ 86 uint8_t *discovery_bin; 87 uint32_t discovery_tmr_size; 88 /* fw reserved memory */ 89 struct amdgpu_bo *fw_reserved_memory; 90 struct amdgpu_bo *fw_reserved_memory_extend; 91 92 /* firmware VRAM reservation */ 93 u64 fw_vram_usage_start_offset; 94 u64 fw_vram_usage_size; 95 struct amdgpu_bo *fw_vram_usage_reserved_bo; 96 void *fw_vram_usage_va; 97 98 /* driver VRAM reservation */ 99 u64 drv_vram_usage_start_offset; 100 u64 drv_vram_usage_size; 101 struct amdgpu_bo *drv_vram_usage_reserved_bo; 102 void *drv_vram_usage_va; 103 104 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 105 struct amdgpu_bo *sdma_access_bo; 106 void *sdma_access_ptr; 107 }; 108 109 struct amdgpu_copy_mem { 110 struct ttm_buffer_object *bo; 111 struct ttm_resource *mem; 112 unsigned long offset; 113 }; 114 115 #define AMDGPU_COPY_FLAGS_TMZ (1 << 0) 116 #define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1) 117 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2) 118 #define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3 119 #define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03 120 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT 5 121 #define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07 122 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8 123 #define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f 124 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14 125 #define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1 126 127 #define AMDGPU_COPY_FLAGS_SET(field, value) \ 128 (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT) 129 #define AMDGPU_COPY_FLAGS_GET(value, field) \ 130 (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK) 131 132 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 133 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 134 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 135 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 136 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 137 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 138 139 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 140 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 141 142 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 143 144 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 145 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 146 struct ttm_resource *mem, 147 u64 offset, u64 size, 148 struct device *dev, 149 enum dma_data_direction dir, 150 struct sg_table **sgt); 151 void amdgpu_vram_mgr_free_sgt(struct device *dev, 152 enum dma_data_direction dir, 153 struct sg_table *sgt); 154 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 155 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 156 uint64_t start, uint64_t size); 157 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 158 uint64_t start); 159 void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev); 160 161 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 162 struct ttm_resource *res); 163 164 int amdgpu_ttm_init(struct amdgpu_device *adev); 165 void amdgpu_ttm_fini(struct amdgpu_device *adev); 166 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 167 bool enable); 168 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 169 uint64_t dst_offset, uint32_t byte_count, 170 struct dma_resv *resv, 171 struct dma_fence **fence, bool direct_submit, 172 bool vm_needs_flush, uint32_t copy_flags); 173 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 174 const struct amdgpu_copy_mem *src, 175 const struct amdgpu_copy_mem *dst, 176 uint64_t size, bool tmz, 177 struct dma_resv *resv, 178 struct dma_fence **f); 179 int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, 180 struct dma_resv *resv, 181 struct dma_fence **fence); 182 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 183 uint32_t src_data, 184 struct dma_resv *resv, 185 struct dma_fence **fence, 186 bool delayed, 187 u64 k_job_id); 188 189 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 190 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 191 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 192 193 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 194 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 195 struct hmm_range **range); 196 void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 197 struct hmm_range *range); 198 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 199 struct hmm_range *range); 200 #else 201 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 202 struct hmm_range **range) 203 { 204 return -EPERM; 205 } 206 static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, 207 struct hmm_range *range) 208 { 209 } 210 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 211 struct hmm_range *range) 212 { 213 return false; 214 } 215 #endif 216 217 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range); 218 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 219 uint64_t *user_addr); 220 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 221 uint64_t addr, uint32_t flags); 222 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 223 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 224 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 225 unsigned long end, unsigned long *userptr); 226 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 227 int *last_invalidated); 228 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 229 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 230 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 231 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 232 struct ttm_resource *mem); 233 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 234 235 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 236 237 #endif 238