1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 45 #include <drm/ttm/ttm_bo_api.h> 46 #include <drm/ttm/ttm_bo_driver.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <drm/ttm/ttm_range_manager.h> 49 50 #include <drm/amdgpu_drm.h> 51 52 #include "amdgpu.h" 53 #include "amdgpu_object.h" 54 #include "amdgpu_trace.h" 55 #include "amdgpu_amdkfd.h" 56 #include "amdgpu_sdma.h" 57 #include "amdgpu_ras.h" 58 #include "amdgpu_atomfirmware.h" 59 #include "amdgpu_res_cursor.h" 60 #include "bif/bif_4_1_d.h" 61 62 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 63 64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 65 struct ttm_tt *ttm, 66 struct ttm_resource *bo_mem); 67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 68 struct ttm_tt *ttm); 69 70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 71 unsigned int type, 72 uint64_t size_in_page) 73 { 74 return ttm_range_man_init(&adev->mman.bdev, type, 75 false, size_in_page); 76 } 77 78 /** 79 * amdgpu_evict_flags - Compute placement flags 80 * 81 * @bo: The buffer object to evict 82 * @placement: Possible destination(s) for evicted BO 83 * 84 * Fill in placement data when ttm_bo_evict() is called 85 */ 86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 87 struct ttm_placement *placement) 88 { 89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 90 struct amdgpu_bo *abo; 91 static const struct ttm_place placements = { 92 .fpfn = 0, 93 .lpfn = 0, 94 .mem_type = TTM_PL_SYSTEM, 95 .flags = 0 96 }; 97 98 /* Don't handle scatter gather BOs */ 99 if (bo->type == ttm_bo_type_sg) { 100 placement->num_placement = 0; 101 placement->num_busy_placement = 0; 102 return; 103 } 104 105 /* Object isn't an AMDGPU object so ignore */ 106 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 107 placement->placement = &placements; 108 placement->busy_placement = &placements; 109 placement->num_placement = 1; 110 placement->num_busy_placement = 1; 111 return; 112 } 113 114 abo = ttm_to_amdgpu_bo(bo); 115 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 116 struct dma_fence *fence; 117 struct dma_resv *resv = &bo->base._resv; 118 119 rcu_read_lock(); 120 fence = rcu_dereference(resv->fence_excl); 121 if (fence && !fence->ops->signaled) 122 dma_fence_enable_sw_signaling(fence); 123 124 placement->num_placement = 0; 125 placement->num_busy_placement = 0; 126 rcu_read_unlock(); 127 return; 128 } 129 130 switch (bo->resource->mem_type) { 131 case AMDGPU_PL_GDS: 132 case AMDGPU_PL_GWS: 133 case AMDGPU_PL_OA: 134 placement->num_placement = 0; 135 placement->num_busy_placement = 0; 136 return; 137 138 case TTM_PL_VRAM: 139 if (!adev->mman.buffer_funcs_enabled) { 140 /* Move to system memory */ 141 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 142 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 143 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 144 amdgpu_bo_in_cpu_visible_vram(abo)) { 145 146 /* Try evicting to the CPU inaccessible part of VRAM 147 * first, but only set GTT as busy placement, so this 148 * BO will be evicted to GTT rather than causing other 149 * BOs to be evicted from VRAM 150 */ 151 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 152 AMDGPU_GEM_DOMAIN_GTT | 153 AMDGPU_GEM_DOMAIN_CPU); 154 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 155 abo->placements[0].lpfn = 0; 156 abo->placement.busy_placement = &abo->placements[1]; 157 abo->placement.num_busy_placement = 1; 158 } else { 159 /* Move to GTT memory */ 160 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 161 AMDGPU_GEM_DOMAIN_CPU); 162 } 163 break; 164 case TTM_PL_TT: 165 case AMDGPU_PL_PREEMPT: 166 default: 167 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 168 break; 169 } 170 *placement = abo->placement; 171 } 172 173 /** 174 * amdgpu_ttm_map_buffer - Map memory into the GART windows 175 * @bo: buffer object to map 176 * @mem: memory object to map 177 * @mm_cur: range to map 178 * @num_pages: number of pages to map 179 * @window: which GART window to use 180 * @ring: DMA ring to use for the copy 181 * @tmz: if we should setup a TMZ enabled mapping 182 * @addr: resulting address inside the MC address space 183 * 184 * Setup one of the GART windows to access a specific piece of memory or return 185 * the physical address for local memory. 186 */ 187 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 188 struct ttm_resource *mem, 189 struct amdgpu_res_cursor *mm_cur, 190 unsigned num_pages, unsigned window, 191 struct amdgpu_ring *ring, bool tmz, 192 uint64_t *addr) 193 { 194 struct amdgpu_device *adev = ring->adev; 195 struct amdgpu_job *job; 196 unsigned num_dw, num_bytes; 197 struct dma_fence *fence; 198 uint64_t src_addr, dst_addr; 199 void *cpu_addr; 200 uint64_t flags; 201 unsigned int i; 202 int r; 203 204 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 205 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 206 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); 207 208 /* Map only what can't be accessed directly */ 209 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 210 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 211 mm_cur->start; 212 return 0; 213 } 214 215 *addr = adev->gmc.gart_start; 216 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 217 AMDGPU_GPU_PAGE_SIZE; 218 *addr += mm_cur->start & ~PAGE_MASK; 219 220 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 221 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 222 223 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 224 AMDGPU_IB_POOL_DELAYED, &job); 225 if (r) 226 return r; 227 228 src_addr = num_dw * 4; 229 src_addr += job->ibs[0].gpu_addr; 230 231 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 232 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 233 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 234 dst_addr, num_bytes, false); 235 236 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 237 WARN_ON(job->ibs[0].length_dw > num_dw); 238 239 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 240 if (tmz) 241 flags |= AMDGPU_PTE_TMZ; 242 243 cpu_addr = &job->ibs[0].ptr[num_dw]; 244 245 if (mem->mem_type == TTM_PL_TT) { 246 dma_addr_t *dma_addr; 247 248 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 249 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 250 cpu_addr); 251 if (r) 252 goto error_free; 253 } else { 254 dma_addr_t dma_address; 255 256 dma_address = mm_cur->start; 257 dma_address += adev->vm_manager.vram_base_offset; 258 259 for (i = 0; i < num_pages; ++i) { 260 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 261 &dma_address, flags, cpu_addr); 262 if (r) 263 goto error_free; 264 265 dma_address += PAGE_SIZE; 266 } 267 } 268 269 r = amdgpu_job_submit(job, &adev->mman.entity, 270 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 271 if (r) 272 goto error_free; 273 274 dma_fence_put(fence); 275 276 return r; 277 278 error_free: 279 amdgpu_job_free(job); 280 return r; 281 } 282 283 /** 284 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 285 * @adev: amdgpu device 286 * @src: buffer/address where to read from 287 * @dst: buffer/address where to write to 288 * @size: number of bytes to copy 289 * @tmz: if a secure copy should be used 290 * @resv: resv object to sync to 291 * @f: Returns the last fence if multiple jobs are submitted. 292 * 293 * The function copies @size bytes from {src->mem + src->offset} to 294 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 295 * move and different for a BO to BO copy. 296 * 297 */ 298 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 299 const struct amdgpu_copy_mem *src, 300 const struct amdgpu_copy_mem *dst, 301 uint64_t size, bool tmz, 302 struct dma_resv *resv, 303 struct dma_fence **f) 304 { 305 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 306 AMDGPU_GPU_PAGE_SIZE); 307 308 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 309 struct amdgpu_res_cursor src_mm, dst_mm; 310 struct dma_fence *fence = NULL; 311 int r = 0; 312 313 if (!adev->mman.buffer_funcs_enabled) { 314 DRM_ERROR("Trying to move memory with ring turned off.\n"); 315 return -EINVAL; 316 } 317 318 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 319 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 320 321 mutex_lock(&adev->mman.gtt_window_lock); 322 while (src_mm.remaining) { 323 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 324 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 325 struct dma_fence *next; 326 uint32_t cur_size; 327 uint64_t from, to; 328 329 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 330 * begins at an offset, then adjust the size accordingly 331 */ 332 cur_size = max(src_page_offset, dst_page_offset); 333 cur_size = min(min3(src_mm.size, dst_mm.size, size), 334 (uint64_t)(GTT_MAX_BYTES - cur_size)); 335 336 /* Map src to window 0 and dst to window 1. */ 337 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 338 PFN_UP(cur_size + src_page_offset), 339 0, ring, tmz, &from); 340 if (r) 341 goto error; 342 343 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 344 PFN_UP(cur_size + dst_page_offset), 345 1, ring, tmz, &to); 346 if (r) 347 goto error; 348 349 r = amdgpu_copy_buffer(ring, from, to, cur_size, 350 resv, &next, false, true, tmz); 351 if (r) 352 goto error; 353 354 dma_fence_put(fence); 355 fence = next; 356 357 amdgpu_res_next(&src_mm, cur_size); 358 amdgpu_res_next(&dst_mm, cur_size); 359 } 360 error: 361 mutex_unlock(&adev->mman.gtt_window_lock); 362 if (f) 363 *f = dma_fence_get(fence); 364 dma_fence_put(fence); 365 return r; 366 } 367 368 /* 369 * amdgpu_move_blit - Copy an entire buffer to another buffer 370 * 371 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 372 * help move buffers to and from VRAM. 373 */ 374 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 375 bool evict, 376 struct ttm_resource *new_mem, 377 struct ttm_resource *old_mem) 378 { 379 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 380 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 381 struct amdgpu_copy_mem src, dst; 382 struct dma_fence *fence = NULL; 383 int r; 384 385 src.bo = bo; 386 dst.bo = bo; 387 src.mem = old_mem; 388 dst.mem = new_mem; 389 src.offset = 0; 390 dst.offset = 0; 391 392 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 393 new_mem->num_pages << PAGE_SHIFT, 394 amdgpu_bo_encrypted(abo), 395 bo->base.resv, &fence); 396 if (r) 397 goto error; 398 399 /* clear the space being freed */ 400 if (old_mem->mem_type == TTM_PL_VRAM && 401 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 402 struct dma_fence *wipe_fence = NULL; 403 404 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 405 NULL, &wipe_fence); 406 if (r) { 407 goto error; 408 } else if (wipe_fence) { 409 dma_fence_put(fence); 410 fence = wipe_fence; 411 } 412 } 413 414 /* Always block for VM page tables before committing the new location */ 415 if (bo->type == ttm_bo_type_kernel) 416 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 417 else 418 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 419 dma_fence_put(fence); 420 return r; 421 422 error: 423 if (fence) 424 dma_fence_wait(fence, false); 425 dma_fence_put(fence); 426 return r; 427 } 428 429 /* 430 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 431 * 432 * Called by amdgpu_bo_move() 433 */ 434 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 435 struct ttm_resource *mem) 436 { 437 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 438 struct amdgpu_res_cursor cursor; 439 440 if (mem->mem_type == TTM_PL_SYSTEM || 441 mem->mem_type == TTM_PL_TT) 442 return true; 443 if (mem->mem_type != TTM_PL_VRAM) 444 return false; 445 446 amdgpu_res_first(mem, 0, mem_size, &cursor); 447 448 /* ttm_resource_ioremap only supports contiguous memory */ 449 if (cursor.size != mem_size) 450 return false; 451 452 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 453 } 454 455 /* 456 * amdgpu_bo_move - Move a buffer object to a new memory location 457 * 458 * Called by ttm_bo_handle_move_mem() 459 */ 460 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 461 struct ttm_operation_ctx *ctx, 462 struct ttm_resource *new_mem, 463 struct ttm_place *hop) 464 { 465 struct amdgpu_device *adev; 466 struct amdgpu_bo *abo; 467 struct ttm_resource *old_mem = bo->resource; 468 int r; 469 470 if (new_mem->mem_type == TTM_PL_TT || 471 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 472 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 473 if (r) 474 return r; 475 } 476 477 /* Can't move a pinned BO */ 478 abo = ttm_to_amdgpu_bo(bo); 479 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 480 return -EINVAL; 481 482 adev = amdgpu_ttm_adev(bo->bdev); 483 484 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 485 ttm_bo_move_null(bo, new_mem); 486 goto out; 487 } 488 if (old_mem->mem_type == TTM_PL_SYSTEM && 489 (new_mem->mem_type == TTM_PL_TT || 490 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 491 ttm_bo_move_null(bo, new_mem); 492 goto out; 493 } 494 if ((old_mem->mem_type == TTM_PL_TT || 495 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 496 new_mem->mem_type == TTM_PL_SYSTEM) { 497 r = ttm_bo_wait_ctx(bo, ctx); 498 if (r) 499 return r; 500 501 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 502 ttm_resource_free(bo, &bo->resource); 503 ttm_bo_assign_mem(bo, new_mem); 504 goto out; 505 } 506 507 if (old_mem->mem_type == AMDGPU_PL_GDS || 508 old_mem->mem_type == AMDGPU_PL_GWS || 509 old_mem->mem_type == AMDGPU_PL_OA || 510 new_mem->mem_type == AMDGPU_PL_GDS || 511 new_mem->mem_type == AMDGPU_PL_GWS || 512 new_mem->mem_type == AMDGPU_PL_OA) { 513 /* Nothing to save here */ 514 ttm_bo_move_null(bo, new_mem); 515 goto out; 516 } 517 518 if (bo->type == ttm_bo_type_device && 519 new_mem->mem_type == TTM_PL_VRAM && 520 old_mem->mem_type != TTM_PL_VRAM) { 521 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 522 * accesses the BO after it's moved. 523 */ 524 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 525 } 526 527 if (adev->mman.buffer_funcs_enabled) { 528 if (((old_mem->mem_type == TTM_PL_SYSTEM && 529 new_mem->mem_type == TTM_PL_VRAM) || 530 (old_mem->mem_type == TTM_PL_VRAM && 531 new_mem->mem_type == TTM_PL_SYSTEM))) { 532 hop->fpfn = 0; 533 hop->lpfn = 0; 534 hop->mem_type = TTM_PL_TT; 535 hop->flags = TTM_PL_FLAG_TEMPORARY; 536 return -EMULTIHOP; 537 } 538 539 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 540 } else { 541 r = -ENODEV; 542 } 543 544 if (r) { 545 /* Check that all memory is CPU accessible */ 546 if (!amdgpu_mem_visible(adev, old_mem) || 547 !amdgpu_mem_visible(adev, new_mem)) { 548 pr_err("Move buffer fallback to memcpy unavailable\n"); 549 return r; 550 } 551 552 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 553 if (r) 554 return r; 555 } 556 557 out: 558 /* update statistics */ 559 atomic64_add(bo->base.size, &adev->num_bytes_moved); 560 amdgpu_bo_move_notify(bo, evict, new_mem); 561 return 0; 562 } 563 564 /* 565 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 566 * 567 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 568 */ 569 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 570 struct ttm_resource *mem) 571 { 572 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 573 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 574 575 switch (mem->mem_type) { 576 case TTM_PL_SYSTEM: 577 /* system memory */ 578 return 0; 579 case TTM_PL_TT: 580 case AMDGPU_PL_PREEMPT: 581 break; 582 case TTM_PL_VRAM: 583 mem->bus.offset = mem->start << PAGE_SHIFT; 584 /* check if it's visible */ 585 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 586 return -EINVAL; 587 588 if (adev->mman.aper_base_kaddr && 589 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 590 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 591 mem->bus.offset; 592 593 mem->bus.offset += adev->gmc.aper_base; 594 mem->bus.is_iomem = true; 595 break; 596 default: 597 return -EINVAL; 598 } 599 return 0; 600 } 601 602 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 603 unsigned long page_offset) 604 { 605 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 606 struct amdgpu_res_cursor cursor; 607 608 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 609 &cursor); 610 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 611 } 612 613 /** 614 * amdgpu_ttm_domain_start - Returns GPU start address 615 * @adev: amdgpu device object 616 * @type: type of the memory 617 * 618 * Returns: 619 * GPU start address of a memory domain 620 */ 621 622 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 623 { 624 switch (type) { 625 case TTM_PL_TT: 626 return adev->gmc.gart_start; 627 case TTM_PL_VRAM: 628 return adev->gmc.vram_start; 629 } 630 631 return 0; 632 } 633 634 /* 635 * TTM backend functions. 636 */ 637 struct amdgpu_ttm_tt { 638 struct ttm_tt ttm; 639 struct drm_gem_object *gobj; 640 u64 offset; 641 uint64_t userptr; 642 struct task_struct *usertask; 643 uint32_t userflags; 644 bool bound; 645 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 646 struct hmm_range *range; 647 #endif 648 }; 649 650 #ifdef CONFIG_DRM_AMDGPU_USERPTR 651 /* 652 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 653 * memory and start HMM tracking CPU page table update 654 * 655 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 656 * once afterwards to stop HMM tracking 657 */ 658 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 659 { 660 struct ttm_tt *ttm = bo->tbo.ttm; 661 struct amdgpu_ttm_tt *gtt = (void *)ttm; 662 unsigned long start = gtt->userptr; 663 struct vm_area_struct *vma; 664 struct mm_struct *mm; 665 bool readonly; 666 int r = 0; 667 668 mm = bo->notifier.mm; 669 if (unlikely(!mm)) { 670 DRM_DEBUG_DRIVER("BO is not registered?\n"); 671 return -EFAULT; 672 } 673 674 /* Another get_user_pages is running at the same time?? */ 675 if (WARN_ON(gtt->range)) 676 return -EFAULT; 677 678 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 679 return -ESRCH; 680 681 mmap_read_lock(mm); 682 vma = vma_lookup(mm, start); 683 if (unlikely(!vma)) { 684 r = -EFAULT; 685 goto out_unlock; 686 } 687 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 688 vma->vm_file)) { 689 r = -EPERM; 690 goto out_unlock; 691 } 692 693 readonly = amdgpu_ttm_tt_is_readonly(ttm); 694 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 695 ttm->num_pages, >t->range, readonly, 696 true, NULL); 697 out_unlock: 698 mmap_read_unlock(mm); 699 if (r) 700 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 701 702 mmput(mm); 703 704 return r; 705 } 706 707 /* 708 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 709 * Check if the pages backing this ttm range have been invalidated 710 * 711 * Returns: true if pages are still valid 712 */ 713 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 714 { 715 struct amdgpu_ttm_tt *gtt = (void *)ttm; 716 bool r = false; 717 718 if (!gtt || !gtt->userptr) 719 return false; 720 721 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 722 gtt->userptr, ttm->num_pages); 723 724 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 725 "No user pages to check\n"); 726 727 if (gtt->range) { 728 /* 729 * FIXME: Must always hold notifier_lock for this, and must 730 * not ignore the return code. 731 */ 732 r = amdgpu_hmm_range_get_pages_done(gtt->range); 733 gtt->range = NULL; 734 } 735 736 return !r; 737 } 738 #endif 739 740 /* 741 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 742 * 743 * Called by amdgpu_cs_list_validate(). This creates the page list 744 * that backs user memory and will ultimately be mapped into the device 745 * address space. 746 */ 747 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 748 { 749 unsigned long i; 750 751 for (i = 0; i < ttm->num_pages; ++i) 752 ttm->pages[i] = pages ? pages[i] : NULL; 753 } 754 755 /* 756 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 757 * 758 * Called by amdgpu_ttm_backend_bind() 759 **/ 760 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 761 struct ttm_tt *ttm) 762 { 763 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 764 struct amdgpu_ttm_tt *gtt = (void *)ttm; 765 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 766 enum dma_data_direction direction = write ? 767 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 768 int r; 769 770 /* Allocate an SG array and squash pages into it */ 771 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 772 (u64)ttm->num_pages << PAGE_SHIFT, 773 GFP_KERNEL); 774 if (r) 775 goto release_sg; 776 777 /* Map SG to device */ 778 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 779 if (r) 780 goto release_sg; 781 782 /* convert SG to linear array of pages and dma addresses */ 783 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 784 ttm->num_pages); 785 786 return 0; 787 788 release_sg: 789 kfree(ttm->sg); 790 ttm->sg = NULL; 791 return r; 792 } 793 794 /* 795 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 796 */ 797 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 798 struct ttm_tt *ttm) 799 { 800 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 801 struct amdgpu_ttm_tt *gtt = (void *)ttm; 802 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 803 enum dma_data_direction direction = write ? 804 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 805 806 /* double check that we don't free the table twice */ 807 if (!ttm->sg || !ttm->sg->sgl) 808 return; 809 810 /* unmap the pages mapped to the device */ 811 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 812 sg_free_table(ttm->sg); 813 814 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 815 if (gtt->range) { 816 unsigned long i; 817 818 for (i = 0; i < ttm->num_pages; i++) { 819 if (ttm->pages[i] != 820 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 821 break; 822 } 823 824 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 825 } 826 #endif 827 } 828 829 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 830 struct ttm_buffer_object *tbo, 831 uint64_t flags) 832 { 833 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 834 struct ttm_tt *ttm = tbo->ttm; 835 struct amdgpu_ttm_tt *gtt = (void *)ttm; 836 int r; 837 838 if (amdgpu_bo_encrypted(abo)) 839 flags |= AMDGPU_PTE_TMZ; 840 841 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 842 uint64_t page_idx = 1; 843 844 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 845 gtt->ttm.dma_address, flags); 846 if (r) 847 goto gart_bind_fail; 848 849 /* The memory type of the first page defaults to UC. Now 850 * modify the memory type to NC from the second page of 851 * the BO onward. 852 */ 853 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 854 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 855 856 r = amdgpu_gart_bind(adev, 857 gtt->offset + (page_idx << PAGE_SHIFT), 858 ttm->num_pages - page_idx, 859 &(gtt->ttm.dma_address[page_idx]), flags); 860 } else { 861 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 862 gtt->ttm.dma_address, flags); 863 } 864 865 gart_bind_fail: 866 if (r) 867 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 868 ttm->num_pages, gtt->offset); 869 870 return r; 871 } 872 873 /* 874 * amdgpu_ttm_backend_bind - Bind GTT memory 875 * 876 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 877 * This handles binding GTT memory to the device address space. 878 */ 879 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 880 struct ttm_tt *ttm, 881 struct ttm_resource *bo_mem) 882 { 883 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 884 struct amdgpu_ttm_tt *gtt = (void*)ttm; 885 uint64_t flags; 886 int r = 0; 887 888 if (!bo_mem) 889 return -EINVAL; 890 891 if (gtt->bound) 892 return 0; 893 894 if (gtt->userptr) { 895 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 896 if (r) { 897 DRM_ERROR("failed to pin userptr\n"); 898 return r; 899 } 900 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 901 if (!ttm->sg) { 902 struct dma_buf_attachment *attach; 903 struct sg_table *sgt; 904 905 attach = gtt->gobj->import_attach; 906 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 907 if (IS_ERR(sgt)) 908 return PTR_ERR(sgt); 909 910 ttm->sg = sgt; 911 } 912 913 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 914 ttm->num_pages); 915 } 916 917 if (!ttm->num_pages) { 918 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 919 ttm->num_pages, bo_mem, ttm); 920 } 921 922 if (bo_mem->mem_type == AMDGPU_PL_GDS || 923 bo_mem->mem_type == AMDGPU_PL_GWS || 924 bo_mem->mem_type == AMDGPU_PL_OA) 925 return -EINVAL; 926 927 if (bo_mem->mem_type != TTM_PL_TT || 928 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 929 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 930 return 0; 931 } 932 933 /* compute PTE flags relevant to this BO memory */ 934 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 935 936 /* bind pages into GART page tables */ 937 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 938 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 939 gtt->ttm.dma_address, flags); 940 941 if (r) 942 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 943 ttm->num_pages, gtt->offset); 944 gtt->bound = true; 945 return r; 946 } 947 948 /* 949 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 950 * through AGP or GART aperture. 951 * 952 * If bo is accessible through AGP aperture, then use AGP aperture 953 * to access bo; otherwise allocate logical space in GART aperture 954 * and map bo to GART aperture. 955 */ 956 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 957 { 958 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 959 struct ttm_operation_ctx ctx = { false, false }; 960 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 961 struct ttm_placement placement; 962 struct ttm_place placements; 963 struct ttm_resource *tmp; 964 uint64_t addr, flags; 965 int r; 966 967 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 968 return 0; 969 970 addr = amdgpu_gmc_agp_addr(bo); 971 if (addr != AMDGPU_BO_INVALID_OFFSET) { 972 bo->resource->start = addr >> PAGE_SHIFT; 973 return 0; 974 } 975 976 /* allocate GART space */ 977 placement.num_placement = 1; 978 placement.placement = &placements; 979 placement.num_busy_placement = 1; 980 placement.busy_placement = &placements; 981 placements.fpfn = 0; 982 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 983 placements.mem_type = TTM_PL_TT; 984 placements.flags = bo->resource->placement; 985 986 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 987 if (unlikely(r)) 988 return r; 989 990 /* compute PTE flags for this buffer object */ 991 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 992 993 /* Bind pages */ 994 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 995 r = amdgpu_ttm_gart_bind(adev, bo, flags); 996 if (unlikely(r)) { 997 ttm_resource_free(bo, &tmp); 998 return r; 999 } 1000 1001 amdgpu_gart_invalidate_tlb(adev); 1002 ttm_resource_free(bo, &bo->resource); 1003 ttm_bo_assign_mem(bo, tmp); 1004 1005 return 0; 1006 } 1007 1008 /* 1009 * amdgpu_ttm_recover_gart - Rebind GTT pages 1010 * 1011 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1012 * rebind GTT pages during a GPU reset. 1013 */ 1014 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1015 { 1016 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1017 uint64_t flags; 1018 int r; 1019 1020 if (!tbo->ttm) 1021 return 0; 1022 1023 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1024 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1025 1026 return r; 1027 } 1028 1029 /* 1030 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1031 * 1032 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1033 * ttm_tt_destroy(). 1034 */ 1035 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1036 struct ttm_tt *ttm) 1037 { 1038 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1039 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1040 int r; 1041 1042 /* if the pages have userptr pinning then clear that first */ 1043 if (gtt->userptr) { 1044 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1045 } else if (ttm->sg && gtt->gobj->import_attach) { 1046 struct dma_buf_attachment *attach; 1047 1048 attach = gtt->gobj->import_attach; 1049 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1050 ttm->sg = NULL; 1051 } 1052 1053 if (!gtt->bound) 1054 return; 1055 1056 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1057 return; 1058 1059 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1060 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1061 if (r) 1062 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1063 gtt->ttm.num_pages, gtt->offset); 1064 gtt->bound = false; 1065 } 1066 1067 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1068 struct ttm_tt *ttm) 1069 { 1070 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1071 1072 if (gtt->usertask) 1073 put_task_struct(gtt->usertask); 1074 1075 ttm_tt_fini(>t->ttm); 1076 kfree(gtt); 1077 } 1078 1079 /** 1080 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1081 * 1082 * @bo: The buffer object to create a GTT ttm_tt object around 1083 * @page_flags: Page flags to be added to the ttm_tt object 1084 * 1085 * Called by ttm_tt_create(). 1086 */ 1087 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1088 uint32_t page_flags) 1089 { 1090 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1091 struct amdgpu_ttm_tt *gtt; 1092 enum ttm_caching caching; 1093 1094 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1095 if (gtt == NULL) { 1096 return NULL; 1097 } 1098 gtt->gobj = &bo->base; 1099 1100 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1101 caching = ttm_write_combined; 1102 else 1103 caching = ttm_cached; 1104 1105 /* allocate space for the uninitialized page entries */ 1106 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1107 kfree(gtt); 1108 return NULL; 1109 } 1110 return >t->ttm; 1111 } 1112 1113 /* 1114 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1115 * 1116 * Map the pages of a ttm_tt object to an address space visible 1117 * to the underlying device. 1118 */ 1119 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1120 struct ttm_tt *ttm, 1121 struct ttm_operation_ctx *ctx) 1122 { 1123 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1124 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1125 pgoff_t i; 1126 int ret; 1127 1128 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1129 if (gtt->userptr) { 1130 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1131 if (!ttm->sg) 1132 return -ENOMEM; 1133 return 0; 1134 } 1135 1136 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1137 return 0; 1138 1139 ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1140 if (ret) 1141 return ret; 1142 1143 for (i = 0; i < ttm->num_pages; ++i) 1144 ttm->pages[i]->mapping = bdev->dev_mapping; 1145 1146 return 0; 1147 } 1148 1149 /* 1150 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1151 * 1152 * Unmaps pages of a ttm_tt object from the device address space and 1153 * unpopulates the page array backing it. 1154 */ 1155 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1156 struct ttm_tt *ttm) 1157 { 1158 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1159 struct amdgpu_device *adev; 1160 pgoff_t i; 1161 1162 amdgpu_ttm_backend_unbind(bdev, ttm); 1163 1164 if (gtt->userptr) { 1165 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1166 kfree(ttm->sg); 1167 ttm->sg = NULL; 1168 return; 1169 } 1170 1171 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1172 return; 1173 1174 for (i = 0; i < ttm->num_pages; ++i) 1175 ttm->pages[i]->mapping = NULL; 1176 1177 adev = amdgpu_ttm_adev(bdev); 1178 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1179 } 1180 1181 /** 1182 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1183 * task 1184 * 1185 * @bo: The ttm_buffer_object to bind this userptr to 1186 * @addr: The address in the current tasks VM space to use 1187 * @flags: Requirements of userptr object. 1188 * 1189 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1190 * to current task 1191 */ 1192 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1193 uint64_t addr, uint32_t flags) 1194 { 1195 struct amdgpu_ttm_tt *gtt; 1196 1197 if (!bo->ttm) { 1198 /* TODO: We want a separate TTM object type for userptrs */ 1199 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1200 if (bo->ttm == NULL) 1201 return -ENOMEM; 1202 } 1203 1204 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1205 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1206 1207 gtt = (void *)bo->ttm; 1208 gtt->userptr = addr; 1209 gtt->userflags = flags; 1210 1211 if (gtt->usertask) 1212 put_task_struct(gtt->usertask); 1213 gtt->usertask = current->group_leader; 1214 get_task_struct(gtt->usertask); 1215 1216 return 0; 1217 } 1218 1219 /* 1220 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1221 */ 1222 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1223 { 1224 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1225 1226 if (gtt == NULL) 1227 return NULL; 1228 1229 if (gtt->usertask == NULL) 1230 return NULL; 1231 1232 return gtt->usertask->mm; 1233 } 1234 1235 /* 1236 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1237 * address range for the current task. 1238 * 1239 */ 1240 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1241 unsigned long end, unsigned long *userptr) 1242 { 1243 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1244 unsigned long size; 1245 1246 if (gtt == NULL || !gtt->userptr) 1247 return false; 1248 1249 /* Return false if no part of the ttm_tt object lies within 1250 * the range 1251 */ 1252 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1253 if (gtt->userptr > end || gtt->userptr + size <= start) 1254 return false; 1255 1256 if (userptr) 1257 *userptr = gtt->userptr; 1258 return true; 1259 } 1260 1261 /* 1262 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1263 */ 1264 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1265 { 1266 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1267 1268 if (gtt == NULL || !gtt->userptr) 1269 return false; 1270 1271 return true; 1272 } 1273 1274 /* 1275 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1276 */ 1277 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1278 { 1279 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1280 1281 if (gtt == NULL) 1282 return false; 1283 1284 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1285 } 1286 1287 /** 1288 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1289 * 1290 * @ttm: The ttm_tt object to compute the flags for 1291 * @mem: The memory registry backing this ttm_tt object 1292 * 1293 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1294 */ 1295 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1296 { 1297 uint64_t flags = 0; 1298 1299 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1300 flags |= AMDGPU_PTE_VALID; 1301 1302 if (mem && (mem->mem_type == TTM_PL_TT || 1303 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1304 flags |= AMDGPU_PTE_SYSTEM; 1305 1306 if (ttm->caching == ttm_cached) 1307 flags |= AMDGPU_PTE_SNOOPED; 1308 } 1309 1310 if (mem && mem->mem_type == TTM_PL_VRAM && 1311 mem->bus.caching == ttm_cached) 1312 flags |= AMDGPU_PTE_SNOOPED; 1313 1314 return flags; 1315 } 1316 1317 /** 1318 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1319 * 1320 * @adev: amdgpu_device pointer 1321 * @ttm: The ttm_tt object to compute the flags for 1322 * @mem: The memory registry backing this ttm_tt object 1323 * 1324 * Figure out the flags to use for a VM PTE (Page Table Entry). 1325 */ 1326 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1327 struct ttm_resource *mem) 1328 { 1329 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1330 1331 flags |= adev->gart.gart_pte_flags; 1332 flags |= AMDGPU_PTE_READABLE; 1333 1334 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1335 flags |= AMDGPU_PTE_WRITEABLE; 1336 1337 return flags; 1338 } 1339 1340 /* 1341 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1342 * object. 1343 * 1344 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1345 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1346 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1347 * used to clean out a memory space. 1348 */ 1349 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1350 const struct ttm_place *place) 1351 { 1352 unsigned long num_pages = bo->resource->num_pages; 1353 struct amdgpu_res_cursor cursor; 1354 struct dma_resv_list *flist; 1355 struct dma_fence *f; 1356 int i; 1357 1358 /* Swapout? */ 1359 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1360 return true; 1361 1362 if (bo->type == ttm_bo_type_kernel && 1363 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1364 return false; 1365 1366 /* If bo is a KFD BO, check if the bo belongs to the current process. 1367 * If true, then return false as any KFD process needs all its BOs to 1368 * be resident to run successfully 1369 */ 1370 flist = dma_resv_shared_list(bo->base.resv); 1371 if (flist) { 1372 for (i = 0; i < flist->shared_count; ++i) { 1373 f = rcu_dereference_protected(flist->shared[i], 1374 dma_resv_held(bo->base.resv)); 1375 if (amdkfd_fence_check_mm(f, current->mm)) 1376 return false; 1377 } 1378 } 1379 1380 switch (bo->resource->mem_type) { 1381 case AMDGPU_PL_PREEMPT: 1382 /* Preemptible BOs don't own system resources managed by the 1383 * driver (pages, VRAM, GART space). They point to resources 1384 * owned by someone else (e.g. pageable memory in user mode 1385 * or a DMABuf). They are used in a preemptible context so we 1386 * can guarantee no deadlocks and good QoS in case of MMU 1387 * notifiers or DMABuf move notifiers from the resource owner. 1388 */ 1389 return false; 1390 case TTM_PL_TT: 1391 if (amdgpu_bo_is_amdgpu_bo(bo) && 1392 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1393 return false; 1394 return true; 1395 1396 case TTM_PL_VRAM: 1397 /* Check each drm MM node individually */ 1398 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1399 &cursor); 1400 while (cursor.remaining) { 1401 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1402 && !(place->lpfn && 1403 place->lpfn <= PFN_DOWN(cursor.start))) 1404 return true; 1405 1406 amdgpu_res_next(&cursor, cursor.size); 1407 } 1408 return false; 1409 1410 default: 1411 break; 1412 } 1413 1414 return ttm_bo_eviction_valuable(bo, place); 1415 } 1416 1417 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1418 void *buf, size_t size, bool write) 1419 { 1420 while (size) { 1421 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1422 uint64_t bytes = 4 - (pos & 0x3); 1423 uint32_t shift = (pos & 0x3) * 8; 1424 uint32_t mask = 0xffffffff << shift; 1425 uint32_t value = 0; 1426 1427 if (size < bytes) { 1428 mask &= 0xffffffff >> (bytes - size) * 8; 1429 bytes = size; 1430 } 1431 1432 if (mask != 0xffffffff) { 1433 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1434 if (write) { 1435 value &= ~mask; 1436 value |= (*(uint32_t *)buf << shift) & mask; 1437 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1438 } else { 1439 value = (value & mask) >> shift; 1440 memcpy(buf, &value, bytes); 1441 } 1442 } else { 1443 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1444 } 1445 1446 pos += bytes; 1447 buf += bytes; 1448 size -= bytes; 1449 } 1450 } 1451 1452 /** 1453 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1454 * 1455 * @bo: The buffer object to read/write 1456 * @offset: Offset into buffer object 1457 * @buf: Secondary buffer to write/read from 1458 * @len: Length in bytes of access 1459 * @write: true if writing 1460 * 1461 * This is used to access VRAM that backs a buffer object via MMIO 1462 * access for debugging purposes. 1463 */ 1464 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1465 unsigned long offset, void *buf, int len, 1466 int write) 1467 { 1468 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1469 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1470 struct amdgpu_res_cursor cursor; 1471 int ret = 0; 1472 1473 if (bo->resource->mem_type != TTM_PL_VRAM) 1474 return -EIO; 1475 1476 amdgpu_res_first(bo->resource, offset, len, &cursor); 1477 while (cursor.remaining) { 1478 size_t count, size = cursor.size; 1479 loff_t pos = cursor.start; 1480 1481 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1482 size -= count; 1483 if (size) { 1484 /* using MM to access rest vram and handle un-aligned address */ 1485 pos += count; 1486 buf += count; 1487 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1488 } 1489 1490 ret += cursor.size; 1491 buf += cursor.size; 1492 amdgpu_res_next(&cursor, cursor.size); 1493 } 1494 1495 return ret; 1496 } 1497 1498 static void 1499 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1500 { 1501 amdgpu_bo_move_notify(bo, false, NULL); 1502 } 1503 1504 static struct ttm_device_funcs amdgpu_bo_driver = { 1505 .ttm_tt_create = &amdgpu_ttm_tt_create, 1506 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1507 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1508 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1509 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1510 .evict_flags = &amdgpu_evict_flags, 1511 .move = &amdgpu_bo_move, 1512 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1513 .release_notify = &amdgpu_bo_release_notify, 1514 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1515 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1516 .access_memory = &amdgpu_ttm_access_memory, 1517 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1518 }; 1519 1520 /* 1521 * Firmware Reservation functions 1522 */ 1523 /** 1524 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1525 * 1526 * @adev: amdgpu_device pointer 1527 * 1528 * free fw reserved vram if it has been reserved. 1529 */ 1530 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1531 { 1532 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1533 NULL, &adev->mman.fw_vram_usage_va); 1534 } 1535 1536 /** 1537 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1538 * 1539 * @adev: amdgpu_device pointer 1540 * 1541 * create bo vram reservation from fw. 1542 */ 1543 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1544 { 1545 uint64_t vram_size = adev->gmc.visible_vram_size; 1546 1547 adev->mman.fw_vram_usage_va = NULL; 1548 adev->mman.fw_vram_usage_reserved_bo = NULL; 1549 1550 if (adev->mman.fw_vram_usage_size == 0 || 1551 adev->mman.fw_vram_usage_size > vram_size) 1552 return 0; 1553 1554 return amdgpu_bo_create_kernel_at(adev, 1555 adev->mman.fw_vram_usage_start_offset, 1556 adev->mman.fw_vram_usage_size, 1557 AMDGPU_GEM_DOMAIN_VRAM, 1558 &adev->mman.fw_vram_usage_reserved_bo, 1559 &adev->mman.fw_vram_usage_va); 1560 } 1561 1562 /* 1563 * Memoy training reservation functions 1564 */ 1565 1566 /** 1567 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1568 * 1569 * @adev: amdgpu_device pointer 1570 * 1571 * free memory training reserved vram if it has been reserved. 1572 */ 1573 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1574 { 1575 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1576 1577 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1578 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1579 ctx->c2p_bo = NULL; 1580 1581 return 0; 1582 } 1583 1584 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1585 { 1586 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1587 1588 memset(ctx, 0, sizeof(*ctx)); 1589 1590 ctx->c2p_train_data_offset = 1591 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1592 ctx->p2c_train_data_offset = 1593 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1594 ctx->train_data_size = 1595 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1596 1597 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1598 ctx->train_data_size, 1599 ctx->p2c_train_data_offset, 1600 ctx->c2p_train_data_offset); 1601 } 1602 1603 /* 1604 * reserve TMR memory at the top of VRAM which holds 1605 * IP Discovery data and is protected by PSP. 1606 */ 1607 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1608 { 1609 int ret; 1610 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1611 bool mem_train_support = false; 1612 1613 if (!amdgpu_sriov_vf(adev)) { 1614 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1615 mem_train_support = true; 1616 else 1617 DRM_DEBUG("memory training does not support!\n"); 1618 } 1619 1620 /* 1621 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1622 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1623 * 1624 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1625 * discovery data and G6 memory training data respectively 1626 */ 1627 adev->mman.discovery_tmr_size = 1628 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1629 if (!adev->mman.discovery_tmr_size) 1630 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1631 1632 if (mem_train_support) { 1633 /* reserve vram for mem train according to TMR location */ 1634 amdgpu_ttm_training_data_block_init(adev); 1635 ret = amdgpu_bo_create_kernel_at(adev, 1636 ctx->c2p_train_data_offset, 1637 ctx->train_data_size, 1638 AMDGPU_GEM_DOMAIN_VRAM, 1639 &ctx->c2p_bo, 1640 NULL); 1641 if (ret) { 1642 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1643 amdgpu_ttm_training_reserve_vram_fini(adev); 1644 return ret; 1645 } 1646 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1647 } 1648 1649 ret = amdgpu_bo_create_kernel_at(adev, 1650 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1651 adev->mman.discovery_tmr_size, 1652 AMDGPU_GEM_DOMAIN_VRAM, 1653 &adev->mman.discovery_memory, 1654 NULL); 1655 if (ret) { 1656 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1657 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1658 return ret; 1659 } 1660 1661 return 0; 1662 } 1663 1664 /* 1665 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1666 * gtt/vram related fields. 1667 * 1668 * This initializes all of the memory space pools that the TTM layer 1669 * will need such as the GTT space (system memory mapped to the device), 1670 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1671 * can be mapped per VMID. 1672 */ 1673 int amdgpu_ttm_init(struct amdgpu_device *adev) 1674 { 1675 uint64_t gtt_size; 1676 int r; 1677 u64 vis_vram_limit; 1678 1679 mutex_init(&adev->mman.gtt_window_lock); 1680 1681 /* No others user of address space so set it to 0 */ 1682 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1683 adev_to_drm(adev)->anon_inode->i_mapping, 1684 adev_to_drm(adev)->vma_offset_manager, 1685 adev->need_swiotlb, 1686 dma_addressing_limited(adev->dev)); 1687 if (r) { 1688 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1689 return r; 1690 } 1691 adev->mman.initialized = true; 1692 1693 /* Initialize VRAM pool with all of VRAM divided into pages */ 1694 r = amdgpu_vram_mgr_init(adev); 1695 if (r) { 1696 DRM_ERROR("Failed initializing VRAM heap.\n"); 1697 return r; 1698 } 1699 1700 /* Reduce size of CPU-visible VRAM if requested */ 1701 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1702 if (amdgpu_vis_vram_limit > 0 && 1703 vis_vram_limit <= adev->gmc.visible_vram_size) 1704 adev->gmc.visible_vram_size = vis_vram_limit; 1705 1706 /* Change the size here instead of the init above so only lpfn is affected */ 1707 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1708 #ifdef CONFIG_64BIT 1709 #ifdef CONFIG_X86 1710 if (adev->gmc.xgmi.connected_to_cpu) 1711 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1712 adev->gmc.visible_vram_size); 1713 1714 else 1715 #endif 1716 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1717 adev->gmc.visible_vram_size); 1718 #endif 1719 1720 /* 1721 *The reserved vram for firmware must be pinned to the specified 1722 *place on the VRAM, so reserve it early. 1723 */ 1724 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1725 if (r) { 1726 return r; 1727 } 1728 1729 /* 1730 * only NAVI10 and onwards ASIC support for IP discovery. 1731 * If IP discovery enabled, a block of memory should be 1732 * reserved for IP discovey. 1733 */ 1734 if (adev->mman.discovery_bin) { 1735 r = amdgpu_ttm_reserve_tmr(adev); 1736 if (r) 1737 return r; 1738 } 1739 1740 /* allocate memory as required for VGA 1741 * This is used for VGA emulation and pre-OS scanout buffers to 1742 * avoid display artifacts while transitioning between pre-OS 1743 * and driver. */ 1744 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1745 AMDGPU_GEM_DOMAIN_VRAM, 1746 &adev->mman.stolen_vga_memory, 1747 NULL); 1748 if (r) 1749 return r; 1750 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1751 adev->mman.stolen_extended_size, 1752 AMDGPU_GEM_DOMAIN_VRAM, 1753 &adev->mman.stolen_extended_memory, 1754 NULL); 1755 if (r) 1756 return r; 1757 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1758 adev->mman.stolen_reserved_size, 1759 AMDGPU_GEM_DOMAIN_VRAM, 1760 &adev->mman.stolen_reserved_memory, 1761 NULL); 1762 if (r) 1763 return r; 1764 1765 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1766 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1767 1768 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1769 * or whatever the user passed on module init */ 1770 if (amdgpu_gtt_size == -1) { 1771 struct sysinfo si; 1772 1773 si_meminfo(&si); 1774 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1775 adev->gmc.mc_vram_size), 1776 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1777 } 1778 else 1779 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1780 1781 /* Initialize GTT memory pool */ 1782 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1783 if (r) { 1784 DRM_ERROR("Failed initializing GTT heap.\n"); 1785 return r; 1786 } 1787 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1788 (unsigned)(gtt_size / (1024 * 1024))); 1789 1790 /* Initialize preemptible memory pool */ 1791 r = amdgpu_preempt_mgr_init(adev); 1792 if (r) { 1793 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1794 return r; 1795 } 1796 1797 /* Initialize various on-chip memory pools */ 1798 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1799 if (r) { 1800 DRM_ERROR("Failed initializing GDS heap.\n"); 1801 return r; 1802 } 1803 1804 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1805 if (r) { 1806 DRM_ERROR("Failed initializing gws heap.\n"); 1807 return r; 1808 } 1809 1810 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1811 if (r) { 1812 DRM_ERROR("Failed initializing oa heap.\n"); 1813 return r; 1814 } 1815 1816 return 0; 1817 } 1818 1819 /* 1820 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1821 */ 1822 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1823 { 1824 if (!adev->mman.initialized) 1825 return; 1826 1827 amdgpu_ttm_training_reserve_vram_fini(adev); 1828 /* return the stolen vga memory back to VRAM */ 1829 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1830 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1831 /* return the IP Discovery TMR memory back to VRAM */ 1832 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1833 if (adev->mman.stolen_reserved_size) 1834 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1835 NULL, NULL); 1836 amdgpu_ttm_fw_reserve_vram_fini(adev); 1837 1838 amdgpu_vram_mgr_fini(adev); 1839 amdgpu_gtt_mgr_fini(adev); 1840 amdgpu_preempt_mgr_fini(adev); 1841 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1842 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1843 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1844 ttm_device_fini(&adev->mman.bdev); 1845 adev->mman.initialized = false; 1846 DRM_INFO("amdgpu: ttm finalized\n"); 1847 } 1848 1849 /** 1850 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1851 * 1852 * @adev: amdgpu_device pointer 1853 * @enable: true when we can use buffer functions. 1854 * 1855 * Enable/disable use of buffer functions during suspend/resume. This should 1856 * only be called at bootup or when userspace isn't running. 1857 */ 1858 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1859 { 1860 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1861 uint64_t size; 1862 int r; 1863 1864 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1865 adev->mman.buffer_funcs_enabled == enable) 1866 return; 1867 1868 if (enable) { 1869 struct amdgpu_ring *ring; 1870 struct drm_gpu_scheduler *sched; 1871 1872 ring = adev->mman.buffer_funcs_ring; 1873 sched = &ring->sched; 1874 r = drm_sched_entity_init(&adev->mman.entity, 1875 DRM_SCHED_PRIORITY_KERNEL, &sched, 1876 1, NULL); 1877 if (r) { 1878 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1879 r); 1880 return; 1881 } 1882 } else { 1883 drm_sched_entity_destroy(&adev->mman.entity); 1884 dma_fence_put(man->move); 1885 man->move = NULL; 1886 } 1887 1888 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1889 if (enable) 1890 size = adev->gmc.real_vram_size; 1891 else 1892 size = adev->gmc.visible_vram_size; 1893 man->size = size >> PAGE_SHIFT; 1894 adev->mman.buffer_funcs_enabled = enable; 1895 } 1896 1897 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1898 uint64_t dst_offset, uint32_t byte_count, 1899 struct dma_resv *resv, 1900 struct dma_fence **fence, bool direct_submit, 1901 bool vm_needs_flush, bool tmz) 1902 { 1903 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1904 AMDGPU_IB_POOL_DELAYED; 1905 struct amdgpu_device *adev = ring->adev; 1906 struct amdgpu_job *job; 1907 1908 uint32_t max_bytes; 1909 unsigned num_loops, num_dw; 1910 unsigned i; 1911 int r; 1912 1913 if (direct_submit && !ring->sched.ready) { 1914 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1915 return -EINVAL; 1916 } 1917 1918 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1919 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1920 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1921 1922 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1923 if (r) 1924 return r; 1925 1926 if (vm_needs_flush) { 1927 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1928 adev->gmc.pdb0_bo : adev->gart.bo); 1929 job->vm_needs_flush = true; 1930 } 1931 if (resv) { 1932 r = amdgpu_sync_resv(adev, &job->sync, resv, 1933 AMDGPU_SYNC_ALWAYS, 1934 AMDGPU_FENCE_OWNER_UNDEFINED); 1935 if (r) { 1936 DRM_ERROR("sync failed (%d).\n", r); 1937 goto error_free; 1938 } 1939 } 1940 1941 for (i = 0; i < num_loops; i++) { 1942 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1943 1944 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1945 dst_offset, cur_size_in_bytes, tmz); 1946 1947 src_offset += cur_size_in_bytes; 1948 dst_offset += cur_size_in_bytes; 1949 byte_count -= cur_size_in_bytes; 1950 } 1951 1952 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1953 WARN_ON(job->ibs[0].length_dw > num_dw); 1954 if (direct_submit) 1955 r = amdgpu_job_submit_direct(job, ring, fence); 1956 else 1957 r = amdgpu_job_submit(job, &adev->mman.entity, 1958 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1959 if (r) 1960 goto error_free; 1961 1962 return r; 1963 1964 error_free: 1965 amdgpu_job_free(job); 1966 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1967 return r; 1968 } 1969 1970 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1971 uint32_t src_data, 1972 struct dma_resv *resv, 1973 struct dma_fence **fence) 1974 { 1975 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1976 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1977 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1978 1979 struct amdgpu_res_cursor cursor; 1980 unsigned int num_loops, num_dw; 1981 uint64_t num_bytes; 1982 1983 struct amdgpu_job *job; 1984 int r; 1985 1986 if (!adev->mman.buffer_funcs_enabled) { 1987 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1988 return -EINVAL; 1989 } 1990 1991 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) { 1992 DRM_ERROR("Trying to clear preemptible memory.\n"); 1993 return -EINVAL; 1994 } 1995 1996 if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1997 r = amdgpu_ttm_alloc_gart(&bo->tbo); 1998 if (r) 1999 return r; 2000 } 2001 2002 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; 2003 num_loops = 0; 2004 2005 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2006 while (cursor.remaining) { 2007 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 2008 amdgpu_res_next(&cursor, cursor.size); 2009 } 2010 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2011 2012 /* for IB padding */ 2013 num_dw += 64; 2014 2015 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2016 &job); 2017 if (r) 2018 return r; 2019 2020 if (resv) { 2021 r = amdgpu_sync_resv(adev, &job->sync, resv, 2022 AMDGPU_SYNC_ALWAYS, 2023 AMDGPU_FENCE_OWNER_UNDEFINED); 2024 if (r) { 2025 DRM_ERROR("sync failed (%d).\n", r); 2026 goto error_free; 2027 } 2028 } 2029 2030 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2031 while (cursor.remaining) { 2032 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2033 uint64_t dst_addr = cursor.start; 2034 2035 dst_addr += amdgpu_ttm_domain_start(adev, 2036 bo->tbo.resource->mem_type); 2037 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2038 cur_size); 2039 2040 amdgpu_res_next(&cursor, cur_size); 2041 } 2042 2043 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2044 WARN_ON(job->ibs[0].length_dw > num_dw); 2045 r = amdgpu_job_submit(job, &adev->mman.entity, 2046 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2047 if (r) 2048 goto error_free; 2049 2050 return 0; 2051 2052 error_free: 2053 amdgpu_job_free(job); 2054 return r; 2055 } 2056 2057 /** 2058 * amdgpu_ttm_evict_resources - evict memory buffers 2059 * @adev: amdgpu device object 2060 * @mem_type: evicted BO's memory type 2061 * 2062 * Evicts all @mem_type buffers on the lru list of the memory type. 2063 * 2064 * Returns: 2065 * 0 for success or a negative error code on failure. 2066 */ 2067 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2068 { 2069 struct ttm_resource_manager *man; 2070 2071 switch (mem_type) { 2072 case TTM_PL_VRAM: 2073 case TTM_PL_TT: 2074 case AMDGPU_PL_GWS: 2075 case AMDGPU_PL_GDS: 2076 case AMDGPU_PL_OA: 2077 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2078 break; 2079 default: 2080 DRM_ERROR("Trying to evict invalid memory type\n"); 2081 return -EINVAL; 2082 } 2083 2084 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2085 } 2086 2087 #if defined(CONFIG_DEBUG_FS) 2088 2089 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2090 { 2091 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2092 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2093 TTM_PL_VRAM); 2094 struct drm_printer p = drm_seq_file_printer(m); 2095 2096 man->func->debug(man, &p); 2097 return 0; 2098 } 2099 2100 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2101 { 2102 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2103 2104 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2105 } 2106 2107 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2108 { 2109 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2110 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2111 TTM_PL_TT); 2112 struct drm_printer p = drm_seq_file_printer(m); 2113 2114 man->func->debug(man, &p); 2115 return 0; 2116 } 2117 2118 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2119 { 2120 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2121 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2122 AMDGPU_PL_GDS); 2123 struct drm_printer p = drm_seq_file_printer(m); 2124 2125 man->func->debug(man, &p); 2126 return 0; 2127 } 2128 2129 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2130 { 2131 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2132 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2133 AMDGPU_PL_GWS); 2134 struct drm_printer p = drm_seq_file_printer(m); 2135 2136 man->func->debug(man, &p); 2137 return 0; 2138 } 2139 2140 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2141 { 2142 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2143 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2144 AMDGPU_PL_OA); 2145 struct drm_printer p = drm_seq_file_printer(m); 2146 2147 man->func->debug(man, &p); 2148 return 0; 2149 } 2150 2151 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2152 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2153 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2154 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2155 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2156 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2157 2158 /* 2159 * amdgpu_ttm_vram_read - Linear read access to VRAM 2160 * 2161 * Accesses VRAM via MMIO for debugging purposes. 2162 */ 2163 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2164 size_t size, loff_t *pos) 2165 { 2166 struct amdgpu_device *adev = file_inode(f)->i_private; 2167 ssize_t result = 0; 2168 2169 if (size & 0x3 || *pos & 0x3) 2170 return -EINVAL; 2171 2172 if (*pos >= adev->gmc.mc_vram_size) 2173 return -ENXIO; 2174 2175 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2176 while (size) { 2177 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2178 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2179 2180 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2181 if (copy_to_user(buf, value, bytes)) 2182 return -EFAULT; 2183 2184 result += bytes; 2185 buf += bytes; 2186 *pos += bytes; 2187 size -= bytes; 2188 } 2189 2190 return result; 2191 } 2192 2193 /* 2194 * amdgpu_ttm_vram_write - Linear write access to VRAM 2195 * 2196 * Accesses VRAM via MMIO for debugging purposes. 2197 */ 2198 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2199 size_t size, loff_t *pos) 2200 { 2201 struct amdgpu_device *adev = file_inode(f)->i_private; 2202 ssize_t result = 0; 2203 int r; 2204 2205 if (size & 0x3 || *pos & 0x3) 2206 return -EINVAL; 2207 2208 if (*pos >= adev->gmc.mc_vram_size) 2209 return -ENXIO; 2210 2211 while (size) { 2212 uint32_t value; 2213 2214 if (*pos >= adev->gmc.mc_vram_size) 2215 return result; 2216 2217 r = get_user(value, (uint32_t *)buf); 2218 if (r) 2219 return r; 2220 2221 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2222 2223 result += 4; 2224 buf += 4; 2225 *pos += 4; 2226 size -= 4; 2227 } 2228 2229 return result; 2230 } 2231 2232 static const struct file_operations amdgpu_ttm_vram_fops = { 2233 .owner = THIS_MODULE, 2234 .read = amdgpu_ttm_vram_read, 2235 .write = amdgpu_ttm_vram_write, 2236 .llseek = default_llseek, 2237 }; 2238 2239 /* 2240 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2241 * 2242 * This function is used to read memory that has been mapped to the 2243 * GPU and the known addresses are not physical addresses but instead 2244 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2245 */ 2246 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2247 size_t size, loff_t *pos) 2248 { 2249 struct amdgpu_device *adev = file_inode(f)->i_private; 2250 struct iommu_domain *dom; 2251 ssize_t result = 0; 2252 int r; 2253 2254 /* retrieve the IOMMU domain if any for this device */ 2255 dom = iommu_get_domain_for_dev(adev->dev); 2256 2257 while (size) { 2258 phys_addr_t addr = *pos & PAGE_MASK; 2259 loff_t off = *pos & ~PAGE_MASK; 2260 size_t bytes = PAGE_SIZE - off; 2261 unsigned long pfn; 2262 struct page *p; 2263 void *ptr; 2264 2265 bytes = bytes < size ? bytes : size; 2266 2267 /* Translate the bus address to a physical address. If 2268 * the domain is NULL it means there is no IOMMU active 2269 * and the address translation is the identity 2270 */ 2271 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2272 2273 pfn = addr >> PAGE_SHIFT; 2274 if (!pfn_valid(pfn)) 2275 return -EPERM; 2276 2277 p = pfn_to_page(pfn); 2278 if (p->mapping != adev->mman.bdev.dev_mapping) 2279 return -EPERM; 2280 2281 ptr = kmap(p); 2282 r = copy_to_user(buf, ptr + off, bytes); 2283 kunmap(p); 2284 if (r) 2285 return -EFAULT; 2286 2287 size -= bytes; 2288 *pos += bytes; 2289 result += bytes; 2290 } 2291 2292 return result; 2293 } 2294 2295 /* 2296 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2297 * 2298 * This function is used to write memory that has been mapped to the 2299 * GPU and the known addresses are not physical addresses but instead 2300 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2301 */ 2302 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2303 size_t size, loff_t *pos) 2304 { 2305 struct amdgpu_device *adev = file_inode(f)->i_private; 2306 struct iommu_domain *dom; 2307 ssize_t result = 0; 2308 int r; 2309 2310 dom = iommu_get_domain_for_dev(adev->dev); 2311 2312 while (size) { 2313 phys_addr_t addr = *pos & PAGE_MASK; 2314 loff_t off = *pos & ~PAGE_MASK; 2315 size_t bytes = PAGE_SIZE - off; 2316 unsigned long pfn; 2317 struct page *p; 2318 void *ptr; 2319 2320 bytes = bytes < size ? bytes : size; 2321 2322 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2323 2324 pfn = addr >> PAGE_SHIFT; 2325 if (!pfn_valid(pfn)) 2326 return -EPERM; 2327 2328 p = pfn_to_page(pfn); 2329 if (p->mapping != adev->mman.bdev.dev_mapping) 2330 return -EPERM; 2331 2332 ptr = kmap(p); 2333 r = copy_from_user(ptr + off, buf, bytes); 2334 kunmap(p); 2335 if (r) 2336 return -EFAULT; 2337 2338 size -= bytes; 2339 *pos += bytes; 2340 result += bytes; 2341 } 2342 2343 return result; 2344 } 2345 2346 static const struct file_operations amdgpu_ttm_iomem_fops = { 2347 .owner = THIS_MODULE, 2348 .read = amdgpu_iomem_read, 2349 .write = amdgpu_iomem_write, 2350 .llseek = default_llseek 2351 }; 2352 2353 #endif 2354 2355 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2356 { 2357 #if defined(CONFIG_DEBUG_FS) 2358 struct drm_minor *minor = adev_to_drm(adev)->primary; 2359 struct dentry *root = minor->debugfs_root; 2360 2361 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2362 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2363 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2364 &amdgpu_ttm_iomem_fops); 2365 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2366 &amdgpu_mm_vram_table_fops); 2367 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2368 &amdgpu_mm_tt_table_fops); 2369 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2370 &amdgpu_mm_gds_table_fops); 2371 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2372 &amdgpu_mm_gws_table_fops); 2373 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2374 &amdgpu_mm_oa_table_fops); 2375 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2376 &amdgpu_ttm_page_pool_fops); 2377 #endif 2378 } 2379