1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 45 #include <drm/ttm/ttm_bo_api.h> 46 #include <drm/ttm/ttm_bo_driver.h> 47 #include <drm/ttm/ttm_placement.h> 48 49 #include <drm/amdgpu_drm.h> 50 51 #include "amdgpu.h" 52 #include "amdgpu_object.h" 53 #include "amdgpu_trace.h" 54 #include "amdgpu_amdkfd.h" 55 #include "amdgpu_sdma.h" 56 #include "amdgpu_ras.h" 57 #include "amdgpu_atomfirmware.h" 58 #include "amdgpu_res_cursor.h" 59 #include "bif/bif_4_1_d.h" 60 61 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 62 63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 64 struct ttm_tt *ttm, 65 struct ttm_resource *bo_mem); 66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 67 struct ttm_tt *ttm); 68 69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 70 unsigned int type, 71 uint64_t size_in_page) 72 { 73 return ttm_range_man_init(&adev->mman.bdev, type, 74 false, size_in_page); 75 } 76 77 /** 78 * amdgpu_evict_flags - Compute placement flags 79 * 80 * @bo: The buffer object to evict 81 * @placement: Possible destination(s) for evicted BO 82 * 83 * Fill in placement data when ttm_bo_evict() is called 84 */ 85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 86 struct ttm_placement *placement) 87 { 88 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 89 struct amdgpu_bo *abo; 90 static const struct ttm_place placements = { 91 .fpfn = 0, 92 .lpfn = 0, 93 .mem_type = TTM_PL_SYSTEM, 94 .flags = 0 95 }; 96 97 /* Don't handle scatter gather BOs */ 98 if (bo->type == ttm_bo_type_sg) { 99 placement->num_placement = 0; 100 placement->num_busy_placement = 0; 101 return; 102 } 103 104 /* Object isn't an AMDGPU object so ignore */ 105 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 106 placement->placement = &placements; 107 placement->busy_placement = &placements; 108 placement->num_placement = 1; 109 placement->num_busy_placement = 1; 110 return; 111 } 112 113 abo = ttm_to_amdgpu_bo(bo); 114 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 115 struct dma_fence *fence; 116 struct dma_resv *resv = &bo->base._resv; 117 118 rcu_read_lock(); 119 fence = rcu_dereference(resv->fence_excl); 120 if (fence && !fence->ops->signaled) 121 dma_fence_enable_sw_signaling(fence); 122 123 placement->num_placement = 0; 124 placement->num_busy_placement = 0; 125 rcu_read_unlock(); 126 return; 127 } 128 129 switch (bo->resource->mem_type) { 130 case AMDGPU_PL_GDS: 131 case AMDGPU_PL_GWS: 132 case AMDGPU_PL_OA: 133 placement->num_placement = 0; 134 placement->num_busy_placement = 0; 135 return; 136 137 case TTM_PL_VRAM: 138 if (!adev->mman.buffer_funcs_enabled) { 139 /* Move to system memory */ 140 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 141 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 142 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 143 amdgpu_bo_in_cpu_visible_vram(abo)) { 144 145 /* Try evicting to the CPU inaccessible part of VRAM 146 * first, but only set GTT as busy placement, so this 147 * BO will be evicted to GTT rather than causing other 148 * BOs to be evicted from VRAM 149 */ 150 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 151 AMDGPU_GEM_DOMAIN_GTT); 152 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 153 abo->placements[0].lpfn = 0; 154 abo->placement.busy_placement = &abo->placements[1]; 155 abo->placement.num_busy_placement = 1; 156 } else { 157 /* Move to GTT memory */ 158 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 159 } 160 break; 161 case TTM_PL_TT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 /** 170 * amdgpu_ttm_map_buffer - Map memory into the GART windows 171 * @bo: buffer object to map 172 * @mem: memory object to map 173 * @mm_cur: range to map 174 * @num_pages: number of pages to map 175 * @window: which GART window to use 176 * @ring: DMA ring to use for the copy 177 * @tmz: if we should setup a TMZ enabled mapping 178 * @addr: resulting address inside the MC address space 179 * 180 * Setup one of the GART windows to access a specific piece of memory or return 181 * the physical address for local memory. 182 */ 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 184 struct ttm_resource *mem, 185 struct amdgpu_res_cursor *mm_cur, 186 unsigned num_pages, unsigned window, 187 struct amdgpu_ring *ring, bool tmz, 188 uint64_t *addr) 189 { 190 struct amdgpu_device *adev = ring->adev; 191 struct amdgpu_job *job; 192 unsigned num_dw, num_bytes; 193 struct dma_fence *fence; 194 uint64_t src_addr, dst_addr; 195 void *cpu_addr; 196 uint64_t flags; 197 unsigned int i; 198 int r; 199 200 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 201 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 202 203 /* Map only what can't be accessed directly */ 204 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 205 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 206 mm_cur->start; 207 return 0; 208 } 209 210 *addr = adev->gmc.gart_start; 211 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 212 AMDGPU_GPU_PAGE_SIZE; 213 *addr += mm_cur->start & ~PAGE_MASK; 214 215 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 216 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 217 218 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 219 AMDGPU_IB_POOL_DELAYED, &job); 220 if (r) 221 return r; 222 223 src_addr = num_dw * 4; 224 src_addr += job->ibs[0].gpu_addr; 225 226 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 227 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 228 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 229 dst_addr, num_bytes, false); 230 231 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 232 WARN_ON(job->ibs[0].length_dw > num_dw); 233 234 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 235 if (tmz) 236 flags |= AMDGPU_PTE_TMZ; 237 238 cpu_addr = &job->ibs[0].ptr[num_dw]; 239 240 if (mem->mem_type == TTM_PL_TT) { 241 dma_addr_t *dma_addr; 242 243 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 244 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 245 cpu_addr); 246 if (r) 247 goto error_free; 248 } else { 249 dma_addr_t dma_address; 250 251 dma_address = mm_cur->start; 252 dma_address += adev->vm_manager.vram_base_offset; 253 254 for (i = 0; i < num_pages; ++i) { 255 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 256 &dma_address, flags, cpu_addr); 257 if (r) 258 goto error_free; 259 260 dma_address += PAGE_SIZE; 261 } 262 } 263 264 r = amdgpu_job_submit(job, &adev->mman.entity, 265 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 266 if (r) 267 goto error_free; 268 269 dma_fence_put(fence); 270 271 return r; 272 273 error_free: 274 amdgpu_job_free(job); 275 return r; 276 } 277 278 /** 279 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 280 * @adev: amdgpu device 281 * @src: buffer/address where to read from 282 * @dst: buffer/address where to write to 283 * @size: number of bytes to copy 284 * @tmz: if a secure copy should be used 285 * @resv: resv object to sync to 286 * @f: Returns the last fence if multiple jobs are submitted. 287 * 288 * The function copies @size bytes from {src->mem + src->offset} to 289 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 290 * move and different for a BO to BO copy. 291 * 292 */ 293 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 294 const struct amdgpu_copy_mem *src, 295 const struct amdgpu_copy_mem *dst, 296 uint64_t size, bool tmz, 297 struct dma_resv *resv, 298 struct dma_fence **f) 299 { 300 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 301 AMDGPU_GPU_PAGE_SIZE); 302 303 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 304 struct amdgpu_res_cursor src_mm, dst_mm; 305 struct dma_fence *fence = NULL; 306 int r = 0; 307 308 if (!adev->mman.buffer_funcs_enabled) { 309 DRM_ERROR("Trying to move memory with ring turned off.\n"); 310 return -EINVAL; 311 } 312 313 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 314 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 315 316 mutex_lock(&adev->mman.gtt_window_lock); 317 while (src_mm.remaining) { 318 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 319 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 320 struct dma_fence *next; 321 uint32_t cur_size; 322 uint64_t from, to; 323 324 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 325 * begins at an offset, then adjust the size accordingly 326 */ 327 cur_size = max(src_page_offset, dst_page_offset); 328 cur_size = min(min3(src_mm.size, dst_mm.size, size), 329 (uint64_t)(GTT_MAX_BYTES - cur_size)); 330 331 /* Map src to window 0 and dst to window 1. */ 332 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 333 PFN_UP(cur_size + src_page_offset), 334 0, ring, tmz, &from); 335 if (r) 336 goto error; 337 338 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 339 PFN_UP(cur_size + dst_page_offset), 340 1, ring, tmz, &to); 341 if (r) 342 goto error; 343 344 r = amdgpu_copy_buffer(ring, from, to, cur_size, 345 resv, &next, false, true, tmz); 346 if (r) 347 goto error; 348 349 dma_fence_put(fence); 350 fence = next; 351 352 amdgpu_res_next(&src_mm, cur_size); 353 amdgpu_res_next(&dst_mm, cur_size); 354 } 355 error: 356 mutex_unlock(&adev->mman.gtt_window_lock); 357 if (f) 358 *f = dma_fence_get(fence); 359 dma_fence_put(fence); 360 return r; 361 } 362 363 /* 364 * amdgpu_move_blit - Copy an entire buffer to another buffer 365 * 366 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 367 * help move buffers to and from VRAM. 368 */ 369 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 370 bool evict, 371 struct ttm_resource *new_mem, 372 struct ttm_resource *old_mem) 373 { 374 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 375 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 376 struct amdgpu_copy_mem src, dst; 377 struct dma_fence *fence = NULL; 378 int r; 379 380 src.bo = bo; 381 dst.bo = bo; 382 src.mem = old_mem; 383 dst.mem = new_mem; 384 src.offset = 0; 385 dst.offset = 0; 386 387 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 388 new_mem->num_pages << PAGE_SHIFT, 389 amdgpu_bo_encrypted(abo), 390 bo->base.resv, &fence); 391 if (r) 392 goto error; 393 394 /* clear the space being freed */ 395 if (old_mem->mem_type == TTM_PL_VRAM && 396 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 397 struct dma_fence *wipe_fence = NULL; 398 399 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 400 NULL, &wipe_fence); 401 if (r) { 402 goto error; 403 } else if (wipe_fence) { 404 dma_fence_put(fence); 405 fence = wipe_fence; 406 } 407 } 408 409 /* Always block for VM page tables before committing the new location */ 410 if (bo->type == ttm_bo_type_kernel) 411 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 412 else 413 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 414 dma_fence_put(fence); 415 return r; 416 417 error: 418 if (fence) 419 dma_fence_wait(fence, false); 420 dma_fence_put(fence); 421 return r; 422 } 423 424 /* 425 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 426 * 427 * Called by amdgpu_bo_move() 428 */ 429 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 430 struct ttm_resource *mem) 431 { 432 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 433 struct amdgpu_res_cursor cursor; 434 435 if (mem->mem_type == TTM_PL_SYSTEM || 436 mem->mem_type == TTM_PL_TT) 437 return true; 438 if (mem->mem_type != TTM_PL_VRAM) 439 return false; 440 441 amdgpu_res_first(mem, 0, mem_size, &cursor); 442 443 /* ttm_resource_ioremap only supports contiguous memory */ 444 if (cursor.size != mem_size) 445 return false; 446 447 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 448 } 449 450 /* 451 * amdgpu_bo_move - Move a buffer object to a new memory location 452 * 453 * Called by ttm_bo_handle_move_mem() 454 */ 455 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 456 struct ttm_operation_ctx *ctx, 457 struct ttm_resource *new_mem, 458 struct ttm_place *hop) 459 { 460 struct amdgpu_device *adev; 461 struct amdgpu_bo *abo; 462 struct ttm_resource *old_mem = bo->resource; 463 int r; 464 465 if (new_mem->mem_type == TTM_PL_TT) { 466 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 467 if (r) 468 return r; 469 } 470 471 /* Can't move a pinned BO */ 472 abo = ttm_to_amdgpu_bo(bo); 473 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 474 return -EINVAL; 475 476 adev = amdgpu_ttm_adev(bo->bdev); 477 478 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 479 ttm_bo_move_null(bo, new_mem); 480 goto out; 481 } 482 if (old_mem->mem_type == TTM_PL_SYSTEM && 483 new_mem->mem_type == TTM_PL_TT) { 484 ttm_bo_move_null(bo, new_mem); 485 goto out; 486 } 487 if (old_mem->mem_type == TTM_PL_TT && 488 new_mem->mem_type == TTM_PL_SYSTEM) { 489 r = ttm_bo_wait_ctx(bo, ctx); 490 if (r) 491 return r; 492 493 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 494 ttm_resource_free(bo, bo->resource); 495 ttm_bo_assign_mem(bo, new_mem); 496 goto out; 497 } 498 499 if (old_mem->mem_type == AMDGPU_PL_GDS || 500 old_mem->mem_type == AMDGPU_PL_GWS || 501 old_mem->mem_type == AMDGPU_PL_OA || 502 new_mem->mem_type == AMDGPU_PL_GDS || 503 new_mem->mem_type == AMDGPU_PL_GWS || 504 new_mem->mem_type == AMDGPU_PL_OA) { 505 /* Nothing to save here */ 506 ttm_bo_move_null(bo, new_mem); 507 goto out; 508 } 509 510 if (adev->mman.buffer_funcs_enabled) { 511 if (((old_mem->mem_type == TTM_PL_SYSTEM && 512 new_mem->mem_type == TTM_PL_VRAM) || 513 (old_mem->mem_type == TTM_PL_VRAM && 514 new_mem->mem_type == TTM_PL_SYSTEM))) { 515 hop->fpfn = 0; 516 hop->lpfn = 0; 517 hop->mem_type = TTM_PL_TT; 518 hop->flags = 0; 519 return -EMULTIHOP; 520 } 521 522 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 523 } else { 524 r = -ENODEV; 525 } 526 527 if (r) { 528 /* Check that all memory is CPU accessible */ 529 if (!amdgpu_mem_visible(adev, old_mem) || 530 !amdgpu_mem_visible(adev, new_mem)) { 531 pr_err("Move buffer fallback to memcpy unavailable\n"); 532 return r; 533 } 534 535 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 536 if (r) 537 return r; 538 } 539 540 if (bo->type == ttm_bo_type_device && 541 new_mem->mem_type == TTM_PL_VRAM && 542 old_mem->mem_type != TTM_PL_VRAM) { 543 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 544 * accesses the BO after it's moved. 545 */ 546 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 547 } 548 549 out: 550 /* update statistics */ 551 atomic64_add(bo->base.size, &adev->num_bytes_moved); 552 amdgpu_bo_move_notify(bo, evict, new_mem); 553 return 0; 554 } 555 556 /* 557 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 558 * 559 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 560 */ 561 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 562 struct ttm_resource *mem) 563 { 564 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 565 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 566 567 switch (mem->mem_type) { 568 case TTM_PL_SYSTEM: 569 /* system memory */ 570 return 0; 571 case TTM_PL_TT: 572 break; 573 case TTM_PL_VRAM: 574 mem->bus.offset = mem->start << PAGE_SHIFT; 575 /* check if it's visible */ 576 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 577 return -EINVAL; 578 579 if (adev->mman.aper_base_kaddr && 580 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 581 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 582 mem->bus.offset; 583 584 mem->bus.offset += adev->gmc.aper_base; 585 mem->bus.is_iomem = true; 586 if (adev->gmc.xgmi.connected_to_cpu) 587 mem->bus.caching = ttm_cached; 588 else 589 mem->bus.caching = ttm_write_combined; 590 break; 591 default: 592 return -EINVAL; 593 } 594 return 0; 595 } 596 597 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 598 unsigned long page_offset) 599 { 600 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 601 struct amdgpu_res_cursor cursor; 602 603 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 604 &cursor); 605 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 606 } 607 608 /** 609 * amdgpu_ttm_domain_start - Returns GPU start address 610 * @adev: amdgpu device object 611 * @type: type of the memory 612 * 613 * Returns: 614 * GPU start address of a memory domain 615 */ 616 617 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 618 { 619 switch (type) { 620 case TTM_PL_TT: 621 return adev->gmc.gart_start; 622 case TTM_PL_VRAM: 623 return adev->gmc.vram_start; 624 } 625 626 return 0; 627 } 628 629 /* 630 * TTM backend functions. 631 */ 632 struct amdgpu_ttm_tt { 633 struct ttm_tt ttm; 634 struct drm_gem_object *gobj; 635 u64 offset; 636 uint64_t userptr; 637 struct task_struct *usertask; 638 uint32_t userflags; 639 bool bound; 640 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 641 struct hmm_range *range; 642 #endif 643 }; 644 645 #ifdef CONFIG_DRM_AMDGPU_USERPTR 646 /* 647 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 648 * memory and start HMM tracking CPU page table update 649 * 650 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 651 * once afterwards to stop HMM tracking 652 */ 653 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 654 { 655 struct ttm_tt *ttm = bo->tbo.ttm; 656 struct amdgpu_ttm_tt *gtt = (void *)ttm; 657 unsigned long start = gtt->userptr; 658 struct vm_area_struct *vma; 659 struct mm_struct *mm; 660 bool readonly; 661 int r = 0; 662 663 mm = bo->notifier.mm; 664 if (unlikely(!mm)) { 665 DRM_DEBUG_DRIVER("BO is not registered?\n"); 666 return -EFAULT; 667 } 668 669 /* Another get_user_pages is running at the same time?? */ 670 if (WARN_ON(gtt->range)) 671 return -EFAULT; 672 673 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 674 return -ESRCH; 675 676 mmap_read_lock(mm); 677 vma = find_vma(mm, start); 678 mmap_read_unlock(mm); 679 if (unlikely(!vma || start < vma->vm_start)) { 680 r = -EFAULT; 681 goto out_putmm; 682 } 683 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 684 vma->vm_file)) { 685 r = -EPERM; 686 goto out_putmm; 687 } 688 689 readonly = amdgpu_ttm_tt_is_readonly(ttm); 690 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 691 ttm->num_pages, >t->range, readonly, 692 false); 693 out_putmm: 694 mmput(mm); 695 696 return r; 697 } 698 699 /* 700 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 701 * Check if the pages backing this ttm range have been invalidated 702 * 703 * Returns: true if pages are still valid 704 */ 705 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 706 { 707 struct amdgpu_ttm_tt *gtt = (void *)ttm; 708 bool r = false; 709 710 if (!gtt || !gtt->userptr) 711 return false; 712 713 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 714 gtt->userptr, ttm->num_pages); 715 716 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 717 "No user pages to check\n"); 718 719 if (gtt->range) { 720 /* 721 * FIXME: Must always hold notifier_lock for this, and must 722 * not ignore the return code. 723 */ 724 r = amdgpu_hmm_range_get_pages_done(gtt->range); 725 gtt->range = NULL; 726 } 727 728 return !r; 729 } 730 #endif 731 732 /* 733 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 734 * 735 * Called by amdgpu_cs_list_validate(). This creates the page list 736 * that backs user memory and will ultimately be mapped into the device 737 * address space. 738 */ 739 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 740 { 741 unsigned long i; 742 743 for (i = 0; i < ttm->num_pages; ++i) 744 ttm->pages[i] = pages ? pages[i] : NULL; 745 } 746 747 /* 748 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 749 * 750 * Called by amdgpu_ttm_backend_bind() 751 **/ 752 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 753 struct ttm_tt *ttm) 754 { 755 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 756 struct amdgpu_ttm_tt *gtt = (void *)ttm; 757 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 758 enum dma_data_direction direction = write ? 759 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 760 int r; 761 762 /* Allocate an SG array and squash pages into it */ 763 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 764 (u64)ttm->num_pages << PAGE_SHIFT, 765 GFP_KERNEL); 766 if (r) 767 goto release_sg; 768 769 /* Map SG to device */ 770 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 771 if (r) 772 goto release_sg; 773 774 /* convert SG to linear array of pages and dma addresses */ 775 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 776 ttm->num_pages); 777 778 return 0; 779 780 release_sg: 781 kfree(ttm->sg); 782 ttm->sg = NULL; 783 return r; 784 } 785 786 /* 787 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 788 */ 789 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 790 struct ttm_tt *ttm) 791 { 792 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 793 struct amdgpu_ttm_tt *gtt = (void *)ttm; 794 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 795 enum dma_data_direction direction = write ? 796 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 797 798 /* double check that we don't free the table twice */ 799 if (!ttm->sg || !ttm->sg->sgl) 800 return; 801 802 /* unmap the pages mapped to the device */ 803 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 804 sg_free_table(ttm->sg); 805 806 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 807 if (gtt->range) { 808 unsigned long i; 809 810 for (i = 0; i < ttm->num_pages; i++) { 811 if (ttm->pages[i] != 812 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 813 break; 814 } 815 816 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 817 } 818 #endif 819 } 820 821 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 822 struct ttm_buffer_object *tbo, 823 uint64_t flags) 824 { 825 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 826 struct ttm_tt *ttm = tbo->ttm; 827 struct amdgpu_ttm_tt *gtt = (void *)ttm; 828 int r; 829 830 if (amdgpu_bo_encrypted(abo)) 831 flags |= AMDGPU_PTE_TMZ; 832 833 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 834 uint64_t page_idx = 1; 835 836 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 837 ttm->pages, gtt->ttm.dma_address, flags); 838 if (r) 839 goto gart_bind_fail; 840 841 /* The memory type of the first page defaults to UC. Now 842 * modify the memory type to NC from the second page of 843 * the BO onward. 844 */ 845 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 846 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 847 848 r = amdgpu_gart_bind(adev, 849 gtt->offset + (page_idx << PAGE_SHIFT), 850 ttm->num_pages - page_idx, 851 &ttm->pages[page_idx], 852 &(gtt->ttm.dma_address[page_idx]), flags); 853 } else { 854 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 855 ttm->pages, gtt->ttm.dma_address, flags); 856 } 857 858 gart_bind_fail: 859 if (r) 860 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 861 ttm->num_pages, gtt->offset); 862 863 return r; 864 } 865 866 /* 867 * amdgpu_ttm_backend_bind - Bind GTT memory 868 * 869 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 870 * This handles binding GTT memory to the device address space. 871 */ 872 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 873 struct ttm_tt *ttm, 874 struct ttm_resource *bo_mem) 875 { 876 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 877 struct amdgpu_ttm_tt *gtt = (void*)ttm; 878 uint64_t flags; 879 int r = 0; 880 881 if (!bo_mem) 882 return -EINVAL; 883 884 if (gtt->bound) 885 return 0; 886 887 if (gtt->userptr) { 888 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 889 if (r) { 890 DRM_ERROR("failed to pin userptr\n"); 891 return r; 892 } 893 } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 894 if (!ttm->sg) { 895 struct dma_buf_attachment *attach; 896 struct sg_table *sgt; 897 898 attach = gtt->gobj->import_attach; 899 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 900 if (IS_ERR(sgt)) 901 return PTR_ERR(sgt); 902 903 ttm->sg = sgt; 904 } 905 906 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 907 ttm->num_pages); 908 } 909 910 if (!ttm->num_pages) { 911 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 912 ttm->num_pages, bo_mem, ttm); 913 } 914 915 if (bo_mem->mem_type == AMDGPU_PL_GDS || 916 bo_mem->mem_type == AMDGPU_PL_GWS || 917 bo_mem->mem_type == AMDGPU_PL_OA) 918 return -EINVAL; 919 920 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 921 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 922 return 0; 923 } 924 925 /* compute PTE flags relevant to this BO memory */ 926 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 927 928 /* bind pages into GART page tables */ 929 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 930 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 931 ttm->pages, gtt->ttm.dma_address, flags); 932 933 if (r) 934 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 935 ttm->num_pages, gtt->offset); 936 gtt->bound = true; 937 return r; 938 } 939 940 /* 941 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 942 * through AGP or GART aperture. 943 * 944 * If bo is accessible through AGP aperture, then use AGP aperture 945 * to access bo; otherwise allocate logical space in GART aperture 946 * and map bo to GART aperture. 947 */ 948 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 949 { 950 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 951 struct ttm_operation_ctx ctx = { false, false }; 952 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 953 struct ttm_resource tmp; 954 struct ttm_placement placement; 955 struct ttm_place placements; 956 uint64_t addr, flags; 957 int r; 958 959 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 960 return 0; 961 962 addr = amdgpu_gmc_agp_addr(bo); 963 if (addr != AMDGPU_BO_INVALID_OFFSET) { 964 bo->resource->start = addr >> PAGE_SHIFT; 965 } else { 966 967 /* allocate GART space */ 968 placement.num_placement = 1; 969 placement.placement = &placements; 970 placement.num_busy_placement = 1; 971 placement.busy_placement = &placements; 972 placements.fpfn = 0; 973 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 974 placements.mem_type = TTM_PL_TT; 975 placements.flags = bo->resource->placement; 976 977 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 978 if (unlikely(r)) 979 return r; 980 981 /* compute PTE flags for this buffer object */ 982 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 983 984 /* Bind pages */ 985 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 986 r = amdgpu_ttm_gart_bind(adev, bo, flags); 987 if (unlikely(r)) { 988 ttm_resource_free(bo, &tmp); 989 return r; 990 } 991 992 ttm_resource_free(bo, bo->resource); 993 ttm_bo_assign_mem(bo, &tmp); 994 } 995 996 return 0; 997 } 998 999 /* 1000 * amdgpu_ttm_recover_gart - Rebind GTT pages 1001 * 1002 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1003 * rebind GTT pages during a GPU reset. 1004 */ 1005 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1006 { 1007 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1008 uint64_t flags; 1009 int r; 1010 1011 if (!tbo->ttm) 1012 return 0; 1013 1014 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1015 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1016 1017 return r; 1018 } 1019 1020 /* 1021 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1022 * 1023 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1024 * ttm_tt_destroy(). 1025 */ 1026 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1027 struct ttm_tt *ttm) 1028 { 1029 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1030 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1031 int r; 1032 1033 /* if the pages have userptr pinning then clear that first */ 1034 if (gtt->userptr) { 1035 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1036 } else if (ttm->sg && gtt->gobj->import_attach) { 1037 struct dma_buf_attachment *attach; 1038 1039 attach = gtt->gobj->import_attach; 1040 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1041 ttm->sg = NULL; 1042 } 1043 1044 if (!gtt->bound) 1045 return; 1046 1047 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1048 return; 1049 1050 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1051 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1052 if (r) 1053 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1054 gtt->ttm.num_pages, gtt->offset); 1055 gtt->bound = false; 1056 } 1057 1058 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1059 struct ttm_tt *ttm) 1060 { 1061 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1062 1063 amdgpu_ttm_backend_unbind(bdev, ttm); 1064 ttm_tt_destroy_common(bdev, ttm); 1065 if (gtt->usertask) 1066 put_task_struct(gtt->usertask); 1067 1068 ttm_tt_fini(>t->ttm); 1069 kfree(gtt); 1070 } 1071 1072 /** 1073 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1074 * 1075 * @bo: The buffer object to create a GTT ttm_tt object around 1076 * @page_flags: Page flags to be added to the ttm_tt object 1077 * 1078 * Called by ttm_tt_create(). 1079 */ 1080 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1081 uint32_t page_flags) 1082 { 1083 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1084 struct amdgpu_ttm_tt *gtt; 1085 enum ttm_caching caching; 1086 1087 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1088 if (gtt == NULL) { 1089 return NULL; 1090 } 1091 gtt->gobj = &bo->base; 1092 1093 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1094 caching = ttm_write_combined; 1095 else 1096 caching = ttm_cached; 1097 1098 /* allocate space for the uninitialized page entries */ 1099 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1100 kfree(gtt); 1101 return NULL; 1102 } 1103 return >t->ttm; 1104 } 1105 1106 /* 1107 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1108 * 1109 * Map the pages of a ttm_tt object to an address space visible 1110 * to the underlying device. 1111 */ 1112 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1113 struct ttm_tt *ttm, 1114 struct ttm_operation_ctx *ctx) 1115 { 1116 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1117 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1118 1119 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1120 if (gtt && gtt->userptr) { 1121 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1122 if (!ttm->sg) 1123 return -ENOMEM; 1124 1125 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1126 return 0; 1127 } 1128 1129 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1130 return 0; 1131 1132 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1133 } 1134 1135 /* 1136 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1137 * 1138 * Unmaps pages of a ttm_tt object from the device address space and 1139 * unpopulates the page array backing it. 1140 */ 1141 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1142 struct ttm_tt *ttm) 1143 { 1144 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1145 struct amdgpu_device *adev; 1146 1147 if (gtt && gtt->userptr) { 1148 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1149 kfree(ttm->sg); 1150 ttm->sg = NULL; 1151 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1152 return; 1153 } 1154 1155 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1156 return; 1157 1158 adev = amdgpu_ttm_adev(bdev); 1159 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1160 } 1161 1162 /** 1163 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1164 * task 1165 * 1166 * @bo: The ttm_buffer_object to bind this userptr to 1167 * @addr: The address in the current tasks VM space to use 1168 * @flags: Requirements of userptr object. 1169 * 1170 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1171 * to current task 1172 */ 1173 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1174 uint64_t addr, uint32_t flags) 1175 { 1176 struct amdgpu_ttm_tt *gtt; 1177 1178 if (!bo->ttm) { 1179 /* TODO: We want a separate TTM object type for userptrs */ 1180 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1181 if (bo->ttm == NULL) 1182 return -ENOMEM; 1183 } 1184 1185 gtt = (void *)bo->ttm; 1186 gtt->userptr = addr; 1187 gtt->userflags = flags; 1188 1189 if (gtt->usertask) 1190 put_task_struct(gtt->usertask); 1191 gtt->usertask = current->group_leader; 1192 get_task_struct(gtt->usertask); 1193 1194 return 0; 1195 } 1196 1197 /* 1198 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1199 */ 1200 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1201 { 1202 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1203 1204 if (gtt == NULL) 1205 return NULL; 1206 1207 if (gtt->usertask == NULL) 1208 return NULL; 1209 1210 return gtt->usertask->mm; 1211 } 1212 1213 /* 1214 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1215 * address range for the current task. 1216 * 1217 */ 1218 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1219 unsigned long end) 1220 { 1221 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1222 unsigned long size; 1223 1224 if (gtt == NULL || !gtt->userptr) 1225 return false; 1226 1227 /* Return false if no part of the ttm_tt object lies within 1228 * the range 1229 */ 1230 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1231 if (gtt->userptr > end || gtt->userptr + size <= start) 1232 return false; 1233 1234 return true; 1235 } 1236 1237 /* 1238 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1239 */ 1240 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1241 { 1242 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1243 1244 if (gtt == NULL || !gtt->userptr) 1245 return false; 1246 1247 return true; 1248 } 1249 1250 /* 1251 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1252 */ 1253 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1254 { 1255 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1256 1257 if (gtt == NULL) 1258 return false; 1259 1260 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1261 } 1262 1263 /** 1264 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1265 * 1266 * @ttm: The ttm_tt object to compute the flags for 1267 * @mem: The memory registry backing this ttm_tt object 1268 * 1269 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1270 */ 1271 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1272 { 1273 uint64_t flags = 0; 1274 1275 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1276 flags |= AMDGPU_PTE_VALID; 1277 1278 if (mem && mem->mem_type == TTM_PL_TT) { 1279 flags |= AMDGPU_PTE_SYSTEM; 1280 1281 if (ttm->caching == ttm_cached) 1282 flags |= AMDGPU_PTE_SNOOPED; 1283 } 1284 1285 if (mem && mem->mem_type == TTM_PL_VRAM && 1286 mem->bus.caching == ttm_cached) 1287 flags |= AMDGPU_PTE_SNOOPED; 1288 1289 return flags; 1290 } 1291 1292 /** 1293 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1294 * 1295 * @adev: amdgpu_device pointer 1296 * @ttm: The ttm_tt object to compute the flags for 1297 * @mem: The memory registry backing this ttm_tt object 1298 * 1299 * Figure out the flags to use for a VM PTE (Page Table Entry). 1300 */ 1301 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1302 struct ttm_resource *mem) 1303 { 1304 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1305 1306 flags |= adev->gart.gart_pte_flags; 1307 flags |= AMDGPU_PTE_READABLE; 1308 1309 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1310 flags |= AMDGPU_PTE_WRITEABLE; 1311 1312 return flags; 1313 } 1314 1315 /* 1316 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1317 * object. 1318 * 1319 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1320 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1321 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1322 * used to clean out a memory space. 1323 */ 1324 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1325 const struct ttm_place *place) 1326 { 1327 unsigned long num_pages = bo->resource->num_pages; 1328 struct amdgpu_res_cursor cursor; 1329 struct dma_resv_list *flist; 1330 struct dma_fence *f; 1331 int i; 1332 1333 if (bo->type == ttm_bo_type_kernel && 1334 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1335 return false; 1336 1337 /* If bo is a KFD BO, check if the bo belongs to the current process. 1338 * If true, then return false as any KFD process needs all its BOs to 1339 * be resident to run successfully 1340 */ 1341 flist = dma_resv_get_list(bo->base.resv); 1342 if (flist) { 1343 for (i = 0; i < flist->shared_count; ++i) { 1344 f = rcu_dereference_protected(flist->shared[i], 1345 dma_resv_held(bo->base.resv)); 1346 if (amdkfd_fence_check_mm(f, current->mm)) 1347 return false; 1348 } 1349 } 1350 1351 switch (bo->resource->mem_type) { 1352 case TTM_PL_TT: 1353 if (amdgpu_bo_is_amdgpu_bo(bo) && 1354 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1355 return false; 1356 return true; 1357 1358 case TTM_PL_VRAM: 1359 /* Check each drm MM node individually */ 1360 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1361 &cursor); 1362 while (cursor.remaining) { 1363 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1364 && !(place->lpfn && 1365 place->lpfn <= PFN_DOWN(cursor.start))) 1366 return true; 1367 1368 amdgpu_res_next(&cursor, cursor.size); 1369 } 1370 return false; 1371 1372 default: 1373 break; 1374 } 1375 1376 return ttm_bo_eviction_valuable(bo, place); 1377 } 1378 1379 /** 1380 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1381 * 1382 * @bo: The buffer object to read/write 1383 * @offset: Offset into buffer object 1384 * @buf: Secondary buffer to write/read from 1385 * @len: Length in bytes of access 1386 * @write: true if writing 1387 * 1388 * This is used to access VRAM that backs a buffer object via MMIO 1389 * access for debugging purposes. 1390 */ 1391 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1392 unsigned long offset, void *buf, int len, 1393 int write) 1394 { 1395 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1396 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1397 struct amdgpu_res_cursor cursor; 1398 unsigned long flags; 1399 uint32_t value = 0; 1400 int ret = 0; 1401 1402 if (bo->resource->mem_type != TTM_PL_VRAM) 1403 return -EIO; 1404 1405 amdgpu_res_first(bo->resource, offset, len, &cursor); 1406 while (cursor.remaining) { 1407 uint64_t aligned_pos = cursor.start & ~(uint64_t)3; 1408 uint64_t bytes = 4 - (cursor.start & 3); 1409 uint32_t shift = (cursor.start & 3) * 8; 1410 uint32_t mask = 0xffffffff << shift; 1411 1412 if (cursor.size < bytes) { 1413 mask &= 0xffffffff >> (bytes - cursor.size) * 8; 1414 bytes = cursor.size; 1415 } 1416 1417 if (mask != 0xffffffff) { 1418 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1419 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1420 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1421 value = RREG32_NO_KIQ(mmMM_DATA); 1422 if (write) { 1423 value &= ~mask; 1424 value |= (*(uint32_t *)buf << shift) & mask; 1425 WREG32_NO_KIQ(mmMM_DATA, value); 1426 } 1427 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1428 if (!write) { 1429 value = (value & mask) >> shift; 1430 memcpy(buf, &value, bytes); 1431 } 1432 } else { 1433 bytes = cursor.size & ~0x3ULL; 1434 amdgpu_device_vram_access(adev, cursor.start, 1435 (uint32_t *)buf, bytes, 1436 write); 1437 } 1438 1439 ret += bytes; 1440 buf = (uint8_t *)buf + bytes; 1441 amdgpu_res_next(&cursor, bytes); 1442 } 1443 1444 return ret; 1445 } 1446 1447 static void 1448 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1449 { 1450 amdgpu_bo_move_notify(bo, false, NULL); 1451 } 1452 1453 static struct ttm_device_funcs amdgpu_bo_driver = { 1454 .ttm_tt_create = &amdgpu_ttm_tt_create, 1455 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1456 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1457 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1458 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1459 .evict_flags = &amdgpu_evict_flags, 1460 .move = &amdgpu_bo_move, 1461 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1462 .release_notify = &amdgpu_bo_release_notify, 1463 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1464 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1465 .access_memory = &amdgpu_ttm_access_memory, 1466 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1467 }; 1468 1469 /* 1470 * Firmware Reservation functions 1471 */ 1472 /** 1473 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1474 * 1475 * @adev: amdgpu_device pointer 1476 * 1477 * free fw reserved vram if it has been reserved. 1478 */ 1479 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1480 { 1481 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1482 NULL, &adev->mman.fw_vram_usage_va); 1483 } 1484 1485 /** 1486 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1487 * 1488 * @adev: amdgpu_device pointer 1489 * 1490 * create bo vram reservation from fw. 1491 */ 1492 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1493 { 1494 uint64_t vram_size = adev->gmc.visible_vram_size; 1495 1496 adev->mman.fw_vram_usage_va = NULL; 1497 adev->mman.fw_vram_usage_reserved_bo = NULL; 1498 1499 if (adev->mman.fw_vram_usage_size == 0 || 1500 adev->mman.fw_vram_usage_size > vram_size) 1501 return 0; 1502 1503 return amdgpu_bo_create_kernel_at(adev, 1504 adev->mman.fw_vram_usage_start_offset, 1505 adev->mman.fw_vram_usage_size, 1506 AMDGPU_GEM_DOMAIN_VRAM, 1507 &adev->mman.fw_vram_usage_reserved_bo, 1508 &adev->mman.fw_vram_usage_va); 1509 } 1510 1511 /* 1512 * Memoy training reservation functions 1513 */ 1514 1515 /** 1516 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1517 * 1518 * @adev: amdgpu_device pointer 1519 * 1520 * free memory training reserved vram if it has been reserved. 1521 */ 1522 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1523 { 1524 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1525 1526 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1527 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1528 ctx->c2p_bo = NULL; 1529 1530 return 0; 1531 } 1532 1533 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1534 { 1535 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1536 1537 memset(ctx, 0, sizeof(*ctx)); 1538 1539 ctx->c2p_train_data_offset = 1540 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1541 ctx->p2c_train_data_offset = 1542 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1543 ctx->train_data_size = 1544 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1545 1546 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1547 ctx->train_data_size, 1548 ctx->p2c_train_data_offset, 1549 ctx->c2p_train_data_offset); 1550 } 1551 1552 /* 1553 * reserve TMR memory at the top of VRAM which holds 1554 * IP Discovery data and is protected by PSP. 1555 */ 1556 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1557 { 1558 int ret; 1559 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1560 bool mem_train_support = false; 1561 1562 if (!amdgpu_sriov_vf(adev)) { 1563 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1564 mem_train_support = true; 1565 else 1566 DRM_DEBUG("memory training does not support!\n"); 1567 } 1568 1569 /* 1570 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1571 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1572 * 1573 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1574 * discovery data and G6 memory training data respectively 1575 */ 1576 adev->mman.discovery_tmr_size = 1577 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1578 if (!adev->mman.discovery_tmr_size) 1579 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1580 1581 if (mem_train_support) { 1582 /* reserve vram for mem train according to TMR location */ 1583 amdgpu_ttm_training_data_block_init(adev); 1584 ret = amdgpu_bo_create_kernel_at(adev, 1585 ctx->c2p_train_data_offset, 1586 ctx->train_data_size, 1587 AMDGPU_GEM_DOMAIN_VRAM, 1588 &ctx->c2p_bo, 1589 NULL); 1590 if (ret) { 1591 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1592 amdgpu_ttm_training_reserve_vram_fini(adev); 1593 return ret; 1594 } 1595 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1596 } 1597 1598 ret = amdgpu_bo_create_kernel_at(adev, 1599 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1600 adev->mman.discovery_tmr_size, 1601 AMDGPU_GEM_DOMAIN_VRAM, 1602 &adev->mman.discovery_memory, 1603 NULL); 1604 if (ret) { 1605 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1606 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1607 return ret; 1608 } 1609 1610 return 0; 1611 } 1612 1613 /* 1614 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1615 * gtt/vram related fields. 1616 * 1617 * This initializes all of the memory space pools that the TTM layer 1618 * will need such as the GTT space (system memory mapped to the device), 1619 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1620 * can be mapped per VMID. 1621 */ 1622 int amdgpu_ttm_init(struct amdgpu_device *adev) 1623 { 1624 uint64_t gtt_size; 1625 int r; 1626 u64 vis_vram_limit; 1627 1628 mutex_init(&adev->mman.gtt_window_lock); 1629 1630 /* No others user of address space so set it to 0 */ 1631 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1632 adev_to_drm(adev)->anon_inode->i_mapping, 1633 adev_to_drm(adev)->vma_offset_manager, 1634 adev->need_swiotlb, 1635 dma_addressing_limited(adev->dev)); 1636 if (r) { 1637 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1638 return r; 1639 } 1640 adev->mman.initialized = true; 1641 1642 /* Initialize VRAM pool with all of VRAM divided into pages */ 1643 r = amdgpu_vram_mgr_init(adev); 1644 if (r) { 1645 DRM_ERROR("Failed initializing VRAM heap.\n"); 1646 return r; 1647 } 1648 1649 /* Reduce size of CPU-visible VRAM if requested */ 1650 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1651 if (amdgpu_vis_vram_limit > 0 && 1652 vis_vram_limit <= adev->gmc.visible_vram_size) 1653 adev->gmc.visible_vram_size = vis_vram_limit; 1654 1655 /* Change the size here instead of the init above so only lpfn is affected */ 1656 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1657 #ifdef CONFIG_64BIT 1658 #ifdef CONFIG_X86 1659 if (adev->gmc.xgmi.connected_to_cpu) 1660 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1661 adev->gmc.visible_vram_size); 1662 1663 else 1664 #endif 1665 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1666 adev->gmc.visible_vram_size); 1667 #endif 1668 1669 /* 1670 *The reserved vram for firmware must be pinned to the specified 1671 *place on the VRAM, so reserve it early. 1672 */ 1673 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1674 if (r) { 1675 return r; 1676 } 1677 1678 /* 1679 * only NAVI10 and onwards ASIC support for IP discovery. 1680 * If IP discovery enabled, a block of memory should be 1681 * reserved for IP discovey. 1682 */ 1683 if (adev->mman.discovery_bin) { 1684 r = amdgpu_ttm_reserve_tmr(adev); 1685 if (r) 1686 return r; 1687 } 1688 1689 /* allocate memory as required for VGA 1690 * This is used for VGA emulation and pre-OS scanout buffers to 1691 * avoid display artifacts while transitioning between pre-OS 1692 * and driver. */ 1693 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1694 AMDGPU_GEM_DOMAIN_VRAM, 1695 &adev->mman.stolen_vga_memory, 1696 NULL); 1697 if (r) 1698 return r; 1699 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1700 adev->mman.stolen_extended_size, 1701 AMDGPU_GEM_DOMAIN_VRAM, 1702 &adev->mman.stolen_extended_memory, 1703 NULL); 1704 if (r) 1705 return r; 1706 1707 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1708 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1709 1710 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1711 * or whatever the user passed on module init */ 1712 if (amdgpu_gtt_size == -1) { 1713 struct sysinfo si; 1714 1715 si_meminfo(&si); 1716 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1717 adev->gmc.mc_vram_size), 1718 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1719 } 1720 else 1721 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1722 1723 /* Initialize GTT memory pool */ 1724 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1725 if (r) { 1726 DRM_ERROR("Failed initializing GTT heap.\n"); 1727 return r; 1728 } 1729 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1730 (unsigned)(gtt_size / (1024 * 1024))); 1731 1732 /* Initialize various on-chip memory pools */ 1733 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1734 if (r) { 1735 DRM_ERROR("Failed initializing GDS heap.\n"); 1736 return r; 1737 } 1738 1739 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1740 if (r) { 1741 DRM_ERROR("Failed initializing gws heap.\n"); 1742 return r; 1743 } 1744 1745 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1746 if (r) { 1747 DRM_ERROR("Failed initializing oa heap.\n"); 1748 return r; 1749 } 1750 1751 return 0; 1752 } 1753 1754 /* 1755 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1756 */ 1757 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1758 { 1759 if (!adev->mman.initialized) 1760 return; 1761 1762 amdgpu_ttm_training_reserve_vram_fini(adev); 1763 /* return the stolen vga memory back to VRAM */ 1764 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1765 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1766 /* return the IP Discovery TMR memory back to VRAM */ 1767 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1768 amdgpu_ttm_fw_reserve_vram_fini(adev); 1769 1770 amdgpu_vram_mgr_fini(adev); 1771 amdgpu_gtt_mgr_fini(adev); 1772 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1773 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1774 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1775 ttm_device_fini(&adev->mman.bdev); 1776 adev->mman.initialized = false; 1777 DRM_INFO("amdgpu: ttm finalized\n"); 1778 } 1779 1780 /** 1781 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1782 * 1783 * @adev: amdgpu_device pointer 1784 * @enable: true when we can use buffer functions. 1785 * 1786 * Enable/disable use of buffer functions during suspend/resume. This should 1787 * only be called at bootup or when userspace isn't running. 1788 */ 1789 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1790 { 1791 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1792 uint64_t size; 1793 int r; 1794 1795 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1796 adev->mman.buffer_funcs_enabled == enable) 1797 return; 1798 1799 if (enable) { 1800 struct amdgpu_ring *ring; 1801 struct drm_gpu_scheduler *sched; 1802 1803 ring = adev->mman.buffer_funcs_ring; 1804 sched = &ring->sched; 1805 r = drm_sched_entity_init(&adev->mman.entity, 1806 DRM_SCHED_PRIORITY_KERNEL, &sched, 1807 1, NULL); 1808 if (r) { 1809 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1810 r); 1811 return; 1812 } 1813 } else { 1814 drm_sched_entity_destroy(&adev->mman.entity); 1815 dma_fence_put(man->move); 1816 man->move = NULL; 1817 } 1818 1819 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1820 if (enable) 1821 size = adev->gmc.real_vram_size; 1822 else 1823 size = adev->gmc.visible_vram_size; 1824 man->size = size >> PAGE_SHIFT; 1825 adev->mman.buffer_funcs_enabled = enable; 1826 } 1827 1828 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1829 uint64_t dst_offset, uint32_t byte_count, 1830 struct dma_resv *resv, 1831 struct dma_fence **fence, bool direct_submit, 1832 bool vm_needs_flush, bool tmz) 1833 { 1834 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1835 AMDGPU_IB_POOL_DELAYED; 1836 struct amdgpu_device *adev = ring->adev; 1837 struct amdgpu_job *job; 1838 1839 uint32_t max_bytes; 1840 unsigned num_loops, num_dw; 1841 unsigned i; 1842 int r; 1843 1844 if (direct_submit && !ring->sched.ready) { 1845 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1846 return -EINVAL; 1847 } 1848 1849 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1850 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1851 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1852 1853 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1854 if (r) 1855 return r; 1856 1857 if (vm_needs_flush) { 1858 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1859 adev->gmc.pdb0_bo : adev->gart.bo); 1860 job->vm_needs_flush = true; 1861 } 1862 if (resv) { 1863 r = amdgpu_sync_resv(adev, &job->sync, resv, 1864 AMDGPU_SYNC_ALWAYS, 1865 AMDGPU_FENCE_OWNER_UNDEFINED); 1866 if (r) { 1867 DRM_ERROR("sync failed (%d).\n", r); 1868 goto error_free; 1869 } 1870 } 1871 1872 for (i = 0; i < num_loops; i++) { 1873 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1874 1875 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1876 dst_offset, cur_size_in_bytes, tmz); 1877 1878 src_offset += cur_size_in_bytes; 1879 dst_offset += cur_size_in_bytes; 1880 byte_count -= cur_size_in_bytes; 1881 } 1882 1883 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1884 WARN_ON(job->ibs[0].length_dw > num_dw); 1885 if (direct_submit) 1886 r = amdgpu_job_submit_direct(job, ring, fence); 1887 else 1888 r = amdgpu_job_submit(job, &adev->mman.entity, 1889 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1890 if (r) 1891 goto error_free; 1892 1893 return r; 1894 1895 error_free: 1896 amdgpu_job_free(job); 1897 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1898 return r; 1899 } 1900 1901 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1902 uint32_t src_data, 1903 struct dma_resv *resv, 1904 struct dma_fence **fence) 1905 { 1906 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1907 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1908 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1909 1910 struct amdgpu_res_cursor cursor; 1911 unsigned int num_loops, num_dw; 1912 uint64_t num_bytes; 1913 1914 struct amdgpu_job *job; 1915 int r; 1916 1917 if (!adev->mman.buffer_funcs_enabled) { 1918 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1919 return -EINVAL; 1920 } 1921 1922 if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1923 r = amdgpu_ttm_alloc_gart(&bo->tbo); 1924 if (r) 1925 return r; 1926 } 1927 1928 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; 1929 num_loops = 0; 1930 1931 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 1932 while (cursor.remaining) { 1933 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 1934 amdgpu_res_next(&cursor, cursor.size); 1935 } 1936 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1937 1938 /* for IB padding */ 1939 num_dw += 64; 1940 1941 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1942 &job); 1943 if (r) 1944 return r; 1945 1946 if (resv) { 1947 r = amdgpu_sync_resv(adev, &job->sync, resv, 1948 AMDGPU_SYNC_ALWAYS, 1949 AMDGPU_FENCE_OWNER_UNDEFINED); 1950 if (r) { 1951 DRM_ERROR("sync failed (%d).\n", r); 1952 goto error_free; 1953 } 1954 } 1955 1956 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 1957 while (cursor.remaining) { 1958 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 1959 uint64_t dst_addr = cursor.start; 1960 1961 dst_addr += amdgpu_ttm_domain_start(adev, 1962 bo->tbo.resource->mem_type); 1963 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 1964 cur_size); 1965 1966 amdgpu_res_next(&cursor, cur_size); 1967 } 1968 1969 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1970 WARN_ON(job->ibs[0].length_dw > num_dw); 1971 r = amdgpu_job_submit(job, &adev->mman.entity, 1972 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1973 if (r) 1974 goto error_free; 1975 1976 return 0; 1977 1978 error_free: 1979 amdgpu_job_free(job); 1980 return r; 1981 } 1982 1983 #if defined(CONFIG_DEBUG_FS) 1984 1985 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 1986 { 1987 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1988 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 1989 TTM_PL_VRAM); 1990 struct drm_printer p = drm_seq_file_printer(m); 1991 1992 man->func->debug(man, &p); 1993 return 0; 1994 } 1995 1996 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 1997 { 1998 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1999 2000 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2001 } 2002 2003 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2004 { 2005 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2006 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2007 TTM_PL_TT); 2008 struct drm_printer p = drm_seq_file_printer(m); 2009 2010 man->func->debug(man, &p); 2011 return 0; 2012 } 2013 2014 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2015 { 2016 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2017 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2018 AMDGPU_PL_GDS); 2019 struct drm_printer p = drm_seq_file_printer(m); 2020 2021 man->func->debug(man, &p); 2022 return 0; 2023 } 2024 2025 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2026 { 2027 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2028 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2029 AMDGPU_PL_GWS); 2030 struct drm_printer p = drm_seq_file_printer(m); 2031 2032 man->func->debug(man, &p); 2033 return 0; 2034 } 2035 2036 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2037 { 2038 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2039 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2040 AMDGPU_PL_OA); 2041 struct drm_printer p = drm_seq_file_printer(m); 2042 2043 man->func->debug(man, &p); 2044 return 0; 2045 } 2046 2047 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2048 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2049 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2050 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2051 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2052 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2053 2054 /* 2055 * amdgpu_ttm_vram_read - Linear read access to VRAM 2056 * 2057 * Accesses VRAM via MMIO for debugging purposes. 2058 */ 2059 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2060 size_t size, loff_t *pos) 2061 { 2062 struct amdgpu_device *adev = file_inode(f)->i_private; 2063 ssize_t result = 0; 2064 2065 if (size & 0x3 || *pos & 0x3) 2066 return -EINVAL; 2067 2068 if (*pos >= adev->gmc.mc_vram_size) 2069 return -ENXIO; 2070 2071 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2072 while (size) { 2073 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2074 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2075 2076 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2077 if (copy_to_user(buf, value, bytes)) 2078 return -EFAULT; 2079 2080 result += bytes; 2081 buf += bytes; 2082 *pos += bytes; 2083 size -= bytes; 2084 } 2085 2086 return result; 2087 } 2088 2089 /* 2090 * amdgpu_ttm_vram_write - Linear write access to VRAM 2091 * 2092 * Accesses VRAM via MMIO for debugging purposes. 2093 */ 2094 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2095 size_t size, loff_t *pos) 2096 { 2097 struct amdgpu_device *adev = file_inode(f)->i_private; 2098 ssize_t result = 0; 2099 int r; 2100 2101 if (size & 0x3 || *pos & 0x3) 2102 return -EINVAL; 2103 2104 if (*pos >= adev->gmc.mc_vram_size) 2105 return -ENXIO; 2106 2107 while (size) { 2108 unsigned long flags; 2109 uint32_t value; 2110 2111 if (*pos >= adev->gmc.mc_vram_size) 2112 return result; 2113 2114 r = get_user(value, (uint32_t *)buf); 2115 if (r) 2116 return r; 2117 2118 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2119 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2120 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2121 WREG32_NO_KIQ(mmMM_DATA, value); 2122 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2123 2124 result += 4; 2125 buf += 4; 2126 *pos += 4; 2127 size -= 4; 2128 } 2129 2130 return result; 2131 } 2132 2133 static const struct file_operations amdgpu_ttm_vram_fops = { 2134 .owner = THIS_MODULE, 2135 .read = amdgpu_ttm_vram_read, 2136 .write = amdgpu_ttm_vram_write, 2137 .llseek = default_llseek, 2138 }; 2139 2140 /* 2141 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2142 * 2143 * This function is used to read memory that has been mapped to the 2144 * GPU and the known addresses are not physical addresses but instead 2145 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2146 */ 2147 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2148 size_t size, loff_t *pos) 2149 { 2150 struct amdgpu_device *adev = file_inode(f)->i_private; 2151 struct iommu_domain *dom; 2152 ssize_t result = 0; 2153 int r; 2154 2155 /* retrieve the IOMMU domain if any for this device */ 2156 dom = iommu_get_domain_for_dev(adev->dev); 2157 2158 while (size) { 2159 phys_addr_t addr = *pos & PAGE_MASK; 2160 loff_t off = *pos & ~PAGE_MASK; 2161 size_t bytes = PAGE_SIZE - off; 2162 unsigned long pfn; 2163 struct page *p; 2164 void *ptr; 2165 2166 bytes = bytes < size ? bytes : size; 2167 2168 /* Translate the bus address to a physical address. If 2169 * the domain is NULL it means there is no IOMMU active 2170 * and the address translation is the identity 2171 */ 2172 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2173 2174 pfn = addr >> PAGE_SHIFT; 2175 if (!pfn_valid(pfn)) 2176 return -EPERM; 2177 2178 p = pfn_to_page(pfn); 2179 if (p->mapping != adev->mman.bdev.dev_mapping) 2180 return -EPERM; 2181 2182 ptr = kmap(p); 2183 r = copy_to_user(buf, ptr + off, bytes); 2184 kunmap(p); 2185 if (r) 2186 return -EFAULT; 2187 2188 size -= bytes; 2189 *pos += bytes; 2190 result += bytes; 2191 } 2192 2193 return result; 2194 } 2195 2196 /* 2197 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2198 * 2199 * This function is used to write memory that has been mapped to the 2200 * GPU and the known addresses are not physical addresses but instead 2201 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2202 */ 2203 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2204 size_t size, loff_t *pos) 2205 { 2206 struct amdgpu_device *adev = file_inode(f)->i_private; 2207 struct iommu_domain *dom; 2208 ssize_t result = 0; 2209 int r; 2210 2211 dom = iommu_get_domain_for_dev(adev->dev); 2212 2213 while (size) { 2214 phys_addr_t addr = *pos & PAGE_MASK; 2215 loff_t off = *pos & ~PAGE_MASK; 2216 size_t bytes = PAGE_SIZE - off; 2217 unsigned long pfn; 2218 struct page *p; 2219 void *ptr; 2220 2221 bytes = bytes < size ? bytes : size; 2222 2223 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2224 2225 pfn = addr >> PAGE_SHIFT; 2226 if (!pfn_valid(pfn)) 2227 return -EPERM; 2228 2229 p = pfn_to_page(pfn); 2230 if (p->mapping != adev->mman.bdev.dev_mapping) 2231 return -EPERM; 2232 2233 ptr = kmap(p); 2234 r = copy_from_user(ptr + off, buf, bytes); 2235 kunmap(p); 2236 if (r) 2237 return -EFAULT; 2238 2239 size -= bytes; 2240 *pos += bytes; 2241 result += bytes; 2242 } 2243 2244 return result; 2245 } 2246 2247 static const struct file_operations amdgpu_ttm_iomem_fops = { 2248 .owner = THIS_MODULE, 2249 .read = amdgpu_iomem_read, 2250 .write = amdgpu_iomem_write, 2251 .llseek = default_llseek 2252 }; 2253 2254 #endif 2255 2256 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2257 { 2258 #if defined(CONFIG_DEBUG_FS) 2259 struct drm_minor *minor = adev_to_drm(adev)->primary; 2260 struct dentry *root = minor->debugfs_root; 2261 2262 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2263 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2264 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2265 &amdgpu_ttm_iomem_fops); 2266 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2267 &amdgpu_mm_vram_table_fops); 2268 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2269 &amdgpu_mm_tt_table_fops); 2270 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2271 &amdgpu_mm_gds_table_fops); 2272 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2273 &amdgpu_mm_gws_table_fops); 2274 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2275 &amdgpu_mm_oa_table_fops); 2276 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2277 &amdgpu_ttm_page_pool_fops); 2278 #endif 2279 } 2280