1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 #include <linux/module.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_range_manager.h> 50 51 #include <drm/amdgpu_drm.h> 52 53 #include "amdgpu.h" 54 #include "amdgpu_object.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_sdma.h" 58 #include "amdgpu_ras.h" 59 #include "amdgpu_atomfirmware.h" 60 #include "amdgpu_res_cursor.h" 61 #include "bif/bif_4_1_d.h" 62 63 MODULE_IMPORT_NS(DMA_BUF); 64 65 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 66 67 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 68 struct ttm_tt *ttm, 69 struct ttm_resource *bo_mem); 70 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 71 struct ttm_tt *ttm); 72 73 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 74 unsigned int type, 75 uint64_t size_in_page) 76 { 77 return ttm_range_man_init(&adev->mman.bdev, type, 78 false, size_in_page); 79 } 80 81 /** 82 * amdgpu_evict_flags - Compute placement flags 83 * 84 * @bo: The buffer object to evict 85 * @placement: Possible destination(s) for evicted BO 86 * 87 * Fill in placement data when ttm_bo_evict() is called 88 */ 89 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 90 struct ttm_placement *placement) 91 { 92 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 93 struct amdgpu_bo *abo; 94 static const struct ttm_place placements = { 95 .fpfn = 0, 96 .lpfn = 0, 97 .mem_type = TTM_PL_SYSTEM, 98 .flags = 0 99 }; 100 101 /* Don't handle scatter gather BOs */ 102 if (bo->type == ttm_bo_type_sg) { 103 placement->num_placement = 0; 104 placement->num_busy_placement = 0; 105 return; 106 } 107 108 /* Object isn't an AMDGPU object so ignore */ 109 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 110 placement->placement = &placements; 111 placement->busy_placement = &placements; 112 placement->num_placement = 1; 113 placement->num_busy_placement = 1; 114 return; 115 } 116 117 abo = ttm_to_amdgpu_bo(bo); 118 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 119 struct dma_fence *fence; 120 struct dma_resv *resv = &bo->base._resv; 121 122 rcu_read_lock(); 123 fence = rcu_dereference(resv->fence_excl); 124 if (fence && !fence->ops->signaled) 125 dma_fence_enable_sw_signaling(fence); 126 127 placement->num_placement = 0; 128 placement->num_busy_placement = 0; 129 rcu_read_unlock(); 130 return; 131 } 132 133 switch (bo->resource->mem_type) { 134 case AMDGPU_PL_GDS: 135 case AMDGPU_PL_GWS: 136 case AMDGPU_PL_OA: 137 placement->num_placement = 0; 138 placement->num_busy_placement = 0; 139 return; 140 141 case TTM_PL_VRAM: 142 if (!adev->mman.buffer_funcs_enabled) { 143 /* Move to system memory */ 144 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 145 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 146 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 147 amdgpu_bo_in_cpu_visible_vram(abo)) { 148 149 /* Try evicting to the CPU inaccessible part of VRAM 150 * first, but only set GTT as busy placement, so this 151 * BO will be evicted to GTT rather than causing other 152 * BOs to be evicted from VRAM 153 */ 154 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 155 AMDGPU_GEM_DOMAIN_GTT | 156 AMDGPU_GEM_DOMAIN_CPU); 157 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 158 abo->placements[0].lpfn = 0; 159 abo->placement.busy_placement = &abo->placements[1]; 160 abo->placement.num_busy_placement = 1; 161 } else { 162 /* Move to GTT memory */ 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 164 AMDGPU_GEM_DOMAIN_CPU); 165 } 166 break; 167 case TTM_PL_TT: 168 case AMDGPU_PL_PREEMPT: 169 default: 170 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 171 break; 172 } 173 *placement = abo->placement; 174 } 175 176 /** 177 * amdgpu_ttm_map_buffer - Map memory into the GART windows 178 * @bo: buffer object to map 179 * @mem: memory object to map 180 * @mm_cur: range to map 181 * @num_pages: number of pages to map 182 * @window: which GART window to use 183 * @ring: DMA ring to use for the copy 184 * @tmz: if we should setup a TMZ enabled mapping 185 * @addr: resulting address inside the MC address space 186 * 187 * Setup one of the GART windows to access a specific piece of memory or return 188 * the physical address for local memory. 189 */ 190 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 191 struct ttm_resource *mem, 192 struct amdgpu_res_cursor *mm_cur, 193 unsigned num_pages, unsigned window, 194 struct amdgpu_ring *ring, bool tmz, 195 uint64_t *addr) 196 { 197 struct amdgpu_device *adev = ring->adev; 198 struct amdgpu_job *job; 199 unsigned num_dw, num_bytes; 200 struct dma_fence *fence; 201 uint64_t src_addr, dst_addr; 202 void *cpu_addr; 203 uint64_t flags; 204 unsigned int i; 205 int r; 206 207 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 208 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 209 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); 210 211 /* Map only what can't be accessed directly */ 212 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 213 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 214 mm_cur->start; 215 return 0; 216 } 217 218 *addr = adev->gmc.gart_start; 219 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 220 AMDGPU_GPU_PAGE_SIZE; 221 *addr += mm_cur->start & ~PAGE_MASK; 222 223 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 224 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 225 226 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 227 AMDGPU_IB_POOL_DELAYED, &job); 228 if (r) 229 return r; 230 231 src_addr = num_dw * 4; 232 src_addr += job->ibs[0].gpu_addr; 233 234 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 235 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 236 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 237 dst_addr, num_bytes, false); 238 239 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 240 WARN_ON(job->ibs[0].length_dw > num_dw); 241 242 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 243 if (tmz) 244 flags |= AMDGPU_PTE_TMZ; 245 246 cpu_addr = &job->ibs[0].ptr[num_dw]; 247 248 if (mem->mem_type == TTM_PL_TT) { 249 dma_addr_t *dma_addr; 250 251 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 252 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 253 cpu_addr); 254 if (r) 255 goto error_free; 256 } else { 257 dma_addr_t dma_address; 258 259 dma_address = mm_cur->start; 260 dma_address += adev->vm_manager.vram_base_offset; 261 262 for (i = 0; i < num_pages; ++i) { 263 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 264 &dma_address, flags, cpu_addr); 265 if (r) 266 goto error_free; 267 268 dma_address += PAGE_SIZE; 269 } 270 } 271 272 r = amdgpu_job_submit(job, &adev->mman.entity, 273 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 274 if (r) 275 goto error_free; 276 277 dma_fence_put(fence); 278 279 return r; 280 281 error_free: 282 amdgpu_job_free(job); 283 return r; 284 } 285 286 /** 287 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 288 * @adev: amdgpu device 289 * @src: buffer/address where to read from 290 * @dst: buffer/address where to write to 291 * @size: number of bytes to copy 292 * @tmz: if a secure copy should be used 293 * @resv: resv object to sync to 294 * @f: Returns the last fence if multiple jobs are submitted. 295 * 296 * The function copies @size bytes from {src->mem + src->offset} to 297 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 298 * move and different for a BO to BO copy. 299 * 300 */ 301 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 302 const struct amdgpu_copy_mem *src, 303 const struct amdgpu_copy_mem *dst, 304 uint64_t size, bool tmz, 305 struct dma_resv *resv, 306 struct dma_fence **f) 307 { 308 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 309 AMDGPU_GPU_PAGE_SIZE); 310 311 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 312 struct amdgpu_res_cursor src_mm, dst_mm; 313 struct dma_fence *fence = NULL; 314 int r = 0; 315 316 if (!adev->mman.buffer_funcs_enabled) { 317 DRM_ERROR("Trying to move memory with ring turned off.\n"); 318 return -EINVAL; 319 } 320 321 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 322 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 323 324 mutex_lock(&adev->mman.gtt_window_lock); 325 while (src_mm.remaining) { 326 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK; 327 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK; 328 struct dma_fence *next; 329 uint32_t cur_size; 330 uint64_t from, to; 331 332 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 333 * begins at an offset, then adjust the size accordingly 334 */ 335 cur_size = max(src_page_offset, dst_page_offset); 336 cur_size = min(min3(src_mm.size, dst_mm.size, size), 337 (uint64_t)(GTT_MAX_BYTES - cur_size)); 338 339 /* Map src to window 0 and dst to window 1. */ 340 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 341 PFN_UP(cur_size + src_page_offset), 342 0, ring, tmz, &from); 343 if (r) 344 goto error; 345 346 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 347 PFN_UP(cur_size + dst_page_offset), 348 1, ring, tmz, &to); 349 if (r) 350 goto error; 351 352 r = amdgpu_copy_buffer(ring, from, to, cur_size, 353 resv, &next, false, true, tmz); 354 if (r) 355 goto error; 356 357 dma_fence_put(fence); 358 fence = next; 359 360 amdgpu_res_next(&src_mm, cur_size); 361 amdgpu_res_next(&dst_mm, cur_size); 362 } 363 error: 364 mutex_unlock(&adev->mman.gtt_window_lock); 365 if (f) 366 *f = dma_fence_get(fence); 367 dma_fence_put(fence); 368 return r; 369 } 370 371 /* 372 * amdgpu_move_blit - Copy an entire buffer to another buffer 373 * 374 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 375 * help move buffers to and from VRAM. 376 */ 377 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 378 bool evict, 379 struct ttm_resource *new_mem, 380 struct ttm_resource *old_mem) 381 { 382 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 383 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 384 struct amdgpu_copy_mem src, dst; 385 struct dma_fence *fence = NULL; 386 int r; 387 388 src.bo = bo; 389 dst.bo = bo; 390 src.mem = old_mem; 391 dst.mem = new_mem; 392 src.offset = 0; 393 dst.offset = 0; 394 395 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 396 new_mem->num_pages << PAGE_SHIFT, 397 amdgpu_bo_encrypted(abo), 398 bo->base.resv, &fence); 399 if (r) 400 goto error; 401 402 /* clear the space being freed */ 403 if (old_mem->mem_type == TTM_PL_VRAM && 404 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 405 struct dma_fence *wipe_fence = NULL; 406 407 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 408 NULL, &wipe_fence); 409 if (r) { 410 goto error; 411 } else if (wipe_fence) { 412 dma_fence_put(fence); 413 fence = wipe_fence; 414 } 415 } 416 417 /* Always block for VM page tables before committing the new location */ 418 if (bo->type == ttm_bo_type_kernel) 419 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 420 else 421 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 422 dma_fence_put(fence); 423 return r; 424 425 error: 426 if (fence) 427 dma_fence_wait(fence, false); 428 dma_fence_put(fence); 429 return r; 430 } 431 432 /* 433 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 434 * 435 * Called by amdgpu_bo_move() 436 */ 437 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 438 struct ttm_resource *mem) 439 { 440 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 441 struct amdgpu_res_cursor cursor; 442 443 if (mem->mem_type == TTM_PL_SYSTEM || 444 mem->mem_type == TTM_PL_TT) 445 return true; 446 if (mem->mem_type != TTM_PL_VRAM) 447 return false; 448 449 amdgpu_res_first(mem, 0, mem_size, &cursor); 450 451 /* ttm_resource_ioremap only supports contiguous memory */ 452 if (cursor.size != mem_size) 453 return false; 454 455 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 456 } 457 458 /* 459 * amdgpu_bo_move - Move a buffer object to a new memory location 460 * 461 * Called by ttm_bo_handle_move_mem() 462 */ 463 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 464 struct ttm_operation_ctx *ctx, 465 struct ttm_resource *new_mem, 466 struct ttm_place *hop) 467 { 468 struct amdgpu_device *adev; 469 struct amdgpu_bo *abo; 470 struct ttm_resource *old_mem = bo->resource; 471 int r; 472 473 if (new_mem->mem_type == TTM_PL_TT || 474 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 475 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 476 if (r) 477 return r; 478 } 479 480 /* Can't move a pinned BO */ 481 abo = ttm_to_amdgpu_bo(bo); 482 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 483 return -EINVAL; 484 485 adev = amdgpu_ttm_adev(bo->bdev); 486 487 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 488 ttm_bo_move_null(bo, new_mem); 489 goto out; 490 } 491 if (old_mem->mem_type == TTM_PL_SYSTEM && 492 (new_mem->mem_type == TTM_PL_TT || 493 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 494 ttm_bo_move_null(bo, new_mem); 495 goto out; 496 } 497 if ((old_mem->mem_type == TTM_PL_TT || 498 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 499 new_mem->mem_type == TTM_PL_SYSTEM) { 500 r = ttm_bo_wait_ctx(bo, ctx); 501 if (r) 502 return r; 503 504 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 505 ttm_resource_free(bo, &bo->resource); 506 ttm_bo_assign_mem(bo, new_mem); 507 goto out; 508 } 509 510 if (old_mem->mem_type == AMDGPU_PL_GDS || 511 old_mem->mem_type == AMDGPU_PL_GWS || 512 old_mem->mem_type == AMDGPU_PL_OA || 513 new_mem->mem_type == AMDGPU_PL_GDS || 514 new_mem->mem_type == AMDGPU_PL_GWS || 515 new_mem->mem_type == AMDGPU_PL_OA) { 516 /* Nothing to save here */ 517 ttm_bo_move_null(bo, new_mem); 518 goto out; 519 } 520 521 if (bo->type == ttm_bo_type_device && 522 new_mem->mem_type == TTM_PL_VRAM && 523 old_mem->mem_type != TTM_PL_VRAM) { 524 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 525 * accesses the BO after it's moved. 526 */ 527 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 528 } 529 530 if (adev->mman.buffer_funcs_enabled) { 531 if (((old_mem->mem_type == TTM_PL_SYSTEM && 532 new_mem->mem_type == TTM_PL_VRAM) || 533 (old_mem->mem_type == TTM_PL_VRAM && 534 new_mem->mem_type == TTM_PL_SYSTEM))) { 535 hop->fpfn = 0; 536 hop->lpfn = 0; 537 hop->mem_type = TTM_PL_TT; 538 hop->flags = TTM_PL_FLAG_TEMPORARY; 539 return -EMULTIHOP; 540 } 541 542 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 543 } else { 544 r = -ENODEV; 545 } 546 547 if (r) { 548 /* Check that all memory is CPU accessible */ 549 if (!amdgpu_mem_visible(adev, old_mem) || 550 !amdgpu_mem_visible(adev, new_mem)) { 551 pr_err("Move buffer fallback to memcpy unavailable\n"); 552 return r; 553 } 554 555 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 556 if (r) 557 return r; 558 } 559 560 out: 561 /* update statistics */ 562 atomic64_add(bo->base.size, &adev->num_bytes_moved); 563 amdgpu_bo_move_notify(bo, evict, new_mem); 564 return 0; 565 } 566 567 /* 568 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 569 * 570 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 571 */ 572 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 573 struct ttm_resource *mem) 574 { 575 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 576 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 577 578 switch (mem->mem_type) { 579 case TTM_PL_SYSTEM: 580 /* system memory */ 581 return 0; 582 case TTM_PL_TT: 583 case AMDGPU_PL_PREEMPT: 584 break; 585 case TTM_PL_VRAM: 586 mem->bus.offset = mem->start << PAGE_SHIFT; 587 /* check if it's visible */ 588 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 589 return -EINVAL; 590 591 if (adev->mman.aper_base_kaddr && 592 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 593 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 594 mem->bus.offset; 595 596 mem->bus.offset += adev->gmc.aper_base; 597 mem->bus.is_iomem = true; 598 break; 599 default: 600 return -EINVAL; 601 } 602 return 0; 603 } 604 605 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 606 unsigned long page_offset) 607 { 608 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 609 struct amdgpu_res_cursor cursor; 610 611 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 612 &cursor); 613 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 614 } 615 616 /** 617 * amdgpu_ttm_domain_start - Returns GPU start address 618 * @adev: amdgpu device object 619 * @type: type of the memory 620 * 621 * Returns: 622 * GPU start address of a memory domain 623 */ 624 625 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 626 { 627 switch (type) { 628 case TTM_PL_TT: 629 return adev->gmc.gart_start; 630 case TTM_PL_VRAM: 631 return adev->gmc.vram_start; 632 } 633 634 return 0; 635 } 636 637 /* 638 * TTM backend functions. 639 */ 640 struct amdgpu_ttm_tt { 641 struct ttm_tt ttm; 642 struct drm_gem_object *gobj; 643 u64 offset; 644 uint64_t userptr; 645 struct task_struct *usertask; 646 uint32_t userflags; 647 bool bound; 648 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 649 struct hmm_range *range; 650 #endif 651 }; 652 653 #ifdef CONFIG_DRM_AMDGPU_USERPTR 654 /* 655 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 656 * memory and start HMM tracking CPU page table update 657 * 658 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 659 * once afterwards to stop HMM tracking 660 */ 661 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 662 { 663 struct ttm_tt *ttm = bo->tbo.ttm; 664 struct amdgpu_ttm_tt *gtt = (void *)ttm; 665 unsigned long start = gtt->userptr; 666 struct vm_area_struct *vma; 667 struct mm_struct *mm; 668 bool readonly; 669 int r = 0; 670 671 mm = bo->notifier.mm; 672 if (unlikely(!mm)) { 673 DRM_DEBUG_DRIVER("BO is not registered?\n"); 674 return -EFAULT; 675 } 676 677 /* Another get_user_pages is running at the same time?? */ 678 if (WARN_ON(gtt->range)) 679 return -EFAULT; 680 681 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 682 return -ESRCH; 683 684 mmap_read_lock(mm); 685 vma = vma_lookup(mm, start); 686 if (unlikely(!vma)) { 687 r = -EFAULT; 688 goto out_unlock; 689 } 690 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 691 vma->vm_file)) { 692 r = -EPERM; 693 goto out_unlock; 694 } 695 696 readonly = amdgpu_ttm_tt_is_readonly(ttm); 697 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 698 ttm->num_pages, >t->range, readonly, 699 true, NULL); 700 out_unlock: 701 mmap_read_unlock(mm); 702 mmput(mm); 703 704 return r; 705 } 706 707 /* 708 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 709 * Check if the pages backing this ttm range have been invalidated 710 * 711 * Returns: true if pages are still valid 712 */ 713 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 714 { 715 struct amdgpu_ttm_tt *gtt = (void *)ttm; 716 bool r = false; 717 718 if (!gtt || !gtt->userptr) 719 return false; 720 721 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 722 gtt->userptr, ttm->num_pages); 723 724 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 725 "No user pages to check\n"); 726 727 if (gtt->range) { 728 /* 729 * FIXME: Must always hold notifier_lock for this, and must 730 * not ignore the return code. 731 */ 732 r = amdgpu_hmm_range_get_pages_done(gtt->range); 733 gtt->range = NULL; 734 } 735 736 return !r; 737 } 738 #endif 739 740 /* 741 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 742 * 743 * Called by amdgpu_cs_list_validate(). This creates the page list 744 * that backs user memory and will ultimately be mapped into the device 745 * address space. 746 */ 747 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 748 { 749 unsigned long i; 750 751 for (i = 0; i < ttm->num_pages; ++i) 752 ttm->pages[i] = pages ? pages[i] : NULL; 753 } 754 755 /* 756 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 757 * 758 * Called by amdgpu_ttm_backend_bind() 759 **/ 760 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 761 struct ttm_tt *ttm) 762 { 763 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 764 struct amdgpu_ttm_tt *gtt = (void *)ttm; 765 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 766 enum dma_data_direction direction = write ? 767 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 768 int r; 769 770 /* Allocate an SG array and squash pages into it */ 771 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 772 (u64)ttm->num_pages << PAGE_SHIFT, 773 GFP_KERNEL); 774 if (r) 775 goto release_sg; 776 777 /* Map SG to device */ 778 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 779 if (r) 780 goto release_sg; 781 782 /* convert SG to linear array of pages and dma addresses */ 783 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 784 ttm->num_pages); 785 786 return 0; 787 788 release_sg: 789 kfree(ttm->sg); 790 ttm->sg = NULL; 791 return r; 792 } 793 794 /* 795 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 796 */ 797 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 798 struct ttm_tt *ttm) 799 { 800 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 801 struct amdgpu_ttm_tt *gtt = (void *)ttm; 802 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 803 enum dma_data_direction direction = write ? 804 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 805 806 /* double check that we don't free the table twice */ 807 if (!ttm->sg || !ttm->sg->sgl) 808 return; 809 810 /* unmap the pages mapped to the device */ 811 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 812 sg_free_table(ttm->sg); 813 814 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 815 if (gtt->range) { 816 unsigned long i; 817 818 for (i = 0; i < ttm->num_pages; i++) { 819 if (ttm->pages[i] != 820 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 821 break; 822 } 823 824 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 825 } 826 #endif 827 } 828 829 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 830 struct ttm_buffer_object *tbo, 831 uint64_t flags) 832 { 833 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 834 struct ttm_tt *ttm = tbo->ttm; 835 struct amdgpu_ttm_tt *gtt = (void *)ttm; 836 int r; 837 838 if (amdgpu_bo_encrypted(abo)) 839 flags |= AMDGPU_PTE_TMZ; 840 841 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 842 uint64_t page_idx = 1; 843 844 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 845 gtt->ttm.dma_address, flags); 846 if (r) 847 goto gart_bind_fail; 848 849 /* The memory type of the first page defaults to UC. Now 850 * modify the memory type to NC from the second page of 851 * the BO onward. 852 */ 853 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 854 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 855 856 r = amdgpu_gart_bind(adev, 857 gtt->offset + (page_idx << PAGE_SHIFT), 858 ttm->num_pages - page_idx, 859 &(gtt->ttm.dma_address[page_idx]), flags); 860 } else { 861 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 862 gtt->ttm.dma_address, flags); 863 } 864 865 gart_bind_fail: 866 if (r) 867 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 868 ttm->num_pages, gtt->offset); 869 870 return r; 871 } 872 873 /* 874 * amdgpu_ttm_backend_bind - Bind GTT memory 875 * 876 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 877 * This handles binding GTT memory to the device address space. 878 */ 879 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 880 struct ttm_tt *ttm, 881 struct ttm_resource *bo_mem) 882 { 883 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 884 struct amdgpu_ttm_tt *gtt = (void*)ttm; 885 uint64_t flags; 886 int r = 0; 887 888 if (!bo_mem) 889 return -EINVAL; 890 891 if (gtt->bound) 892 return 0; 893 894 if (gtt->userptr) { 895 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 896 if (r) { 897 DRM_ERROR("failed to pin userptr\n"); 898 return r; 899 } 900 } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 901 if (!ttm->sg) { 902 struct dma_buf_attachment *attach; 903 struct sg_table *sgt; 904 905 attach = gtt->gobj->import_attach; 906 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 907 if (IS_ERR(sgt)) 908 return PTR_ERR(sgt); 909 910 ttm->sg = sgt; 911 } 912 913 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 914 ttm->num_pages); 915 } 916 917 if (!ttm->num_pages) { 918 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 919 ttm->num_pages, bo_mem, ttm); 920 } 921 922 if (bo_mem->mem_type == AMDGPU_PL_GDS || 923 bo_mem->mem_type == AMDGPU_PL_GWS || 924 bo_mem->mem_type == AMDGPU_PL_OA) 925 return -EINVAL; 926 927 if (bo_mem->mem_type != TTM_PL_TT || 928 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 929 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 930 return 0; 931 } 932 933 /* compute PTE flags relevant to this BO memory */ 934 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 935 936 /* bind pages into GART page tables */ 937 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 938 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 939 gtt->ttm.dma_address, flags); 940 941 if (r) 942 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 943 ttm->num_pages, gtt->offset); 944 gtt->bound = true; 945 return r; 946 } 947 948 /* 949 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 950 * through AGP or GART aperture. 951 * 952 * If bo is accessible through AGP aperture, then use AGP aperture 953 * to access bo; otherwise allocate logical space in GART aperture 954 * and map bo to GART aperture. 955 */ 956 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 957 { 958 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 959 struct ttm_operation_ctx ctx = { false, false }; 960 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 961 struct ttm_placement placement; 962 struct ttm_place placements; 963 struct ttm_resource *tmp; 964 uint64_t addr, flags; 965 int r; 966 967 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 968 return 0; 969 970 addr = amdgpu_gmc_agp_addr(bo); 971 if (addr != AMDGPU_BO_INVALID_OFFSET) { 972 bo->resource->start = addr >> PAGE_SHIFT; 973 return 0; 974 } 975 976 /* allocate GART space */ 977 placement.num_placement = 1; 978 placement.placement = &placements; 979 placement.num_busy_placement = 1; 980 placement.busy_placement = &placements; 981 placements.fpfn = 0; 982 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 983 placements.mem_type = TTM_PL_TT; 984 placements.flags = bo->resource->placement; 985 986 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 987 if (unlikely(r)) 988 return r; 989 990 /* compute PTE flags for this buffer object */ 991 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 992 993 /* Bind pages */ 994 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 995 r = amdgpu_ttm_gart_bind(adev, bo, flags); 996 if (unlikely(r)) { 997 ttm_resource_free(bo, &tmp); 998 return r; 999 } 1000 1001 amdgpu_gart_invalidate_tlb(adev); 1002 ttm_resource_free(bo, &bo->resource); 1003 ttm_bo_assign_mem(bo, tmp); 1004 1005 return 0; 1006 } 1007 1008 /* 1009 * amdgpu_ttm_recover_gart - Rebind GTT pages 1010 * 1011 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1012 * rebind GTT pages during a GPU reset. 1013 */ 1014 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1015 { 1016 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1017 uint64_t flags; 1018 int r; 1019 1020 if (!tbo->ttm) 1021 return 0; 1022 1023 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1024 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1025 1026 return r; 1027 } 1028 1029 /* 1030 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1031 * 1032 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1033 * ttm_tt_destroy(). 1034 */ 1035 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1036 struct ttm_tt *ttm) 1037 { 1038 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1039 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1040 int r; 1041 1042 /* if the pages have userptr pinning then clear that first */ 1043 if (gtt->userptr) { 1044 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1045 } else if (ttm->sg && gtt->gobj->import_attach) { 1046 struct dma_buf_attachment *attach; 1047 1048 attach = gtt->gobj->import_attach; 1049 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1050 ttm->sg = NULL; 1051 } 1052 1053 if (!gtt->bound) 1054 return; 1055 1056 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1057 return; 1058 1059 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1060 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1061 if (r) 1062 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1063 gtt->ttm.num_pages, gtt->offset); 1064 gtt->bound = false; 1065 } 1066 1067 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1068 struct ttm_tt *ttm) 1069 { 1070 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1071 1072 amdgpu_ttm_backend_unbind(bdev, ttm); 1073 ttm_tt_destroy_common(bdev, ttm); 1074 if (gtt->usertask) 1075 put_task_struct(gtt->usertask); 1076 1077 ttm_tt_fini(>t->ttm); 1078 kfree(gtt); 1079 } 1080 1081 /** 1082 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1083 * 1084 * @bo: The buffer object to create a GTT ttm_tt object around 1085 * @page_flags: Page flags to be added to the ttm_tt object 1086 * 1087 * Called by ttm_tt_create(). 1088 */ 1089 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1090 uint32_t page_flags) 1091 { 1092 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1093 struct amdgpu_ttm_tt *gtt; 1094 enum ttm_caching caching; 1095 1096 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1097 if (gtt == NULL) { 1098 return NULL; 1099 } 1100 gtt->gobj = &bo->base; 1101 1102 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1103 caching = ttm_write_combined; 1104 else 1105 caching = ttm_cached; 1106 1107 /* allocate space for the uninitialized page entries */ 1108 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1109 kfree(gtt); 1110 return NULL; 1111 } 1112 return >t->ttm; 1113 } 1114 1115 /* 1116 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1117 * 1118 * Map the pages of a ttm_tt object to an address space visible 1119 * to the underlying device. 1120 */ 1121 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1122 struct ttm_tt *ttm, 1123 struct ttm_operation_ctx *ctx) 1124 { 1125 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1126 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1127 1128 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1129 if (gtt->userptr) { 1130 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1131 if (!ttm->sg) 1132 return -ENOMEM; 1133 return 0; 1134 } 1135 1136 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1137 return 0; 1138 1139 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1140 } 1141 1142 /* 1143 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1144 * 1145 * Unmaps pages of a ttm_tt object from the device address space and 1146 * unpopulates the page array backing it. 1147 */ 1148 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1149 struct ttm_tt *ttm) 1150 { 1151 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1152 struct amdgpu_device *adev; 1153 1154 if (gtt->userptr) { 1155 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1156 kfree(ttm->sg); 1157 ttm->sg = NULL; 1158 return; 1159 } 1160 1161 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1162 return; 1163 1164 adev = amdgpu_ttm_adev(bdev); 1165 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1166 } 1167 1168 /** 1169 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1170 * task 1171 * 1172 * @bo: The ttm_buffer_object to bind this userptr to 1173 * @addr: The address in the current tasks VM space to use 1174 * @flags: Requirements of userptr object. 1175 * 1176 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1177 * to current task 1178 */ 1179 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1180 uint64_t addr, uint32_t flags) 1181 { 1182 struct amdgpu_ttm_tt *gtt; 1183 1184 if (!bo->ttm) { 1185 /* TODO: We want a separate TTM object type for userptrs */ 1186 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1187 if (bo->ttm == NULL) 1188 return -ENOMEM; 1189 } 1190 1191 /* Set TTM_PAGE_FLAG_SG before populate but after create. */ 1192 bo->ttm->page_flags |= TTM_PAGE_FLAG_SG; 1193 1194 gtt = (void *)bo->ttm; 1195 gtt->userptr = addr; 1196 gtt->userflags = flags; 1197 1198 if (gtt->usertask) 1199 put_task_struct(gtt->usertask); 1200 gtt->usertask = current->group_leader; 1201 get_task_struct(gtt->usertask); 1202 1203 return 0; 1204 } 1205 1206 /* 1207 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1208 */ 1209 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1210 { 1211 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1212 1213 if (gtt == NULL) 1214 return NULL; 1215 1216 if (gtt->usertask == NULL) 1217 return NULL; 1218 1219 return gtt->usertask->mm; 1220 } 1221 1222 /* 1223 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1224 * address range for the current task. 1225 * 1226 */ 1227 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1228 unsigned long end) 1229 { 1230 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1231 unsigned long size; 1232 1233 if (gtt == NULL || !gtt->userptr) 1234 return false; 1235 1236 /* Return false if no part of the ttm_tt object lies within 1237 * the range 1238 */ 1239 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1240 if (gtt->userptr > end || gtt->userptr + size <= start) 1241 return false; 1242 1243 return true; 1244 } 1245 1246 /* 1247 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1248 */ 1249 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1250 { 1251 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1252 1253 if (gtt == NULL || !gtt->userptr) 1254 return false; 1255 1256 return true; 1257 } 1258 1259 /* 1260 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1261 */ 1262 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1263 { 1264 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1265 1266 if (gtt == NULL) 1267 return false; 1268 1269 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1270 } 1271 1272 /** 1273 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1274 * 1275 * @ttm: The ttm_tt object to compute the flags for 1276 * @mem: The memory registry backing this ttm_tt object 1277 * 1278 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1279 */ 1280 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1281 { 1282 uint64_t flags = 0; 1283 1284 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1285 flags |= AMDGPU_PTE_VALID; 1286 1287 if (mem && (mem->mem_type == TTM_PL_TT || 1288 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1289 flags |= AMDGPU_PTE_SYSTEM; 1290 1291 if (ttm->caching == ttm_cached) 1292 flags |= AMDGPU_PTE_SNOOPED; 1293 } 1294 1295 if (mem && mem->mem_type == TTM_PL_VRAM && 1296 mem->bus.caching == ttm_cached) 1297 flags |= AMDGPU_PTE_SNOOPED; 1298 1299 return flags; 1300 } 1301 1302 /** 1303 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1304 * 1305 * @adev: amdgpu_device pointer 1306 * @ttm: The ttm_tt object to compute the flags for 1307 * @mem: The memory registry backing this ttm_tt object 1308 * 1309 * Figure out the flags to use for a VM PTE (Page Table Entry). 1310 */ 1311 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1312 struct ttm_resource *mem) 1313 { 1314 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1315 1316 flags |= adev->gart.gart_pte_flags; 1317 flags |= AMDGPU_PTE_READABLE; 1318 1319 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1320 flags |= AMDGPU_PTE_WRITEABLE; 1321 1322 return flags; 1323 } 1324 1325 /* 1326 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1327 * object. 1328 * 1329 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1330 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1331 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1332 * used to clean out a memory space. 1333 */ 1334 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1335 const struct ttm_place *place) 1336 { 1337 unsigned long num_pages = bo->resource->num_pages; 1338 struct amdgpu_res_cursor cursor; 1339 struct dma_resv_list *flist; 1340 struct dma_fence *f; 1341 int i; 1342 1343 /* Swapout? */ 1344 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1345 return true; 1346 1347 if (bo->type == ttm_bo_type_kernel && 1348 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1349 return false; 1350 1351 /* If bo is a KFD BO, check if the bo belongs to the current process. 1352 * If true, then return false as any KFD process needs all its BOs to 1353 * be resident to run successfully 1354 */ 1355 flist = dma_resv_shared_list(bo->base.resv); 1356 if (flist) { 1357 for (i = 0; i < flist->shared_count; ++i) { 1358 f = rcu_dereference_protected(flist->shared[i], 1359 dma_resv_held(bo->base.resv)); 1360 if (amdkfd_fence_check_mm(f, current->mm)) 1361 return false; 1362 } 1363 } 1364 1365 switch (bo->resource->mem_type) { 1366 case AMDGPU_PL_PREEMPT: 1367 /* Preemptible BOs don't own system resources managed by the 1368 * driver (pages, VRAM, GART space). They point to resources 1369 * owned by someone else (e.g. pageable memory in user mode 1370 * or a DMABuf). They are used in a preemptible context so we 1371 * can guarantee no deadlocks and good QoS in case of MMU 1372 * notifiers or DMABuf move notifiers from the resource owner. 1373 */ 1374 return false; 1375 case TTM_PL_TT: 1376 if (amdgpu_bo_is_amdgpu_bo(bo) && 1377 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1378 return false; 1379 return true; 1380 1381 case TTM_PL_VRAM: 1382 /* Check each drm MM node individually */ 1383 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1384 &cursor); 1385 while (cursor.remaining) { 1386 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1387 && !(place->lpfn && 1388 place->lpfn <= PFN_DOWN(cursor.start))) 1389 return true; 1390 1391 amdgpu_res_next(&cursor, cursor.size); 1392 } 1393 return false; 1394 1395 default: 1396 break; 1397 } 1398 1399 return ttm_bo_eviction_valuable(bo, place); 1400 } 1401 1402 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1403 void *buf, size_t size, bool write) 1404 { 1405 while (size) { 1406 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1407 uint64_t bytes = 4 - (pos & 0x3); 1408 uint32_t shift = (pos & 0x3) * 8; 1409 uint32_t mask = 0xffffffff << shift; 1410 uint32_t value = 0; 1411 1412 if (size < bytes) { 1413 mask &= 0xffffffff >> (bytes - size) * 8; 1414 bytes = size; 1415 } 1416 1417 if (mask != 0xffffffff) { 1418 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1419 if (write) { 1420 value &= ~mask; 1421 value |= (*(uint32_t *)buf << shift) & mask; 1422 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1423 } else { 1424 value = (value & mask) >> shift; 1425 memcpy(buf, &value, bytes); 1426 } 1427 } else { 1428 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1429 } 1430 1431 pos += bytes; 1432 buf += bytes; 1433 size -= bytes; 1434 } 1435 } 1436 1437 /** 1438 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1439 * 1440 * @bo: The buffer object to read/write 1441 * @offset: Offset into buffer object 1442 * @buf: Secondary buffer to write/read from 1443 * @len: Length in bytes of access 1444 * @write: true if writing 1445 * 1446 * This is used to access VRAM that backs a buffer object via MMIO 1447 * access for debugging purposes. 1448 */ 1449 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1450 unsigned long offset, void *buf, int len, 1451 int write) 1452 { 1453 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1454 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1455 struct amdgpu_res_cursor cursor; 1456 int ret = 0; 1457 1458 if (bo->resource->mem_type != TTM_PL_VRAM) 1459 return -EIO; 1460 1461 amdgpu_res_first(bo->resource, offset, len, &cursor); 1462 while (cursor.remaining) { 1463 size_t count, size = cursor.size; 1464 loff_t pos = cursor.start; 1465 1466 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1467 size -= count; 1468 if (size) { 1469 /* using MM to access rest vram and handle un-aligned address */ 1470 pos += count; 1471 buf += count; 1472 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1473 } 1474 1475 ret += cursor.size; 1476 buf += cursor.size; 1477 amdgpu_res_next(&cursor, cursor.size); 1478 } 1479 1480 return ret; 1481 } 1482 1483 static void 1484 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1485 { 1486 amdgpu_bo_move_notify(bo, false, NULL); 1487 } 1488 1489 static struct ttm_device_funcs amdgpu_bo_driver = { 1490 .ttm_tt_create = &amdgpu_ttm_tt_create, 1491 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1492 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1493 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1494 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1495 .evict_flags = &amdgpu_evict_flags, 1496 .move = &amdgpu_bo_move, 1497 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1498 .release_notify = &amdgpu_bo_release_notify, 1499 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1500 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1501 .access_memory = &amdgpu_ttm_access_memory, 1502 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1503 }; 1504 1505 /* 1506 * Firmware Reservation functions 1507 */ 1508 /** 1509 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1510 * 1511 * @adev: amdgpu_device pointer 1512 * 1513 * free fw reserved vram if it has been reserved. 1514 */ 1515 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1516 { 1517 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1518 NULL, &adev->mman.fw_vram_usage_va); 1519 } 1520 1521 /** 1522 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1523 * 1524 * @adev: amdgpu_device pointer 1525 * 1526 * create bo vram reservation from fw. 1527 */ 1528 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1529 { 1530 uint64_t vram_size = adev->gmc.visible_vram_size; 1531 1532 adev->mman.fw_vram_usage_va = NULL; 1533 adev->mman.fw_vram_usage_reserved_bo = NULL; 1534 1535 if (adev->mman.fw_vram_usage_size == 0 || 1536 adev->mman.fw_vram_usage_size > vram_size) 1537 return 0; 1538 1539 return amdgpu_bo_create_kernel_at(adev, 1540 adev->mman.fw_vram_usage_start_offset, 1541 adev->mman.fw_vram_usage_size, 1542 AMDGPU_GEM_DOMAIN_VRAM, 1543 &adev->mman.fw_vram_usage_reserved_bo, 1544 &adev->mman.fw_vram_usage_va); 1545 } 1546 1547 /* 1548 * Memoy training reservation functions 1549 */ 1550 1551 /** 1552 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1553 * 1554 * @adev: amdgpu_device pointer 1555 * 1556 * free memory training reserved vram if it has been reserved. 1557 */ 1558 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1559 { 1560 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1561 1562 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1563 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1564 ctx->c2p_bo = NULL; 1565 1566 return 0; 1567 } 1568 1569 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1570 { 1571 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1572 1573 memset(ctx, 0, sizeof(*ctx)); 1574 1575 ctx->c2p_train_data_offset = 1576 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1577 ctx->p2c_train_data_offset = 1578 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1579 ctx->train_data_size = 1580 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1581 1582 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1583 ctx->train_data_size, 1584 ctx->p2c_train_data_offset, 1585 ctx->c2p_train_data_offset); 1586 } 1587 1588 /* 1589 * reserve TMR memory at the top of VRAM which holds 1590 * IP Discovery data and is protected by PSP. 1591 */ 1592 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1593 { 1594 int ret; 1595 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1596 bool mem_train_support = false; 1597 1598 if (!amdgpu_sriov_vf(adev)) { 1599 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1600 mem_train_support = true; 1601 else 1602 DRM_DEBUG("memory training does not support!\n"); 1603 } 1604 1605 /* 1606 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1607 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1608 * 1609 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1610 * discovery data and G6 memory training data respectively 1611 */ 1612 adev->mman.discovery_tmr_size = 1613 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1614 if (!adev->mman.discovery_tmr_size) 1615 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1616 1617 if (mem_train_support) { 1618 /* reserve vram for mem train according to TMR location */ 1619 amdgpu_ttm_training_data_block_init(adev); 1620 ret = amdgpu_bo_create_kernel_at(adev, 1621 ctx->c2p_train_data_offset, 1622 ctx->train_data_size, 1623 AMDGPU_GEM_DOMAIN_VRAM, 1624 &ctx->c2p_bo, 1625 NULL); 1626 if (ret) { 1627 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1628 amdgpu_ttm_training_reserve_vram_fini(adev); 1629 return ret; 1630 } 1631 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1632 } 1633 1634 ret = amdgpu_bo_create_kernel_at(adev, 1635 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1636 adev->mman.discovery_tmr_size, 1637 AMDGPU_GEM_DOMAIN_VRAM, 1638 &adev->mman.discovery_memory, 1639 NULL); 1640 if (ret) { 1641 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1642 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1643 return ret; 1644 } 1645 1646 return 0; 1647 } 1648 1649 /* 1650 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1651 * gtt/vram related fields. 1652 * 1653 * This initializes all of the memory space pools that the TTM layer 1654 * will need such as the GTT space (system memory mapped to the device), 1655 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1656 * can be mapped per VMID. 1657 */ 1658 int amdgpu_ttm_init(struct amdgpu_device *adev) 1659 { 1660 uint64_t gtt_size; 1661 int r; 1662 u64 vis_vram_limit; 1663 1664 mutex_init(&adev->mman.gtt_window_lock); 1665 1666 /* No others user of address space so set it to 0 */ 1667 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1668 adev_to_drm(adev)->anon_inode->i_mapping, 1669 adev_to_drm(adev)->vma_offset_manager, 1670 adev->need_swiotlb, 1671 dma_addressing_limited(adev->dev)); 1672 if (r) { 1673 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1674 return r; 1675 } 1676 adev->mman.initialized = true; 1677 1678 /* Initialize VRAM pool with all of VRAM divided into pages */ 1679 r = amdgpu_vram_mgr_init(adev); 1680 if (r) { 1681 DRM_ERROR("Failed initializing VRAM heap.\n"); 1682 return r; 1683 } 1684 1685 /* Reduce size of CPU-visible VRAM if requested */ 1686 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1687 if (amdgpu_vis_vram_limit > 0 && 1688 vis_vram_limit <= adev->gmc.visible_vram_size) 1689 adev->gmc.visible_vram_size = vis_vram_limit; 1690 1691 /* Change the size here instead of the init above so only lpfn is affected */ 1692 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1693 #ifdef CONFIG_64BIT 1694 #ifdef CONFIG_X86 1695 if (adev->gmc.xgmi.connected_to_cpu) 1696 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1697 adev->gmc.visible_vram_size); 1698 1699 else 1700 #endif 1701 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1702 adev->gmc.visible_vram_size); 1703 #endif 1704 1705 /* 1706 *The reserved vram for firmware must be pinned to the specified 1707 *place on the VRAM, so reserve it early. 1708 */ 1709 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1710 if (r) { 1711 return r; 1712 } 1713 1714 /* 1715 * only NAVI10 and onwards ASIC support for IP discovery. 1716 * If IP discovery enabled, a block of memory should be 1717 * reserved for IP discovey. 1718 */ 1719 if (adev->mman.discovery_bin) { 1720 r = amdgpu_ttm_reserve_tmr(adev); 1721 if (r) 1722 return r; 1723 } 1724 1725 /* allocate memory as required for VGA 1726 * This is used for VGA emulation and pre-OS scanout buffers to 1727 * avoid display artifacts while transitioning between pre-OS 1728 * and driver. */ 1729 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1730 AMDGPU_GEM_DOMAIN_VRAM, 1731 &adev->mman.stolen_vga_memory, 1732 NULL); 1733 if (r) 1734 return r; 1735 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1736 adev->mman.stolen_extended_size, 1737 AMDGPU_GEM_DOMAIN_VRAM, 1738 &adev->mman.stolen_extended_memory, 1739 NULL); 1740 if (r) 1741 return r; 1742 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1743 adev->mman.stolen_reserved_size, 1744 AMDGPU_GEM_DOMAIN_VRAM, 1745 &adev->mman.stolen_reserved_memory, 1746 NULL); 1747 if (r) 1748 return r; 1749 1750 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1751 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1752 1753 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1754 * or whatever the user passed on module init */ 1755 if (amdgpu_gtt_size == -1) { 1756 struct sysinfo si; 1757 1758 si_meminfo(&si); 1759 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1760 adev->gmc.mc_vram_size), 1761 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1762 } 1763 else 1764 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1765 1766 /* Initialize GTT memory pool */ 1767 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1768 if (r) { 1769 DRM_ERROR("Failed initializing GTT heap.\n"); 1770 return r; 1771 } 1772 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1773 (unsigned)(gtt_size / (1024 * 1024))); 1774 1775 /* Initialize preemptible memory pool */ 1776 r = amdgpu_preempt_mgr_init(adev); 1777 if (r) { 1778 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1779 return r; 1780 } 1781 1782 /* Initialize various on-chip memory pools */ 1783 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1784 if (r) { 1785 DRM_ERROR("Failed initializing GDS heap.\n"); 1786 return r; 1787 } 1788 1789 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1790 if (r) { 1791 DRM_ERROR("Failed initializing gws heap.\n"); 1792 return r; 1793 } 1794 1795 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1796 if (r) { 1797 DRM_ERROR("Failed initializing oa heap.\n"); 1798 return r; 1799 } 1800 1801 return 0; 1802 } 1803 1804 /* 1805 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1806 */ 1807 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1808 { 1809 if (!adev->mman.initialized) 1810 return; 1811 1812 amdgpu_ttm_training_reserve_vram_fini(adev); 1813 /* return the stolen vga memory back to VRAM */ 1814 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1815 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1816 /* return the IP Discovery TMR memory back to VRAM */ 1817 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1818 if (adev->mman.stolen_reserved_size) 1819 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1820 NULL, NULL); 1821 amdgpu_ttm_fw_reserve_vram_fini(adev); 1822 1823 amdgpu_vram_mgr_fini(adev); 1824 amdgpu_gtt_mgr_fini(adev); 1825 amdgpu_preempt_mgr_fini(adev); 1826 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1827 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1828 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1829 ttm_device_fini(&adev->mman.bdev); 1830 adev->mman.initialized = false; 1831 DRM_INFO("amdgpu: ttm finalized\n"); 1832 } 1833 1834 /** 1835 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1836 * 1837 * @adev: amdgpu_device pointer 1838 * @enable: true when we can use buffer functions. 1839 * 1840 * Enable/disable use of buffer functions during suspend/resume. This should 1841 * only be called at bootup or when userspace isn't running. 1842 */ 1843 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1844 { 1845 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1846 uint64_t size; 1847 int r; 1848 1849 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1850 adev->mman.buffer_funcs_enabled == enable) 1851 return; 1852 1853 if (enable) { 1854 struct amdgpu_ring *ring; 1855 struct drm_gpu_scheduler *sched; 1856 1857 ring = adev->mman.buffer_funcs_ring; 1858 sched = &ring->sched; 1859 r = drm_sched_entity_init(&adev->mman.entity, 1860 DRM_SCHED_PRIORITY_KERNEL, &sched, 1861 1, NULL); 1862 if (r) { 1863 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1864 r); 1865 return; 1866 } 1867 } else { 1868 drm_sched_entity_destroy(&adev->mman.entity); 1869 dma_fence_put(man->move); 1870 man->move = NULL; 1871 } 1872 1873 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1874 if (enable) 1875 size = adev->gmc.real_vram_size; 1876 else 1877 size = adev->gmc.visible_vram_size; 1878 man->size = size >> PAGE_SHIFT; 1879 adev->mman.buffer_funcs_enabled = enable; 1880 } 1881 1882 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1883 uint64_t dst_offset, uint32_t byte_count, 1884 struct dma_resv *resv, 1885 struct dma_fence **fence, bool direct_submit, 1886 bool vm_needs_flush, bool tmz) 1887 { 1888 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1889 AMDGPU_IB_POOL_DELAYED; 1890 struct amdgpu_device *adev = ring->adev; 1891 struct amdgpu_job *job; 1892 1893 uint32_t max_bytes; 1894 unsigned num_loops, num_dw; 1895 unsigned i; 1896 int r; 1897 1898 if (direct_submit && !ring->sched.ready) { 1899 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1900 return -EINVAL; 1901 } 1902 1903 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1904 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1905 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1906 1907 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1908 if (r) 1909 return r; 1910 1911 if (vm_needs_flush) { 1912 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1913 adev->gmc.pdb0_bo : adev->gart.bo); 1914 job->vm_needs_flush = true; 1915 } 1916 if (resv) { 1917 r = amdgpu_sync_resv(adev, &job->sync, resv, 1918 AMDGPU_SYNC_ALWAYS, 1919 AMDGPU_FENCE_OWNER_UNDEFINED); 1920 if (r) { 1921 DRM_ERROR("sync failed (%d).\n", r); 1922 goto error_free; 1923 } 1924 } 1925 1926 for (i = 0; i < num_loops; i++) { 1927 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1928 1929 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1930 dst_offset, cur_size_in_bytes, tmz); 1931 1932 src_offset += cur_size_in_bytes; 1933 dst_offset += cur_size_in_bytes; 1934 byte_count -= cur_size_in_bytes; 1935 } 1936 1937 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1938 WARN_ON(job->ibs[0].length_dw > num_dw); 1939 if (direct_submit) 1940 r = amdgpu_job_submit_direct(job, ring, fence); 1941 else 1942 r = amdgpu_job_submit(job, &adev->mman.entity, 1943 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1944 if (r) 1945 goto error_free; 1946 1947 return r; 1948 1949 error_free: 1950 amdgpu_job_free(job); 1951 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1952 return r; 1953 } 1954 1955 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1956 uint32_t src_data, 1957 struct dma_resv *resv, 1958 struct dma_fence **fence) 1959 { 1960 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1961 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1962 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1963 1964 struct amdgpu_res_cursor cursor; 1965 unsigned int num_loops, num_dw; 1966 uint64_t num_bytes; 1967 1968 struct amdgpu_job *job; 1969 int r; 1970 1971 if (!adev->mman.buffer_funcs_enabled) { 1972 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1973 return -EINVAL; 1974 } 1975 1976 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) { 1977 DRM_ERROR("Trying to clear preemptible memory.\n"); 1978 return -EINVAL; 1979 } 1980 1981 if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1982 r = amdgpu_ttm_alloc_gart(&bo->tbo); 1983 if (r) 1984 return r; 1985 } 1986 1987 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; 1988 num_loops = 0; 1989 1990 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 1991 while (cursor.remaining) { 1992 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 1993 amdgpu_res_next(&cursor, cursor.size); 1994 } 1995 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1996 1997 /* for IB padding */ 1998 num_dw += 64; 1999 2000 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2001 &job); 2002 if (r) 2003 return r; 2004 2005 if (resv) { 2006 r = amdgpu_sync_resv(adev, &job->sync, resv, 2007 AMDGPU_SYNC_ALWAYS, 2008 AMDGPU_FENCE_OWNER_UNDEFINED); 2009 if (r) { 2010 DRM_ERROR("sync failed (%d).\n", r); 2011 goto error_free; 2012 } 2013 } 2014 2015 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2016 while (cursor.remaining) { 2017 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2018 uint64_t dst_addr = cursor.start; 2019 2020 dst_addr += amdgpu_ttm_domain_start(adev, 2021 bo->tbo.resource->mem_type); 2022 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2023 cur_size); 2024 2025 amdgpu_res_next(&cursor, cur_size); 2026 } 2027 2028 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2029 WARN_ON(job->ibs[0].length_dw > num_dw); 2030 r = amdgpu_job_submit(job, &adev->mman.entity, 2031 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2032 if (r) 2033 goto error_free; 2034 2035 return 0; 2036 2037 error_free: 2038 amdgpu_job_free(job); 2039 return r; 2040 } 2041 2042 #if defined(CONFIG_DEBUG_FS) 2043 2044 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2045 { 2046 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2047 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2048 TTM_PL_VRAM); 2049 struct drm_printer p = drm_seq_file_printer(m); 2050 2051 man->func->debug(man, &p); 2052 return 0; 2053 } 2054 2055 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2056 { 2057 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2058 2059 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2060 } 2061 2062 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2063 { 2064 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2065 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2066 TTM_PL_TT); 2067 struct drm_printer p = drm_seq_file_printer(m); 2068 2069 man->func->debug(man, &p); 2070 return 0; 2071 } 2072 2073 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2074 { 2075 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2076 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2077 AMDGPU_PL_GDS); 2078 struct drm_printer p = drm_seq_file_printer(m); 2079 2080 man->func->debug(man, &p); 2081 return 0; 2082 } 2083 2084 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2085 { 2086 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2087 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2088 AMDGPU_PL_GWS); 2089 struct drm_printer p = drm_seq_file_printer(m); 2090 2091 man->func->debug(man, &p); 2092 return 0; 2093 } 2094 2095 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2096 { 2097 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2098 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2099 AMDGPU_PL_OA); 2100 struct drm_printer p = drm_seq_file_printer(m); 2101 2102 man->func->debug(man, &p); 2103 return 0; 2104 } 2105 2106 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2107 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2108 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2109 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2110 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2111 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2112 2113 /* 2114 * amdgpu_ttm_vram_read - Linear read access to VRAM 2115 * 2116 * Accesses VRAM via MMIO for debugging purposes. 2117 */ 2118 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2119 size_t size, loff_t *pos) 2120 { 2121 struct amdgpu_device *adev = file_inode(f)->i_private; 2122 ssize_t result = 0; 2123 2124 if (size & 0x3 || *pos & 0x3) 2125 return -EINVAL; 2126 2127 if (*pos >= adev->gmc.mc_vram_size) 2128 return -ENXIO; 2129 2130 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2131 while (size) { 2132 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2133 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2134 2135 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2136 if (copy_to_user(buf, value, bytes)) 2137 return -EFAULT; 2138 2139 result += bytes; 2140 buf += bytes; 2141 *pos += bytes; 2142 size -= bytes; 2143 } 2144 2145 return result; 2146 } 2147 2148 /* 2149 * amdgpu_ttm_vram_write - Linear write access to VRAM 2150 * 2151 * Accesses VRAM via MMIO for debugging purposes. 2152 */ 2153 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2154 size_t size, loff_t *pos) 2155 { 2156 struct amdgpu_device *adev = file_inode(f)->i_private; 2157 ssize_t result = 0; 2158 int r; 2159 2160 if (size & 0x3 || *pos & 0x3) 2161 return -EINVAL; 2162 2163 if (*pos >= adev->gmc.mc_vram_size) 2164 return -ENXIO; 2165 2166 while (size) { 2167 uint32_t value; 2168 2169 if (*pos >= adev->gmc.mc_vram_size) 2170 return result; 2171 2172 r = get_user(value, (uint32_t *)buf); 2173 if (r) 2174 return r; 2175 2176 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2177 2178 result += 4; 2179 buf += 4; 2180 *pos += 4; 2181 size -= 4; 2182 } 2183 2184 return result; 2185 } 2186 2187 static const struct file_operations amdgpu_ttm_vram_fops = { 2188 .owner = THIS_MODULE, 2189 .read = amdgpu_ttm_vram_read, 2190 .write = amdgpu_ttm_vram_write, 2191 .llseek = default_llseek, 2192 }; 2193 2194 /* 2195 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2196 * 2197 * This function is used to read memory that has been mapped to the 2198 * GPU and the known addresses are not physical addresses but instead 2199 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2200 */ 2201 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2202 size_t size, loff_t *pos) 2203 { 2204 struct amdgpu_device *adev = file_inode(f)->i_private; 2205 struct iommu_domain *dom; 2206 ssize_t result = 0; 2207 int r; 2208 2209 /* retrieve the IOMMU domain if any for this device */ 2210 dom = iommu_get_domain_for_dev(adev->dev); 2211 2212 while (size) { 2213 phys_addr_t addr = *pos & PAGE_MASK; 2214 loff_t off = *pos & ~PAGE_MASK; 2215 size_t bytes = PAGE_SIZE - off; 2216 unsigned long pfn; 2217 struct page *p; 2218 void *ptr; 2219 2220 bytes = bytes < size ? bytes : size; 2221 2222 /* Translate the bus address to a physical address. If 2223 * the domain is NULL it means there is no IOMMU active 2224 * and the address translation is the identity 2225 */ 2226 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2227 2228 pfn = addr >> PAGE_SHIFT; 2229 if (!pfn_valid(pfn)) 2230 return -EPERM; 2231 2232 p = pfn_to_page(pfn); 2233 if (p->mapping != adev->mman.bdev.dev_mapping) 2234 return -EPERM; 2235 2236 ptr = kmap(p); 2237 r = copy_to_user(buf, ptr + off, bytes); 2238 kunmap(p); 2239 if (r) 2240 return -EFAULT; 2241 2242 size -= bytes; 2243 *pos += bytes; 2244 result += bytes; 2245 } 2246 2247 return result; 2248 } 2249 2250 /* 2251 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2252 * 2253 * This function is used to write memory that has been mapped to the 2254 * GPU and the known addresses are not physical addresses but instead 2255 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2256 */ 2257 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2258 size_t size, loff_t *pos) 2259 { 2260 struct amdgpu_device *adev = file_inode(f)->i_private; 2261 struct iommu_domain *dom; 2262 ssize_t result = 0; 2263 int r; 2264 2265 dom = iommu_get_domain_for_dev(adev->dev); 2266 2267 while (size) { 2268 phys_addr_t addr = *pos & PAGE_MASK; 2269 loff_t off = *pos & ~PAGE_MASK; 2270 size_t bytes = PAGE_SIZE - off; 2271 unsigned long pfn; 2272 struct page *p; 2273 void *ptr; 2274 2275 bytes = bytes < size ? bytes : size; 2276 2277 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2278 2279 pfn = addr >> PAGE_SHIFT; 2280 if (!pfn_valid(pfn)) 2281 return -EPERM; 2282 2283 p = pfn_to_page(pfn); 2284 if (p->mapping != adev->mman.bdev.dev_mapping) 2285 return -EPERM; 2286 2287 ptr = kmap(p); 2288 r = copy_from_user(ptr + off, buf, bytes); 2289 kunmap(p); 2290 if (r) 2291 return -EFAULT; 2292 2293 size -= bytes; 2294 *pos += bytes; 2295 result += bytes; 2296 } 2297 2298 return result; 2299 } 2300 2301 static const struct file_operations amdgpu_ttm_iomem_fops = { 2302 .owner = THIS_MODULE, 2303 .read = amdgpu_iomem_read, 2304 .write = amdgpu_iomem_write, 2305 .llseek = default_llseek 2306 }; 2307 2308 #endif 2309 2310 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2311 { 2312 #if defined(CONFIG_DEBUG_FS) 2313 struct drm_minor *minor = adev_to_drm(adev)->primary; 2314 struct dentry *root = minor->debugfs_root; 2315 2316 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2317 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2318 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2319 &amdgpu_ttm_iomem_fops); 2320 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2321 &amdgpu_mm_vram_table_fops); 2322 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2323 &amdgpu_mm_tt_table_fops); 2324 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2325 &amdgpu_mm_gds_table_fops); 2326 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2327 &amdgpu_mm_gws_table_fops); 2328 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2329 &amdgpu_mm_oa_table_fops); 2330 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2331 &amdgpu_ttm_page_pool_fops); 2332 #endif 2333 } 2334