1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/dma-buf.h> 42 #include <linux/sizes.h> 43 #include <linux/module.h> 44 45 #include <drm/drm_drv.h> 46 #include <drm/ttm/ttm_bo.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <drm/ttm/ttm_range_manager.h> 49 #include <drm/ttm/ttm_tt.h> 50 51 #include <drm/amdgpu_drm.h> 52 53 #include "amdgpu.h" 54 #include "amdgpu_object.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_sdma.h" 58 #include "amdgpu_ras.h" 59 #include "amdgpu_hmm.h" 60 #include "amdgpu_atomfirmware.h" 61 #include "amdgpu_res_cursor.h" 62 #include "bif/bif_4_1_d.h" 63 #include "kfd_svm.h" 64 65 MODULE_IMPORT_NS("DMA_BUF"); 66 67 #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) 68 69 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 70 struct ttm_tt *ttm, 71 struct ttm_resource *bo_mem); 72 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 73 struct ttm_tt *ttm); 74 75 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 76 unsigned int type, 77 uint64_t size_in_page) 78 { 79 if (!size_in_page) 80 return 0; 81 82 return ttm_range_man_init(&adev->mman.bdev, type, 83 false, size_in_page); 84 } 85 86 /** 87 * amdgpu_evict_flags - Compute placement flags 88 * 89 * @bo: The buffer object to evict 90 * @placement: Possible destination(s) for evicted BO 91 * 92 * Fill in placement data when ttm_bo_evict() is called 93 */ 94 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 95 struct ttm_placement *placement) 96 { 97 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 98 struct amdgpu_bo *abo; 99 static const struct ttm_place placements = { 100 .fpfn = 0, 101 .lpfn = 0, 102 .mem_type = TTM_PL_SYSTEM, 103 .flags = 0 104 }; 105 106 /* Don't handle scatter gather BOs */ 107 if (bo->type == ttm_bo_type_sg) { 108 placement->num_placement = 0; 109 return; 110 } 111 112 /* Object isn't an AMDGPU object so ignore */ 113 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 114 placement->placement = &placements; 115 placement->num_placement = 1; 116 return; 117 } 118 119 abo = ttm_to_amdgpu_bo(bo); 120 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 121 placement->num_placement = 0; 122 return; 123 } 124 125 switch (bo->resource->mem_type) { 126 case AMDGPU_PL_GDS: 127 case AMDGPU_PL_GWS: 128 case AMDGPU_PL_OA: 129 case AMDGPU_PL_DOORBELL: 130 case AMDGPU_PL_MMIO_REMAP: 131 placement->num_placement = 0; 132 return; 133 134 case TTM_PL_VRAM: 135 if (!adev->mman.buffer_funcs_enabled) { 136 /* Move to system memory */ 137 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 138 139 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 140 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 141 amdgpu_res_cpu_visible(adev, bo->resource)) { 142 143 /* Try evicting to the CPU inaccessible part of VRAM 144 * first, but only set GTT as busy placement, so this 145 * BO will be evicted to GTT rather than causing other 146 * BOs to be evicted from VRAM 147 */ 148 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 149 AMDGPU_GEM_DOMAIN_GTT | 150 AMDGPU_GEM_DOMAIN_CPU); 151 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 152 abo->placements[0].lpfn = 0; 153 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; 154 } else { 155 /* Move to GTT memory */ 156 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 157 AMDGPU_GEM_DOMAIN_CPU); 158 } 159 break; 160 case TTM_PL_TT: 161 case AMDGPU_PL_PREEMPT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 static struct dma_fence * 170 amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, 171 struct amdgpu_job *job, u32 num_dw) 172 { 173 struct amdgpu_ring *ring; 174 175 ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); 176 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 177 WARN_ON(job->ibs[0].length_dw > num_dw); 178 179 lockdep_assert_held(&entity->lock); 180 181 return amdgpu_job_submit(job); 182 } 183 184 /** 185 * amdgpu_ttm_map_buffer - Map memory into the GART windows 186 * @entity: entity to run the window setup job 187 * @bo: buffer object to map 188 * @mem: memory object to map 189 * @mm_cur: range to map 190 * @window: which GART window to use 191 * @tmz: if we should setup a TMZ enabled mapping 192 * @size: in number of bytes to map, out number of bytes mapped 193 * @addr: resulting address inside the MC address space 194 * 195 * Setup one of the GART windows to access a specific piece of memory or return 196 * the physical address for local memory. 197 */ 198 static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity, 199 struct ttm_buffer_object *bo, 200 struct ttm_resource *mem, 201 struct amdgpu_res_cursor *mm_cur, 202 unsigned int window, 203 bool tmz, uint64_t *size, uint64_t *addr) 204 { 205 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 206 unsigned int offset, num_pages, num_dw, num_bytes; 207 uint64_t src_addr, dst_addr; 208 struct amdgpu_job *job; 209 void *cpu_addr; 210 uint64_t flags; 211 int r; 212 const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); 213 214 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 215 GTT_MAX_PAGES * AMDGPU_GPU_PAGES_IN_CPU_PAGE * 8); 216 217 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT)) 218 return -EINVAL; 219 220 /* Map only what can't be accessed directly */ 221 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 222 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 223 mm_cur->start; 224 return 0; 225 } 226 227 228 /* 229 * If start begins at an offset inside the page, then adjust the size 230 * and addr accordingly 231 */ 232 offset = mm_cur->start & ~PAGE_MASK; 233 234 num_pages = PFN_UP(*size + offset); 235 num_pages = min_t(uint32_t, num_pages, GTT_MAX_PAGES); 236 237 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 238 239 *addr = amdgpu_compute_gart_address(&adev->gmc, entity, window); 240 *addr += offset; 241 242 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 243 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 244 245 r = amdgpu_job_alloc_with_ib(adev, &entity->base, 246 AMDGPU_FENCE_OWNER_UNDEFINED, 247 num_dw * 4 + num_bytes, 248 AMDGPU_IB_POOL_DELAYED, 249 AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER, 250 &job); 251 if (r) 252 return r; 253 254 src_addr = num_dw * 4; 255 src_addr += job->ibs[0].gpu_addr; 256 257 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 258 dst_addr += (entity->gart_window_offs[window] >> AMDGPU_GPU_PAGE_SHIFT) * 8; 259 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 260 dst_addr, num_bytes, 0); 261 262 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 263 if (tmz) 264 flags |= AMDGPU_PTE_TMZ; 265 266 cpu_addr = &job->ibs[0].ptr[num_dw]; 267 268 if (mem->mem_type == TTM_PL_TT) { 269 dma_addr_t *dma_addr; 270 271 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 272 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 273 } else { 274 u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset; 275 276 amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); 277 } 278 279 dma_fence_put(amdgpu_ttm_job_submit(adev, entity, job, num_dw)); 280 return 0; 281 } 282 283 /** 284 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 285 * @adev: amdgpu device 286 * @entity: entity to run the jobs 287 * @src: buffer/address where to read from 288 * @dst: buffer/address where to write to 289 * @size: number of bytes to copy 290 * @tmz: if a secure copy should be used 291 * @resv: resv object to sync to 292 * @f: Returns the last fence if multiple jobs are submitted. 293 * 294 * The function copies @size bytes from {src->mem + src->offset} to 295 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 296 * move and different for a BO to BO copy. 297 * 298 */ 299 __attribute__((nonnull)) 300 static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 301 struct amdgpu_ttm_buffer_entity *entity, 302 const struct amdgpu_copy_mem *src, 303 const struct amdgpu_copy_mem *dst, 304 uint64_t size, bool tmz, 305 struct dma_resv *resv, 306 struct dma_fence **f) 307 { 308 struct amdgpu_res_cursor src_mm, dst_mm; 309 struct dma_fence *fence = NULL; 310 int r = 0; 311 uint32_t copy_flags = 0; 312 struct amdgpu_bo *abo_src, *abo_dst; 313 314 if (!adev->mman.buffer_funcs_enabled) { 315 dev_err(adev->dev, 316 "Trying to move memory with ring turned off.\n"); 317 return -EINVAL; 318 } 319 320 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 321 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 322 323 mutex_lock(&entity->lock); 324 while (src_mm.remaining) { 325 uint64_t from, to, cur_size, tiling_flags; 326 uint32_t num_type, data_format, max_com, write_compress_disable; 327 struct dma_fence *next; 328 329 /* Never copy more than 256MiB at once to avoid a timeout */ 330 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 331 332 /* Map src to window 0 and dst to window 1. */ 333 r = amdgpu_ttm_map_buffer(entity, src->bo, src->mem, &src_mm, 334 0, tmz, &cur_size, &from); 335 if (r) 336 goto error; 337 338 r = amdgpu_ttm_map_buffer(entity, dst->bo, dst->mem, &dst_mm, 339 1, tmz, &cur_size, &to); 340 if (r) 341 goto error; 342 343 abo_src = ttm_to_amdgpu_bo(src->bo); 344 abo_dst = ttm_to_amdgpu_bo(dst->bo); 345 if (tmz) 346 copy_flags |= AMDGPU_COPY_FLAGS_TMZ; 347 if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) && 348 (abo_src->tbo.resource->mem_type == TTM_PL_VRAM)) 349 copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED; 350 if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) && 351 (dst->mem->mem_type == TTM_PL_VRAM)) { 352 copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED; 353 amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags); 354 max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); 355 num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE); 356 data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT); 357 write_compress_disable = 358 AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE); 359 copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) | 360 AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) | 361 AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) | 362 AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE, 363 write_compress_disable)); 364 } 365 366 r = amdgpu_copy_buffer(adev, entity, from, to, cur_size, resv, 367 &next, true, copy_flags); 368 if (r) 369 goto error; 370 371 dma_fence_put(fence); 372 fence = next; 373 374 amdgpu_res_next(&src_mm, cur_size); 375 amdgpu_res_next(&dst_mm, cur_size); 376 } 377 error: 378 mutex_unlock(&entity->lock); 379 *f = fence; 380 return r; 381 } 382 383 /* 384 * amdgpu_move_blit - Copy an entire buffer to another buffer 385 * 386 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 387 * help move buffers to and from VRAM. 388 */ 389 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 390 bool evict, 391 struct ttm_resource *new_mem, 392 struct ttm_resource *old_mem) 393 { 394 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 395 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 396 struct amdgpu_ttm_buffer_entity *entity; 397 struct amdgpu_copy_mem src, dst; 398 struct dma_fence *fence = NULL; 399 int r; 400 u32 e; 401 402 src.bo = bo; 403 dst.bo = bo; 404 src.mem = old_mem; 405 dst.mem = new_mem; 406 src.offset = 0; 407 dst.offset = 0; 408 409 e = atomic_inc_return(&adev->mman.next_move_entity) % 410 adev->mman.num_move_entities; 411 entity = &adev->mman.move_entities[e]; 412 413 r = amdgpu_ttm_copy_mem_to_mem(adev, 414 entity, 415 &src, &dst, 416 new_mem->size, 417 amdgpu_bo_encrypted(abo), 418 bo->base.resv, &fence); 419 if (r) 420 goto error; 421 422 /* clear the space being freed */ 423 if (old_mem->mem_type == TTM_PL_VRAM && 424 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 425 struct dma_fence *wipe_fence = NULL; 426 r = amdgpu_ttm_clear_buffer(entity, abo, NULL, &wipe_fence, 427 false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); 428 if (r) { 429 goto error; 430 } else if (wipe_fence) { 431 amdgpu_vram_mgr_set_cleared(bo->resource); 432 dma_fence_put(fence); 433 fence = wipe_fence; 434 } 435 } 436 437 /* Always block for VM page tables before committing the new location */ 438 if (bo->type == ttm_bo_type_kernel) 439 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 440 else 441 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 442 dma_fence_put(fence); 443 return r; 444 445 error: 446 if (fence) 447 dma_fence_wait(fence, false); 448 dma_fence_put(fence); 449 return r; 450 } 451 452 /** 453 * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU 454 * @adev: amdgpu device 455 * @res: the resource to check 456 * 457 * Returns: true if the full resource is CPU visible, false otherwise. 458 */ 459 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 460 struct ttm_resource *res) 461 { 462 struct amdgpu_res_cursor cursor; 463 464 if (!res) 465 return false; 466 467 if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT || 468 res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL || 469 res->mem_type == AMDGPU_PL_MMIO_REMAP) 470 return true; 471 472 if (res->mem_type != TTM_PL_VRAM) 473 return false; 474 475 amdgpu_res_first(res, 0, res->size, &cursor); 476 while (cursor.remaining) { 477 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) 478 return false; 479 amdgpu_res_next(&cursor, cursor.size); 480 } 481 482 return true; 483 } 484 485 /* 486 * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy 487 * 488 * Called by amdgpu_bo_move() 489 */ 490 static bool amdgpu_res_copyable(struct amdgpu_device *adev, 491 struct ttm_resource *mem) 492 { 493 if (!amdgpu_res_cpu_visible(adev, mem)) 494 return false; 495 496 /* ttm_resource_ioremap only supports contiguous memory */ 497 if (mem->mem_type == TTM_PL_VRAM && 498 !(mem->placement & TTM_PL_FLAG_CONTIGUOUS)) 499 return false; 500 501 return true; 502 } 503 504 /* 505 * amdgpu_bo_move - Move a buffer object to a new memory location 506 * 507 * Called by ttm_bo_handle_move_mem() 508 */ 509 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 510 struct ttm_operation_ctx *ctx, 511 struct ttm_resource *new_mem, 512 struct ttm_place *hop) 513 { 514 struct amdgpu_device *adev; 515 struct amdgpu_bo *abo; 516 struct ttm_resource *old_mem = bo->resource; 517 int r; 518 519 if (new_mem->mem_type == TTM_PL_TT || 520 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 521 if (old_mem && (old_mem->mem_type == TTM_PL_TT || 522 old_mem->mem_type == AMDGPU_PL_PREEMPT)) { 523 r = ttm_bo_wait_ctx(bo, ctx); 524 if (r) 525 return r; 526 527 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 528 } 529 530 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 531 if (r) 532 return r; 533 } 534 535 abo = ttm_to_amdgpu_bo(bo); 536 adev = amdgpu_ttm_adev(bo->bdev); 537 538 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 539 bo->ttm == NULL)) { 540 amdgpu_bo_move_notify(bo, evict, new_mem); 541 ttm_bo_move_null(bo, new_mem); 542 return 0; 543 } 544 if (old_mem->mem_type == TTM_PL_SYSTEM && 545 (new_mem->mem_type == TTM_PL_TT || 546 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 547 amdgpu_bo_move_notify(bo, evict, new_mem); 548 ttm_bo_move_null(bo, new_mem); 549 return 0; 550 } 551 if ((old_mem->mem_type == TTM_PL_TT || 552 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 553 new_mem->mem_type == TTM_PL_SYSTEM) { 554 r = ttm_bo_wait_ctx(bo, ctx); 555 if (r) 556 return r; 557 558 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 559 amdgpu_bo_move_notify(bo, evict, new_mem); 560 ttm_resource_free(bo, &bo->resource); 561 ttm_bo_assign_mem(bo, new_mem); 562 return 0; 563 } 564 if ((old_mem->mem_type == TTM_PL_TT || 565 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 566 (new_mem->mem_type == TTM_PL_TT || 567 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 568 amdgpu_bo_move_notify(bo, evict, new_mem); 569 ttm_resource_free(bo, &bo->resource); 570 ttm_bo_assign_mem(bo, new_mem); 571 return 0; 572 } 573 574 if (old_mem->mem_type == AMDGPU_PL_GDS || 575 old_mem->mem_type == AMDGPU_PL_GWS || 576 old_mem->mem_type == AMDGPU_PL_OA || 577 old_mem->mem_type == AMDGPU_PL_DOORBELL || 578 old_mem->mem_type == AMDGPU_PL_MMIO_REMAP || 579 new_mem->mem_type == AMDGPU_PL_GDS || 580 new_mem->mem_type == AMDGPU_PL_GWS || 581 new_mem->mem_type == AMDGPU_PL_OA || 582 new_mem->mem_type == AMDGPU_PL_DOORBELL || 583 new_mem->mem_type == AMDGPU_PL_MMIO_REMAP) { 584 /* Nothing to save here */ 585 amdgpu_bo_move_notify(bo, evict, new_mem); 586 ttm_bo_move_null(bo, new_mem); 587 return 0; 588 } 589 590 if (bo->type == ttm_bo_type_device && 591 new_mem->mem_type == TTM_PL_VRAM && 592 old_mem->mem_type != TTM_PL_VRAM) { 593 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 594 * accesses the BO after it's moved. 595 */ 596 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 597 } 598 599 if (adev->mman.buffer_funcs_enabled && 600 ((old_mem->mem_type == TTM_PL_SYSTEM && 601 new_mem->mem_type == TTM_PL_VRAM) || 602 (old_mem->mem_type == TTM_PL_VRAM && 603 new_mem->mem_type == TTM_PL_SYSTEM))) { 604 hop->fpfn = 0; 605 hop->lpfn = 0; 606 hop->mem_type = TTM_PL_TT; 607 hop->flags = TTM_PL_FLAG_TEMPORARY; 608 return -EMULTIHOP; 609 } 610 611 amdgpu_bo_move_notify(bo, evict, new_mem); 612 if (adev->mman.buffer_funcs_enabled) 613 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 614 else 615 r = -ENODEV; 616 617 if (r) { 618 /* Check that all memory is CPU accessible */ 619 if (!amdgpu_res_copyable(adev, old_mem) || 620 !amdgpu_res_copyable(adev, new_mem)) { 621 pr_err("Move buffer fallback to memcpy unavailable\n"); 622 return r; 623 } 624 625 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 626 if (r) 627 return r; 628 } 629 630 /* update statistics after the move */ 631 if (evict) 632 atomic64_inc(&adev->num_evictions); 633 atomic64_add(bo->base.size, &adev->num_bytes_moved); 634 return 0; 635 } 636 637 /* 638 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 639 * 640 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 641 */ 642 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 643 struct ttm_resource *mem) 644 { 645 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 646 647 switch (mem->mem_type) { 648 case TTM_PL_SYSTEM: 649 /* system memory */ 650 return 0; 651 case TTM_PL_TT: 652 case AMDGPU_PL_PREEMPT: 653 break; 654 case TTM_PL_VRAM: 655 mem->bus.offset = mem->start << PAGE_SHIFT; 656 657 if (adev->mman.aper_base_kaddr && 658 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 659 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 660 mem->bus.offset; 661 662 mem->bus.offset += adev->gmc.aper_base; 663 mem->bus.is_iomem = true; 664 break; 665 case AMDGPU_PL_DOORBELL: 666 mem->bus.offset = mem->start << PAGE_SHIFT; 667 mem->bus.offset += adev->doorbell.base; 668 mem->bus.is_iomem = true; 669 mem->bus.caching = ttm_uncached; 670 break; 671 case AMDGPU_PL_MMIO_REMAP: 672 mem->bus.offset = mem->start << PAGE_SHIFT; 673 mem->bus.offset += adev->rmmio_remap.bus_addr; 674 mem->bus.is_iomem = true; 675 mem->bus.caching = ttm_uncached; 676 break; 677 default: 678 return -EINVAL; 679 } 680 return 0; 681 } 682 683 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 684 unsigned long page_offset) 685 { 686 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 687 struct amdgpu_res_cursor cursor; 688 689 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 690 &cursor); 691 692 if (bo->resource->mem_type == AMDGPU_PL_DOORBELL) 693 return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT; 694 else if (bo->resource->mem_type == AMDGPU_PL_MMIO_REMAP) 695 return ((uint64_t)(adev->rmmio_remap.bus_addr + cursor.start)) >> PAGE_SHIFT; 696 697 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 698 } 699 700 /** 701 * amdgpu_ttm_domain_start - Returns GPU start address 702 * @adev: amdgpu device object 703 * @type: type of the memory 704 * 705 * Returns: 706 * GPU start address of a memory domain 707 */ 708 709 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 710 { 711 switch (type) { 712 case TTM_PL_TT: 713 return adev->gmc.gart_start; 714 case TTM_PL_VRAM: 715 return adev->gmc.vram_start; 716 } 717 718 return 0; 719 } 720 721 /* 722 * TTM backend functions. 723 */ 724 struct amdgpu_ttm_tt { 725 struct ttm_tt ttm; 726 struct drm_gem_object *gobj; 727 u64 offset; 728 uint64_t userptr; 729 struct task_struct *usertask; 730 uint32_t userflags; 731 bool bound; 732 int32_t pool_id; 733 }; 734 735 #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) 736 737 #ifdef CONFIG_DRM_AMDGPU_USERPTR 738 /* 739 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 740 * memory and start HMM tracking CPU page table update 741 * 742 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 743 * once afterwards to stop HMM tracking. Its the caller responsibility to ensure 744 * that range is a valid memory and it is freed too. 745 */ 746 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 747 struct amdgpu_hmm_range *range) 748 { 749 struct ttm_tt *ttm = bo->tbo.ttm; 750 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 751 unsigned long start = gtt->userptr; 752 struct vm_area_struct *vma; 753 struct mm_struct *mm; 754 bool readonly; 755 int r = 0; 756 757 mm = bo->notifier.mm; 758 if (unlikely(!mm)) { 759 DRM_DEBUG_DRIVER("BO is not registered?\n"); 760 return -EFAULT; 761 } 762 763 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 764 return -ESRCH; 765 766 mmap_read_lock(mm); 767 vma = vma_lookup(mm, start); 768 if (unlikely(!vma)) { 769 r = -EFAULT; 770 goto out_unlock; 771 } 772 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 773 vma->vm_file)) { 774 r = -EPERM; 775 goto out_unlock; 776 } 777 778 readonly = amdgpu_ttm_tt_is_readonly(ttm); 779 r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages, 780 readonly, NULL, range); 781 out_unlock: 782 mmap_read_unlock(mm); 783 if (r) 784 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 785 786 mmput(mm); 787 788 return r; 789 } 790 791 #endif 792 793 /* 794 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 795 * 796 * Called by amdgpu_cs_list_validate(). This creates the page list 797 * that backs user memory and will ultimately be mapped into the device 798 * address space. 799 */ 800 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range) 801 { 802 unsigned long i; 803 804 for (i = 0; i < ttm->num_pages; ++i) 805 ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; 806 } 807 808 /* 809 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 810 * 811 * Called by amdgpu_ttm_backend_bind() 812 **/ 813 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 814 struct ttm_tt *ttm) 815 { 816 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 817 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 818 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 819 enum dma_data_direction direction = write ? 820 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 821 int r; 822 823 /* Allocate an SG array and squash pages into it */ 824 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 825 (u64)ttm->num_pages << PAGE_SHIFT, 826 GFP_KERNEL); 827 if (r) 828 goto release_sg; 829 830 /* Map SG to device */ 831 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 832 if (r) 833 goto release_sg_table; 834 835 /* convert SG to linear array of pages and dma addresses */ 836 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 837 ttm->num_pages); 838 839 return 0; 840 841 release_sg_table: 842 sg_free_table(ttm->sg); 843 release_sg: 844 kfree(ttm->sg); 845 ttm->sg = NULL; 846 return r; 847 } 848 849 /* 850 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 851 */ 852 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 853 struct ttm_tt *ttm) 854 { 855 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 856 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 857 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 858 enum dma_data_direction direction = write ? 859 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 860 861 /* double check that we don't free the table twice */ 862 if (!ttm->sg || !ttm->sg->sgl) 863 return; 864 865 /* unmap the pages mapped to the device */ 866 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 867 sg_free_table(ttm->sg); 868 } 869 870 /* 871 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ... 872 * MQDn+CtrlStackn where n is the number of XCCs per partition. 873 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD 874 * and uses memory type default, UC. The rest of pages_per_xcc are 875 * Ctrl stack and modify their memory type to NC. 876 */ 877 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, 878 struct ttm_tt *ttm, uint64_t flags) 879 { 880 struct amdgpu_ttm_tt *gtt = (void *)ttm; 881 uint64_t total_pages = ttm->num_pages; 882 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); 883 uint64_t page_idx, pages_per_xcc; 884 int i; 885 886 pages_per_xcc = total_pages; 887 do_div(pages_per_xcc, num_xcc); 888 889 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { 890 amdgpu_gart_map_gfx9_mqd(adev, 891 gtt->offset + (page_idx << PAGE_SHIFT), 892 pages_per_xcc, >t->ttm.dma_address[page_idx], 893 flags); 894 } 895 } 896 897 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 898 struct ttm_buffer_object *tbo, 899 uint64_t flags) 900 { 901 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 902 struct ttm_tt *ttm = tbo->ttm; 903 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 904 905 if (amdgpu_bo_encrypted(abo)) 906 flags |= AMDGPU_PTE_TMZ; 907 908 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 909 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags); 910 } else { 911 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 912 gtt->ttm.dma_address, flags); 913 } 914 gtt->bound = true; 915 } 916 917 /* 918 * amdgpu_ttm_backend_bind - Bind GTT memory 919 * 920 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 921 * This handles binding GTT memory to the device address space. 922 */ 923 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 924 struct ttm_tt *ttm, 925 struct ttm_resource *bo_mem) 926 { 927 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 928 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 929 uint64_t flags; 930 int r; 931 932 if (!bo_mem) 933 return -EINVAL; 934 935 if (gtt->bound) 936 return 0; 937 938 if (gtt->userptr) { 939 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 940 if (r) { 941 dev_err(adev->dev, "failed to pin userptr\n"); 942 return r; 943 } 944 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 945 if (!ttm->sg) { 946 struct dma_buf_attachment *attach; 947 struct sg_table *sgt; 948 949 attach = gtt->gobj->import_attach; 950 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 951 if (IS_ERR(sgt)) 952 return PTR_ERR(sgt); 953 954 ttm->sg = sgt; 955 } 956 957 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 958 ttm->num_pages); 959 } 960 961 if (!ttm->num_pages) { 962 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 963 ttm->num_pages, bo_mem, ttm); 964 } 965 966 if (bo_mem->mem_type != TTM_PL_TT || 967 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 968 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 969 return 0; 970 } 971 972 /* compute PTE flags relevant to this BO memory */ 973 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 974 975 /* bind pages into GART page tables */ 976 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 977 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 978 gtt->ttm.dma_address, flags); 979 gtt->bound = true; 980 return 0; 981 } 982 983 /* 984 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 985 * through AGP or GART aperture. 986 * 987 * If bo is accessible through AGP aperture, then use AGP aperture 988 * to access bo; otherwise allocate logical space in GART aperture 989 * and map bo to GART aperture. 990 */ 991 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 992 { 993 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 994 struct ttm_operation_ctx ctx = { false, false }; 995 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 996 struct ttm_placement placement; 997 struct ttm_place placements; 998 struct ttm_resource *tmp; 999 uint64_t addr, flags; 1000 int r; 1001 1002 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 1003 return 0; 1004 1005 addr = amdgpu_gmc_agp_addr(bo); 1006 if (addr != AMDGPU_BO_INVALID_OFFSET) 1007 return 0; 1008 1009 /* allocate GART space */ 1010 placement.num_placement = 1; 1011 placement.placement = &placements; 1012 placements.fpfn = 0; 1013 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1014 placements.mem_type = TTM_PL_TT; 1015 placements.flags = bo->resource->placement; 1016 1017 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1018 if (unlikely(r)) 1019 return r; 1020 1021 /* compute PTE flags for this buffer object */ 1022 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 1023 1024 /* Bind pages */ 1025 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 1026 amdgpu_ttm_gart_bind(adev, bo, flags); 1027 amdgpu_gart_invalidate_tlb(adev); 1028 ttm_resource_free(bo, &bo->resource); 1029 ttm_bo_assign_mem(bo, tmp); 1030 1031 return 0; 1032 } 1033 1034 /* 1035 * amdgpu_ttm_recover_gart - Rebind GTT pages 1036 * 1037 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1038 * rebind GTT pages during a GPU reset. 1039 */ 1040 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1041 { 1042 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1043 uint64_t flags; 1044 1045 if (!tbo->ttm) 1046 return; 1047 1048 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1049 amdgpu_ttm_gart_bind(adev, tbo, flags); 1050 } 1051 1052 /* 1053 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1054 * 1055 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1056 * ttm_tt_destroy(). 1057 */ 1058 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1059 struct ttm_tt *ttm) 1060 { 1061 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1062 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1063 1064 /* if the pages have userptr pinning then clear that first */ 1065 if (gtt->userptr) { 1066 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1067 } else if (ttm->sg && drm_gem_is_imported(gtt->gobj)) { 1068 struct dma_buf_attachment *attach; 1069 1070 attach = gtt->gobj->import_attach; 1071 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1072 ttm->sg = NULL; 1073 } 1074 1075 if (!gtt->bound) 1076 return; 1077 1078 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1079 return; 1080 1081 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1082 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1083 gtt->bound = false; 1084 } 1085 1086 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1087 struct ttm_tt *ttm) 1088 { 1089 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1090 1091 if (gtt->usertask) 1092 put_task_struct(gtt->usertask); 1093 1094 ttm_tt_fini(>t->ttm); 1095 kfree(gtt); 1096 } 1097 1098 /** 1099 * amdgpu_ttm_mmio_remap_alloc_sgt - build an sg_table for MMIO_REMAP I/O aperture 1100 * @adev: amdgpu device providing the remap BAR base (adev->rmmio_remap.bus_addr) 1101 * @res: TTM resource of the BO to export; expected to live in AMDGPU_PL_MMIO_REMAP 1102 * @dev: importing device to map for (typically @attach->dev in dma-buf paths) 1103 * @dir: DMA data direction for the importer (passed to dma_map_resource()) 1104 * @sgt: output; on success, set to a newly allocated sg_table describing the I/O span 1105 * 1106 * The HDP flush page (AMDGPU_PL_MMIO_REMAP) is a fixed hardware I/O window in a PCI 1107 * BAR—there are no struct pages to back it. Importers still need a DMA address list, 1108 * so we synthesize a minimal sg_table and populate it from dma_map_resource(), not 1109 * from pages. Using the common amdgpu_res_cursor walker keeps the offset/size math 1110 * consistent with other TTM/manager users. 1111 * 1112 * - @res is assumed to be a small, contiguous I/O region (typically a single 4 KiB 1113 * page) in AMDGPU_PL_MMIO_REMAP. Callers should validate placement before calling. 1114 * - The sg entry is created with sg_set_page(sg, NULL, …) to reflect I/O space. 1115 * - The mapping uses DMA_ATTR_SKIP_CPU_SYNC because this is MMIO, not cacheable RAM. 1116 * - Peer reachability / p2pdma policy checks must be done by the caller. 1117 * 1118 * Return: 1119 * * 0 on success, with *@sgt set to a valid table that must be freed via 1120 * amdgpu_ttm_mmio_remap_free_sgt(). 1121 * * -ENOMEM if allocation of the sg_table fails. 1122 * * -EIO if dma_map_resource() fails. 1123 * 1124 */ 1125 int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev, 1126 struct ttm_resource *res, 1127 struct device *dev, 1128 enum dma_data_direction dir, 1129 struct sg_table **sgt) 1130 { 1131 struct amdgpu_res_cursor cur; 1132 dma_addr_t dma; 1133 resource_size_t phys; 1134 struct scatterlist *sg; 1135 int r; 1136 1137 /* Walk the resource once; MMIO_REMAP is expected to be contiguous+small. */ 1138 amdgpu_res_first(res, 0, res->size, &cur); 1139 1140 /* Translate byte offset in the remap window into a host physical BAR address. */ 1141 phys = adev->rmmio_remap.bus_addr + cur.start; 1142 1143 /* Build a single-entry sg_table mapped as I/O (no struct page backing). */ 1144 *sgt = kzalloc_obj(**sgt); 1145 if (!*sgt) 1146 return -ENOMEM; 1147 r = sg_alloc_table(*sgt, 1, GFP_KERNEL); 1148 if (r) { 1149 kfree(*sgt); 1150 return r; 1151 } 1152 sg = (*sgt)->sgl; 1153 sg_set_page(sg, NULL, cur.size, 0); /* WHY: I/O space → no pages */ 1154 1155 dma = dma_map_resource(dev, phys, cur.size, dir, DMA_ATTR_SKIP_CPU_SYNC); 1156 if (dma_mapping_error(dev, dma)) { 1157 sg_free_table(*sgt); 1158 kfree(*sgt); 1159 return -EIO; 1160 } 1161 sg_dma_address(sg) = dma; 1162 sg_dma_len(sg) = cur.size; 1163 return 0; 1164 } 1165 1166 void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev, 1167 enum dma_data_direction dir, 1168 struct sg_table *sgt) 1169 { 1170 struct scatterlist *sg = sgt->sgl; 1171 1172 dma_unmap_resource(dev, sg_dma_address(sg), sg_dma_len(sg), 1173 dir, DMA_ATTR_SKIP_CPU_SYNC); 1174 sg_free_table(sgt); 1175 kfree(sgt); 1176 } 1177 1178 /** 1179 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1180 * 1181 * @bo: The buffer object to create a GTT ttm_tt object around 1182 * @page_flags: Page flags to be added to the ttm_tt object 1183 * 1184 * Called by ttm_tt_create(). 1185 */ 1186 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1187 uint32_t page_flags) 1188 { 1189 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1190 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1191 struct amdgpu_ttm_tt *gtt; 1192 enum ttm_caching caching; 1193 1194 gtt = kzalloc_obj(struct amdgpu_ttm_tt); 1195 if (!gtt) 1196 return NULL; 1197 1198 gtt->gobj = &bo->base; 1199 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) 1200 gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 1201 else 1202 gtt->pool_id = abo->xcp_id; 1203 1204 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1205 caching = ttm_write_combined; 1206 else 1207 caching = ttm_cached; 1208 1209 /* allocate space for the uninitialized page entries */ 1210 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1211 kfree(gtt); 1212 return NULL; 1213 } 1214 return >t->ttm; 1215 } 1216 1217 /* 1218 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1219 * 1220 * Map the pages of a ttm_tt object to an address space visible 1221 * to the underlying device. 1222 */ 1223 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1224 struct ttm_tt *ttm, 1225 struct ttm_operation_ctx *ctx) 1226 { 1227 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1228 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1229 struct ttm_pool *pool; 1230 pgoff_t i; 1231 int ret; 1232 1233 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1234 if (gtt->userptr) { 1235 ttm->sg = kzalloc_obj(struct sg_table); 1236 if (!ttm->sg) 1237 return -ENOMEM; 1238 return 0; 1239 } 1240 1241 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1242 return 0; 1243 1244 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1245 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1246 else 1247 pool = &adev->mman.bdev.pool; 1248 ret = ttm_pool_alloc(pool, ttm, ctx); 1249 if (ret) 1250 return ret; 1251 1252 for (i = 0; i < ttm->num_pages; ++i) 1253 ttm->pages[i]->mapping = bdev->dev_mapping; 1254 1255 return 0; 1256 } 1257 1258 /* 1259 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1260 * 1261 * Unmaps pages of a ttm_tt object from the device address space and 1262 * unpopulates the page array backing it. 1263 */ 1264 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1265 struct ttm_tt *ttm) 1266 { 1267 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1268 struct amdgpu_device *adev; 1269 struct ttm_pool *pool; 1270 pgoff_t i; 1271 1272 amdgpu_ttm_backend_unbind(bdev, ttm); 1273 1274 if (gtt->userptr) { 1275 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1276 kfree(ttm->sg); 1277 ttm->sg = NULL; 1278 return; 1279 } 1280 1281 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1282 return; 1283 1284 for (i = 0; i < ttm->num_pages; ++i) 1285 ttm->pages[i]->mapping = NULL; 1286 1287 adev = amdgpu_ttm_adev(bdev); 1288 1289 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1290 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1291 else 1292 pool = &adev->mman.bdev.pool; 1293 1294 return ttm_pool_free(pool, ttm); 1295 } 1296 1297 /** 1298 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current 1299 * task 1300 * 1301 * @tbo: The ttm_buffer_object that contains the userptr 1302 * @user_addr: The returned value 1303 */ 1304 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 1305 uint64_t *user_addr) 1306 { 1307 struct amdgpu_ttm_tt *gtt; 1308 1309 if (!tbo->ttm) 1310 return -EINVAL; 1311 1312 gtt = (void *)tbo->ttm; 1313 *user_addr = gtt->userptr; 1314 return 0; 1315 } 1316 1317 /** 1318 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1319 * task 1320 * 1321 * @bo: The ttm_buffer_object to bind this userptr to 1322 * @addr: The address in the current tasks VM space to use 1323 * @flags: Requirements of userptr object. 1324 * 1325 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to 1326 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to 1327 * initialize GPU VM for a KFD process. 1328 */ 1329 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1330 uint64_t addr, uint32_t flags) 1331 { 1332 struct amdgpu_ttm_tt *gtt; 1333 1334 if (!bo->ttm) { 1335 /* TODO: We want a separate TTM object type for userptrs */ 1336 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1337 if (bo->ttm == NULL) 1338 return -ENOMEM; 1339 } 1340 1341 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1342 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1343 1344 gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 1345 gtt->userptr = addr; 1346 gtt->userflags = flags; 1347 1348 if (gtt->usertask) 1349 put_task_struct(gtt->usertask); 1350 gtt->usertask = current->group_leader; 1351 get_task_struct(gtt->usertask); 1352 1353 return 0; 1354 } 1355 1356 /* 1357 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1358 */ 1359 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1360 { 1361 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1362 1363 if (gtt == NULL) 1364 return NULL; 1365 1366 if (gtt->usertask == NULL) 1367 return NULL; 1368 1369 return gtt->usertask->mm; 1370 } 1371 1372 /* 1373 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1374 * address range for the current task. 1375 * 1376 */ 1377 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1378 unsigned long end, unsigned long *userptr) 1379 { 1380 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1381 unsigned long size; 1382 1383 if (gtt == NULL || !gtt->userptr) 1384 return false; 1385 1386 /* Return false if no part of the ttm_tt object lies within 1387 * the range 1388 */ 1389 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1390 if (gtt->userptr > end || gtt->userptr + size <= start) 1391 return false; 1392 1393 if (userptr) 1394 *userptr = gtt->userptr; 1395 return true; 1396 } 1397 1398 /* 1399 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1400 */ 1401 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1402 { 1403 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1404 1405 if (gtt == NULL || !gtt->userptr) 1406 return false; 1407 1408 return true; 1409 } 1410 1411 /* 1412 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1413 */ 1414 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1415 { 1416 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1417 1418 if (gtt == NULL) 1419 return false; 1420 1421 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1422 } 1423 1424 /** 1425 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1426 * 1427 * @ttm: The ttm_tt object to compute the flags for 1428 * @mem: The memory registry backing this ttm_tt object 1429 * 1430 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1431 */ 1432 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1433 { 1434 uint64_t flags = 0; 1435 1436 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1437 flags |= AMDGPU_PTE_VALID; 1438 1439 if (mem && (mem->mem_type == TTM_PL_TT || 1440 mem->mem_type == AMDGPU_PL_DOORBELL || 1441 mem->mem_type == AMDGPU_PL_PREEMPT || 1442 mem->mem_type == AMDGPU_PL_MMIO_REMAP)) { 1443 flags |= AMDGPU_PTE_SYSTEM; 1444 1445 if (ttm && ttm->caching == ttm_cached) 1446 flags |= AMDGPU_PTE_SNOOPED; 1447 } 1448 1449 if (mem && mem->mem_type == TTM_PL_VRAM && 1450 mem->bus.caching == ttm_cached) 1451 flags |= AMDGPU_PTE_SNOOPED; 1452 1453 return flags; 1454 } 1455 1456 /** 1457 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1458 * 1459 * @adev: amdgpu_device pointer 1460 * @ttm: The ttm_tt object to compute the flags for 1461 * @mem: The memory registry backing this ttm_tt object 1462 * 1463 * Figure out the flags to use for a VM PTE (Page Table Entry). 1464 */ 1465 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1466 struct ttm_resource *mem) 1467 { 1468 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1469 1470 flags |= adev->gart.gart_pte_flags; 1471 flags |= AMDGPU_PTE_READABLE; 1472 1473 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1474 flags |= AMDGPU_PTE_WRITEABLE; 1475 1476 return flags; 1477 } 1478 1479 /* 1480 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1481 * object. 1482 * 1483 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1484 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1485 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1486 * used to clean out a memory space. 1487 */ 1488 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1489 const struct ttm_place *place) 1490 { 1491 struct dma_resv_iter resv_cursor; 1492 struct amdgpu_bo *abo; 1493 struct dma_fence *f; 1494 1495 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1496 return ttm_bo_eviction_valuable(bo, place); 1497 1498 /* Swapout? */ 1499 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1500 return true; 1501 1502 abo = ttm_to_amdgpu_bo(bo); 1503 if ((abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 1504 bo->destroy == &svm_range_bo_destroy) { 1505 /* 1506 * SVM BOs are migrated to system memory synchronously in this 1507 * TTM eviction context. The migration needs the owning 1508 * process's mmap lock, but the normal lock order is 1509 * mmap_lock -> BO reservation and the BO is already reserved 1510 * here. svm_range_evict_svm_bo() only trylocks the mmap lock; 1511 * if the eviction fails for any reason, we return false so TTM 1512 * skips this BO instead of risking a deadlock. 1513 */ 1514 if (svm_range_evict_svm_bo(abo) < 0) 1515 return false; 1516 } 1517 1518 if (bo->type == ttm_bo_type_kernel && 1519 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1520 return false; 1521 1522 /* If bo is a KFD BO, check if the bo belongs to the current process. 1523 * If true, then return false as any KFD process needs all its BOs to 1524 * be resident to run successfully 1525 */ 1526 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, 1527 DMA_RESV_USAGE_BOOKKEEP, f) { 1528 if (amdkfd_fence_check_mm(f, current->mm) && 1529 !(place && (place->flags & TTM_PL_FLAG_CONTIGUOUS))) 1530 return false; 1531 } 1532 1533 /* Preemptible BOs don't own system resources managed by the 1534 * driver (pages, VRAM, GART space). They point to resources 1535 * owned by someone else (e.g. pageable memory in user mode 1536 * or a DMABuf). They are used in a preemptible context so we 1537 * can guarantee no deadlocks and good QoS in case of MMU 1538 * notifiers or DMABuf move notifiers from the resource owner. 1539 */ 1540 if (bo->resource->mem_type == AMDGPU_PL_PREEMPT) 1541 return false; 1542 1543 if (bo->resource->mem_type == TTM_PL_TT && 1544 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1545 return false; 1546 1547 return ttm_bo_eviction_valuable(bo, place); 1548 } 1549 1550 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1551 void *buf, size_t size, bool write) 1552 { 1553 while (size) { 1554 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1555 uint64_t bytes = 4 - (pos & 0x3); 1556 uint32_t shift = (pos & 0x3) * 8; 1557 uint32_t mask = 0xffffffff << shift; 1558 uint32_t value = 0; 1559 1560 if (size < bytes) { 1561 mask &= 0xffffffff >> (bytes - size) * 8; 1562 bytes = size; 1563 } 1564 1565 if (mask != 0xffffffff) { 1566 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1567 if (write) { 1568 value &= ~mask; 1569 value |= (*(uint32_t *)buf << shift) & mask; 1570 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1571 } else { 1572 value = (value & mask) >> shift; 1573 memcpy(buf, &value, bytes); 1574 } 1575 } else { 1576 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1577 } 1578 1579 pos += bytes; 1580 buf += bytes; 1581 size -= bytes; 1582 } 1583 } 1584 1585 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1586 unsigned long offset, void *buf, 1587 int len, int write) 1588 { 1589 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1590 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1591 struct amdgpu_res_cursor src_mm; 1592 struct amdgpu_job *job; 1593 struct dma_fence *fence; 1594 uint64_t src_addr, dst_addr; 1595 unsigned int num_dw; 1596 int r, idx; 1597 1598 if (len != PAGE_SIZE) 1599 return -EINVAL; 1600 1601 if (!adev->mman.sdma_access_ptr) 1602 return -EACCES; 1603 1604 if (!adev->mman.buffer_funcs_enabled || !drm_dev_enter(adev_to_drm(adev), &idx)) 1605 return -ENODEV; 1606 1607 if (write) 1608 memcpy(adev->mman.sdma_access_ptr, buf, len); 1609 1610 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1611 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, 1612 AMDGPU_FENCE_OWNER_UNDEFINED, 1613 num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1614 AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA, 1615 &job); 1616 if (r) 1617 goto out; 1618 1619 mutex_lock(&adev->mman.default_entity.lock); 1620 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1621 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + 1622 src_mm.start; 1623 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1624 if (write) 1625 swap(src_addr, dst_addr); 1626 1627 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, 1628 PAGE_SIZE, 0); 1629 1630 fence = amdgpu_ttm_job_submit(adev, &adev->mman.default_entity, job, num_dw); 1631 mutex_unlock(&adev->mman.default_entity.lock); 1632 1633 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1634 r = -ETIMEDOUT; 1635 dma_fence_put(fence); 1636 1637 if (!(r || write)) 1638 memcpy(buf, adev->mman.sdma_access_ptr, len); 1639 out: 1640 drm_dev_exit(idx); 1641 return r; 1642 } 1643 1644 /** 1645 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1646 * 1647 * @bo: The buffer object to read/write 1648 * @offset: Offset into buffer object 1649 * @buf: Secondary buffer to write/read from 1650 * @len: Length in bytes of access 1651 * @write: true if writing 1652 * 1653 * This is used to access VRAM that backs a buffer object via MMIO 1654 * access for debugging purposes. 1655 */ 1656 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1657 unsigned long offset, void *buf, int len, 1658 int write) 1659 { 1660 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1661 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1662 struct amdgpu_res_cursor cursor; 1663 int ret = 0; 1664 1665 if (bo->resource->mem_type != TTM_PL_VRAM) 1666 return -EIO; 1667 1668 if (amdgpu_device_has_timeouts_enabled(adev) && 1669 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1670 return len; 1671 1672 amdgpu_res_first(bo->resource, offset, len, &cursor); 1673 while (cursor.remaining) { 1674 size_t count, size = cursor.size; 1675 loff_t pos = cursor.start; 1676 1677 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1678 size -= count; 1679 if (size) { 1680 /* using MM to access rest vram and handle un-aligned address */ 1681 pos += count; 1682 buf += count; 1683 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1684 } 1685 1686 ret += cursor.size; 1687 buf += cursor.size; 1688 amdgpu_res_next(&cursor, cursor.size); 1689 } 1690 1691 return ret; 1692 } 1693 1694 static void 1695 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1696 { 1697 if (bo->resource && bo->resource->mem_type == TTM_PL_TT) 1698 amdgpu_gtt_mgr_mark_bo_teardown(bo); 1699 1700 amdgpu_bo_move_notify(bo, false, NULL); 1701 } 1702 1703 static struct ttm_device_funcs amdgpu_bo_driver = { 1704 .ttm_tt_create = &amdgpu_ttm_tt_create, 1705 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1706 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1707 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1708 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1709 .evict_flags = &amdgpu_evict_flags, 1710 .move = &amdgpu_bo_move, 1711 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1712 .release_notify = &amdgpu_bo_release_notify, 1713 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1714 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1715 .access_memory = &amdgpu_ttm_access_memory, 1716 }; 1717 1718 void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev, 1719 enum amdgpu_resv_region_id id, 1720 uint64_t offset, uint64_t size, 1721 bool needs_cpu_map) 1722 { 1723 struct amdgpu_vram_resv *resv; 1724 1725 if (id >= AMDGPU_RESV_MAX) 1726 return; 1727 1728 resv = &adev->mman.resv_region[id]; 1729 resv->offset = offset; 1730 resv->size = size; 1731 resv->needs_cpu_map = needs_cpu_map; 1732 } 1733 1734 static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev) 1735 { 1736 uint32_t reserve_size = 0; 1737 1738 if (!adev->discovery.reserve_tmr) 1739 return; 1740 1741 /* 1742 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1743 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1744 * 1745 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1746 * discovery data and G6 memory training data respectively 1747 */ 1748 if (adev->bios) 1749 reserve_size = 1750 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1751 1752 if (!adev->bios && 1753 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1754 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1755 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) 1756 reserve_size = max(reserve_size, (uint32_t)280 << 20); 1757 else if (!adev->bios && 1758 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { 1759 reserve_size = max(reserve_size, (uint32_t)150 << 20); 1760 } else if (!reserve_size) 1761 reserve_size = DISCOVERY_TMR_OFFSET; 1762 1763 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1764 adev->gmc.real_vram_size - reserve_size, 1765 reserve_size, false); 1766 } 1767 1768 static void amdgpu_ttm_init_mem_train_resv_region(struct amdgpu_device *adev) 1769 { 1770 uint64_t reserve_size; 1771 uint64_t offset; 1772 1773 if (!adev->discovery.reserve_tmr) 1774 return; 1775 1776 if (!adev->bios || amdgpu_sriov_vf(adev)) 1777 return; 1778 1779 if (!amdgpu_atomfirmware_mem_training_supported(adev)) 1780 return; 1781 1782 reserve_size = adev->mman.resv_region[AMDGPU_RESV_FW].size; 1783 offset = ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1784 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_MEM_TRAIN, 1785 offset, 1786 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES, 1787 false); 1788 } 1789 1790 static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev) 1791 { 1792 uint64_t vram_size = adev->gmc.visible_vram_size; 1793 1794 /* Initialize memory reservations as required for VGA. 1795 * This is used for VGA emulation and pre-OS scanout buffers to 1796 * avoid display artifacts while transitioning between pre-OS 1797 * and driver. 1798 */ 1799 amdgpu_gmc_init_vga_resv_regions(adev); 1800 amdgpu_ttm_init_fw_resv_region(adev); 1801 amdgpu_ttm_init_mem_train_resv_region(adev); 1802 1803 if (adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size > vram_size) 1804 adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size = 0; 1805 1806 if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size > vram_size) 1807 adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0; 1808 } 1809 1810 int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, 1811 enum amdgpu_resv_region_id id) 1812 { 1813 struct amdgpu_vram_resv *resv; 1814 int ret; 1815 1816 if (id >= AMDGPU_RESV_MAX) 1817 return -EINVAL; 1818 1819 resv = &adev->mman.resv_region[id]; 1820 if (!resv->size) 1821 return 0; 1822 1823 ret = amdgpu_bo_create_kernel_at(adev, resv->offset, resv->size, 1824 &resv->bo, 1825 resv->needs_cpu_map ? &resv->cpu_ptr : NULL); 1826 if (ret) { 1827 dev_err(adev->dev, 1828 "reserve vram failed: id=%d offset=0x%llx size=0x%llx ret=%d\n", 1829 id, resv->offset, resv->size, ret); 1830 memset(resv, 0, sizeof(*resv)); 1831 } 1832 1833 return ret; 1834 } 1835 1836 void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, 1837 enum amdgpu_resv_region_id id) 1838 { 1839 struct amdgpu_vram_resv *resv; 1840 1841 if (id >= AMDGPU_RESV_MAX) 1842 return; 1843 1844 resv = &adev->mman.resv_region[id]; 1845 if (!resv->bo) 1846 return; 1847 1848 amdgpu_bo_free_kernel(&resv->bo, NULL, 1849 resv->needs_cpu_map ? &resv->cpu_ptr : NULL); 1850 memset(resv, 0, sizeof(*resv)); 1851 } 1852 1853 /* 1854 * Reserve all regions with non-zero size. Regions whose info is not 1855 * yet available (e.g., fw extended region) may still be reserved 1856 * during runtime. 1857 */ 1858 static int amdgpu_ttm_alloc_vram_resv_regions(struct amdgpu_device *adev) 1859 { 1860 int i, r; 1861 1862 for (i = 0; i < AMDGPU_RESV_MAX; i++) { 1863 r = amdgpu_ttm_mark_vram_reserved(adev, i); 1864 if (r) 1865 return r; 1866 } 1867 1868 return 0; 1869 } 1870 1871 /* 1872 * Memoy training reservation functions 1873 */ 1874 1875 /** 1876 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1877 * 1878 * @adev: amdgpu_device pointer 1879 * 1880 * free memory training reserved vram if it has been reserved. 1881 */ 1882 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1883 { 1884 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1885 1886 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1887 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_MEM_TRAIN); 1888 1889 return 0; 1890 } 1891 1892 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1893 { 1894 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1895 struct amdgpu_vram_resv *resv = 1896 &adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN]; 1897 1898 memset(ctx, 0, sizeof(*ctx)); 1899 1900 ctx->c2p_train_data_offset = resv->offset; 1901 ctx->p2c_train_data_offset = 1902 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1903 ctx->train_data_size = resv->size; 1904 1905 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1906 ctx->train_data_size, 1907 ctx->p2c_train_data_offset, 1908 ctx->c2p_train_data_offset); 1909 } 1910 1911 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) 1912 { 1913 int i; 1914 1915 if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions) 1916 return 0; 1917 1918 adev->mman.ttm_pools = kzalloc_objs(*adev->mman.ttm_pools, 1919 adev->gmc.num_mem_partitions); 1920 if (!adev->mman.ttm_pools) 1921 return -ENOMEM; 1922 1923 for (i = 0; i < adev->gmc.num_mem_partitions; i++) { 1924 ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev, 1925 adev->gmc.mem_partitions[i].numa.node, 1926 TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M))); 1927 } 1928 return 0; 1929 } 1930 1931 static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) 1932 { 1933 int i; 1934 1935 if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools) 1936 return; 1937 1938 for (i = 0; i < adev->gmc.num_mem_partitions; i++) 1939 ttm_pool_fini(&adev->mman.ttm_pools[i]); 1940 1941 kfree(adev->mman.ttm_pools); 1942 adev->mman.ttm_pools = NULL; 1943 } 1944 1945 /** 1946 * amdgpu_ttm_alloc_mmio_remap_bo - Allocate the singleton MMIO_REMAP BO 1947 * @adev: amdgpu device 1948 * 1949 * Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the 1950 * hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host 1951 * PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular 1952 * GEM object (amdgpu_bo_create). 1953 * 1954 * Return: 1955 * * 0 on success or intentional skip (feature not present/unsupported) 1956 * * negative errno on allocation failure 1957 */ 1958 static int amdgpu_ttm_alloc_mmio_remap_bo(struct amdgpu_device *adev) 1959 { 1960 struct ttm_operation_ctx ctx = { false, false }; 1961 struct ttm_placement placement; 1962 struct ttm_buffer_object *tbo; 1963 struct ttm_place placements; 1964 struct amdgpu_bo_param bp; 1965 struct ttm_resource *tmp; 1966 int r; 1967 1968 /* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */ 1969 if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE) 1970 return 0; 1971 1972 /* 1973 * Allocate a BO first and then move it to AMDGPU_PL_MMIO_REMAP. 1974 * The initial TTM resource assigned by amdgpu_bo_create() is 1975 * replaced below with a fixed MMIO_REMAP placement. 1976 */ 1977 memset(&bp, 0, sizeof(bp)); 1978 bp.type = ttm_bo_type_device; 1979 bp.size = AMDGPU_GPU_PAGE_SIZE; 1980 bp.byte_align = AMDGPU_GPU_PAGE_SIZE; 1981 bp.domain = 0; 1982 bp.flags = 0; 1983 bp.resv = NULL; 1984 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 1985 r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo); 1986 if (r) 1987 return r; 1988 1989 r = amdgpu_bo_reserve(adev->rmmio_remap.bo, true); 1990 if (r) 1991 goto err_unref; 1992 1993 tbo = &adev->rmmio_remap.bo->tbo; 1994 1995 /* 1996 * MMIO_REMAP is a fixed I/O placement (AMDGPU_PL_MMIO_REMAP). 1997 */ 1998 placement.num_placement = 1; 1999 placement.placement = &placements; 2000 placements.fpfn = 0; 2001 placements.lpfn = 0; 2002 placements.mem_type = AMDGPU_PL_MMIO_REMAP; 2003 placements.flags = 0; 2004 /* Force the BO into the fixed MMIO_REMAP placement */ 2005 r = ttm_bo_mem_space(tbo, &placement, &tmp, &ctx); 2006 if (unlikely(r)) 2007 goto err_unlock; 2008 2009 ttm_resource_free(tbo, &tbo->resource); 2010 ttm_bo_assign_mem(tbo, tmp); 2011 ttm_bo_pin(tbo); 2012 2013 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 2014 return 0; 2015 2016 err_unlock: 2017 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 2018 2019 err_unref: 2020 amdgpu_bo_unref(&adev->rmmio_remap.bo); 2021 adev->rmmio_remap.bo = NULL; 2022 return r; 2023 } 2024 2025 /** 2026 * amdgpu_ttm_free_mmio_remap_bo - Free the singleton MMIO_REMAP BO 2027 * @adev: amdgpu device 2028 * 2029 * Frees the kernel-owned MMIO_REMAP BO if it was allocated by 2030 * amdgpu_ttm_mmio_remap_bo_init(). 2031 */ 2032 static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) 2033 { 2034 if (!adev->rmmio_remap.bo) 2035 return; 2036 2037 if (!amdgpu_bo_reserve(adev->rmmio_remap.bo, true)) { 2038 ttm_bo_unpin(&adev->rmmio_remap.bo->tbo); 2039 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 2040 } 2041 2042 /* 2043 * At this point we rely on normal DRM teardown ordering: 2044 * no new user ioctls can access the global MMIO_REMAP BO 2045 * once TTM teardown begins. 2046 */ 2047 amdgpu_bo_unref(&adev->rmmio_remap.bo); 2048 adev->rmmio_remap.bo = NULL; 2049 } 2050 2051 static int amdgpu_ttm_buffer_entity_init(struct amdgpu_gtt_mgr *mgr, 2052 struct amdgpu_ttm_buffer_entity *entity, 2053 enum drm_sched_priority prio, 2054 struct drm_gpu_scheduler **scheds, 2055 int num_schedulers, 2056 u32 num_gart_windows) 2057 { 2058 int i, r, num_pages; 2059 const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); 2060 2061 r = drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, NULL); 2062 if (r) 2063 return r; 2064 2065 mutex_init(&entity->lock); 2066 2067 if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) 2068 return -EINVAL; 2069 if (num_gart_windows == 0) 2070 return 0; 2071 2072 num_pages = num_gart_windows * GTT_MAX_PAGES; 2073 r = amdgpu_gtt_mgr_alloc_entries(mgr, &entity->gart_node, num_pages, 2074 DRM_MM_INSERT_BEST); 2075 if (r) { 2076 drm_sched_entity_destroy(&entity->base); 2077 return r; 2078 } 2079 2080 for (i = 0; i < num_gart_windows; i++) { 2081 entity->gart_window_offs[i] = 2082 amdgpu_gtt_node_to_byte_offset(&entity->gart_node) + 2083 i * GTT_MAX_PAGES * PAGE_SIZE; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_gtt_mgr *mgr, 2090 struct amdgpu_ttm_buffer_entity *entity) 2091 { 2092 amdgpu_gtt_mgr_free_entries(mgr, &entity->gart_node); 2093 drm_sched_entity_destroy(&entity->base); 2094 } 2095 2096 /* 2097 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 2098 * gtt/vram related fields. 2099 * 2100 * This initializes all of the memory space pools that the TTM layer 2101 * will need such as the GTT space (system memory mapped to the device), 2102 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 2103 * can be mapped per VMID. 2104 */ 2105 int amdgpu_ttm_init(struct amdgpu_device *adev) 2106 { 2107 uint64_t gtt_size; 2108 int r; 2109 2110 dma_set_max_seg_size(adev->dev, UINT_MAX); 2111 /* No others user of address space so set it to 0 */ 2112 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 2113 adev_to_drm(adev)->anon_inode->i_mapping, 2114 adev_to_drm(adev)->vma_offset_manager, 2115 (adev->need_swiotlb ? 2116 TTM_ALLOCATION_POOL_USE_DMA_ALLOC : 0) | 2117 (dma_addressing_limited(adev->dev) ? 2118 TTM_ALLOCATION_POOL_USE_DMA32 : 0) | 2119 TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M))); 2120 if (r) { 2121 dev_err(adev->dev, 2122 "failed initializing buffer object driver(%d).\n", r); 2123 return r; 2124 } 2125 2126 r = amdgpu_ttm_pools_init(adev); 2127 if (r) { 2128 dev_err(adev->dev, "failed to init ttm pools(%d).\n", r); 2129 return r; 2130 } 2131 adev->mman.initialized = true; 2132 2133 if (!adev->gmc.is_app_apu) { 2134 /* Initialize VRAM pool with all of VRAM divided into pages */ 2135 r = amdgpu_vram_mgr_init(adev); 2136 if (r) { 2137 dev_err(adev->dev, "Failed initializing VRAM heap.\n"); 2138 return r; 2139 } 2140 } 2141 2142 /* Change the size here instead of the init above so only lpfn is affected */ 2143 amdgpu_ttm_disable_buffer_funcs(adev); 2144 #ifdef CONFIG_64BIT 2145 #ifdef CONFIG_X86 2146 if (adev->gmc.xgmi.connected_to_cpu) 2147 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 2148 adev->gmc.visible_vram_size); 2149 else if (adev->gmc.is_app_apu) 2150 DRM_DEBUG_DRIVER( 2151 "No need to ioremap when real vram size is 0\n"); 2152 else 2153 #endif 2154 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 2155 adev->gmc.visible_vram_size); 2156 #endif 2157 2158 amdgpu_ttm_init_vram_resv_regions(adev); 2159 2160 r = amdgpu_ttm_alloc_vram_resv_regions(adev); 2161 if (r) 2162 return r; 2163 2164 if (adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN].size) { 2165 struct psp_memory_training_context *ctx = 2166 &adev->psp.mem_train_ctx; 2167 2168 amdgpu_ttm_training_data_block_init(adev); 2169 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 2170 } 2171 2172 dev_info(adev->dev, " %uM of VRAM memory ready\n", 2173 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024))); 2174 2175 /* Compute GTT size, either based on TTM limit 2176 * or whatever the user passed on module init. 2177 */ 2178 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT; 2179 if (amdgpu_gtt_size != -1) { 2180 uint64_t configured_size = (uint64_t)amdgpu_gtt_size << 20; 2181 2182 drm_warn(&adev->ddev, 2183 "Configuring gttsize via module parameter is deprecated, please use ttm.pages_limit\n"); 2184 if (gtt_size != configured_size) 2185 drm_warn(&adev->ddev, 2186 "GTT size has been set as %llu but TTM size has been set as %llu, this is unusual\n", 2187 configured_size, gtt_size); 2188 2189 gtt_size = configured_size; 2190 } 2191 2192 /* Cap GTT so that it does not exceed total physical RAM. */ 2193 if (adev->flags & AMD_IS_APU) { 2194 u64 phys_ram = (u64)totalram_pages() << PAGE_SHIFT; 2195 2196 if (gtt_size > phys_ram) { 2197 gtt_size = phys_ram; 2198 dev_info(adev->dev, 2199 "Capping GTT to %uM to not exceed available system memory\n", 2200 (unsigned int)(gtt_size / (1024 * 1024))); 2201 } 2202 } 2203 2204 /* Initialize GTT memory pool */ 2205 r = amdgpu_gtt_mgr_init(adev, gtt_size); 2206 if (r) { 2207 dev_err(adev->dev, "Failed initializing GTT heap.\n"); 2208 return r; 2209 } 2210 dev_info(adev->dev, " %uM of GTT memory ready.\n", 2211 (unsigned int)(gtt_size / (1024 * 1024))); 2212 2213 if (adev->flags & AMD_IS_APU) { 2214 if (adev->gmc.real_vram_size < gtt_size) 2215 adev->apu_prefer_gtt = true; 2216 } 2217 2218 /* Initialize doorbell pool on PCI BAR */ 2219 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); 2220 if (r) { 2221 dev_err(adev->dev, "Failed initializing doorbell heap.\n"); 2222 return r; 2223 } 2224 2225 /* Create a doorbell page for kernel usages */ 2226 r = amdgpu_doorbell_create_kernel_doorbells(adev); 2227 if (r) { 2228 dev_err(adev->dev, "Failed to initialize kernel doorbells.\n"); 2229 return r; 2230 } 2231 2232 /* Initialize MMIO-remap pool (single page 4K) */ 2233 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_MMIO_REMAP, 1); 2234 if (r) { 2235 dev_err(adev->dev, "Failed initializing MMIO-remap heap.\n"); 2236 return r; 2237 } 2238 2239 /* Allocate the singleton MMIO_REMAP BO if supported */ 2240 r = amdgpu_ttm_alloc_mmio_remap_bo(adev); 2241 if (r) 2242 return r; 2243 2244 /* Initialize preemptible memory pool */ 2245 r = amdgpu_preempt_mgr_init(adev); 2246 if (r) { 2247 dev_err(adev->dev, "Failed initializing PREEMPT heap.\n"); 2248 return r; 2249 } 2250 2251 /* Initialize various on-chip memory pools */ 2252 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 2253 if (r) { 2254 dev_err(adev->dev, "Failed initializing GDS heap.\n"); 2255 return r; 2256 } 2257 2258 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 2259 if (r) { 2260 dev_err(adev->dev, "Failed initializing gws heap.\n"); 2261 return r; 2262 } 2263 2264 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 2265 if (r) { 2266 dev_err(adev->dev, "Failed initializing oa heap.\n"); 2267 return r; 2268 } 2269 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 2270 AMDGPU_GEM_DOMAIN_GTT, 2271 &adev->mman.sdma_access_bo, NULL, 2272 &adev->mman.sdma_access_ptr)) 2273 drm_warn(adev_to_drm(adev), 2274 "Debug VRAM access will use slowpath MM access\n"); 2275 2276 return 0; 2277 } 2278 2279 /* 2280 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2281 */ 2282 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2283 { 2284 if (!adev->mman.initialized) 2285 return; 2286 2287 amdgpu_ttm_pools_fini(adev); 2288 2289 amdgpu_ttm_training_reserve_vram_fini(adev); 2290 /* return the stolen vga memory back to VRAM */ 2291 if (!adev->gmc.is_app_apu) { 2292 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 2293 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 2294 /* return the FW reserved memory back to VRAM */ 2295 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 2296 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 2297 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_RESERVED); 2298 } 2299 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 2300 &adev->mman.sdma_access_ptr); 2301 2302 amdgpu_ttm_free_mmio_remap_bo(adev); 2303 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE); 2304 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); 2305 2306 if (adev->mman.aper_base_kaddr) { 2307 iounmap(adev->mman.aper_base_kaddr); 2308 adev->mman.aper_base_kaddr = NULL; 2309 } 2310 2311 if (!adev->gmc.is_app_apu) 2312 amdgpu_vram_mgr_fini(adev); 2313 amdgpu_gtt_mgr_fini(adev); 2314 amdgpu_preempt_mgr_fini(adev); 2315 amdgpu_doorbell_fini(adev); 2316 2317 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 2318 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2319 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2320 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DOORBELL); 2321 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_MMIO_REMAP); 2322 ttm_device_fini(&adev->mman.bdev); 2323 adev->mman.initialized = false; 2324 dev_info(adev->dev, " ttm finalized\n"); 2325 } 2326 2327 /** 2328 * amdgpu_ttm_enable_buffer_funcs - enable use of buffer functions 2329 * 2330 * @adev: amdgpu_device pointer 2331 * 2332 * Enable use of buffer functions during suspend/resume. This should 2333 * only be called at bootup or when userspace isn't running. 2334 */ 2335 void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev) 2336 { 2337 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2338 u32 num_clear_entities, num_move_entities; 2339 int r, i, j; 2340 2341 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 2342 adev->mman.buffer_funcs_enabled || adev->gmc.is_app_apu) 2343 return; 2344 2345 if (!adev->mman.num_buffer_funcs_scheds) { 2346 dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); 2347 return; 2348 } 2349 2350 /* default_entity doesn't need multiple schedulers so pass only 1. */ 2351 r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, 2352 &adev->mman.default_entity, 2353 DRM_SCHED_PRIORITY_KERNEL, 2354 adev->mman.buffer_funcs_scheds, 1, 0); 2355 if (r < 0) { 2356 dev_err(adev->dev, 2357 "Failed setting up TTM entity (%d)\n", r); 2358 return; 2359 } 2360 2361 num_clear_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); 2362 num_move_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); 2363 2364 adev->mman.clear_entities = kcalloc(num_clear_entities, 2365 sizeof(struct amdgpu_ttm_buffer_entity), 2366 GFP_KERNEL); 2367 atomic_set(&adev->mman.next_clear_entity, 0); 2368 if (!adev->mman.clear_entities) 2369 goto error_free_default_entity; 2370 2371 adev->mman.num_clear_entities = num_clear_entities; 2372 2373 for (i = 0; i < num_clear_entities; i++) { 2374 r = amdgpu_ttm_buffer_entity_init( 2375 &adev->mman.gtt_mgr, 2376 &adev->mman.clear_entities[i], 2377 DRM_SCHED_PRIORITY_KERNEL, 2378 adev->mman.buffer_funcs_scheds, 2379 adev->mman.num_buffer_funcs_scheds, 1); 2380 2381 if (r < 0) { 2382 for (j = 0; j < i; j++) 2383 amdgpu_ttm_buffer_entity_fini( 2384 &adev->mman.gtt_mgr, &adev->mman.clear_entities[j]); 2385 adev->mman.num_clear_entities = 0; 2386 kfree(adev->mman.clear_entities); 2387 goto error_free_default_entity; 2388 } 2389 } 2390 2391 adev->mman.num_move_entities = num_move_entities; 2392 atomic_set(&adev->mman.next_move_entity, 0); 2393 for (i = 0; i < num_move_entities; i++) { 2394 r = amdgpu_ttm_buffer_entity_init( 2395 &adev->mman.gtt_mgr, 2396 &adev->mman.move_entities[i], 2397 DRM_SCHED_PRIORITY_KERNEL, 2398 adev->mman.buffer_funcs_scheds, 2399 adev->mman.num_buffer_funcs_scheds, 2); 2400 2401 if (r < 0) { 2402 for (j = 0; j < i; j++) 2403 amdgpu_ttm_buffer_entity_fini( 2404 &adev->mman.gtt_mgr, 2405 &adev->mman.move_entities[j]); 2406 adev->mman.num_move_entities = 0; 2407 goto error_free_clear_entities; 2408 } 2409 } 2410 2411 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2412 man->size = adev->gmc.real_vram_size; 2413 adev->mman.buffer_funcs_enabled = true; 2414 2415 return; 2416 2417 error_free_clear_entities: 2418 for (i = 0; i < adev->mman.num_clear_entities; i++) 2419 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2420 &adev->mman.clear_entities[i]); 2421 kfree(adev->mman.clear_entities); 2422 adev->mman.clear_entities = NULL; 2423 adev->mman.num_clear_entities = 0; 2424 error_free_default_entity: 2425 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2426 &adev->mman.default_entity); 2427 } 2428 2429 /** 2430 * amdgpu_ttm_disable_buffer_funcs - disable use of buffer functions 2431 * 2432 * @adev: amdgpu_device pointer 2433 */ 2434 void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev) 2435 { 2436 struct ttm_resource_manager *man = 2437 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2438 int i; 2439 2440 if (!adev->mman.buffer_funcs_enabled || amdgpu_in_reset(adev)) 2441 return; 2442 2443 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2444 &adev->mman.default_entity); 2445 for (i = 0; i < adev->mman.num_move_entities; i++) 2446 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2447 &adev->mman.move_entities[i]); 2448 for (i = 0; i < adev->mman.num_clear_entities; i++) 2449 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2450 &adev->mman.clear_entities[i]); 2451 /* Drop all the old fences since re-creating the scheduler entities 2452 * will allocate new contexts. 2453 */ 2454 ttm_resource_manager_cleanup(man); 2455 2456 kfree(adev->mman.clear_entities); 2457 adev->mman.clear_entities = NULL; 2458 adev->mman.num_clear_entities = 0; 2459 adev->mman.num_move_entities = 0; 2460 2461 man->size = adev->gmc.visible_vram_size; 2462 adev->mman.buffer_funcs_enabled = false; 2463 } 2464 2465 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, 2466 struct amdgpu_ttm_buffer_entity *entity, 2467 unsigned int num_dw, 2468 struct dma_resv *resv, 2469 bool vm_needs_flush, 2470 struct amdgpu_job **job, 2471 u64 k_job_id) 2472 { 2473 enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED; 2474 int r; 2475 r = amdgpu_job_alloc_with_ib(adev, &entity->base, 2476 AMDGPU_FENCE_OWNER_UNDEFINED, 2477 num_dw * 4, pool, k_job_id, job); 2478 if (r) 2479 return r; 2480 2481 if (vm_needs_flush) { 2482 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 2483 adev->gmc.pdb0_bo : 2484 adev->gart.bo); 2485 (*job)->vm_needs_flush = true; 2486 } 2487 if (!resv) 2488 return 0; 2489 2490 return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, 2491 DMA_RESV_USAGE_BOOKKEEP); 2492 } 2493 2494 static int amdgpu_calc_bytes_per_packet(u32 max_bytes_per_packet, 2495 u32 byte_count) 2496 { 2497 /* Byte count is dword-aligned and fits a single packet */ 2498 if (!(byte_count & 0x3) && byte_count <= max_bytes_per_packet) 2499 return max_bytes_per_packet; 2500 2501 /* 2502 * Align down maximum byte count to 256 bytes so that 2503 * the copy optimally uses all memory channels and 2504 * also to ensure that SDMA can use its dword mode, which 2505 * is faster. 2506 * 2507 * This assumes that the starting addresses of BOs are always 2508 * dword aligned, which should be the case for every copy 2509 * operation in the kernel, because the kernel always copies 2510 * pages. 2511 */ 2512 return ALIGN_DOWN(max_bytes_per_packet, SZ_256); 2513 } 2514 2515 int amdgpu_copy_buffer(struct amdgpu_device *adev, 2516 struct amdgpu_ttm_buffer_entity *entity, 2517 uint64_t src_offset, 2518 uint64_t dst_offset, uint32_t byte_count, 2519 struct dma_resv *resv, 2520 struct dma_fence **fence, 2521 bool vm_needs_flush, uint32_t copy_flags) 2522 { 2523 unsigned int num_loops, num_dw; 2524 struct amdgpu_ring *ring; 2525 struct amdgpu_job *job; 2526 uint32_t max_bytes; 2527 unsigned int i; 2528 int r; 2529 2530 ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); 2531 2532 if (!ring->sched.ready) { 2533 dev_err(adev->dev, 2534 "Trying to move memory with ring turned off.\n"); 2535 return -EINVAL; 2536 } 2537 2538 max_bytes = amdgpu_calc_bytes_per_packet(adev->mman.buffer_funcs->copy_max_bytes, 2539 byte_count); 2540 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2541 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2542 r = amdgpu_ttm_prepare_job(adev, entity, num_dw, 2543 resv, vm_needs_flush, &job, 2544 AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); 2545 if (r) 2546 goto error_free; 2547 2548 for (i = 0; i < num_loops; i++) { 2549 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2550 2551 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2552 dst_offset, cur_size_in_bytes, copy_flags); 2553 src_offset += cur_size_in_bytes; 2554 dst_offset += cur_size_in_bytes; 2555 byte_count -= cur_size_in_bytes; 2556 } 2557 2558 *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); 2559 2560 return 0; 2561 2562 error_free: 2563 amdgpu_job_free(job); 2564 dev_err(adev->dev, "Error scheduling IBs (%d)\n", r); 2565 return r; 2566 } 2567 2568 static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, 2569 struct amdgpu_ttm_buffer_entity *entity, 2570 uint32_t src_data, 2571 uint64_t dst_addr, uint32_t byte_count, 2572 struct dma_resv *resv, 2573 struct dma_fence **fence, 2574 bool vm_needs_flush, 2575 u64 k_job_id) 2576 { 2577 unsigned int num_loops, num_dw; 2578 struct amdgpu_job *job; 2579 uint32_t max_bytes; 2580 unsigned int i; 2581 int r; 2582 2583 max_bytes = amdgpu_calc_bytes_per_packet(adev->mman.buffer_funcs->fill_max_bytes, 2584 byte_count); 2585 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); 2586 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); 2587 r = amdgpu_ttm_prepare_job(adev, entity, num_dw, resv, 2588 vm_needs_flush, &job, k_job_id); 2589 if (r) 2590 return r; 2591 2592 for (i = 0; i < num_loops; i++) { 2593 uint32_t cur_size = min(byte_count, max_bytes); 2594 2595 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2596 cur_size); 2597 2598 dst_addr += cur_size; 2599 byte_count -= cur_size; 2600 } 2601 2602 *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); 2603 return 0; 2604 } 2605 2606 /** 2607 * amdgpu_ttm_clear_buffer - fill a buffer with 0 2608 * @entity: entity to use 2609 * @bo: the bo to fill 2610 * @resv: fences contained in this reservation will be used as dependencies. 2611 * @out_fence: the fence from the last clear will be stored here. It might be 2612 * NULL if no job was run. 2613 * @consider_clear_status: true if region reported as cleared by amdgpu_res_cleared() 2614 * are skipped. 2615 * @k_job_id: trace id 2616 * 2617 */ 2618 int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, 2619 struct amdgpu_bo *bo, 2620 struct dma_resv *resv, 2621 struct dma_fence **out_fence, 2622 bool consider_clear_status, 2623 u64 k_job_id) 2624 { 2625 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2626 struct dma_fence *fence = NULL; 2627 struct amdgpu_res_cursor dst; 2628 int r; 2629 2630 if (!entity) 2631 return -EINVAL; 2632 2633 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); 2634 2635 mutex_lock(&entity->lock); 2636 while (dst.remaining) { 2637 struct dma_fence *next; 2638 uint64_t cur_size, to; 2639 2640 if (consider_clear_status && amdgpu_res_cleared(&dst)) { 2641 amdgpu_res_next(&dst, dst.size); 2642 continue; 2643 } 2644 2645 /* Never fill more than 256MiB at once to avoid timeouts */ 2646 cur_size = min(dst.size, 256ULL << 20); 2647 2648 r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &dst, 2649 0, false, &cur_size, &to); 2650 if (r) 2651 goto error; 2652 2653 r = amdgpu_ttm_fill_mem(adev, entity, 2654 0, to, cur_size, resv, 2655 &next, true, k_job_id); 2656 if (r) 2657 goto error; 2658 2659 dma_fence_put(fence); 2660 fence = next; 2661 2662 amdgpu_res_next(&dst, cur_size); 2663 } 2664 error: 2665 mutex_unlock(&entity->lock); 2666 *out_fence = fence; 2667 return r; 2668 } 2669 2670 struct amdgpu_ttm_buffer_entity * 2671 amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev) 2672 { 2673 struct amdgpu_mman *mman = &adev->mman; 2674 u32 i; 2675 2676 if (mman->num_clear_entities == 0) 2677 return NULL; 2678 2679 i = atomic_inc_return(&mman->next_clear_entity) % 2680 mman->num_clear_entities; 2681 return &mman->clear_entities[i]; 2682 } 2683 2684 /** 2685 * amdgpu_ttm_evict_resources - evict memory buffers 2686 * @adev: amdgpu device object 2687 * @mem_type: evicted BO's memory type 2688 * 2689 * Evicts all @mem_type buffers on the lru list of the memory type. 2690 * 2691 * Returns: 2692 * 0 for success or a negative error code on failure. 2693 */ 2694 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2695 { 2696 struct ttm_resource_manager *man; 2697 2698 switch (mem_type) { 2699 case TTM_PL_VRAM: 2700 case TTM_PL_TT: 2701 case AMDGPU_PL_GWS: 2702 case AMDGPU_PL_GDS: 2703 case AMDGPU_PL_OA: 2704 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2705 break; 2706 default: 2707 dev_err(adev->dev, "Trying to evict invalid memory type\n"); 2708 return -EINVAL; 2709 } 2710 2711 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2712 } 2713 2714 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 2715 const struct amdgpu_buffer_funcs *buffer_funcs) 2716 { 2717 struct drm_gpu_scheduler *sched; 2718 struct amdgpu_vmhub *hub; 2719 int i, n; 2720 2721 adev->mman.buffer_funcs = buffer_funcs; 2722 2723 for (i = 0, n = 0; i < adev->sdma.num_instances; i++) { 2724 if (adev->sdma.has_page_queue) 2725 sched = &adev->sdma.instance[i].page.sched; 2726 else 2727 sched = &adev->sdma.instance[i].ring.sched; 2728 2729 if (!sched->ready) 2730 continue; 2731 2732 adev->mman.buffer_funcs_scheds[n++] = sched; 2733 } 2734 2735 if (n == 0) { 2736 adev->mman.num_buffer_funcs_scheds = 0; 2737 drm_warn(&adev->ddev, "No working sdma ring available\n"); 2738 return; 2739 } 2740 2741 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 2742 2743 /* 2744 * Allow using multiple SDMA schedulers only on GPUs where 2745 * we are allowed to do concurrent VM flushes. 2746 * This consideration is necessary because all GART windows 2747 * are mapped in VMID 0 (the kernel VMID) so each buffer 2748 * entity would flush VMID 0 concurrently. 2749 * 2750 * Also consider the SDMA invalidation workaround on 2751 * Navi 1x GPUs, which also prevents us from using 2752 * multiple SDMA engines on VMID 0 at the same time. 2753 */ 2754 adev->mman.num_buffer_funcs_scheds = 2755 (adev->vm_manager.concurrent_flush && 2756 !hub->sdma_invalidation_workaround) ? n : 1; 2757 } 2758 2759 #if defined(CONFIG_DEBUG_FS) 2760 2761 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2762 { 2763 struct amdgpu_device *adev = m->private; 2764 2765 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2766 } 2767 2768 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2769 2770 /* 2771 * amdgpu_ttm_vram_read - Linear read access to VRAM 2772 * 2773 * Accesses VRAM via MMIO for debugging purposes. 2774 */ 2775 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2776 size_t size, loff_t *pos) 2777 { 2778 struct amdgpu_device *adev = file_inode(f)->i_private; 2779 ssize_t result = 0; 2780 2781 if (size & 0x3 || *pos & 0x3) 2782 return -EINVAL; 2783 2784 if (*pos >= adev->gmc.mc_vram_size) 2785 return -ENXIO; 2786 2787 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2788 while (size) { 2789 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2790 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2791 2792 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2793 if (copy_to_user(buf, value, bytes)) 2794 return -EFAULT; 2795 2796 result += bytes; 2797 buf += bytes; 2798 *pos += bytes; 2799 size -= bytes; 2800 } 2801 2802 return result; 2803 } 2804 2805 /* 2806 * amdgpu_ttm_vram_write - Linear write access to VRAM 2807 * 2808 * Accesses VRAM via MMIO for debugging purposes. 2809 */ 2810 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2811 size_t size, loff_t *pos) 2812 { 2813 struct amdgpu_device *adev = file_inode(f)->i_private; 2814 ssize_t result = 0; 2815 int r; 2816 2817 if (size & 0x3 || *pos & 0x3) 2818 return -EINVAL; 2819 2820 if (*pos >= adev->gmc.mc_vram_size) 2821 return -ENXIO; 2822 2823 while (size) { 2824 uint32_t value; 2825 2826 if (*pos >= adev->gmc.mc_vram_size) 2827 return result; 2828 2829 r = get_user(value, (uint32_t *)buf); 2830 if (r) 2831 return r; 2832 2833 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2834 2835 result += 4; 2836 buf += 4; 2837 *pos += 4; 2838 size -= 4; 2839 } 2840 2841 return result; 2842 } 2843 2844 static const struct file_operations amdgpu_ttm_vram_fops = { 2845 .owner = THIS_MODULE, 2846 .read = amdgpu_ttm_vram_read, 2847 .write = amdgpu_ttm_vram_write, 2848 .llseek = default_llseek, 2849 }; 2850 2851 /* 2852 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2853 * 2854 * This function is used to read memory that has been mapped to the 2855 * GPU and the known addresses are not physical addresses but instead 2856 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2857 */ 2858 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2859 size_t size, loff_t *pos) 2860 { 2861 struct amdgpu_device *adev = file_inode(f)->i_private; 2862 struct iommu_domain *dom; 2863 ssize_t result = 0; 2864 int r; 2865 2866 /* retrieve the IOMMU domain if any for this device */ 2867 dom = iommu_get_domain_for_dev(adev->dev); 2868 2869 while (size) { 2870 phys_addr_t addr = *pos & PAGE_MASK; 2871 loff_t off = *pos & ~PAGE_MASK; 2872 size_t bytes = PAGE_SIZE - off; 2873 unsigned long pfn; 2874 struct page *p; 2875 void *ptr; 2876 2877 bytes = min(bytes, size); 2878 2879 /* Translate the bus address to a physical address. If 2880 * the domain is NULL it means there is no IOMMU active 2881 * and the address translation is the identity 2882 */ 2883 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2884 2885 pfn = addr >> PAGE_SHIFT; 2886 if (!pfn_valid(pfn)) 2887 return -EPERM; 2888 2889 p = pfn_to_page(pfn); 2890 if (p->mapping != adev->mman.bdev.dev_mapping) 2891 return -EPERM; 2892 2893 ptr = kmap_local_page(p); 2894 r = copy_to_user(buf, ptr + off, bytes); 2895 kunmap_local(ptr); 2896 if (r) 2897 return -EFAULT; 2898 2899 size -= bytes; 2900 *pos += bytes; 2901 result += bytes; 2902 } 2903 2904 return result; 2905 } 2906 2907 /* 2908 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2909 * 2910 * This function is used to write memory that has been mapped to the 2911 * GPU and the known addresses are not physical addresses but instead 2912 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2913 */ 2914 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2915 size_t size, loff_t *pos) 2916 { 2917 struct amdgpu_device *adev = file_inode(f)->i_private; 2918 struct iommu_domain *dom; 2919 ssize_t result = 0; 2920 int r; 2921 2922 dom = iommu_get_domain_for_dev(adev->dev); 2923 2924 while (size) { 2925 phys_addr_t addr = *pos & PAGE_MASK; 2926 loff_t off = *pos & ~PAGE_MASK; 2927 size_t bytes = PAGE_SIZE - off; 2928 unsigned long pfn; 2929 struct page *p; 2930 void *ptr; 2931 2932 bytes = min(bytes, size); 2933 2934 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2935 2936 pfn = addr >> PAGE_SHIFT; 2937 if (!pfn_valid(pfn)) 2938 return -EPERM; 2939 2940 p = pfn_to_page(pfn); 2941 if (p->mapping != adev->mman.bdev.dev_mapping) 2942 return -EPERM; 2943 2944 ptr = kmap_local_page(p); 2945 r = copy_from_user(ptr + off, buf, bytes); 2946 kunmap_local(ptr); 2947 if (r) 2948 return -EFAULT; 2949 2950 size -= bytes; 2951 *pos += bytes; 2952 result += bytes; 2953 } 2954 2955 return result; 2956 } 2957 2958 static const struct file_operations amdgpu_ttm_iomem_fops = { 2959 .owner = THIS_MODULE, 2960 .read = amdgpu_iomem_read, 2961 .write = amdgpu_iomem_write, 2962 .llseek = default_llseek 2963 }; 2964 2965 #endif 2966 2967 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2968 { 2969 #if defined(CONFIG_DEBUG_FS) 2970 struct drm_minor *minor = adev_to_drm(adev)->primary; 2971 struct dentry *root = minor->debugfs_root; 2972 2973 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2974 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2975 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2976 &amdgpu_ttm_iomem_fops); 2977 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2978 &amdgpu_ttm_page_pool_fops); 2979 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2980 TTM_PL_VRAM), 2981 root, "amdgpu_vram_mm"); 2982 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2983 TTM_PL_TT), 2984 root, "amdgpu_gtt_mm"); 2985 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2986 AMDGPU_PL_GDS), 2987 root, "amdgpu_gds_mm"); 2988 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2989 AMDGPU_PL_GWS), 2990 root, "amdgpu_gws_mm"); 2991 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2992 AMDGPU_PL_OA), 2993 root, "amdgpu_oa_mm"); 2994 2995 #endif 2996 } 2997