1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <ttm/ttm_bo_api.h> 33 #include <ttm/ttm_bo_driver.h> 34 #include <ttm/ttm_placement.h> 35 #include <ttm/ttm_module.h> 36 #include <ttm/ttm_page_alloc.h> 37 #include <drm/drmP.h> 38 #include <drm/amdgpu_drm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swiotlb.h> 42 #include <linux/swap.h> 43 #include <linux/pagemap.h> 44 #include <linux/debugfs.h> 45 #include "amdgpu.h" 46 #include "bif/bif_4_1_d.h" 47 48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 49 50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); 52 53 54 /* 55 * Global memory. 56 */ 57 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) 58 { 59 return ttm_mem_global_init(ref->object); 60 } 61 62 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) 63 { 64 ttm_mem_global_release(ref->object); 65 } 66 67 static int amdgpu_ttm_global_init(struct amdgpu_device *adev) 68 { 69 struct drm_global_reference *global_ref; 70 struct amdgpu_ring *ring; 71 struct amd_sched_rq *rq; 72 int r; 73 74 adev->mman.mem_global_referenced = false; 75 global_ref = &adev->mman.mem_global_ref; 76 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 77 global_ref->size = sizeof(struct ttm_mem_global); 78 global_ref->init = &amdgpu_ttm_mem_global_init; 79 global_ref->release = &amdgpu_ttm_mem_global_release; 80 r = drm_global_item_ref(global_ref); 81 if (r) { 82 DRM_ERROR("Failed setting up TTM memory accounting " 83 "subsystem.\n"); 84 goto error_mem; 85 } 86 87 adev->mman.bo_global_ref.mem_glob = 88 adev->mman.mem_global_ref.object; 89 global_ref = &adev->mman.bo_global_ref.ref; 90 global_ref->global_type = DRM_GLOBAL_TTM_BO; 91 global_ref->size = sizeof(struct ttm_bo_global); 92 global_ref->init = &ttm_bo_global_init; 93 global_ref->release = &ttm_bo_global_release; 94 r = drm_global_item_ref(global_ref); 95 if (r) { 96 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 97 goto error_bo; 98 } 99 100 ring = adev->mman.buffer_funcs_ring; 101 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; 102 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, 103 rq, amdgpu_sched_jobs); 104 if (r) { 105 DRM_ERROR("Failed setting up TTM BO move run queue.\n"); 106 goto error_entity; 107 } 108 109 adev->mman.mem_global_referenced = true; 110 111 return 0; 112 113 error_entity: 114 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 115 error_bo: 116 drm_global_item_unref(&adev->mman.mem_global_ref); 117 error_mem: 118 return r; 119 } 120 121 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) 122 { 123 if (adev->mman.mem_global_referenced) { 124 amd_sched_entity_fini(adev->mman.entity.sched, 125 &adev->mman.entity); 126 drm_global_item_unref(&adev->mman.bo_global_ref.ref); 127 drm_global_item_unref(&adev->mman.mem_global_ref); 128 adev->mman.mem_global_referenced = false; 129 } 130 } 131 132 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 133 { 134 return 0; 135 } 136 137 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 138 struct ttm_mem_type_manager *man) 139 { 140 struct amdgpu_device *adev; 141 142 adev = amdgpu_ttm_adev(bdev); 143 144 switch (type) { 145 case TTM_PL_SYSTEM: 146 /* System memory */ 147 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 148 man->available_caching = TTM_PL_MASK_CACHING; 149 man->default_caching = TTM_PL_FLAG_CACHED; 150 break; 151 case TTM_PL_TT: 152 man->func = &amdgpu_gtt_mgr_func; 153 man->gpu_offset = adev->mc.gtt_start; 154 man->available_caching = TTM_PL_MASK_CACHING; 155 man->default_caching = TTM_PL_FLAG_CACHED; 156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 157 break; 158 case TTM_PL_VRAM: 159 /* "On-card" video ram */ 160 man->func = &amdgpu_vram_mgr_func; 161 man->gpu_offset = adev->mc.vram_start; 162 man->flags = TTM_MEMTYPE_FLAG_FIXED | 163 TTM_MEMTYPE_FLAG_MAPPABLE; 164 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 165 man->default_caching = TTM_PL_FLAG_WC; 166 break; 167 case AMDGPU_PL_GDS: 168 case AMDGPU_PL_GWS: 169 case AMDGPU_PL_OA: 170 /* On-chip GDS memory*/ 171 man->func = &ttm_bo_manager_func; 172 man->gpu_offset = 0; 173 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; 174 man->available_caching = TTM_PL_FLAG_UNCACHED; 175 man->default_caching = TTM_PL_FLAG_UNCACHED; 176 break; 177 default: 178 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 179 return -EINVAL; 180 } 181 return 0; 182 } 183 184 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 185 struct ttm_placement *placement) 186 { 187 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 188 struct amdgpu_bo *abo; 189 static struct ttm_place placements = { 190 .fpfn = 0, 191 .lpfn = 0, 192 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 193 }; 194 unsigned i; 195 196 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { 197 placement->placement = &placements; 198 placement->busy_placement = &placements; 199 placement->num_placement = 1; 200 placement->num_busy_placement = 1; 201 return; 202 } 203 abo = container_of(bo, struct amdgpu_bo, tbo); 204 switch (bo->mem.mem_type) { 205 case TTM_PL_VRAM: 206 if (adev->mman.buffer_funcs_ring->ready == false) { 207 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 208 } else { 209 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 210 for (i = 0; i < abo->placement.num_placement; ++i) { 211 if (!(abo->placements[i].flags & 212 TTM_PL_FLAG_TT)) 213 continue; 214 215 if (abo->placements[i].lpfn) 216 continue; 217 218 /* set an upper limit to force directly 219 * allocating address space for the BO. 220 */ 221 abo->placements[i].lpfn = 222 adev->mc.gtt_size >> PAGE_SHIFT; 223 } 224 } 225 break; 226 case TTM_PL_TT: 227 default: 228 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 229 } 230 *placement = abo->placement; 231 } 232 233 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 234 { 235 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo); 236 237 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 238 return -EPERM; 239 return drm_vma_node_verify_access(&abo->gem_base.vma_node, 240 filp->private_data); 241 } 242 243 static void amdgpu_move_null(struct ttm_buffer_object *bo, 244 struct ttm_mem_reg *new_mem) 245 { 246 struct ttm_mem_reg *old_mem = &bo->mem; 247 248 BUG_ON(old_mem->mm_node != NULL); 249 *old_mem = *new_mem; 250 new_mem->mm_node = NULL; 251 } 252 253 static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 254 struct drm_mm_node *mm_node, 255 struct ttm_mem_reg *mem, 256 uint64_t *addr) 257 { 258 int r; 259 260 switch (mem->mem_type) { 261 case TTM_PL_TT: 262 r = amdgpu_ttm_bind(bo, mem); 263 if (r) 264 return r; 265 266 case TTM_PL_VRAM: 267 *addr = mm_node->start << PAGE_SHIFT; 268 *addr += bo->bdev->man[mem->mem_type].gpu_offset; 269 break; 270 default: 271 DRM_ERROR("Unknown placement %d\n", mem->mem_type); 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 279 bool evict, bool no_wait_gpu, 280 struct ttm_mem_reg *new_mem, 281 struct ttm_mem_reg *old_mem) 282 { 283 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 284 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 285 286 struct drm_mm_node *old_mm, *new_mm; 287 uint64_t old_start, old_size, new_start, new_size; 288 unsigned long num_pages; 289 struct dma_fence *fence = NULL; 290 int r; 291 292 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); 293 294 if (!ring->ready) { 295 DRM_ERROR("Trying to move memory with ring turned off.\n"); 296 return -EINVAL; 297 } 298 299 old_mm = old_mem->mm_node; 300 r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start); 301 if (r) 302 return r; 303 old_size = old_mm->size; 304 305 306 new_mm = new_mem->mm_node; 307 r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start); 308 if (r) 309 return r; 310 new_size = new_mm->size; 311 312 num_pages = new_mem->num_pages; 313 while (num_pages) { 314 unsigned long cur_pages = min(old_size, new_size); 315 struct dma_fence *next; 316 317 r = amdgpu_copy_buffer(ring, old_start, new_start, 318 cur_pages * PAGE_SIZE, 319 bo->resv, &next, false); 320 if (r) 321 goto error; 322 323 dma_fence_put(fence); 324 fence = next; 325 326 num_pages -= cur_pages; 327 if (!num_pages) 328 break; 329 330 old_size -= cur_pages; 331 if (!old_size) { 332 r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem, 333 &old_start); 334 if (r) 335 goto error; 336 old_size = old_mm->size; 337 } else { 338 old_start += cur_pages * PAGE_SIZE; 339 } 340 341 new_size -= cur_pages; 342 if (!new_size) { 343 r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem, 344 &new_start); 345 if (r) 346 goto error; 347 348 new_size = new_mm->size; 349 } else { 350 new_start += cur_pages * PAGE_SIZE; 351 } 352 } 353 354 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); 355 dma_fence_put(fence); 356 return r; 357 358 error: 359 if (fence) 360 dma_fence_wait(fence, false); 361 dma_fence_put(fence); 362 return r; 363 } 364 365 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, 366 bool evict, bool interruptible, 367 bool no_wait_gpu, 368 struct ttm_mem_reg *new_mem) 369 { 370 struct amdgpu_device *adev; 371 struct ttm_mem_reg *old_mem = &bo->mem; 372 struct ttm_mem_reg tmp_mem; 373 struct ttm_place placements; 374 struct ttm_placement placement; 375 int r; 376 377 adev = amdgpu_ttm_adev(bo->bdev); 378 tmp_mem = *new_mem; 379 tmp_mem.mm_node = NULL; 380 placement.num_placement = 1; 381 placement.placement = &placements; 382 placement.num_busy_placement = 1; 383 placement.busy_placement = &placements; 384 placements.fpfn = 0; 385 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT; 386 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 387 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 388 interruptible, no_wait_gpu); 389 if (unlikely(r)) { 390 return r; 391 } 392 393 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 394 if (unlikely(r)) { 395 goto out_cleanup; 396 } 397 398 r = ttm_tt_bind(bo->ttm, &tmp_mem); 399 if (unlikely(r)) { 400 goto out_cleanup; 401 } 402 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 403 if (unlikely(r)) { 404 goto out_cleanup; 405 } 406 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); 407 out_cleanup: 408 ttm_bo_mem_put(bo, &tmp_mem); 409 return r; 410 } 411 412 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, 413 bool evict, bool interruptible, 414 bool no_wait_gpu, 415 struct ttm_mem_reg *new_mem) 416 { 417 struct amdgpu_device *adev; 418 struct ttm_mem_reg *old_mem = &bo->mem; 419 struct ttm_mem_reg tmp_mem; 420 struct ttm_placement placement; 421 struct ttm_place placements; 422 int r; 423 424 adev = amdgpu_ttm_adev(bo->bdev); 425 tmp_mem = *new_mem; 426 tmp_mem.mm_node = NULL; 427 placement.num_placement = 1; 428 placement.placement = &placements; 429 placement.num_busy_placement = 1; 430 placement.busy_placement = &placements; 431 placements.fpfn = 0; 432 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT; 433 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 434 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 435 interruptible, no_wait_gpu); 436 if (unlikely(r)) { 437 return r; 438 } 439 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); 440 if (unlikely(r)) { 441 goto out_cleanup; 442 } 443 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 444 if (unlikely(r)) { 445 goto out_cleanup; 446 } 447 out_cleanup: 448 ttm_bo_mem_put(bo, &tmp_mem); 449 return r; 450 } 451 452 static int amdgpu_bo_move(struct ttm_buffer_object *bo, 453 bool evict, bool interruptible, 454 bool no_wait_gpu, 455 struct ttm_mem_reg *new_mem) 456 { 457 struct amdgpu_device *adev; 458 struct amdgpu_bo *abo; 459 struct ttm_mem_reg *old_mem = &bo->mem; 460 int r; 461 462 /* Can't move a pinned BO */ 463 abo = container_of(bo, struct amdgpu_bo, tbo); 464 if (WARN_ON_ONCE(abo->pin_count > 0)) 465 return -EINVAL; 466 467 adev = amdgpu_ttm_adev(bo->bdev); 468 469 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 470 amdgpu_move_null(bo, new_mem); 471 return 0; 472 } 473 if ((old_mem->mem_type == TTM_PL_TT && 474 new_mem->mem_type == TTM_PL_SYSTEM) || 475 (old_mem->mem_type == TTM_PL_SYSTEM && 476 new_mem->mem_type == TTM_PL_TT)) { 477 /* bind is enough */ 478 amdgpu_move_null(bo, new_mem); 479 return 0; 480 } 481 if (adev->mman.buffer_funcs == NULL || 482 adev->mman.buffer_funcs_ring == NULL || 483 !adev->mman.buffer_funcs_ring->ready) { 484 /* use memcpy */ 485 goto memcpy; 486 } 487 488 if (old_mem->mem_type == TTM_PL_VRAM && 489 new_mem->mem_type == TTM_PL_SYSTEM) { 490 r = amdgpu_move_vram_ram(bo, evict, interruptible, 491 no_wait_gpu, new_mem); 492 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 493 new_mem->mem_type == TTM_PL_VRAM) { 494 r = amdgpu_move_ram_vram(bo, evict, interruptible, 495 no_wait_gpu, new_mem); 496 } else { 497 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 498 } 499 500 if (r) { 501 memcpy: 502 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); 503 if (r) { 504 return r; 505 } 506 } 507 508 /* update statistics */ 509 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 510 return 0; 511 } 512 513 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 514 { 515 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 516 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 517 518 mem->bus.addr = NULL; 519 mem->bus.offset = 0; 520 mem->bus.size = mem->num_pages << PAGE_SHIFT; 521 mem->bus.base = 0; 522 mem->bus.is_iomem = false; 523 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 524 return -EINVAL; 525 switch (mem->mem_type) { 526 case TTM_PL_SYSTEM: 527 /* system memory */ 528 return 0; 529 case TTM_PL_TT: 530 break; 531 case TTM_PL_VRAM: 532 mem->bus.offset = mem->start << PAGE_SHIFT; 533 /* check if it's visible */ 534 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) 535 return -EINVAL; 536 mem->bus.base = adev->mc.aper_base; 537 mem->bus.is_iomem = true; 538 break; 539 default: 540 return -EINVAL; 541 } 542 return 0; 543 } 544 545 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 546 { 547 } 548 549 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 550 unsigned long page_offset) 551 { 552 struct drm_mm_node *mm = bo->mem.mm_node; 553 uint64_t size = mm->size; 554 uint64_t offset = page_offset; 555 556 page_offset = do_div(offset, size); 557 mm += offset; 558 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset; 559 } 560 561 /* 562 * TTM backend functions. 563 */ 564 struct amdgpu_ttm_gup_task_list { 565 struct list_head list; 566 struct task_struct *task; 567 }; 568 569 struct amdgpu_ttm_tt { 570 struct ttm_dma_tt ttm; 571 struct amdgpu_device *adev; 572 u64 offset; 573 uint64_t userptr; 574 struct mm_struct *usermm; 575 uint32_t userflags; 576 spinlock_t guptasklock; 577 struct list_head guptasks; 578 atomic_t mmu_invalidations; 579 struct list_head list; 580 }; 581 582 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) 583 { 584 struct amdgpu_ttm_tt *gtt = (void *)ttm; 585 unsigned int flags = 0; 586 unsigned pinned = 0; 587 int r; 588 589 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 590 flags |= FOLL_WRITE; 591 592 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { 593 /* check that we only use anonymous memory 594 to prevent problems with writeback */ 595 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 596 struct vm_area_struct *vma; 597 598 vma = find_vma(gtt->usermm, gtt->userptr); 599 if (!vma || vma->vm_file || vma->vm_end < end) 600 return -EPERM; 601 } 602 603 do { 604 unsigned num_pages = ttm->num_pages - pinned; 605 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 606 struct page **p = pages + pinned; 607 struct amdgpu_ttm_gup_task_list guptask; 608 609 guptask.task = current; 610 spin_lock(>t->guptasklock); 611 list_add(&guptask.list, >t->guptasks); 612 spin_unlock(>t->guptasklock); 613 614 r = get_user_pages(userptr, num_pages, flags, p, NULL); 615 616 spin_lock(>t->guptasklock); 617 list_del(&guptask.list); 618 spin_unlock(>t->guptasklock); 619 620 if (r < 0) 621 goto release_pages; 622 623 pinned += r; 624 625 } while (pinned < ttm->num_pages); 626 627 return 0; 628 629 release_pages: 630 release_pages(pages, pinned, 0); 631 return r; 632 } 633 634 /* prepare the sg table with the user pages */ 635 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) 636 { 637 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 638 struct amdgpu_ttm_tt *gtt = (void *)ttm; 639 unsigned nents; 640 int r; 641 642 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 643 enum dma_data_direction direction = write ? 644 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 645 646 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 647 ttm->num_pages << PAGE_SHIFT, 648 GFP_KERNEL); 649 if (r) 650 goto release_sg; 651 652 r = -ENOMEM; 653 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 654 if (nents != ttm->sg->nents) 655 goto release_sg; 656 657 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 658 gtt->ttm.dma_address, ttm->num_pages); 659 660 return 0; 661 662 release_sg: 663 kfree(ttm->sg); 664 return r; 665 } 666 667 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 668 { 669 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); 670 struct amdgpu_ttm_tt *gtt = (void *)ttm; 671 struct sg_page_iter sg_iter; 672 673 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 674 enum dma_data_direction direction = write ? 675 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 676 677 /* double check that we don't free the table twice */ 678 if (!ttm->sg->sgl) 679 return; 680 681 /* free the sg table and pages again */ 682 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 683 684 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { 685 struct page *page = sg_page_iter_page(&sg_iter); 686 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) 687 set_page_dirty(page); 688 689 mark_page_accessed(page); 690 put_page(page); 691 } 692 693 sg_free_table(ttm->sg); 694 } 695 696 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, 697 struct ttm_mem_reg *bo_mem) 698 { 699 struct amdgpu_ttm_tt *gtt = (void*)ttm; 700 int r; 701 702 if (gtt->userptr) { 703 r = amdgpu_ttm_tt_pin_userptr(ttm); 704 if (r) { 705 DRM_ERROR("failed to pin userptr\n"); 706 return r; 707 } 708 } 709 if (!ttm->num_pages) { 710 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 711 ttm->num_pages, bo_mem, ttm); 712 } 713 714 if (bo_mem->mem_type == AMDGPU_PL_GDS || 715 bo_mem->mem_type == AMDGPU_PL_GWS || 716 bo_mem->mem_type == AMDGPU_PL_OA) 717 return -EINVAL; 718 719 return 0; 720 } 721 722 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) 723 { 724 struct amdgpu_ttm_tt *gtt = (void *)ttm; 725 726 return gtt && !list_empty(>t->list); 727 } 728 729 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) 730 { 731 struct ttm_tt *ttm = bo->ttm; 732 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 733 uint64_t flags; 734 int r; 735 736 if (!ttm || amdgpu_ttm_is_bound(ttm)) 737 return 0; 738 739 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo, 740 NULL, bo_mem); 741 if (r) { 742 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r); 743 return r; 744 } 745 746 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 747 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 748 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, 749 ttm->pages, gtt->ttm.dma_address, flags); 750 751 if (r) { 752 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 753 ttm->num_pages, gtt->offset); 754 return r; 755 } 756 spin_lock(>t->adev->gtt_list_lock); 757 list_add_tail(>t->list, >t->adev->gtt_list); 758 spin_unlock(>t->adev->gtt_list_lock); 759 return 0; 760 } 761 762 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) 763 { 764 struct amdgpu_ttm_tt *gtt, *tmp; 765 struct ttm_mem_reg bo_mem; 766 uint32_t flags; 767 int r; 768 769 bo_mem.mem_type = TTM_PL_TT; 770 spin_lock(&adev->gtt_list_lock); 771 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) { 772 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem); 773 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, 774 gtt->ttm.ttm.pages, gtt->ttm.dma_address, 775 flags); 776 if (r) { 777 spin_unlock(&adev->gtt_list_lock); 778 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 779 gtt->ttm.ttm.num_pages, gtt->offset); 780 return r; 781 } 782 } 783 spin_unlock(&adev->gtt_list_lock); 784 return 0; 785 } 786 787 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) 788 { 789 struct amdgpu_ttm_tt *gtt = (void *)ttm; 790 791 if (gtt->userptr) 792 amdgpu_ttm_tt_unpin_userptr(ttm); 793 794 if (!amdgpu_ttm_is_bound(ttm)) 795 return 0; 796 797 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 798 if (gtt->adev->gart.ready) 799 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); 800 801 spin_lock(>t->adev->gtt_list_lock); 802 list_del_init(>t->list); 803 spin_unlock(>t->adev->gtt_list_lock); 804 805 return 0; 806 } 807 808 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) 809 { 810 struct amdgpu_ttm_tt *gtt = (void *)ttm; 811 812 ttm_dma_tt_fini(>t->ttm); 813 kfree(gtt); 814 } 815 816 static struct ttm_backend_func amdgpu_backend_func = { 817 .bind = &amdgpu_ttm_backend_bind, 818 .unbind = &amdgpu_ttm_backend_unbind, 819 .destroy = &amdgpu_ttm_backend_destroy, 820 }; 821 822 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, 823 unsigned long size, uint32_t page_flags, 824 struct page *dummy_read_page) 825 { 826 struct amdgpu_device *adev; 827 struct amdgpu_ttm_tt *gtt; 828 829 adev = amdgpu_ttm_adev(bdev); 830 831 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 832 if (gtt == NULL) { 833 return NULL; 834 } 835 gtt->ttm.ttm.func = &amdgpu_backend_func; 836 gtt->adev = adev; 837 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 838 kfree(gtt); 839 return NULL; 840 } 841 INIT_LIST_HEAD(>t->list); 842 return >t->ttm.ttm; 843 } 844 845 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) 846 { 847 struct amdgpu_device *adev; 848 struct amdgpu_ttm_tt *gtt = (void *)ttm; 849 unsigned i; 850 int r; 851 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 852 853 if (ttm->state != tt_unpopulated) 854 return 0; 855 856 if (gtt && gtt->userptr) { 857 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 858 if (!ttm->sg) 859 return -ENOMEM; 860 861 ttm->page_flags |= TTM_PAGE_FLAG_SG; 862 ttm->state = tt_unbound; 863 return 0; 864 } 865 866 if (slave && ttm->sg) { 867 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 868 gtt->ttm.dma_address, ttm->num_pages); 869 ttm->state = tt_unbound; 870 return 0; 871 } 872 873 adev = amdgpu_ttm_adev(ttm->bdev); 874 875 #ifdef CONFIG_SWIOTLB 876 if (swiotlb_nr_tbl()) { 877 return ttm_dma_populate(>t->ttm, adev->dev); 878 } 879 #endif 880 881 r = ttm_pool_populate(ttm); 882 if (r) { 883 return r; 884 } 885 886 for (i = 0; i < ttm->num_pages; i++) { 887 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], 888 0, PAGE_SIZE, 889 PCI_DMA_BIDIRECTIONAL); 890 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { 891 while (i--) { 892 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 893 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 894 gtt->ttm.dma_address[i] = 0; 895 } 896 ttm_pool_unpopulate(ttm); 897 return -EFAULT; 898 } 899 } 900 return 0; 901 } 902 903 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) 904 { 905 struct amdgpu_device *adev; 906 struct amdgpu_ttm_tt *gtt = (void *)ttm; 907 unsigned i; 908 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 909 910 if (gtt && gtt->userptr) { 911 kfree(ttm->sg); 912 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 913 return; 914 } 915 916 if (slave) 917 return; 918 919 adev = amdgpu_ttm_adev(ttm->bdev); 920 921 #ifdef CONFIG_SWIOTLB 922 if (swiotlb_nr_tbl()) { 923 ttm_dma_unpopulate(>t->ttm, adev->dev); 924 return; 925 } 926 #endif 927 928 for (i = 0; i < ttm->num_pages; i++) { 929 if (gtt->ttm.dma_address[i]) { 930 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], 931 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 932 } 933 } 934 935 ttm_pool_unpopulate(ttm); 936 } 937 938 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 939 uint32_t flags) 940 { 941 struct amdgpu_ttm_tt *gtt = (void *)ttm; 942 943 if (gtt == NULL) 944 return -EINVAL; 945 946 gtt->userptr = addr; 947 gtt->usermm = current->mm; 948 gtt->userflags = flags; 949 spin_lock_init(>t->guptasklock); 950 INIT_LIST_HEAD(>t->guptasks); 951 atomic_set(>t->mmu_invalidations, 0); 952 953 return 0; 954 } 955 956 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 957 { 958 struct amdgpu_ttm_tt *gtt = (void *)ttm; 959 960 if (gtt == NULL) 961 return NULL; 962 963 return gtt->usermm; 964 } 965 966 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 967 unsigned long end) 968 { 969 struct amdgpu_ttm_tt *gtt = (void *)ttm; 970 struct amdgpu_ttm_gup_task_list *entry; 971 unsigned long size; 972 973 if (gtt == NULL || !gtt->userptr) 974 return false; 975 976 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 977 if (gtt->userptr > end || gtt->userptr + size <= start) 978 return false; 979 980 spin_lock(>t->guptasklock); 981 list_for_each_entry(entry, >t->guptasks, list) { 982 if (entry->task == current) { 983 spin_unlock(>t->guptasklock); 984 return false; 985 } 986 } 987 spin_unlock(>t->guptasklock); 988 989 atomic_inc(>t->mmu_invalidations); 990 991 return true; 992 } 993 994 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 995 int *last_invalidated) 996 { 997 struct amdgpu_ttm_tt *gtt = (void *)ttm; 998 int prev_invalidated = *last_invalidated; 999 1000 *last_invalidated = atomic_read(>t->mmu_invalidations); 1001 return prev_invalidated != *last_invalidated; 1002 } 1003 1004 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1005 { 1006 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1007 1008 if (gtt == NULL) 1009 return false; 1010 1011 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1012 } 1013 1014 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1015 struct ttm_mem_reg *mem) 1016 { 1017 uint64_t flags = 0; 1018 1019 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1020 flags |= AMDGPU_PTE_VALID; 1021 1022 if (mem && mem->mem_type == TTM_PL_TT) { 1023 flags |= AMDGPU_PTE_SYSTEM; 1024 1025 if (ttm->caching_state == tt_cached) 1026 flags |= AMDGPU_PTE_SNOOPED; 1027 } 1028 1029 flags |= adev->gart.gart_pte_flags; 1030 flags |= AMDGPU_PTE_READABLE; 1031 1032 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1033 flags |= AMDGPU_PTE_WRITEABLE; 1034 1035 return flags; 1036 } 1037 1038 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1039 const struct ttm_place *place) 1040 { 1041 if (bo->mem.mem_type == TTM_PL_VRAM && 1042 bo->mem.start == AMDGPU_BO_INVALID_OFFSET) { 1043 unsigned long num_pages = bo->mem.num_pages; 1044 struct drm_mm_node *node = bo->mem.mm_node; 1045 1046 /* Check each drm MM node individually */ 1047 while (num_pages) { 1048 if (place->fpfn < (node->start + node->size) && 1049 !(place->lpfn && place->lpfn <= node->start)) 1050 return true; 1051 1052 num_pages -= node->size; 1053 ++node; 1054 } 1055 1056 return false; 1057 } 1058 1059 return ttm_bo_eviction_valuable(bo, place); 1060 } 1061 1062 static struct ttm_bo_driver amdgpu_bo_driver = { 1063 .ttm_tt_create = &amdgpu_ttm_tt_create, 1064 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1065 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1066 .invalidate_caches = &amdgpu_invalidate_caches, 1067 .init_mem_type = &amdgpu_init_mem_type, 1068 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1069 .evict_flags = &amdgpu_evict_flags, 1070 .move = &amdgpu_bo_move, 1071 .verify_access = &amdgpu_verify_access, 1072 .move_notify = &amdgpu_bo_move_notify, 1073 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1074 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1075 .io_mem_free = &amdgpu_ttm_io_mem_free, 1076 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1077 }; 1078 1079 int amdgpu_ttm_init(struct amdgpu_device *adev) 1080 { 1081 int r; 1082 1083 r = amdgpu_ttm_global_init(adev); 1084 if (r) { 1085 return r; 1086 } 1087 /* No others user of address space so set it to 0 */ 1088 r = ttm_bo_device_init(&adev->mman.bdev, 1089 adev->mman.bo_global_ref.ref.object, 1090 &amdgpu_bo_driver, 1091 adev->ddev->anon_inode->i_mapping, 1092 DRM_FILE_PAGE_OFFSET, 1093 adev->need_dma32); 1094 if (r) { 1095 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1096 return r; 1097 } 1098 adev->mman.initialized = true; 1099 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, 1100 adev->mc.real_vram_size >> PAGE_SHIFT); 1101 if (r) { 1102 DRM_ERROR("Failed initializing VRAM heap.\n"); 1103 return r; 1104 } 1105 /* Change the size here instead of the init above so only lpfn is affected */ 1106 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 1107 1108 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, 1109 AMDGPU_GEM_DOMAIN_VRAM, 1110 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1111 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1112 NULL, NULL, &adev->stollen_vga_memory); 1113 if (r) { 1114 return r; 1115 } 1116 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1117 if (r) 1118 return r; 1119 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); 1120 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1121 if (r) { 1122 amdgpu_bo_unref(&adev->stollen_vga_memory); 1123 return r; 1124 } 1125 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1126 (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); 1127 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, 1128 adev->mc.gtt_size >> PAGE_SHIFT); 1129 if (r) { 1130 DRM_ERROR("Failed initializing GTT heap.\n"); 1131 return r; 1132 } 1133 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1134 (unsigned)(adev->mc.gtt_size / (1024 * 1024))); 1135 1136 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; 1137 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; 1138 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; 1139 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; 1140 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; 1141 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; 1142 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; 1143 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; 1144 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; 1145 /* GDS Memory */ 1146 if (adev->gds.mem.total_size) { 1147 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 1148 adev->gds.mem.total_size >> PAGE_SHIFT); 1149 if (r) { 1150 DRM_ERROR("Failed initializing GDS heap.\n"); 1151 return r; 1152 } 1153 } 1154 1155 /* GWS */ 1156 if (adev->gds.gws.total_size) { 1157 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 1158 adev->gds.gws.total_size >> PAGE_SHIFT); 1159 if (r) { 1160 DRM_ERROR("Failed initializing gws heap.\n"); 1161 return r; 1162 } 1163 } 1164 1165 /* OA */ 1166 if (adev->gds.oa.total_size) { 1167 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 1168 adev->gds.oa.total_size >> PAGE_SHIFT); 1169 if (r) { 1170 DRM_ERROR("Failed initializing oa heap.\n"); 1171 return r; 1172 } 1173 } 1174 1175 r = amdgpu_ttm_debugfs_init(adev); 1176 if (r) { 1177 DRM_ERROR("Failed to init debugfs\n"); 1178 return r; 1179 } 1180 return 0; 1181 } 1182 1183 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1184 { 1185 int r; 1186 1187 if (!adev->mman.initialized) 1188 return; 1189 amdgpu_ttm_debugfs_fini(adev); 1190 if (adev->stollen_vga_memory) { 1191 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); 1192 if (r == 0) { 1193 amdgpu_bo_unpin(adev->stollen_vga_memory); 1194 amdgpu_bo_unreserve(adev->stollen_vga_memory); 1195 } 1196 amdgpu_bo_unref(&adev->stollen_vga_memory); 1197 } 1198 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); 1199 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); 1200 if (adev->gds.mem.total_size) 1201 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); 1202 if (adev->gds.gws.total_size) 1203 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); 1204 if (adev->gds.oa.total_size) 1205 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); 1206 ttm_bo_device_release(&adev->mman.bdev); 1207 amdgpu_gart_fini(adev); 1208 amdgpu_ttm_global_fini(adev); 1209 adev->mman.initialized = false; 1210 DRM_INFO("amdgpu: ttm finalized\n"); 1211 } 1212 1213 /* this should only be called at bootup or when userspace 1214 * isn't running */ 1215 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) 1216 { 1217 struct ttm_mem_type_manager *man; 1218 1219 if (!adev->mman.initialized) 1220 return; 1221 1222 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 1223 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1224 man->size = size >> PAGE_SHIFT; 1225 } 1226 1227 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 1228 { 1229 struct drm_file *file_priv; 1230 struct amdgpu_device *adev; 1231 1232 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 1233 return -EINVAL; 1234 1235 file_priv = filp->private_data; 1236 adev = file_priv->minor->dev->dev_private; 1237 if (adev == NULL) 1238 return -EINVAL; 1239 1240 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 1241 } 1242 1243 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 1244 uint64_t src_offset, 1245 uint64_t dst_offset, 1246 uint32_t byte_count, 1247 struct reservation_object *resv, 1248 struct dma_fence **fence, bool direct_submit) 1249 { 1250 struct amdgpu_device *adev = ring->adev; 1251 struct amdgpu_job *job; 1252 1253 uint32_t max_bytes; 1254 unsigned num_loops, num_dw; 1255 unsigned i; 1256 int r; 1257 1258 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1259 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1260 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; 1261 1262 /* for IB padding */ 1263 while (num_dw & 0x7) 1264 num_dw++; 1265 1266 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1267 if (r) 1268 return r; 1269 1270 if (resv) { 1271 r = amdgpu_sync_resv(adev, &job->sync, resv, 1272 AMDGPU_FENCE_OWNER_UNDEFINED); 1273 if (r) { 1274 DRM_ERROR("sync failed (%d).\n", r); 1275 goto error_free; 1276 } 1277 } 1278 1279 for (i = 0; i < num_loops; i++) { 1280 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1281 1282 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1283 dst_offset, cur_size_in_bytes); 1284 1285 src_offset += cur_size_in_bytes; 1286 dst_offset += cur_size_in_bytes; 1287 byte_count -= cur_size_in_bytes; 1288 } 1289 1290 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1291 WARN_ON(job->ibs[0].length_dw > num_dw); 1292 if (direct_submit) { 1293 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, 1294 NULL, fence); 1295 job->fence = dma_fence_get(*fence); 1296 if (r) 1297 DRM_ERROR("Error scheduling IBs (%d)\n", r); 1298 amdgpu_job_free(job); 1299 } else { 1300 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1301 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1302 if (r) 1303 goto error_free; 1304 } 1305 1306 return r; 1307 1308 error_free: 1309 amdgpu_job_free(job); 1310 return r; 1311 } 1312 1313 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1314 uint32_t src_data, 1315 struct reservation_object *resv, 1316 struct dma_fence **fence) 1317 { 1318 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1319 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1320 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1321 1322 struct drm_mm_node *mm_node; 1323 unsigned long num_pages; 1324 unsigned int num_loops, num_dw; 1325 1326 struct amdgpu_job *job; 1327 int r; 1328 1329 if (!ring->ready) { 1330 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 1331 return -EINVAL; 1332 } 1333 1334 num_pages = bo->tbo.num_pages; 1335 mm_node = bo->tbo.mem.mm_node; 1336 num_loops = 0; 1337 while (num_pages) { 1338 uint32_t byte_count = mm_node->size << PAGE_SHIFT; 1339 1340 num_loops += DIV_ROUND_UP(byte_count, max_bytes); 1341 num_pages -= mm_node->size; 1342 ++mm_node; 1343 } 1344 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1345 1346 /* for IB padding */ 1347 num_dw += 64; 1348 1349 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1350 if (r) 1351 return r; 1352 1353 if (resv) { 1354 r = amdgpu_sync_resv(adev, &job->sync, resv, 1355 AMDGPU_FENCE_OWNER_UNDEFINED); 1356 if (r) { 1357 DRM_ERROR("sync failed (%d).\n", r); 1358 goto error_free; 1359 } 1360 } 1361 1362 num_pages = bo->tbo.num_pages; 1363 mm_node = bo->tbo.mem.mm_node; 1364 1365 while (num_pages) { 1366 uint32_t byte_count = mm_node->size << PAGE_SHIFT; 1367 uint64_t dst_addr; 1368 1369 r = amdgpu_mm_node_addr(&bo->tbo, mm_node, 1370 &bo->tbo.mem, &dst_addr); 1371 if (r) 1372 return r; 1373 1374 while (byte_count) { 1375 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1376 1377 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 1378 dst_addr, cur_size_in_bytes); 1379 1380 dst_addr += cur_size_in_bytes; 1381 byte_count -= cur_size_in_bytes; 1382 } 1383 1384 num_pages -= mm_node->size; 1385 ++mm_node; 1386 } 1387 1388 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1389 WARN_ON(job->ibs[0].length_dw > num_dw); 1390 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1391 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1392 if (r) 1393 goto error_free; 1394 1395 return 0; 1396 1397 error_free: 1398 amdgpu_job_free(job); 1399 return r; 1400 } 1401 1402 #if defined(CONFIG_DEBUG_FS) 1403 1404 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 1405 { 1406 struct drm_info_node *node = (struct drm_info_node *)m->private; 1407 unsigned ttm_pl = *(int *)node->info_ent->data; 1408 struct drm_device *dev = node->minor->dev; 1409 struct amdgpu_device *adev = dev->dev_private; 1410 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; 1411 struct ttm_bo_global *glob = adev->mman.bdev.glob; 1412 struct drm_printer p = drm_seq_file_printer(m); 1413 1414 spin_lock(&glob->lru_lock); 1415 drm_mm_print(mm, &p); 1416 spin_unlock(&glob->lru_lock); 1417 if (ttm_pl == TTM_PL_VRAM) 1418 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", 1419 adev->mman.bdev.man[ttm_pl].size, 1420 (u64)atomic64_read(&adev->vram_usage) >> 20, 1421 (u64)atomic64_read(&adev->vram_vis_usage) >> 20); 1422 return 0; 1423 } 1424 1425 static int ttm_pl_vram = TTM_PL_VRAM; 1426 static int ttm_pl_tt = TTM_PL_TT; 1427 1428 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 1429 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, 1430 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, 1431 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 1432 #ifdef CONFIG_SWIOTLB 1433 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 1434 #endif 1435 }; 1436 1437 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 1438 size_t size, loff_t *pos) 1439 { 1440 struct amdgpu_device *adev = file_inode(f)->i_private; 1441 ssize_t result = 0; 1442 int r; 1443 1444 if (size & 0x3 || *pos & 0x3) 1445 return -EINVAL; 1446 1447 while (size) { 1448 unsigned long flags; 1449 uint32_t value; 1450 1451 if (*pos >= adev->mc.mc_vram_size) 1452 return result; 1453 1454 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1455 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 1456 WREG32(mmMM_INDEX_HI, *pos >> 31); 1457 value = RREG32(mmMM_DATA); 1458 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1459 1460 r = put_user(value, (uint32_t *)buf); 1461 if (r) 1462 return r; 1463 1464 result += 4; 1465 buf += 4; 1466 *pos += 4; 1467 size -= 4; 1468 } 1469 1470 return result; 1471 } 1472 1473 static const struct file_operations amdgpu_ttm_vram_fops = { 1474 .owner = THIS_MODULE, 1475 .read = amdgpu_ttm_vram_read, 1476 .llseek = default_llseek 1477 }; 1478 1479 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1480 1481 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 1482 size_t size, loff_t *pos) 1483 { 1484 struct amdgpu_device *adev = file_inode(f)->i_private; 1485 ssize_t result = 0; 1486 int r; 1487 1488 while (size) { 1489 loff_t p = *pos / PAGE_SIZE; 1490 unsigned off = *pos & ~PAGE_MASK; 1491 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1492 struct page *page; 1493 void *ptr; 1494 1495 if (p >= adev->gart.num_cpu_pages) 1496 return result; 1497 1498 page = adev->gart.pages[p]; 1499 if (page) { 1500 ptr = kmap(page); 1501 ptr += off; 1502 1503 r = copy_to_user(buf, ptr, cur_size); 1504 kunmap(adev->gart.pages[p]); 1505 } else 1506 r = clear_user(buf, cur_size); 1507 1508 if (r) 1509 return -EFAULT; 1510 1511 result += cur_size; 1512 buf += cur_size; 1513 *pos += cur_size; 1514 size -= cur_size; 1515 } 1516 1517 return result; 1518 } 1519 1520 static const struct file_operations amdgpu_ttm_gtt_fops = { 1521 .owner = THIS_MODULE, 1522 .read = amdgpu_ttm_gtt_read, 1523 .llseek = default_llseek 1524 }; 1525 1526 #endif 1527 1528 #endif 1529 1530 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 1531 { 1532 #if defined(CONFIG_DEBUG_FS) 1533 unsigned count; 1534 1535 struct drm_minor *minor = adev->ddev->primary; 1536 struct dentry *ent, *root = minor->debugfs_root; 1537 1538 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, 1539 adev, &amdgpu_ttm_vram_fops); 1540 if (IS_ERR(ent)) 1541 return PTR_ERR(ent); 1542 i_size_write(ent->d_inode, adev->mc.mc_vram_size); 1543 adev->mman.vram = ent; 1544 1545 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1546 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, 1547 adev, &amdgpu_ttm_gtt_fops); 1548 if (IS_ERR(ent)) 1549 return PTR_ERR(ent); 1550 i_size_write(ent->d_inode, adev->mc.gtt_size); 1551 adev->mman.gtt = ent; 1552 1553 #endif 1554 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 1555 1556 #ifdef CONFIG_SWIOTLB 1557 if (!swiotlb_nr_tbl()) 1558 --count; 1559 #endif 1560 1561 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 1562 #else 1563 1564 return 0; 1565 #endif 1566 } 1567 1568 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) 1569 { 1570 #if defined(CONFIG_DEBUG_FS) 1571 1572 debugfs_remove(adev->mman.vram); 1573 adev->mman.vram = NULL; 1574 1575 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 1576 debugfs_remove(adev->mman.gtt); 1577 adev->mman.gtt = NULL; 1578 #endif 1579 1580 #endif 1581 } 1582