1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 #include <linux/module.h> 45 46 #include <drm/drm_drv.h> 47 #include <drm/ttm/ttm_bo_api.h> 48 #include <drm/ttm/ttm_bo_driver.h> 49 #include <drm/ttm/ttm_placement.h> 50 #include <drm/ttm/ttm_range_manager.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_drv.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "amdgpu_atomfirmware.h" 62 #include "amdgpu_res_cursor.h" 63 #include "bif/bif_4_1_d.h" 64 65 MODULE_IMPORT_NS(DMA_BUF); 66 67 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 68 69 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 70 struct ttm_tt *ttm, 71 struct ttm_resource *bo_mem); 72 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 73 struct ttm_tt *ttm); 74 75 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 76 unsigned int type, 77 uint64_t size_in_page) 78 { 79 return ttm_range_man_init(&adev->mman.bdev, type, 80 false, size_in_page); 81 } 82 83 /** 84 * amdgpu_evict_flags - Compute placement flags 85 * 86 * @bo: The buffer object to evict 87 * @placement: Possible destination(s) for evicted BO 88 * 89 * Fill in placement data when ttm_bo_evict() is called 90 */ 91 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 92 struct ttm_placement *placement) 93 { 94 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 95 struct amdgpu_bo *abo; 96 static const struct ttm_place placements = { 97 .fpfn = 0, 98 .lpfn = 0, 99 .mem_type = TTM_PL_SYSTEM, 100 .flags = 0 101 }; 102 103 /* Don't handle scatter gather BOs */ 104 if (bo->type == ttm_bo_type_sg) { 105 placement->num_placement = 0; 106 placement->num_busy_placement = 0; 107 return; 108 } 109 110 /* Object isn't an AMDGPU object so ignore */ 111 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 112 placement->placement = &placements; 113 placement->busy_placement = &placements; 114 placement->num_placement = 1; 115 placement->num_busy_placement = 1; 116 return; 117 } 118 119 abo = ttm_to_amdgpu_bo(bo); 120 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 121 placement->num_placement = 0; 122 placement->num_busy_placement = 0; 123 return; 124 } 125 126 switch (bo->resource->mem_type) { 127 case AMDGPU_PL_GDS: 128 case AMDGPU_PL_GWS: 129 case AMDGPU_PL_OA: 130 placement->num_placement = 0; 131 placement->num_busy_placement = 0; 132 return; 133 134 case TTM_PL_VRAM: 135 if (!adev->mman.buffer_funcs_enabled) { 136 /* Move to system memory */ 137 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 139 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 140 amdgpu_bo_in_cpu_visible_vram(abo)) { 141 142 /* Try evicting to the CPU inaccessible part of VRAM 143 * first, but only set GTT as busy placement, so this 144 * BO will be evicted to GTT rather than causing other 145 * BOs to be evicted from VRAM 146 */ 147 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 148 AMDGPU_GEM_DOMAIN_GTT | 149 AMDGPU_GEM_DOMAIN_CPU); 150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 151 abo->placements[0].lpfn = 0; 152 abo->placement.busy_placement = &abo->placements[1]; 153 abo->placement.num_busy_placement = 1; 154 } else { 155 /* Move to GTT memory */ 156 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 157 AMDGPU_GEM_DOMAIN_CPU); 158 } 159 break; 160 case TTM_PL_TT: 161 case AMDGPU_PL_PREEMPT: 162 default: 163 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 164 break; 165 } 166 *placement = abo->placement; 167 } 168 169 /** 170 * amdgpu_ttm_map_buffer - Map memory into the GART windows 171 * @bo: buffer object to map 172 * @mem: memory object to map 173 * @mm_cur: range to map 174 * @window: which GART window to use 175 * @ring: DMA ring to use for the copy 176 * @tmz: if we should setup a TMZ enabled mapping 177 * @size: in number of bytes to map, out number of bytes mapped 178 * @addr: resulting address inside the MC address space 179 * 180 * Setup one of the GART windows to access a specific piece of memory or return 181 * the physical address for local memory. 182 */ 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 184 struct ttm_resource *mem, 185 struct amdgpu_res_cursor *mm_cur, 186 unsigned window, struct amdgpu_ring *ring, 187 bool tmz, uint64_t *size, uint64_t *addr) 188 { 189 struct amdgpu_device *adev = ring->adev; 190 unsigned offset, num_pages, num_dw, num_bytes; 191 uint64_t src_addr, dst_addr; 192 struct dma_fence *fence; 193 struct amdgpu_job *job; 194 void *cpu_addr; 195 uint64_t flags; 196 unsigned int i; 197 int r; 198 199 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 200 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 201 202 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT)) 203 return -EINVAL; 204 205 /* Map only what can't be accessed directly */ 206 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 207 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 208 mm_cur->start; 209 return 0; 210 } 211 212 213 /* 214 * If start begins at an offset inside the page, then adjust the size 215 * and addr accordingly 216 */ 217 offset = mm_cur->start & ~PAGE_MASK; 218 219 num_pages = PFN_UP(*size + offset); 220 num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE); 221 222 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 223 224 *addr = adev->gmc.gart_start; 225 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 226 AMDGPU_GPU_PAGE_SIZE; 227 *addr += offset; 228 229 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 230 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 231 232 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 233 AMDGPU_IB_POOL_DELAYED, &job); 234 if (r) 235 return r; 236 237 src_addr = num_dw * 4; 238 src_addr += job->ibs[0].gpu_addr; 239 240 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 241 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 242 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 243 dst_addr, num_bytes, false); 244 245 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 246 WARN_ON(job->ibs[0].length_dw > num_dw); 247 248 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 249 if (tmz) 250 flags |= AMDGPU_PTE_TMZ; 251 252 cpu_addr = &job->ibs[0].ptr[num_dw]; 253 254 if (mem->mem_type == TTM_PL_TT) { 255 dma_addr_t *dma_addr; 256 257 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 258 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 259 } else { 260 dma_addr_t dma_address; 261 262 dma_address = mm_cur->start; 263 dma_address += adev->vm_manager.vram_base_offset; 264 265 for (i = 0; i < num_pages; ++i) { 266 amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address, 267 flags, cpu_addr); 268 dma_address += PAGE_SIZE; 269 } 270 } 271 272 r = amdgpu_job_submit(job, &adev->mman.entity, 273 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 274 if (r) 275 goto error_free; 276 277 dma_fence_put(fence); 278 279 return r; 280 281 error_free: 282 amdgpu_job_free(job); 283 return r; 284 } 285 286 /** 287 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 288 * @adev: amdgpu device 289 * @src: buffer/address where to read from 290 * @dst: buffer/address where to write to 291 * @size: number of bytes to copy 292 * @tmz: if a secure copy should be used 293 * @resv: resv object to sync to 294 * @f: Returns the last fence if multiple jobs are submitted. 295 * 296 * The function copies @size bytes from {src->mem + src->offset} to 297 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 298 * move and different for a BO to BO copy. 299 * 300 */ 301 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 302 const struct amdgpu_copy_mem *src, 303 const struct amdgpu_copy_mem *dst, 304 uint64_t size, bool tmz, 305 struct dma_resv *resv, 306 struct dma_fence **f) 307 { 308 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 309 struct amdgpu_res_cursor src_mm, dst_mm; 310 struct dma_fence *fence = NULL; 311 int r = 0; 312 313 if (!adev->mman.buffer_funcs_enabled) { 314 DRM_ERROR("Trying to move memory with ring turned off.\n"); 315 return -EINVAL; 316 } 317 318 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 319 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 320 321 mutex_lock(&adev->mman.gtt_window_lock); 322 while (src_mm.remaining) { 323 uint64_t from, to, cur_size; 324 struct dma_fence *next; 325 326 /* Never copy more than 256MiB at once to avoid a timeout */ 327 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 328 329 /* Map src to window 0 and dst to window 1. */ 330 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 331 0, ring, tmz, &cur_size, &from); 332 if (r) 333 goto error; 334 335 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 336 1, ring, tmz, &cur_size, &to); 337 if (r) 338 goto error; 339 340 r = amdgpu_copy_buffer(ring, from, to, cur_size, 341 resv, &next, false, true, tmz); 342 if (r) 343 goto error; 344 345 dma_fence_put(fence); 346 fence = next; 347 348 amdgpu_res_next(&src_mm, cur_size); 349 amdgpu_res_next(&dst_mm, cur_size); 350 } 351 error: 352 mutex_unlock(&adev->mman.gtt_window_lock); 353 if (f) 354 *f = dma_fence_get(fence); 355 dma_fence_put(fence); 356 return r; 357 } 358 359 /* 360 * amdgpu_move_blit - Copy an entire buffer to another buffer 361 * 362 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 363 * help move buffers to and from VRAM. 364 */ 365 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 366 bool evict, 367 struct ttm_resource *new_mem, 368 struct ttm_resource *old_mem) 369 { 370 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 371 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 372 struct amdgpu_copy_mem src, dst; 373 struct dma_fence *fence = NULL; 374 int r; 375 376 src.bo = bo; 377 dst.bo = bo; 378 src.mem = old_mem; 379 dst.mem = new_mem; 380 src.offset = 0; 381 dst.offset = 0; 382 383 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 384 new_mem->num_pages << PAGE_SHIFT, 385 amdgpu_bo_encrypted(abo), 386 bo->base.resv, &fence); 387 if (r) 388 goto error; 389 390 /* clear the space being freed */ 391 if (old_mem->mem_type == TTM_PL_VRAM && 392 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 393 struct dma_fence *wipe_fence = NULL; 394 395 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence); 396 if (r) { 397 goto error; 398 } else if (wipe_fence) { 399 dma_fence_put(fence); 400 fence = wipe_fence; 401 } 402 } 403 404 /* Always block for VM page tables before committing the new location */ 405 if (bo->type == ttm_bo_type_kernel) 406 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 407 else 408 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 409 dma_fence_put(fence); 410 return r; 411 412 error: 413 if (fence) 414 dma_fence_wait(fence, false); 415 dma_fence_put(fence); 416 return r; 417 } 418 419 /* 420 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 421 * 422 * Called by amdgpu_bo_move() 423 */ 424 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 425 struct ttm_resource *mem) 426 { 427 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 428 struct amdgpu_res_cursor cursor; 429 430 if (mem->mem_type == TTM_PL_SYSTEM || 431 mem->mem_type == TTM_PL_TT) 432 return true; 433 if (mem->mem_type != TTM_PL_VRAM) 434 return false; 435 436 amdgpu_res_first(mem, 0, mem_size, &cursor); 437 438 /* ttm_resource_ioremap only supports contiguous memory */ 439 if (cursor.size != mem_size) 440 return false; 441 442 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 443 } 444 445 /* 446 * amdgpu_bo_move - Move a buffer object to a new memory location 447 * 448 * Called by ttm_bo_handle_move_mem() 449 */ 450 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 451 struct ttm_operation_ctx *ctx, 452 struct ttm_resource *new_mem, 453 struct ttm_place *hop) 454 { 455 struct amdgpu_device *adev; 456 struct amdgpu_bo *abo; 457 struct ttm_resource *old_mem = bo->resource; 458 int r; 459 460 if (new_mem->mem_type == TTM_PL_TT || 461 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 462 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 463 if (r) 464 return r; 465 } 466 467 /* Can't move a pinned BO */ 468 abo = ttm_to_amdgpu_bo(bo); 469 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 470 return -EINVAL; 471 472 adev = amdgpu_ttm_adev(bo->bdev); 473 474 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 475 bo->ttm == NULL)) { 476 ttm_bo_move_null(bo, new_mem); 477 goto out; 478 } 479 if (old_mem->mem_type == TTM_PL_SYSTEM && 480 (new_mem->mem_type == TTM_PL_TT || 481 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 482 ttm_bo_move_null(bo, new_mem); 483 goto out; 484 } 485 if ((old_mem->mem_type == TTM_PL_TT || 486 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 487 new_mem->mem_type == TTM_PL_SYSTEM) { 488 r = ttm_bo_wait_ctx(bo, ctx); 489 if (r) 490 return r; 491 492 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 493 ttm_resource_free(bo, &bo->resource); 494 ttm_bo_assign_mem(bo, new_mem); 495 goto out; 496 } 497 498 if (old_mem->mem_type == AMDGPU_PL_GDS || 499 old_mem->mem_type == AMDGPU_PL_GWS || 500 old_mem->mem_type == AMDGPU_PL_OA || 501 new_mem->mem_type == AMDGPU_PL_GDS || 502 new_mem->mem_type == AMDGPU_PL_GWS || 503 new_mem->mem_type == AMDGPU_PL_OA) { 504 /* Nothing to save here */ 505 ttm_bo_move_null(bo, new_mem); 506 goto out; 507 } 508 509 if (bo->type == ttm_bo_type_device && 510 new_mem->mem_type == TTM_PL_VRAM && 511 old_mem->mem_type != TTM_PL_VRAM) { 512 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 513 * accesses the BO after it's moved. 514 */ 515 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 516 } 517 518 if (adev->mman.buffer_funcs_enabled) { 519 if (((old_mem->mem_type == TTM_PL_SYSTEM && 520 new_mem->mem_type == TTM_PL_VRAM) || 521 (old_mem->mem_type == TTM_PL_VRAM && 522 new_mem->mem_type == TTM_PL_SYSTEM))) { 523 hop->fpfn = 0; 524 hop->lpfn = 0; 525 hop->mem_type = TTM_PL_TT; 526 hop->flags = TTM_PL_FLAG_TEMPORARY; 527 return -EMULTIHOP; 528 } 529 530 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 531 } else { 532 r = -ENODEV; 533 } 534 535 if (r) { 536 /* Check that all memory is CPU accessible */ 537 if (!amdgpu_mem_visible(adev, old_mem) || 538 !amdgpu_mem_visible(adev, new_mem)) { 539 pr_err("Move buffer fallback to memcpy unavailable\n"); 540 return r; 541 } 542 543 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 544 if (r) 545 return r; 546 } 547 548 out: 549 /* update statistics */ 550 atomic64_add(bo->base.size, &adev->num_bytes_moved); 551 amdgpu_bo_move_notify(bo, evict, new_mem); 552 return 0; 553 } 554 555 /* 556 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 557 * 558 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 559 */ 560 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 561 struct ttm_resource *mem) 562 { 563 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 564 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 565 566 switch (mem->mem_type) { 567 case TTM_PL_SYSTEM: 568 /* system memory */ 569 return 0; 570 case TTM_PL_TT: 571 case AMDGPU_PL_PREEMPT: 572 break; 573 case TTM_PL_VRAM: 574 mem->bus.offset = mem->start << PAGE_SHIFT; 575 /* check if it's visible */ 576 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 577 return -EINVAL; 578 579 if (adev->mman.aper_base_kaddr && 580 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 581 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 582 mem->bus.offset; 583 584 mem->bus.offset += adev->gmc.aper_base; 585 mem->bus.is_iomem = true; 586 break; 587 default: 588 return -EINVAL; 589 } 590 return 0; 591 } 592 593 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 594 unsigned long page_offset) 595 { 596 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 597 struct amdgpu_res_cursor cursor; 598 599 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 600 &cursor); 601 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 602 } 603 604 /** 605 * amdgpu_ttm_domain_start - Returns GPU start address 606 * @adev: amdgpu device object 607 * @type: type of the memory 608 * 609 * Returns: 610 * GPU start address of a memory domain 611 */ 612 613 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 614 { 615 switch (type) { 616 case TTM_PL_TT: 617 return adev->gmc.gart_start; 618 case TTM_PL_VRAM: 619 return adev->gmc.vram_start; 620 } 621 622 return 0; 623 } 624 625 /* 626 * TTM backend functions. 627 */ 628 struct amdgpu_ttm_tt { 629 struct ttm_tt ttm; 630 struct drm_gem_object *gobj; 631 u64 offset; 632 uint64_t userptr; 633 struct task_struct *usertask; 634 uint32_t userflags; 635 bool bound; 636 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 637 struct hmm_range *range; 638 #endif 639 }; 640 641 #ifdef CONFIG_DRM_AMDGPU_USERPTR 642 /* 643 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 644 * memory and start HMM tracking CPU page table update 645 * 646 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 647 * once afterwards to stop HMM tracking 648 */ 649 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 650 { 651 struct ttm_tt *ttm = bo->tbo.ttm; 652 struct amdgpu_ttm_tt *gtt = (void *)ttm; 653 unsigned long start = gtt->userptr; 654 struct vm_area_struct *vma; 655 struct mm_struct *mm; 656 bool readonly; 657 int r = 0; 658 659 mm = bo->notifier.mm; 660 if (unlikely(!mm)) { 661 DRM_DEBUG_DRIVER("BO is not registered?\n"); 662 return -EFAULT; 663 } 664 665 /* Another get_user_pages is running at the same time?? */ 666 if (WARN_ON(gtt->range)) 667 return -EFAULT; 668 669 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 670 return -ESRCH; 671 672 mmap_read_lock(mm); 673 vma = vma_lookup(mm, start); 674 if (unlikely(!vma)) { 675 r = -EFAULT; 676 goto out_unlock; 677 } 678 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 679 vma->vm_file)) { 680 r = -EPERM; 681 goto out_unlock; 682 } 683 684 readonly = amdgpu_ttm_tt_is_readonly(ttm); 685 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 686 ttm->num_pages, >t->range, readonly, 687 true, NULL); 688 out_unlock: 689 mmap_read_unlock(mm); 690 if (r) 691 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 692 693 mmput(mm); 694 695 return r; 696 } 697 698 /* 699 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 700 * Check if the pages backing this ttm range have been invalidated 701 * 702 * Returns: true if pages are still valid 703 */ 704 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 705 { 706 struct amdgpu_ttm_tt *gtt = (void *)ttm; 707 bool r = false; 708 709 if (!gtt || !gtt->userptr) 710 return false; 711 712 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 713 gtt->userptr, ttm->num_pages); 714 715 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 716 "No user pages to check\n"); 717 718 if (gtt->range) { 719 /* 720 * FIXME: Must always hold notifier_lock for this, and must 721 * not ignore the return code. 722 */ 723 r = amdgpu_hmm_range_get_pages_done(gtt->range); 724 gtt->range = NULL; 725 } 726 727 return !r; 728 } 729 #endif 730 731 /* 732 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 733 * 734 * Called by amdgpu_cs_list_validate(). This creates the page list 735 * that backs user memory and will ultimately be mapped into the device 736 * address space. 737 */ 738 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 739 { 740 unsigned long i; 741 742 for (i = 0; i < ttm->num_pages; ++i) 743 ttm->pages[i] = pages ? pages[i] : NULL; 744 } 745 746 /* 747 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 748 * 749 * Called by amdgpu_ttm_backend_bind() 750 **/ 751 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 752 struct ttm_tt *ttm) 753 { 754 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 755 struct amdgpu_ttm_tt *gtt = (void *)ttm; 756 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 757 enum dma_data_direction direction = write ? 758 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 759 int r; 760 761 /* Allocate an SG array and squash pages into it */ 762 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 763 (u64)ttm->num_pages << PAGE_SHIFT, 764 GFP_KERNEL); 765 if (r) 766 goto release_sg; 767 768 /* Map SG to device */ 769 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 770 if (r) 771 goto release_sg; 772 773 /* convert SG to linear array of pages and dma addresses */ 774 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 775 ttm->num_pages); 776 777 return 0; 778 779 release_sg: 780 kfree(ttm->sg); 781 ttm->sg = NULL; 782 return r; 783 } 784 785 /* 786 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 787 */ 788 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 789 struct ttm_tt *ttm) 790 { 791 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 792 struct amdgpu_ttm_tt *gtt = (void *)ttm; 793 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 794 enum dma_data_direction direction = write ? 795 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 796 797 /* double check that we don't free the table twice */ 798 if (!ttm->sg || !ttm->sg->sgl) 799 return; 800 801 /* unmap the pages mapped to the device */ 802 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 803 sg_free_table(ttm->sg); 804 805 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 806 if (gtt->range) { 807 unsigned long i; 808 809 for (i = 0; i < ttm->num_pages; i++) { 810 if (ttm->pages[i] != 811 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 812 break; 813 } 814 815 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 816 } 817 #endif 818 } 819 820 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 821 struct ttm_buffer_object *tbo, 822 uint64_t flags) 823 { 824 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 825 struct ttm_tt *ttm = tbo->ttm; 826 struct amdgpu_ttm_tt *gtt = (void *)ttm; 827 828 if (amdgpu_bo_encrypted(abo)) 829 flags |= AMDGPU_PTE_TMZ; 830 831 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 832 uint64_t page_idx = 1; 833 834 amdgpu_gart_bind(adev, gtt->offset, page_idx, 835 gtt->ttm.dma_address, flags); 836 837 /* The memory type of the first page defaults to UC. Now 838 * modify the memory type to NC from the second page of 839 * the BO onward. 840 */ 841 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 842 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 843 844 amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT), 845 ttm->num_pages - page_idx, 846 &(gtt->ttm.dma_address[page_idx]), flags); 847 } else { 848 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 849 gtt->ttm.dma_address, flags); 850 } 851 } 852 853 /* 854 * amdgpu_ttm_backend_bind - Bind GTT memory 855 * 856 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 857 * This handles binding GTT memory to the device address space. 858 */ 859 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 860 struct ttm_tt *ttm, 861 struct ttm_resource *bo_mem) 862 { 863 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 864 struct amdgpu_ttm_tt *gtt = (void*)ttm; 865 uint64_t flags; 866 int r; 867 868 if (!bo_mem) 869 return -EINVAL; 870 871 if (gtt->bound) 872 return 0; 873 874 if (gtt->userptr) { 875 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 876 if (r) { 877 DRM_ERROR("failed to pin userptr\n"); 878 return r; 879 } 880 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 881 if (!ttm->sg) { 882 struct dma_buf_attachment *attach; 883 struct sg_table *sgt; 884 885 attach = gtt->gobj->import_attach; 886 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 887 if (IS_ERR(sgt)) 888 return PTR_ERR(sgt); 889 890 ttm->sg = sgt; 891 } 892 893 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 894 ttm->num_pages); 895 } 896 897 if (!ttm->num_pages) { 898 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 899 ttm->num_pages, bo_mem, ttm); 900 } 901 902 if (bo_mem->mem_type != TTM_PL_TT || 903 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 904 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 905 return 0; 906 } 907 908 /* compute PTE flags relevant to this BO memory */ 909 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 910 911 /* bind pages into GART page tables */ 912 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 913 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 914 gtt->ttm.dma_address, flags); 915 gtt->bound = true; 916 return 0; 917 } 918 919 /* 920 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 921 * through AGP or GART aperture. 922 * 923 * If bo is accessible through AGP aperture, then use AGP aperture 924 * to access bo; otherwise allocate logical space in GART aperture 925 * and map bo to GART aperture. 926 */ 927 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 928 { 929 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 930 struct ttm_operation_ctx ctx = { false, false }; 931 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 932 struct ttm_placement placement; 933 struct ttm_place placements; 934 struct ttm_resource *tmp; 935 uint64_t addr, flags; 936 int r; 937 938 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 939 return 0; 940 941 addr = amdgpu_gmc_agp_addr(bo); 942 if (addr != AMDGPU_BO_INVALID_OFFSET) { 943 bo->resource->start = addr >> PAGE_SHIFT; 944 return 0; 945 } 946 947 /* allocate GART space */ 948 placement.num_placement = 1; 949 placement.placement = &placements; 950 placement.num_busy_placement = 1; 951 placement.busy_placement = &placements; 952 placements.fpfn = 0; 953 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 954 placements.mem_type = TTM_PL_TT; 955 placements.flags = bo->resource->placement; 956 957 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 958 if (unlikely(r)) 959 return r; 960 961 /* compute PTE flags for this buffer object */ 962 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 963 964 /* Bind pages */ 965 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 966 amdgpu_ttm_gart_bind(adev, bo, flags); 967 amdgpu_gart_invalidate_tlb(adev); 968 ttm_resource_free(bo, &bo->resource); 969 ttm_bo_assign_mem(bo, tmp); 970 971 return 0; 972 } 973 974 /* 975 * amdgpu_ttm_recover_gart - Rebind GTT pages 976 * 977 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 978 * rebind GTT pages during a GPU reset. 979 */ 980 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 981 { 982 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 983 uint64_t flags; 984 985 if (!tbo->ttm) 986 return; 987 988 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 989 amdgpu_ttm_gart_bind(adev, tbo, flags); 990 } 991 992 /* 993 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 994 * 995 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 996 * ttm_tt_destroy(). 997 */ 998 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 999 struct ttm_tt *ttm) 1000 { 1001 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1002 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1003 1004 /* if the pages have userptr pinning then clear that first */ 1005 if (gtt->userptr) { 1006 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1007 } else if (ttm->sg && gtt->gobj->import_attach) { 1008 struct dma_buf_attachment *attach; 1009 1010 attach = gtt->gobj->import_attach; 1011 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1012 ttm->sg = NULL; 1013 } 1014 1015 if (!gtt->bound) 1016 return; 1017 1018 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1019 return; 1020 1021 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1022 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1023 gtt->bound = false; 1024 } 1025 1026 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1027 struct ttm_tt *ttm) 1028 { 1029 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1030 1031 if (gtt->usertask) 1032 put_task_struct(gtt->usertask); 1033 1034 ttm_tt_fini(>t->ttm); 1035 kfree(gtt); 1036 } 1037 1038 /** 1039 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1040 * 1041 * @bo: The buffer object to create a GTT ttm_tt object around 1042 * @page_flags: Page flags to be added to the ttm_tt object 1043 * 1044 * Called by ttm_tt_create(). 1045 */ 1046 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1047 uint32_t page_flags) 1048 { 1049 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1050 struct amdgpu_ttm_tt *gtt; 1051 enum ttm_caching caching; 1052 1053 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1054 if (gtt == NULL) { 1055 return NULL; 1056 } 1057 gtt->gobj = &bo->base; 1058 1059 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1060 caching = ttm_write_combined; 1061 else 1062 caching = ttm_cached; 1063 1064 /* allocate space for the uninitialized page entries */ 1065 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1066 kfree(gtt); 1067 return NULL; 1068 } 1069 return >t->ttm; 1070 } 1071 1072 /* 1073 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1074 * 1075 * Map the pages of a ttm_tt object to an address space visible 1076 * to the underlying device. 1077 */ 1078 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1079 struct ttm_tt *ttm, 1080 struct ttm_operation_ctx *ctx) 1081 { 1082 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1083 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1084 pgoff_t i; 1085 int ret; 1086 1087 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1088 if (gtt->userptr) { 1089 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1090 if (!ttm->sg) 1091 return -ENOMEM; 1092 return 0; 1093 } 1094 1095 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1096 return 0; 1097 1098 ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1099 if (ret) 1100 return ret; 1101 1102 for (i = 0; i < ttm->num_pages; ++i) 1103 ttm->pages[i]->mapping = bdev->dev_mapping; 1104 1105 return 0; 1106 } 1107 1108 /* 1109 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1110 * 1111 * Unmaps pages of a ttm_tt object from the device address space and 1112 * unpopulates the page array backing it. 1113 */ 1114 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1115 struct ttm_tt *ttm) 1116 { 1117 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1118 struct amdgpu_device *adev; 1119 pgoff_t i; 1120 1121 amdgpu_ttm_backend_unbind(bdev, ttm); 1122 1123 if (gtt->userptr) { 1124 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1125 kfree(ttm->sg); 1126 ttm->sg = NULL; 1127 return; 1128 } 1129 1130 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1131 return; 1132 1133 for (i = 0; i < ttm->num_pages; ++i) 1134 ttm->pages[i]->mapping = NULL; 1135 1136 adev = amdgpu_ttm_adev(bdev); 1137 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1138 } 1139 1140 /** 1141 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current 1142 * task 1143 * 1144 * @tbo: The ttm_buffer_object that contains the userptr 1145 * @user_addr: The returned value 1146 */ 1147 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 1148 uint64_t *user_addr) 1149 { 1150 struct amdgpu_ttm_tt *gtt; 1151 1152 if (!tbo->ttm) 1153 return -EINVAL; 1154 1155 gtt = (void *)tbo->ttm; 1156 *user_addr = gtt->userptr; 1157 return 0; 1158 } 1159 1160 /** 1161 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1162 * task 1163 * 1164 * @bo: The ttm_buffer_object to bind this userptr to 1165 * @addr: The address in the current tasks VM space to use 1166 * @flags: Requirements of userptr object. 1167 * 1168 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1169 * to current task 1170 */ 1171 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1172 uint64_t addr, uint32_t flags) 1173 { 1174 struct amdgpu_ttm_tt *gtt; 1175 1176 if (!bo->ttm) { 1177 /* TODO: We want a separate TTM object type for userptrs */ 1178 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1179 if (bo->ttm == NULL) 1180 return -ENOMEM; 1181 } 1182 1183 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1184 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1185 1186 gtt = (void *)bo->ttm; 1187 gtt->userptr = addr; 1188 gtt->userflags = flags; 1189 1190 if (gtt->usertask) 1191 put_task_struct(gtt->usertask); 1192 gtt->usertask = current->group_leader; 1193 get_task_struct(gtt->usertask); 1194 1195 return 0; 1196 } 1197 1198 /* 1199 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1200 */ 1201 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1202 { 1203 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1204 1205 if (gtt == NULL) 1206 return NULL; 1207 1208 if (gtt->usertask == NULL) 1209 return NULL; 1210 1211 return gtt->usertask->mm; 1212 } 1213 1214 /* 1215 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1216 * address range for the current task. 1217 * 1218 */ 1219 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1220 unsigned long end, unsigned long *userptr) 1221 { 1222 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1223 unsigned long size; 1224 1225 if (gtt == NULL || !gtt->userptr) 1226 return false; 1227 1228 /* Return false if no part of the ttm_tt object lies within 1229 * the range 1230 */ 1231 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1232 if (gtt->userptr > end || gtt->userptr + size <= start) 1233 return false; 1234 1235 if (userptr) 1236 *userptr = gtt->userptr; 1237 return true; 1238 } 1239 1240 /* 1241 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1242 */ 1243 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1244 { 1245 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1246 1247 if (gtt == NULL || !gtt->userptr) 1248 return false; 1249 1250 return true; 1251 } 1252 1253 /* 1254 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1255 */ 1256 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1257 { 1258 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1259 1260 if (gtt == NULL) 1261 return false; 1262 1263 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1264 } 1265 1266 /** 1267 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1268 * 1269 * @ttm: The ttm_tt object to compute the flags for 1270 * @mem: The memory registry backing this ttm_tt object 1271 * 1272 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1273 */ 1274 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1275 { 1276 uint64_t flags = 0; 1277 1278 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1279 flags |= AMDGPU_PTE_VALID; 1280 1281 if (mem && (mem->mem_type == TTM_PL_TT || 1282 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1283 flags |= AMDGPU_PTE_SYSTEM; 1284 1285 if (ttm->caching == ttm_cached) 1286 flags |= AMDGPU_PTE_SNOOPED; 1287 } 1288 1289 if (mem && mem->mem_type == TTM_PL_VRAM && 1290 mem->bus.caching == ttm_cached) 1291 flags |= AMDGPU_PTE_SNOOPED; 1292 1293 return flags; 1294 } 1295 1296 /** 1297 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1298 * 1299 * @adev: amdgpu_device pointer 1300 * @ttm: The ttm_tt object to compute the flags for 1301 * @mem: The memory registry backing this ttm_tt object 1302 * 1303 * Figure out the flags to use for a VM PTE (Page Table Entry). 1304 */ 1305 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1306 struct ttm_resource *mem) 1307 { 1308 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1309 1310 flags |= adev->gart.gart_pte_flags; 1311 flags |= AMDGPU_PTE_READABLE; 1312 1313 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1314 flags |= AMDGPU_PTE_WRITEABLE; 1315 1316 return flags; 1317 } 1318 1319 /* 1320 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1321 * object. 1322 * 1323 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1324 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1325 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1326 * used to clean out a memory space. 1327 */ 1328 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1329 const struct ttm_place *place) 1330 { 1331 unsigned long num_pages = bo->resource->num_pages; 1332 struct dma_resv_iter resv_cursor; 1333 struct amdgpu_res_cursor cursor; 1334 struct dma_fence *f; 1335 1336 /* Swapout? */ 1337 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1338 return true; 1339 1340 if (bo->type == ttm_bo_type_kernel && 1341 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1342 return false; 1343 1344 /* If bo is a KFD BO, check if the bo belongs to the current process. 1345 * If true, then return false as any KFD process needs all its BOs to 1346 * be resident to run successfully 1347 */ 1348 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, 1349 DMA_RESV_USAGE_BOOKKEEP, f) { 1350 if (amdkfd_fence_check_mm(f, current->mm)) 1351 return false; 1352 } 1353 1354 switch (bo->resource->mem_type) { 1355 case AMDGPU_PL_PREEMPT: 1356 /* Preemptible BOs don't own system resources managed by the 1357 * driver (pages, VRAM, GART space). They point to resources 1358 * owned by someone else (e.g. pageable memory in user mode 1359 * or a DMABuf). They are used in a preemptible context so we 1360 * can guarantee no deadlocks and good QoS in case of MMU 1361 * notifiers or DMABuf move notifiers from the resource owner. 1362 */ 1363 return false; 1364 case TTM_PL_TT: 1365 if (amdgpu_bo_is_amdgpu_bo(bo) && 1366 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1367 return false; 1368 return true; 1369 1370 case TTM_PL_VRAM: 1371 /* Check each drm MM node individually */ 1372 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1373 &cursor); 1374 while (cursor.remaining) { 1375 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1376 && !(place->lpfn && 1377 place->lpfn <= PFN_DOWN(cursor.start))) 1378 return true; 1379 1380 amdgpu_res_next(&cursor, cursor.size); 1381 } 1382 return false; 1383 1384 default: 1385 break; 1386 } 1387 1388 return ttm_bo_eviction_valuable(bo, place); 1389 } 1390 1391 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1392 void *buf, size_t size, bool write) 1393 { 1394 while (size) { 1395 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1396 uint64_t bytes = 4 - (pos & 0x3); 1397 uint32_t shift = (pos & 0x3) * 8; 1398 uint32_t mask = 0xffffffff << shift; 1399 uint32_t value = 0; 1400 1401 if (size < bytes) { 1402 mask &= 0xffffffff >> (bytes - size) * 8; 1403 bytes = size; 1404 } 1405 1406 if (mask != 0xffffffff) { 1407 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1408 if (write) { 1409 value &= ~mask; 1410 value |= (*(uint32_t *)buf << shift) & mask; 1411 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1412 } else { 1413 value = (value & mask) >> shift; 1414 memcpy(buf, &value, bytes); 1415 } 1416 } else { 1417 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1418 } 1419 1420 pos += bytes; 1421 buf += bytes; 1422 size -= bytes; 1423 } 1424 } 1425 1426 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1427 unsigned long offset, void *buf, int len, int write) 1428 { 1429 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1430 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1431 struct amdgpu_res_cursor src_mm; 1432 struct amdgpu_job *job; 1433 struct dma_fence *fence; 1434 uint64_t src_addr, dst_addr; 1435 unsigned int num_dw; 1436 int r, idx; 1437 1438 if (len != PAGE_SIZE) 1439 return -EINVAL; 1440 1441 if (!adev->mman.sdma_access_ptr) 1442 return -EACCES; 1443 1444 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 1445 return -ENODEV; 1446 1447 if (write) 1448 memcpy(adev->mman.sdma_access_ptr, buf, len); 1449 1450 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1451 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job); 1452 if (r) 1453 goto out; 1454 1455 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1456 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start; 1457 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1458 if (write) 1459 swap(src_addr, dst_addr); 1460 1461 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, false); 1462 1463 amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); 1464 WARN_ON(job->ibs[0].length_dw > num_dw); 1465 1466 r = amdgpu_job_submit(job, &adev->mman.entity, AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 1467 if (r) { 1468 amdgpu_job_free(job); 1469 goto out; 1470 } 1471 1472 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1473 r = -ETIMEDOUT; 1474 dma_fence_put(fence); 1475 1476 if (!(r || write)) 1477 memcpy(buf, adev->mman.sdma_access_ptr, len); 1478 out: 1479 drm_dev_exit(idx); 1480 return r; 1481 } 1482 1483 /** 1484 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1485 * 1486 * @bo: The buffer object to read/write 1487 * @offset: Offset into buffer object 1488 * @buf: Secondary buffer to write/read from 1489 * @len: Length in bytes of access 1490 * @write: true if writing 1491 * 1492 * This is used to access VRAM that backs a buffer object via MMIO 1493 * access for debugging purposes. 1494 */ 1495 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1496 unsigned long offset, void *buf, int len, 1497 int write) 1498 { 1499 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1500 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1501 struct amdgpu_res_cursor cursor; 1502 int ret = 0; 1503 1504 if (bo->resource->mem_type != TTM_PL_VRAM) 1505 return -EIO; 1506 1507 if (amdgpu_device_has_timeouts_enabled(adev) && 1508 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1509 return len; 1510 1511 amdgpu_res_first(bo->resource, offset, len, &cursor); 1512 while (cursor.remaining) { 1513 size_t count, size = cursor.size; 1514 loff_t pos = cursor.start; 1515 1516 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1517 size -= count; 1518 if (size) { 1519 /* using MM to access rest vram and handle un-aligned address */ 1520 pos += count; 1521 buf += count; 1522 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1523 } 1524 1525 ret += cursor.size; 1526 buf += cursor.size; 1527 amdgpu_res_next(&cursor, cursor.size); 1528 } 1529 1530 return ret; 1531 } 1532 1533 static void 1534 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1535 { 1536 amdgpu_bo_move_notify(bo, false, NULL); 1537 } 1538 1539 static struct ttm_device_funcs amdgpu_bo_driver = { 1540 .ttm_tt_create = &amdgpu_ttm_tt_create, 1541 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1542 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1543 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1544 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1545 .evict_flags = &amdgpu_evict_flags, 1546 .move = &amdgpu_bo_move, 1547 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1548 .release_notify = &amdgpu_bo_release_notify, 1549 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1550 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1551 .access_memory = &amdgpu_ttm_access_memory, 1552 }; 1553 1554 /* 1555 * Firmware Reservation functions 1556 */ 1557 /** 1558 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1559 * 1560 * @adev: amdgpu_device pointer 1561 * 1562 * free fw reserved vram if it has been reserved. 1563 */ 1564 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1565 { 1566 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1567 NULL, &adev->mman.fw_vram_usage_va); 1568 } 1569 1570 /** 1571 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1572 * 1573 * @adev: amdgpu_device pointer 1574 * 1575 * create bo vram reservation from fw. 1576 */ 1577 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1578 { 1579 uint64_t vram_size = adev->gmc.visible_vram_size; 1580 1581 adev->mman.fw_vram_usage_va = NULL; 1582 adev->mman.fw_vram_usage_reserved_bo = NULL; 1583 1584 if (adev->mman.fw_vram_usage_size == 0 || 1585 adev->mman.fw_vram_usage_size > vram_size) 1586 return 0; 1587 1588 return amdgpu_bo_create_kernel_at(adev, 1589 adev->mman.fw_vram_usage_start_offset, 1590 adev->mman.fw_vram_usage_size, 1591 AMDGPU_GEM_DOMAIN_VRAM, 1592 &adev->mman.fw_vram_usage_reserved_bo, 1593 &adev->mman.fw_vram_usage_va); 1594 } 1595 1596 /* 1597 * Memoy training reservation functions 1598 */ 1599 1600 /** 1601 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1602 * 1603 * @adev: amdgpu_device pointer 1604 * 1605 * free memory training reserved vram if it has been reserved. 1606 */ 1607 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1608 { 1609 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1610 1611 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1612 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1613 ctx->c2p_bo = NULL; 1614 1615 return 0; 1616 } 1617 1618 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1619 { 1620 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1621 1622 memset(ctx, 0, sizeof(*ctx)); 1623 1624 ctx->c2p_train_data_offset = 1625 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1626 ctx->p2c_train_data_offset = 1627 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1628 ctx->train_data_size = 1629 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1630 1631 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1632 ctx->train_data_size, 1633 ctx->p2c_train_data_offset, 1634 ctx->c2p_train_data_offset); 1635 } 1636 1637 /* 1638 * reserve TMR memory at the top of VRAM which holds 1639 * IP Discovery data and is protected by PSP. 1640 */ 1641 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1642 { 1643 int ret; 1644 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1645 bool mem_train_support = false; 1646 1647 if (!amdgpu_sriov_vf(adev)) { 1648 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1649 mem_train_support = true; 1650 else 1651 DRM_DEBUG("memory training does not support!\n"); 1652 } 1653 1654 /* 1655 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1656 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1657 * 1658 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1659 * discovery data and G6 memory training data respectively 1660 */ 1661 adev->mman.discovery_tmr_size = 1662 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1663 if (!adev->mman.discovery_tmr_size) 1664 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1665 1666 if (mem_train_support) { 1667 /* reserve vram for mem train according to TMR location */ 1668 amdgpu_ttm_training_data_block_init(adev); 1669 ret = amdgpu_bo_create_kernel_at(adev, 1670 ctx->c2p_train_data_offset, 1671 ctx->train_data_size, 1672 AMDGPU_GEM_DOMAIN_VRAM, 1673 &ctx->c2p_bo, 1674 NULL); 1675 if (ret) { 1676 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1677 amdgpu_ttm_training_reserve_vram_fini(adev); 1678 return ret; 1679 } 1680 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1681 } 1682 1683 ret = amdgpu_bo_create_kernel_at(adev, 1684 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1685 adev->mman.discovery_tmr_size, 1686 AMDGPU_GEM_DOMAIN_VRAM, 1687 &adev->mman.discovery_memory, 1688 NULL); 1689 if (ret) { 1690 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1691 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1692 return ret; 1693 } 1694 1695 return 0; 1696 } 1697 1698 /* 1699 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1700 * gtt/vram related fields. 1701 * 1702 * This initializes all of the memory space pools that the TTM layer 1703 * will need such as the GTT space (system memory mapped to the device), 1704 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1705 * can be mapped per VMID. 1706 */ 1707 int amdgpu_ttm_init(struct amdgpu_device *adev) 1708 { 1709 uint64_t gtt_size; 1710 int r; 1711 u64 vis_vram_limit; 1712 1713 mutex_init(&adev->mman.gtt_window_lock); 1714 1715 /* No others user of address space so set it to 0 */ 1716 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1717 adev_to_drm(adev)->anon_inode->i_mapping, 1718 adev_to_drm(adev)->vma_offset_manager, 1719 adev->need_swiotlb, 1720 dma_addressing_limited(adev->dev)); 1721 if (r) { 1722 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1723 return r; 1724 } 1725 adev->mman.initialized = true; 1726 1727 /* Initialize VRAM pool with all of VRAM divided into pages */ 1728 r = amdgpu_vram_mgr_init(adev); 1729 if (r) { 1730 DRM_ERROR("Failed initializing VRAM heap.\n"); 1731 return r; 1732 } 1733 1734 /* Reduce size of CPU-visible VRAM if requested */ 1735 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1736 if (amdgpu_vis_vram_limit > 0 && 1737 vis_vram_limit <= adev->gmc.visible_vram_size) 1738 adev->gmc.visible_vram_size = vis_vram_limit; 1739 1740 /* Change the size here instead of the init above so only lpfn is affected */ 1741 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1742 #ifdef CONFIG_64BIT 1743 #ifdef CONFIG_X86 1744 if (adev->gmc.xgmi.connected_to_cpu) 1745 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1746 adev->gmc.visible_vram_size); 1747 1748 else 1749 #endif 1750 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1751 adev->gmc.visible_vram_size); 1752 #endif 1753 1754 /* 1755 *The reserved vram for firmware must be pinned to the specified 1756 *place on the VRAM, so reserve it early. 1757 */ 1758 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1759 if (r) { 1760 return r; 1761 } 1762 1763 /* 1764 * only NAVI10 and onwards ASIC support for IP discovery. 1765 * If IP discovery enabled, a block of memory should be 1766 * reserved for IP discovey. 1767 */ 1768 if (adev->mman.discovery_bin) { 1769 r = amdgpu_ttm_reserve_tmr(adev); 1770 if (r) 1771 return r; 1772 } 1773 1774 /* allocate memory as required for VGA 1775 * This is used for VGA emulation and pre-OS scanout buffers to 1776 * avoid display artifacts while transitioning between pre-OS 1777 * and driver. */ 1778 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1779 AMDGPU_GEM_DOMAIN_VRAM, 1780 &adev->mman.stolen_vga_memory, 1781 NULL); 1782 if (r) 1783 return r; 1784 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1785 adev->mman.stolen_extended_size, 1786 AMDGPU_GEM_DOMAIN_VRAM, 1787 &adev->mman.stolen_extended_memory, 1788 NULL); 1789 if (r) 1790 return r; 1791 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1792 adev->mman.stolen_reserved_size, 1793 AMDGPU_GEM_DOMAIN_VRAM, 1794 &adev->mman.stolen_reserved_memory, 1795 NULL); 1796 if (r) 1797 return r; 1798 1799 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1800 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1801 1802 /* Compute GTT size, either based on 1/2 the size of RAM size 1803 * or whatever the user passed on module init */ 1804 if (amdgpu_gtt_size == -1) { 1805 struct sysinfo si; 1806 1807 si_meminfo(&si); 1808 /* Certain GL unit tests for large textures can cause problems 1809 * with the OOM killer since there is no way to link this memory 1810 * to a process. This was originally mitigated (but not necessarily 1811 * eliminated) by limiting the GTT size. The problem is this limit 1812 * is often too low for many modern games so just make the limit 1/2 1813 * of system memory which aligns with TTM. The OOM accounting needs 1814 * to be addressed, but we shouldn't prevent common 3D applications 1815 * from being usable just to potentially mitigate that corner case. 1816 */ 1817 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1818 (u64)si.totalram * si.mem_unit / 2); 1819 } else { 1820 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1821 } 1822 1823 /* Initialize GTT memory pool */ 1824 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1825 if (r) { 1826 DRM_ERROR("Failed initializing GTT heap.\n"); 1827 return r; 1828 } 1829 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1830 (unsigned)(gtt_size / (1024 * 1024))); 1831 1832 /* Initialize preemptible memory pool */ 1833 r = amdgpu_preempt_mgr_init(adev); 1834 if (r) { 1835 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1836 return r; 1837 } 1838 1839 /* Initialize various on-chip memory pools */ 1840 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1841 if (r) { 1842 DRM_ERROR("Failed initializing GDS heap.\n"); 1843 return r; 1844 } 1845 1846 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1847 if (r) { 1848 DRM_ERROR("Failed initializing gws heap.\n"); 1849 return r; 1850 } 1851 1852 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1853 if (r) { 1854 DRM_ERROR("Failed initializing oa heap.\n"); 1855 return r; 1856 } 1857 1858 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 1859 AMDGPU_GEM_DOMAIN_GTT, 1860 &adev->mman.sdma_access_bo, NULL, 1861 &adev->mman.sdma_access_ptr)) 1862 DRM_WARN("Debug VRAM access will use slowpath MM access\n"); 1863 1864 return 0; 1865 } 1866 1867 /* 1868 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1869 */ 1870 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1871 { 1872 int idx; 1873 if (!adev->mman.initialized) 1874 return; 1875 1876 amdgpu_ttm_training_reserve_vram_fini(adev); 1877 /* return the stolen vga memory back to VRAM */ 1878 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1879 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1880 /* return the IP Discovery TMR memory back to VRAM */ 1881 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1882 if (adev->mman.stolen_reserved_size) 1883 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1884 NULL, NULL); 1885 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 1886 &adev->mman.sdma_access_ptr); 1887 amdgpu_ttm_fw_reserve_vram_fini(adev); 1888 1889 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1890 1891 if (adev->mman.aper_base_kaddr) 1892 iounmap(adev->mman.aper_base_kaddr); 1893 adev->mman.aper_base_kaddr = NULL; 1894 1895 drm_dev_exit(idx); 1896 } 1897 1898 amdgpu_vram_mgr_fini(adev); 1899 amdgpu_gtt_mgr_fini(adev); 1900 amdgpu_preempt_mgr_fini(adev); 1901 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1902 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1903 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1904 ttm_device_fini(&adev->mman.bdev); 1905 adev->mman.initialized = false; 1906 DRM_INFO("amdgpu: ttm finalized\n"); 1907 } 1908 1909 /** 1910 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1911 * 1912 * @adev: amdgpu_device pointer 1913 * @enable: true when we can use buffer functions. 1914 * 1915 * Enable/disable use of buffer functions during suspend/resume. This should 1916 * only be called at bootup or when userspace isn't running. 1917 */ 1918 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1919 { 1920 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1921 uint64_t size; 1922 int r; 1923 1924 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1925 adev->mman.buffer_funcs_enabled == enable) 1926 return; 1927 1928 if (enable) { 1929 struct amdgpu_ring *ring; 1930 struct drm_gpu_scheduler *sched; 1931 1932 ring = adev->mman.buffer_funcs_ring; 1933 sched = &ring->sched; 1934 r = drm_sched_entity_init(&adev->mman.entity, 1935 DRM_SCHED_PRIORITY_KERNEL, &sched, 1936 1, NULL); 1937 if (r) { 1938 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1939 r); 1940 return; 1941 } 1942 } else { 1943 drm_sched_entity_destroy(&adev->mman.entity); 1944 dma_fence_put(man->move); 1945 man->move = NULL; 1946 } 1947 1948 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1949 if (enable) 1950 size = adev->gmc.real_vram_size; 1951 else 1952 size = adev->gmc.visible_vram_size; 1953 man->size = size; 1954 adev->mman.buffer_funcs_enabled = enable; 1955 } 1956 1957 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, 1958 bool direct_submit, 1959 unsigned int num_dw, 1960 struct dma_resv *resv, 1961 bool vm_needs_flush, 1962 struct amdgpu_job **job) 1963 { 1964 enum amdgpu_ib_pool_type pool = direct_submit ? 1965 AMDGPU_IB_POOL_DIRECT : 1966 AMDGPU_IB_POOL_DELAYED; 1967 int r; 1968 1969 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, job); 1970 if (r) 1971 return r; 1972 1973 if (vm_needs_flush) { 1974 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1975 adev->gmc.pdb0_bo : 1976 adev->gart.bo); 1977 (*job)->vm_needs_flush = true; 1978 } 1979 if (resv) { 1980 r = amdgpu_sync_resv(adev, &(*job)->sync, resv, 1981 AMDGPU_SYNC_ALWAYS, 1982 AMDGPU_FENCE_OWNER_UNDEFINED); 1983 if (r) { 1984 DRM_ERROR("sync failed (%d).\n", r); 1985 amdgpu_job_free(*job); 1986 return r; 1987 } 1988 } 1989 return 0; 1990 } 1991 1992 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1993 uint64_t dst_offset, uint32_t byte_count, 1994 struct dma_resv *resv, 1995 struct dma_fence **fence, bool direct_submit, 1996 bool vm_needs_flush, bool tmz) 1997 { 1998 struct amdgpu_device *adev = ring->adev; 1999 unsigned num_loops, num_dw; 2000 struct amdgpu_job *job; 2001 uint32_t max_bytes; 2002 unsigned i; 2003 int r; 2004 2005 if (!direct_submit && !ring->sched.ready) { 2006 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2007 return -EINVAL; 2008 } 2009 2010 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2011 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2012 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2013 r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, 2014 resv, vm_needs_flush, &job); 2015 if (r) 2016 return r; 2017 2018 for (i = 0; i < num_loops; i++) { 2019 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2020 2021 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2022 dst_offset, cur_size_in_bytes, tmz); 2023 2024 src_offset += cur_size_in_bytes; 2025 dst_offset += cur_size_in_bytes; 2026 byte_count -= cur_size_in_bytes; 2027 } 2028 2029 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2030 WARN_ON(job->ibs[0].length_dw > num_dw); 2031 if (direct_submit) 2032 r = amdgpu_job_submit_direct(job, ring, fence); 2033 else 2034 r = amdgpu_job_submit(job, &adev->mman.entity, 2035 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2036 if (r) 2037 goto error_free; 2038 2039 return r; 2040 2041 error_free: 2042 amdgpu_job_free(job); 2043 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2044 return r; 2045 } 2046 2047 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, 2048 uint64_t dst_addr, uint32_t byte_count, 2049 struct dma_resv *resv, 2050 struct dma_fence **fence, 2051 bool vm_needs_flush) 2052 { 2053 struct amdgpu_device *adev = ring->adev; 2054 unsigned int num_loops, num_dw; 2055 struct amdgpu_job *job; 2056 uint32_t max_bytes; 2057 unsigned int i; 2058 int r; 2059 2060 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2061 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); 2062 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); 2063 r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, 2064 &job); 2065 if (r) 2066 return r; 2067 2068 for (i = 0; i < num_loops; i++) { 2069 uint32_t cur_size = min(byte_count, max_bytes); 2070 2071 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2072 cur_size); 2073 2074 dst_addr += cur_size; 2075 byte_count -= cur_size; 2076 } 2077 2078 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2079 WARN_ON(job->ibs[0].length_dw > num_dw); 2080 r = amdgpu_job_submit(job, &adev->mman.entity, 2081 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2082 if (r) 2083 goto error_free; 2084 2085 return 0; 2086 2087 error_free: 2088 amdgpu_job_free(job); 2089 return r; 2090 } 2091 2092 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2093 uint32_t src_data, 2094 struct dma_resv *resv, 2095 struct dma_fence **f) 2096 { 2097 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2098 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2099 struct dma_fence *fence = NULL; 2100 struct amdgpu_res_cursor dst; 2101 int r; 2102 2103 if (!adev->mman.buffer_funcs_enabled) { 2104 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2105 return -EINVAL; 2106 } 2107 2108 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); 2109 2110 mutex_lock(&adev->mman.gtt_window_lock); 2111 while (dst.remaining) { 2112 struct dma_fence *next; 2113 uint64_t cur_size, to; 2114 2115 /* Never fill more than 256MiB at once to avoid timeouts */ 2116 cur_size = min(dst.size, 256ULL << 20); 2117 2118 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst, 2119 1, ring, false, &cur_size, &to); 2120 if (r) 2121 goto error; 2122 2123 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, 2124 &next, true); 2125 if (r) 2126 goto error; 2127 2128 dma_fence_put(fence); 2129 fence = next; 2130 2131 amdgpu_res_next(&dst, cur_size); 2132 } 2133 error: 2134 mutex_unlock(&adev->mman.gtt_window_lock); 2135 if (f) 2136 *f = dma_fence_get(fence); 2137 dma_fence_put(fence); 2138 return r; 2139 } 2140 2141 /** 2142 * amdgpu_ttm_evict_resources - evict memory buffers 2143 * @adev: amdgpu device object 2144 * @mem_type: evicted BO's memory type 2145 * 2146 * Evicts all @mem_type buffers on the lru list of the memory type. 2147 * 2148 * Returns: 2149 * 0 for success or a negative error code on failure. 2150 */ 2151 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2152 { 2153 struct ttm_resource_manager *man; 2154 2155 switch (mem_type) { 2156 case TTM_PL_VRAM: 2157 case TTM_PL_TT: 2158 case AMDGPU_PL_GWS: 2159 case AMDGPU_PL_GDS: 2160 case AMDGPU_PL_OA: 2161 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2162 break; 2163 default: 2164 DRM_ERROR("Trying to evict invalid memory type\n"); 2165 return -EINVAL; 2166 } 2167 2168 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2169 } 2170 2171 #if defined(CONFIG_DEBUG_FS) 2172 2173 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2174 { 2175 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2176 2177 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2178 } 2179 2180 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2181 2182 /* 2183 * amdgpu_ttm_vram_read - Linear read access to VRAM 2184 * 2185 * Accesses VRAM via MMIO for debugging purposes. 2186 */ 2187 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2188 size_t size, loff_t *pos) 2189 { 2190 struct amdgpu_device *adev = file_inode(f)->i_private; 2191 ssize_t result = 0; 2192 2193 if (size & 0x3 || *pos & 0x3) 2194 return -EINVAL; 2195 2196 if (*pos >= adev->gmc.mc_vram_size) 2197 return -ENXIO; 2198 2199 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2200 while (size) { 2201 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2202 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2203 2204 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2205 if (copy_to_user(buf, value, bytes)) 2206 return -EFAULT; 2207 2208 result += bytes; 2209 buf += bytes; 2210 *pos += bytes; 2211 size -= bytes; 2212 } 2213 2214 return result; 2215 } 2216 2217 /* 2218 * amdgpu_ttm_vram_write - Linear write access to VRAM 2219 * 2220 * Accesses VRAM via MMIO for debugging purposes. 2221 */ 2222 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2223 size_t size, loff_t *pos) 2224 { 2225 struct amdgpu_device *adev = file_inode(f)->i_private; 2226 ssize_t result = 0; 2227 int r; 2228 2229 if (size & 0x3 || *pos & 0x3) 2230 return -EINVAL; 2231 2232 if (*pos >= adev->gmc.mc_vram_size) 2233 return -ENXIO; 2234 2235 while (size) { 2236 uint32_t value; 2237 2238 if (*pos >= adev->gmc.mc_vram_size) 2239 return result; 2240 2241 r = get_user(value, (uint32_t *)buf); 2242 if (r) 2243 return r; 2244 2245 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2246 2247 result += 4; 2248 buf += 4; 2249 *pos += 4; 2250 size -= 4; 2251 } 2252 2253 return result; 2254 } 2255 2256 static const struct file_operations amdgpu_ttm_vram_fops = { 2257 .owner = THIS_MODULE, 2258 .read = amdgpu_ttm_vram_read, 2259 .write = amdgpu_ttm_vram_write, 2260 .llseek = default_llseek, 2261 }; 2262 2263 /* 2264 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2265 * 2266 * This function is used to read memory that has been mapped to the 2267 * GPU and the known addresses are not physical addresses but instead 2268 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2269 */ 2270 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2271 size_t size, loff_t *pos) 2272 { 2273 struct amdgpu_device *adev = file_inode(f)->i_private; 2274 struct iommu_domain *dom; 2275 ssize_t result = 0; 2276 int r; 2277 2278 /* retrieve the IOMMU domain if any for this device */ 2279 dom = iommu_get_domain_for_dev(adev->dev); 2280 2281 while (size) { 2282 phys_addr_t addr = *pos & PAGE_MASK; 2283 loff_t off = *pos & ~PAGE_MASK; 2284 size_t bytes = PAGE_SIZE - off; 2285 unsigned long pfn; 2286 struct page *p; 2287 void *ptr; 2288 2289 bytes = bytes < size ? bytes : size; 2290 2291 /* Translate the bus address to a physical address. If 2292 * the domain is NULL it means there is no IOMMU active 2293 * and the address translation is the identity 2294 */ 2295 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2296 2297 pfn = addr >> PAGE_SHIFT; 2298 if (!pfn_valid(pfn)) 2299 return -EPERM; 2300 2301 p = pfn_to_page(pfn); 2302 if (p->mapping != adev->mman.bdev.dev_mapping) 2303 return -EPERM; 2304 2305 ptr = kmap(p); 2306 r = copy_to_user(buf, ptr + off, bytes); 2307 kunmap(p); 2308 if (r) 2309 return -EFAULT; 2310 2311 size -= bytes; 2312 *pos += bytes; 2313 result += bytes; 2314 } 2315 2316 return result; 2317 } 2318 2319 /* 2320 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2321 * 2322 * This function is used to write memory that has been mapped to the 2323 * GPU and the known addresses are not physical addresses but instead 2324 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2325 */ 2326 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2327 size_t size, loff_t *pos) 2328 { 2329 struct amdgpu_device *adev = file_inode(f)->i_private; 2330 struct iommu_domain *dom; 2331 ssize_t result = 0; 2332 int r; 2333 2334 dom = iommu_get_domain_for_dev(adev->dev); 2335 2336 while (size) { 2337 phys_addr_t addr = *pos & PAGE_MASK; 2338 loff_t off = *pos & ~PAGE_MASK; 2339 size_t bytes = PAGE_SIZE - off; 2340 unsigned long pfn; 2341 struct page *p; 2342 void *ptr; 2343 2344 bytes = bytes < size ? bytes : size; 2345 2346 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2347 2348 pfn = addr >> PAGE_SHIFT; 2349 if (!pfn_valid(pfn)) 2350 return -EPERM; 2351 2352 p = pfn_to_page(pfn); 2353 if (p->mapping != adev->mman.bdev.dev_mapping) 2354 return -EPERM; 2355 2356 ptr = kmap(p); 2357 r = copy_from_user(ptr + off, buf, bytes); 2358 kunmap(p); 2359 if (r) 2360 return -EFAULT; 2361 2362 size -= bytes; 2363 *pos += bytes; 2364 result += bytes; 2365 } 2366 2367 return result; 2368 } 2369 2370 static const struct file_operations amdgpu_ttm_iomem_fops = { 2371 .owner = THIS_MODULE, 2372 .read = amdgpu_iomem_read, 2373 .write = amdgpu_iomem_write, 2374 .llseek = default_llseek 2375 }; 2376 2377 #endif 2378 2379 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2380 { 2381 #if defined(CONFIG_DEBUG_FS) 2382 struct drm_minor *minor = adev_to_drm(adev)->primary; 2383 struct dentry *root = minor->debugfs_root; 2384 2385 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2386 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2387 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2388 &amdgpu_ttm_iomem_fops); 2389 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2390 &amdgpu_ttm_page_pool_fops); 2391 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2392 TTM_PL_VRAM), 2393 root, "amdgpu_vram_mm"); 2394 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2395 TTM_PL_TT), 2396 root, "amdgpu_gtt_mm"); 2397 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2398 AMDGPU_PL_GDS), 2399 root, "amdgpu_gds_mm"); 2400 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2401 AMDGPU_PL_GWS), 2402 root, "amdgpu_gws_mm"); 2403 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2404 AMDGPU_PL_OA), 2405 root, "amdgpu_oa_mm"); 2406 2407 #endif 2408 } 2409