1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/hmm.h> 36 #include <linux/pagemap.h> 37 #include <linux/sched/task.h> 38 #include <linux/sched/mm.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/swap.h> 42 #include <linux/swiotlb.h> 43 #include <linux/dma-buf.h> 44 #include <linux/sizes.h> 45 46 #include <drm/ttm/ttm_bo_api.h> 47 #include <drm/ttm/ttm_bo_driver.h> 48 #include <drm/ttm/ttm_placement.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 52 #include <drm/drm_debugfs.h> 53 #include <drm/amdgpu_drm.h> 54 55 #include "amdgpu.h" 56 #include "amdgpu_object.h" 57 #include "amdgpu_trace.h" 58 #include "amdgpu_amdkfd.h" 59 #include "amdgpu_sdma.h" 60 #include "amdgpu_ras.h" 61 #include "amdgpu_atomfirmware.h" 62 #include "bif/bif_4_1_d.h" 63 64 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 65 66 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, 67 struct ttm_tt *ttm, 68 struct ttm_resource *bo_mem); 69 70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 71 unsigned int type, 72 uint64_t size) 73 { 74 return ttm_range_man_init(&adev->mman.bdev, type, 75 false, size >> PAGE_SHIFT); 76 } 77 78 /** 79 * amdgpu_evict_flags - Compute placement flags 80 * 81 * @bo: The buffer object to evict 82 * @placement: Possible destination(s) for evicted BO 83 * 84 * Fill in placement data when ttm_bo_evict() is called 85 */ 86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 87 struct ttm_placement *placement) 88 { 89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 90 struct amdgpu_bo *abo; 91 static const struct ttm_place placements = { 92 .fpfn = 0, 93 .lpfn = 0, 94 .mem_type = TTM_PL_SYSTEM, 95 .flags = TTM_PL_MASK_CACHING 96 }; 97 98 /* Don't handle scatter gather BOs */ 99 if (bo->type == ttm_bo_type_sg) { 100 placement->num_placement = 0; 101 placement->num_busy_placement = 0; 102 return; 103 } 104 105 /* Object isn't an AMDGPU object so ignore */ 106 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 107 placement->placement = &placements; 108 placement->busy_placement = &placements; 109 placement->num_placement = 1; 110 placement->num_busy_placement = 1; 111 return; 112 } 113 114 abo = ttm_to_amdgpu_bo(bo); 115 switch (bo->mem.mem_type) { 116 case AMDGPU_PL_GDS: 117 case AMDGPU_PL_GWS: 118 case AMDGPU_PL_OA: 119 placement->num_placement = 0; 120 placement->num_busy_placement = 0; 121 return; 122 123 case TTM_PL_VRAM: 124 if (!adev->mman.buffer_funcs_enabled) { 125 /* Move to system memory */ 126 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 127 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 128 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 129 amdgpu_bo_in_cpu_visible_vram(abo)) { 130 131 /* Try evicting to the CPU inaccessible part of VRAM 132 * first, but only set GTT as busy placement, so this 133 * BO will be evicted to GTT rather than causing other 134 * BOs to be evicted from VRAM 135 */ 136 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 137 AMDGPU_GEM_DOMAIN_GTT); 138 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 139 abo->placements[0].lpfn = 0; 140 abo->placement.busy_placement = &abo->placements[1]; 141 abo->placement.num_busy_placement = 1; 142 } else { 143 /* Move to GTT memory */ 144 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 145 } 146 break; 147 case TTM_PL_TT: 148 default: 149 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 150 break; 151 } 152 *placement = abo->placement; 153 } 154 155 /** 156 * amdgpu_verify_access - Verify access for a mmap call 157 * 158 * @bo: The buffer object to map 159 * @filp: The file pointer from the process performing the mmap 160 * 161 * This is called by ttm_bo_mmap() to verify whether a process 162 * has the right to mmap a BO to their process space. 163 */ 164 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) 165 { 166 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 167 168 /* 169 * Don't verify access for KFD BOs. They don't have a GEM 170 * object associated with them. 171 */ 172 if (abo->kfd_bo) 173 return 0; 174 175 if (amdgpu_ttm_tt_get_usermm(bo->ttm)) 176 return -EPERM; 177 return drm_vma_node_verify_access(&abo->tbo.base.vma_node, 178 filp->private_data); 179 } 180 181 /** 182 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. 183 * 184 * @bo: The bo to assign the memory to. 185 * @mm_node: Memory manager node for drm allocator. 186 * @mem: The region where the bo resides. 187 * 188 */ 189 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, 190 struct drm_mm_node *mm_node, 191 struct ttm_resource *mem) 192 { 193 uint64_t addr = 0; 194 195 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { 196 addr = mm_node->start << PAGE_SHIFT; 197 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev), 198 mem->mem_type); 199 } 200 return addr; 201 } 202 203 /** 204 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to 205 * @offset. It also modifies the offset to be within the drm_mm_node returned 206 * 207 * @mem: The region where the bo resides. 208 * @offset: The offset that drm_mm_node is used for finding. 209 * 210 */ 211 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem, 212 uint64_t *offset) 213 { 214 struct drm_mm_node *mm_node = mem->mm_node; 215 216 while (*offset >= (mm_node->size << PAGE_SHIFT)) { 217 *offset -= (mm_node->size << PAGE_SHIFT); 218 ++mm_node; 219 } 220 return mm_node; 221 } 222 223 /** 224 * amdgpu_ttm_map_buffer - Map memory into the GART windows 225 * @bo: buffer object to map 226 * @mem: memory object to map 227 * @mm_node: drm_mm node object to map 228 * @num_pages: number of pages to map 229 * @offset: offset into @mm_node where to start 230 * @window: which GART window to use 231 * @ring: DMA ring to use for the copy 232 * @tmz: if we should setup a TMZ enabled mapping 233 * @addr: resulting address inside the MC address space 234 * 235 * Setup one of the GART windows to access a specific piece of memory or return 236 * the physical address for local memory. 237 */ 238 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 239 struct ttm_resource *mem, 240 struct drm_mm_node *mm_node, 241 unsigned num_pages, uint64_t offset, 242 unsigned window, struct amdgpu_ring *ring, 243 bool tmz, uint64_t *addr) 244 { 245 struct amdgpu_device *adev = ring->adev; 246 struct amdgpu_job *job; 247 unsigned num_dw, num_bytes; 248 struct dma_fence *fence; 249 uint64_t src_addr, dst_addr; 250 void *cpu_addr; 251 uint64_t flags; 252 unsigned int i; 253 int r; 254 255 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 256 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 257 258 /* Map only what can't be accessed directly */ 259 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 260 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset; 261 return 0; 262 } 263 264 *addr = adev->gmc.gart_start; 265 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 266 AMDGPU_GPU_PAGE_SIZE; 267 *addr += offset & ~PAGE_MASK; 268 269 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 270 num_bytes = num_pages * 8; 271 272 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 273 AMDGPU_IB_POOL_DELAYED, &job); 274 if (r) 275 return r; 276 277 src_addr = num_dw * 4; 278 src_addr += job->ibs[0].gpu_addr; 279 280 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 281 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 282 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 283 dst_addr, num_bytes, false); 284 285 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 286 WARN_ON(job->ibs[0].length_dw > num_dw); 287 288 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 289 if (tmz) 290 flags |= AMDGPU_PTE_TMZ; 291 292 cpu_addr = &job->ibs[0].ptr[num_dw]; 293 294 if (mem->mem_type == TTM_PL_TT) { 295 struct ttm_dma_tt *dma; 296 dma_addr_t *dma_address; 297 298 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm); 299 dma_address = &dma->dma_address[offset >> PAGE_SHIFT]; 300 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, 301 cpu_addr); 302 if (r) 303 goto error_free; 304 } else { 305 dma_addr_t dma_address; 306 307 dma_address = (mm_node->start << PAGE_SHIFT) + offset; 308 dma_address += adev->vm_manager.vram_base_offset; 309 310 for (i = 0; i < num_pages; ++i) { 311 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 312 &dma_address, flags, cpu_addr); 313 if (r) 314 goto error_free; 315 316 dma_address += PAGE_SIZE; 317 } 318 } 319 320 r = amdgpu_job_submit(job, &adev->mman.entity, 321 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 322 if (r) 323 goto error_free; 324 325 dma_fence_put(fence); 326 327 return r; 328 329 error_free: 330 amdgpu_job_free(job); 331 return r; 332 } 333 334 /** 335 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy 336 * @adev: amdgpu device 337 * @src: buffer/address where to read from 338 * @dst: buffer/address where to write to 339 * @size: number of bytes to copy 340 * @tmz: if a secure copy should be used 341 * @resv: resv object to sync to 342 * @f: Returns the last fence if multiple jobs are submitted. 343 * 344 * The function copies @size bytes from {src->mem + src->offset} to 345 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 346 * move and different for a BO to BO copy. 347 * 348 */ 349 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 350 const struct amdgpu_copy_mem *src, 351 const struct amdgpu_copy_mem *dst, 352 uint64_t size, bool tmz, 353 struct dma_resv *resv, 354 struct dma_fence **f) 355 { 356 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 357 AMDGPU_GPU_PAGE_SIZE); 358 359 uint64_t src_node_size, dst_node_size, src_offset, dst_offset; 360 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 361 struct drm_mm_node *src_mm, *dst_mm; 362 struct dma_fence *fence = NULL; 363 int r = 0; 364 365 if (!adev->mman.buffer_funcs_enabled) { 366 DRM_ERROR("Trying to move memory with ring turned off.\n"); 367 return -EINVAL; 368 } 369 370 src_offset = src->offset; 371 if (src->mem->mm_node) { 372 src_mm = amdgpu_find_mm_node(src->mem, &src_offset); 373 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset; 374 } else { 375 src_mm = NULL; 376 src_node_size = ULLONG_MAX; 377 } 378 379 dst_offset = dst->offset; 380 if (dst->mem->mm_node) { 381 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset); 382 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset; 383 } else { 384 dst_mm = NULL; 385 dst_node_size = ULLONG_MAX; 386 } 387 388 mutex_lock(&adev->mman.gtt_window_lock); 389 390 while (size) { 391 uint32_t src_page_offset = src_offset & ~PAGE_MASK; 392 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK; 393 struct dma_fence *next; 394 uint32_t cur_size; 395 uint64_t from, to; 396 397 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 398 * begins at an offset, then adjust the size accordingly 399 */ 400 cur_size = max(src_page_offset, dst_page_offset); 401 cur_size = min(min3(src_node_size, dst_node_size, size), 402 (uint64_t)(GTT_MAX_BYTES - cur_size)); 403 404 /* Map src to window 0 and dst to window 1. */ 405 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm, 406 PFN_UP(cur_size + src_page_offset), 407 src_offset, 0, ring, tmz, &from); 408 if (r) 409 goto error; 410 411 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm, 412 PFN_UP(cur_size + dst_page_offset), 413 dst_offset, 1, ring, tmz, &to); 414 if (r) 415 goto error; 416 417 r = amdgpu_copy_buffer(ring, from, to, cur_size, 418 resv, &next, false, true, tmz); 419 if (r) 420 goto error; 421 422 dma_fence_put(fence); 423 fence = next; 424 425 size -= cur_size; 426 if (!size) 427 break; 428 429 src_node_size -= cur_size; 430 if (!src_node_size) { 431 ++src_mm; 432 src_node_size = src_mm->size << PAGE_SHIFT; 433 src_offset = 0; 434 } else { 435 src_offset += cur_size; 436 } 437 438 dst_node_size -= cur_size; 439 if (!dst_node_size) { 440 ++dst_mm; 441 dst_node_size = dst_mm->size << PAGE_SHIFT; 442 dst_offset = 0; 443 } else { 444 dst_offset += cur_size; 445 } 446 } 447 error: 448 mutex_unlock(&adev->mman.gtt_window_lock); 449 if (f) 450 *f = dma_fence_get(fence); 451 dma_fence_put(fence); 452 return r; 453 } 454 455 /** 456 * amdgpu_move_blit - Copy an entire buffer to another buffer 457 * 458 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 459 * help move buffers to and from VRAM. 460 */ 461 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 462 bool evict, 463 struct ttm_resource *new_mem, 464 struct ttm_resource *old_mem) 465 { 466 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 467 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 468 struct amdgpu_copy_mem src, dst; 469 struct dma_fence *fence = NULL; 470 int r; 471 472 src.bo = bo; 473 dst.bo = bo; 474 src.mem = old_mem; 475 dst.mem = new_mem; 476 src.offset = 0; 477 dst.offset = 0; 478 479 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 480 new_mem->num_pages << PAGE_SHIFT, 481 amdgpu_bo_encrypted(abo), 482 bo->base.resv, &fence); 483 if (r) 484 goto error; 485 486 /* clear the space being freed */ 487 if (old_mem->mem_type == TTM_PL_VRAM && 488 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 489 struct dma_fence *wipe_fence = NULL; 490 491 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 492 NULL, &wipe_fence); 493 if (r) { 494 goto error; 495 } else if (wipe_fence) { 496 dma_fence_put(fence); 497 fence = wipe_fence; 498 } 499 } 500 501 /* Always block for VM page tables before committing the new location */ 502 if (bo->type == ttm_bo_type_kernel) 503 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 504 else 505 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 506 dma_fence_put(fence); 507 return r; 508 509 error: 510 if (fence) 511 dma_fence_wait(fence, false); 512 dma_fence_put(fence); 513 return r; 514 } 515 516 /** 517 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer 518 * 519 * Called by amdgpu_bo_move(). 520 */ 521 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 522 struct ttm_operation_ctx *ctx, 523 struct ttm_resource *new_mem) 524 { 525 struct ttm_resource *old_mem = &bo->mem; 526 struct ttm_resource tmp_mem; 527 struct ttm_place placements; 528 struct ttm_placement placement; 529 int r; 530 531 /* create space/pages for new_mem in GTT space */ 532 tmp_mem = *new_mem; 533 tmp_mem.mm_node = NULL; 534 placement.num_placement = 1; 535 placement.placement = &placements; 536 placement.num_busy_placement = 1; 537 placement.busy_placement = &placements; 538 placements.fpfn = 0; 539 placements.lpfn = 0; 540 placements.mem_type = TTM_PL_TT; 541 placements.flags = TTM_PL_MASK_CACHING; 542 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 543 if (unlikely(r)) { 544 pr_err("Failed to find GTT space for blit from VRAM\n"); 545 return r; 546 } 547 548 /* set caching flags */ 549 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 550 if (unlikely(r)) { 551 goto out_cleanup; 552 } 553 554 r = ttm_tt_populate(bo->bdev, bo->ttm, ctx); 555 if (unlikely(r)) 556 goto out_cleanup; 557 558 /* Bind the memory to the GTT space */ 559 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem); 560 if (unlikely(r)) { 561 goto out_cleanup; 562 } 563 564 /* blit VRAM to GTT */ 565 r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem); 566 if (unlikely(r)) { 567 goto out_cleanup; 568 } 569 570 /* move BO (in tmp_mem) to new_mem */ 571 r = ttm_bo_move_ttm(bo, ctx, new_mem); 572 out_cleanup: 573 ttm_resource_free(bo, &tmp_mem); 574 return r; 575 } 576 577 /** 578 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM 579 * 580 * Called by amdgpu_bo_move(). 581 */ 582 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 583 struct ttm_operation_ctx *ctx, 584 struct ttm_resource *new_mem) 585 { 586 struct ttm_resource *old_mem = &bo->mem; 587 struct ttm_resource tmp_mem; 588 struct ttm_placement placement; 589 struct ttm_place placements; 590 int r; 591 592 /* make space in GTT for old_mem buffer */ 593 tmp_mem = *new_mem; 594 tmp_mem.mm_node = NULL; 595 placement.num_placement = 1; 596 placement.placement = &placements; 597 placement.num_busy_placement = 1; 598 placement.busy_placement = &placements; 599 placements.fpfn = 0; 600 placements.lpfn = 0; 601 placements.mem_type = TTM_PL_TT; 602 placements.flags = TTM_PL_MASK_CACHING; 603 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 604 if (unlikely(r)) { 605 pr_err("Failed to find GTT space for blit to VRAM\n"); 606 return r; 607 } 608 609 /* move/bind old memory to GTT space */ 610 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); 611 if (unlikely(r)) { 612 goto out_cleanup; 613 } 614 615 /* copy to VRAM */ 616 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 617 if (unlikely(r)) { 618 goto out_cleanup; 619 } 620 out_cleanup: 621 ttm_resource_free(bo, &tmp_mem); 622 return r; 623 } 624 625 /** 626 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 627 * 628 * Called by amdgpu_bo_move() 629 */ 630 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 631 struct ttm_resource *mem) 632 { 633 struct drm_mm_node *nodes = mem->mm_node; 634 635 if (mem->mem_type == TTM_PL_SYSTEM || 636 mem->mem_type == TTM_PL_TT) 637 return true; 638 if (mem->mem_type != TTM_PL_VRAM) 639 return false; 640 641 /* ttm_resource_ioremap only supports contiguous memory */ 642 if (nodes->size != mem->num_pages) 643 return false; 644 645 return ((nodes->start + nodes->size) << PAGE_SHIFT) 646 <= adev->gmc.visible_vram_size; 647 } 648 649 /** 650 * amdgpu_bo_move - Move a buffer object to a new memory location 651 * 652 * Called by ttm_bo_handle_move_mem() 653 */ 654 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 655 struct ttm_operation_ctx *ctx, 656 struct ttm_resource *new_mem) 657 { 658 struct amdgpu_device *adev; 659 struct amdgpu_bo *abo; 660 struct ttm_resource *old_mem = &bo->mem; 661 int r; 662 663 /* Can't move a pinned BO */ 664 abo = ttm_to_amdgpu_bo(bo); 665 if (WARN_ON_ONCE(abo->pin_count > 0)) 666 return -EINVAL; 667 668 adev = amdgpu_ttm_adev(bo->bdev); 669 670 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 671 ttm_bo_move_null(bo, new_mem); 672 return 0; 673 } 674 if ((old_mem->mem_type == TTM_PL_TT && 675 new_mem->mem_type == TTM_PL_SYSTEM) || 676 (old_mem->mem_type == TTM_PL_SYSTEM && 677 new_mem->mem_type == TTM_PL_TT)) { 678 /* bind is enough */ 679 ttm_bo_move_null(bo, new_mem); 680 return 0; 681 } 682 if (old_mem->mem_type == AMDGPU_PL_GDS || 683 old_mem->mem_type == AMDGPU_PL_GWS || 684 old_mem->mem_type == AMDGPU_PL_OA || 685 new_mem->mem_type == AMDGPU_PL_GDS || 686 new_mem->mem_type == AMDGPU_PL_GWS || 687 new_mem->mem_type == AMDGPU_PL_OA) { 688 /* Nothing to save here */ 689 ttm_bo_move_null(bo, new_mem); 690 return 0; 691 } 692 693 if (!adev->mman.buffer_funcs_enabled) { 694 r = -ENODEV; 695 goto memcpy; 696 } 697 698 if (old_mem->mem_type == TTM_PL_VRAM && 699 new_mem->mem_type == TTM_PL_SYSTEM) { 700 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); 701 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 702 new_mem->mem_type == TTM_PL_VRAM) { 703 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); 704 } else { 705 r = amdgpu_move_blit(bo, evict, 706 new_mem, old_mem); 707 } 708 709 if (r) { 710 memcpy: 711 /* Check that all memory is CPU accessible */ 712 if (!amdgpu_mem_visible(adev, old_mem) || 713 !amdgpu_mem_visible(adev, new_mem)) { 714 pr_err("Move buffer fallback to memcpy unavailable\n"); 715 return r; 716 } 717 718 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 719 if (r) 720 return r; 721 } 722 723 if (bo->type == ttm_bo_type_device && 724 new_mem->mem_type == TTM_PL_VRAM && 725 old_mem->mem_type != TTM_PL_VRAM) { 726 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 727 * accesses the BO after it's moved. 728 */ 729 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 730 } 731 732 /* update statistics */ 733 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); 734 return 0; 735 } 736 737 /** 738 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 739 * 740 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 741 */ 742 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem) 743 { 744 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 745 struct drm_mm_node *mm_node = mem->mm_node; 746 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 747 748 switch (mem->mem_type) { 749 case TTM_PL_SYSTEM: 750 /* system memory */ 751 return 0; 752 case TTM_PL_TT: 753 break; 754 case TTM_PL_VRAM: 755 mem->bus.offset = mem->start << PAGE_SHIFT; 756 /* check if it's visible */ 757 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 758 return -EINVAL; 759 /* Only physically contiguous buffers apply. In a contiguous 760 * buffer, size of the first mm_node would match the number of 761 * pages in ttm_resource. 762 */ 763 if (adev->mman.aper_base_kaddr && 764 (mm_node->size == mem->num_pages)) 765 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 766 mem->bus.offset; 767 768 mem->bus.offset += adev->gmc.aper_base; 769 mem->bus.is_iomem = true; 770 break; 771 default: 772 return -EINVAL; 773 } 774 return 0; 775 } 776 777 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 778 unsigned long page_offset) 779 { 780 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 781 uint64_t offset = (page_offset << PAGE_SHIFT); 782 struct drm_mm_node *mm; 783 784 mm = amdgpu_find_mm_node(&bo->mem, &offset); 785 offset += adev->gmc.aper_base; 786 return mm->start + (offset >> PAGE_SHIFT); 787 } 788 789 /** 790 * amdgpu_ttm_domain_start - Returns GPU start address 791 * @adev: amdgpu device object 792 * @type: type of the memory 793 * 794 * Returns: 795 * GPU start address of a memory domain 796 */ 797 798 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 799 { 800 switch (type) { 801 case TTM_PL_TT: 802 return adev->gmc.gart_start; 803 case TTM_PL_VRAM: 804 return adev->gmc.vram_start; 805 } 806 807 return 0; 808 } 809 810 /* 811 * TTM backend functions. 812 */ 813 struct amdgpu_ttm_tt { 814 struct ttm_dma_tt ttm; 815 struct drm_gem_object *gobj; 816 u64 offset; 817 uint64_t userptr; 818 struct task_struct *usertask; 819 uint32_t userflags; 820 bool bound; 821 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 822 struct hmm_range *range; 823 #endif 824 }; 825 826 #ifdef CONFIG_DRM_AMDGPU_USERPTR 827 /** 828 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 829 * memory and start HMM tracking CPU page table update 830 * 831 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 832 * once afterwards to stop HMM tracking 833 */ 834 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) 835 { 836 struct ttm_tt *ttm = bo->tbo.ttm; 837 struct amdgpu_ttm_tt *gtt = (void *)ttm; 838 unsigned long start = gtt->userptr; 839 struct vm_area_struct *vma; 840 struct hmm_range *range; 841 unsigned long timeout; 842 struct mm_struct *mm; 843 unsigned long i; 844 int r = 0; 845 846 mm = bo->notifier.mm; 847 if (unlikely(!mm)) { 848 DRM_DEBUG_DRIVER("BO is not registered?\n"); 849 return -EFAULT; 850 } 851 852 /* Another get_user_pages is running at the same time?? */ 853 if (WARN_ON(gtt->range)) 854 return -EFAULT; 855 856 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 857 return -ESRCH; 858 859 range = kzalloc(sizeof(*range), GFP_KERNEL); 860 if (unlikely(!range)) { 861 r = -ENOMEM; 862 goto out; 863 } 864 range->notifier = &bo->notifier; 865 range->start = bo->notifier.interval_tree.start; 866 range->end = bo->notifier.interval_tree.last + 1; 867 range->default_flags = HMM_PFN_REQ_FAULT; 868 if (!amdgpu_ttm_tt_is_readonly(ttm)) 869 range->default_flags |= HMM_PFN_REQ_WRITE; 870 871 range->hmm_pfns = kvmalloc_array(ttm->num_pages, 872 sizeof(*range->hmm_pfns), GFP_KERNEL); 873 if (unlikely(!range->hmm_pfns)) { 874 r = -ENOMEM; 875 goto out_free_ranges; 876 } 877 878 mmap_read_lock(mm); 879 vma = find_vma(mm, start); 880 if (unlikely(!vma || start < vma->vm_start)) { 881 r = -EFAULT; 882 goto out_unlock; 883 } 884 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 885 vma->vm_file)) { 886 r = -EPERM; 887 goto out_unlock; 888 } 889 mmap_read_unlock(mm); 890 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 891 892 retry: 893 range->notifier_seq = mmu_interval_read_begin(&bo->notifier); 894 895 mmap_read_lock(mm); 896 r = hmm_range_fault(range); 897 mmap_read_unlock(mm); 898 if (unlikely(r)) { 899 /* 900 * FIXME: This timeout should encompass the retry from 901 * mmu_interval_read_retry() as well. 902 */ 903 if (r == -EBUSY && !time_after(jiffies, timeout)) 904 goto retry; 905 goto out_free_pfns; 906 } 907 908 /* 909 * Due to default_flags, all pages are HMM_PFN_VALID or 910 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside 911 * the notifier_lock, and mmu_interval_read_retry() must be done first. 912 */ 913 for (i = 0; i < ttm->num_pages; i++) 914 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]); 915 916 gtt->range = range; 917 mmput(mm); 918 919 return 0; 920 921 out_unlock: 922 mmap_read_unlock(mm); 923 out_free_pfns: 924 kvfree(range->hmm_pfns); 925 out_free_ranges: 926 kfree(range); 927 out: 928 mmput(mm); 929 return r; 930 } 931 932 /** 933 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 934 * Check if the pages backing this ttm range have been invalidated 935 * 936 * Returns: true if pages are still valid 937 */ 938 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 939 { 940 struct amdgpu_ttm_tt *gtt = (void *)ttm; 941 bool r = false; 942 943 if (!gtt || !gtt->userptr) 944 return false; 945 946 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n", 947 gtt->userptr, ttm->num_pages); 948 949 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 950 "No user pages to check\n"); 951 952 if (gtt->range) { 953 /* 954 * FIXME: Must always hold notifier_lock for this, and must 955 * not ignore the return code. 956 */ 957 r = mmu_interval_read_retry(gtt->range->notifier, 958 gtt->range->notifier_seq); 959 kvfree(gtt->range->hmm_pfns); 960 kfree(gtt->range); 961 gtt->range = NULL; 962 } 963 964 return !r; 965 } 966 #endif 967 968 /** 969 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 970 * 971 * Called by amdgpu_cs_list_validate(). This creates the page list 972 * that backs user memory and will ultimately be mapped into the device 973 * address space. 974 */ 975 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) 976 { 977 unsigned long i; 978 979 for (i = 0; i < ttm->num_pages; ++i) 980 ttm->pages[i] = pages ? pages[i] : NULL; 981 } 982 983 /** 984 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 985 * 986 * Called by amdgpu_ttm_backend_bind() 987 **/ 988 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, 989 struct ttm_tt *ttm) 990 { 991 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 992 struct amdgpu_ttm_tt *gtt = (void *)ttm; 993 int r; 994 995 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 996 enum dma_data_direction direction = write ? 997 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 998 999 /* Allocate an SG array and squash pages into it */ 1000 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 1001 ttm->num_pages << PAGE_SHIFT, 1002 GFP_KERNEL); 1003 if (r) 1004 goto release_sg; 1005 1006 /* Map SG to device */ 1007 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 1008 if (r) 1009 goto release_sg; 1010 1011 /* convert SG to linear array of pages and dma addresses */ 1012 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1013 gtt->ttm.dma_address, ttm->num_pages); 1014 1015 return 0; 1016 1017 release_sg: 1018 kfree(ttm->sg); 1019 return r; 1020 } 1021 1022 /** 1023 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 1024 */ 1025 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, 1026 struct ttm_tt *ttm) 1027 { 1028 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1029 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1030 1031 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1032 enum dma_data_direction direction = write ? 1033 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 1034 1035 /* double check that we don't free the table twice */ 1036 if (!ttm->sg->sgl) 1037 return; 1038 1039 /* unmap the pages mapped to the device */ 1040 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 1041 sg_free_table(ttm->sg); 1042 1043 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 1044 if (gtt->range) { 1045 unsigned long i; 1046 1047 for (i = 0; i < ttm->num_pages; i++) { 1048 if (ttm->pages[i] != 1049 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 1050 break; 1051 } 1052 1053 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 1054 } 1055 #endif 1056 } 1057 1058 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 1059 struct ttm_buffer_object *tbo, 1060 uint64_t flags) 1061 { 1062 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 1063 struct ttm_tt *ttm = tbo->ttm; 1064 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1065 int r; 1066 1067 if (amdgpu_bo_encrypted(abo)) 1068 flags |= AMDGPU_PTE_TMZ; 1069 1070 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 1071 uint64_t page_idx = 1; 1072 1073 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 1074 ttm->pages, gtt->ttm.dma_address, flags); 1075 if (r) 1076 goto gart_bind_fail; 1077 1078 /* The memory type of the first page defaults to UC. Now 1079 * modify the memory type to NC from the second page of 1080 * the BO onward. 1081 */ 1082 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1083 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 1084 1085 r = amdgpu_gart_bind(adev, 1086 gtt->offset + (page_idx << PAGE_SHIFT), 1087 ttm->num_pages - page_idx, 1088 &ttm->pages[page_idx], 1089 &(gtt->ttm.dma_address[page_idx]), flags); 1090 } else { 1091 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1092 ttm->pages, gtt->ttm.dma_address, flags); 1093 } 1094 1095 gart_bind_fail: 1096 if (r) 1097 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1098 ttm->num_pages, gtt->offset); 1099 1100 return r; 1101 } 1102 1103 /** 1104 * amdgpu_ttm_backend_bind - Bind GTT memory 1105 * 1106 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 1107 * This handles binding GTT memory to the device address space. 1108 */ 1109 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev, 1110 struct ttm_tt *ttm, 1111 struct ttm_resource *bo_mem) 1112 { 1113 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1114 struct amdgpu_ttm_tt *gtt = (void*)ttm; 1115 uint64_t flags; 1116 int r = 0; 1117 1118 if (!bo_mem) 1119 return -EINVAL; 1120 1121 if (gtt->bound) 1122 return 0; 1123 1124 if (gtt->userptr) { 1125 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 1126 if (r) { 1127 DRM_ERROR("failed to pin userptr\n"); 1128 return r; 1129 } 1130 } 1131 if (!ttm->num_pages) { 1132 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 1133 ttm->num_pages, bo_mem, ttm); 1134 } 1135 1136 if (bo_mem->mem_type == AMDGPU_PL_GDS || 1137 bo_mem->mem_type == AMDGPU_PL_GWS || 1138 bo_mem->mem_type == AMDGPU_PL_OA) 1139 return -EINVAL; 1140 1141 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 1142 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 1143 return 0; 1144 } 1145 1146 /* compute PTE flags relevant to this BO memory */ 1147 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 1148 1149 /* bind pages into GART page tables */ 1150 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 1151 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 1152 ttm->pages, gtt->ttm.dma_address, flags); 1153 1154 if (r) 1155 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", 1156 ttm->num_pages, gtt->offset); 1157 gtt->bound = true; 1158 return r; 1159 } 1160 1161 /** 1162 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object 1163 */ 1164 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 1165 { 1166 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1167 struct ttm_operation_ctx ctx = { false, false }; 1168 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; 1169 struct ttm_resource tmp; 1170 struct ttm_placement placement; 1171 struct ttm_place placements; 1172 uint64_t addr, flags; 1173 int r; 1174 1175 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) 1176 return 0; 1177 1178 addr = amdgpu_gmc_agp_addr(bo); 1179 if (addr != AMDGPU_BO_INVALID_OFFSET) { 1180 bo->mem.start = addr >> PAGE_SHIFT; 1181 } else { 1182 1183 /* allocate GART space */ 1184 tmp = bo->mem; 1185 tmp.mm_node = NULL; 1186 placement.num_placement = 1; 1187 placement.placement = &placements; 1188 placement.num_busy_placement = 1; 1189 placement.busy_placement = &placements; 1190 placements.fpfn = 0; 1191 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1192 placements.mem_type = TTM_PL_TT; 1193 placements.flags = bo->mem.placement; 1194 1195 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1196 if (unlikely(r)) 1197 return r; 1198 1199 /* compute PTE flags for this buffer object */ 1200 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); 1201 1202 /* Bind pages */ 1203 gtt->offset = (u64)tmp.start << PAGE_SHIFT; 1204 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1205 if (unlikely(r)) { 1206 ttm_resource_free(bo, &tmp); 1207 return r; 1208 } 1209 1210 ttm_resource_free(bo, &bo->mem); 1211 bo->mem = tmp; 1212 } 1213 1214 return 0; 1215 } 1216 1217 /** 1218 * amdgpu_ttm_recover_gart - Rebind GTT pages 1219 * 1220 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1221 * rebind GTT pages during a GPU reset. 1222 */ 1223 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1224 { 1225 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1226 uint64_t flags; 1227 int r; 1228 1229 if (!tbo->ttm) 1230 return 0; 1231 1232 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); 1233 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1234 1235 return r; 1236 } 1237 1238 /** 1239 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1240 * 1241 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1242 * ttm_tt_destroy(). 1243 */ 1244 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev, 1245 struct ttm_tt *ttm) 1246 { 1247 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1248 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1249 int r; 1250 1251 if (!gtt->bound) 1252 return; 1253 1254 /* if the pages have userptr pinning then clear that first */ 1255 if (gtt->userptr) 1256 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1257 1258 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1259 return; 1260 1261 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1262 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1263 if (r) 1264 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", 1265 gtt->ttm.ttm.num_pages, gtt->offset); 1266 gtt->bound = false; 1267 } 1268 1269 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev, 1270 struct ttm_tt *ttm) 1271 { 1272 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1273 1274 amdgpu_ttm_backend_unbind(bdev, ttm); 1275 ttm_tt_destroy_common(bdev, ttm); 1276 if (gtt->usertask) 1277 put_task_struct(gtt->usertask); 1278 1279 ttm_dma_tt_fini(>t->ttm); 1280 kfree(gtt); 1281 } 1282 1283 /** 1284 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1285 * 1286 * @bo: The buffer object to create a GTT ttm_tt object around 1287 * 1288 * Called by ttm_tt_create(). 1289 */ 1290 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1291 uint32_t page_flags) 1292 { 1293 struct amdgpu_ttm_tt *gtt; 1294 1295 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1296 if (gtt == NULL) { 1297 return NULL; 1298 } 1299 gtt->gobj = &bo->base; 1300 1301 /* allocate space for the uninitialized page entries */ 1302 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) { 1303 kfree(gtt); 1304 return NULL; 1305 } 1306 return >t->ttm.ttm; 1307 } 1308 1309 /** 1310 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1311 * 1312 * Map the pages of a ttm_tt object to an address space visible 1313 * to the underlying device. 1314 */ 1315 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev, 1316 struct ttm_tt *ttm, 1317 struct ttm_operation_ctx *ctx) 1318 { 1319 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1320 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1321 1322 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1323 if (gtt && gtt->userptr) { 1324 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1325 if (!ttm->sg) 1326 return -ENOMEM; 1327 1328 ttm->page_flags |= TTM_PAGE_FLAG_SG; 1329 ttm_tt_set_populated(ttm); 1330 return 0; 1331 } 1332 1333 if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 1334 if (!ttm->sg) { 1335 struct dma_buf_attachment *attach; 1336 struct sg_table *sgt; 1337 1338 attach = gtt->gobj->import_attach; 1339 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 1340 if (IS_ERR(sgt)) 1341 return PTR_ERR(sgt); 1342 1343 ttm->sg = sgt; 1344 } 1345 1346 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1347 gtt->ttm.dma_address, 1348 ttm->num_pages); 1349 ttm_tt_set_populated(ttm); 1350 return 0; 1351 } 1352 1353 #ifdef CONFIG_SWIOTLB 1354 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1355 return ttm_dma_populate(>t->ttm, adev->dev, ctx); 1356 } 1357 #endif 1358 1359 /* fall back to generic helper to populate the page array 1360 * and map them to the device */ 1361 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx); 1362 } 1363 1364 /** 1365 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1366 * 1367 * Unmaps pages of a ttm_tt object from the device address space and 1368 * unpopulates the page array backing it. 1369 */ 1370 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm) 1371 { 1372 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1373 struct amdgpu_device *adev; 1374 1375 if (gtt && gtt->userptr) { 1376 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1377 kfree(ttm->sg); 1378 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 1379 return; 1380 } 1381 1382 if (ttm->sg && gtt->gobj->import_attach) { 1383 struct dma_buf_attachment *attach; 1384 1385 attach = gtt->gobj->import_attach; 1386 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1387 ttm->sg = NULL; 1388 return; 1389 } 1390 1391 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1392 return; 1393 1394 adev = amdgpu_ttm_adev(bdev); 1395 1396 #ifdef CONFIG_SWIOTLB 1397 if (adev->need_swiotlb && swiotlb_nr_tbl()) { 1398 ttm_dma_unpopulate(>t->ttm, adev->dev); 1399 return; 1400 } 1401 #endif 1402 1403 /* fall back to generic helper to unmap and unpopulate array */ 1404 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); 1405 } 1406 1407 /** 1408 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1409 * task 1410 * 1411 * @bo: The ttm_buffer_object to bind this userptr to 1412 * @addr: The address in the current tasks VM space to use 1413 * @flags: Requirements of userptr object. 1414 * 1415 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1416 * to current task 1417 */ 1418 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1419 uint64_t addr, uint32_t flags) 1420 { 1421 struct amdgpu_ttm_tt *gtt; 1422 1423 if (!bo->ttm) { 1424 /* TODO: We want a separate TTM object type for userptrs */ 1425 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1426 if (bo->ttm == NULL) 1427 return -ENOMEM; 1428 } 1429 1430 gtt = (void*)bo->ttm; 1431 gtt->userptr = addr; 1432 gtt->userflags = flags; 1433 1434 if (gtt->usertask) 1435 put_task_struct(gtt->usertask); 1436 gtt->usertask = current->group_leader; 1437 get_task_struct(gtt->usertask); 1438 1439 return 0; 1440 } 1441 1442 /** 1443 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1444 */ 1445 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1446 { 1447 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1448 1449 if (gtt == NULL) 1450 return NULL; 1451 1452 if (gtt->usertask == NULL) 1453 return NULL; 1454 1455 return gtt->usertask->mm; 1456 } 1457 1458 /** 1459 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1460 * address range for the current task. 1461 * 1462 */ 1463 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1464 unsigned long end) 1465 { 1466 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1467 unsigned long size; 1468 1469 if (gtt == NULL || !gtt->userptr) 1470 return false; 1471 1472 /* Return false if no part of the ttm_tt object lies within 1473 * the range 1474 */ 1475 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; 1476 if (gtt->userptr > end || gtt->userptr + size <= start) 1477 return false; 1478 1479 return true; 1480 } 1481 1482 /** 1483 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1484 */ 1485 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1486 { 1487 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1488 1489 if (gtt == NULL || !gtt->userptr) 1490 return false; 1491 1492 return true; 1493 } 1494 1495 /** 1496 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1497 */ 1498 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1499 { 1500 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1501 1502 if (gtt == NULL) 1503 return false; 1504 1505 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1506 } 1507 1508 /** 1509 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1510 * 1511 * @ttm: The ttm_tt object to compute the flags for 1512 * @mem: The memory registry backing this ttm_tt object 1513 * 1514 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1515 */ 1516 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1517 { 1518 uint64_t flags = 0; 1519 1520 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1521 flags |= AMDGPU_PTE_VALID; 1522 1523 if (mem && mem->mem_type == TTM_PL_TT) { 1524 flags |= AMDGPU_PTE_SYSTEM; 1525 1526 if (ttm->caching_state == tt_cached) 1527 flags |= AMDGPU_PTE_SNOOPED; 1528 } 1529 1530 return flags; 1531 } 1532 1533 /** 1534 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1535 * 1536 * @ttm: The ttm_tt object to compute the flags for 1537 * @mem: The memory registry backing this ttm_tt object 1538 1539 * Figure out the flags to use for a VM PTE (Page Table Entry). 1540 */ 1541 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1542 struct ttm_resource *mem) 1543 { 1544 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1545 1546 flags |= adev->gart.gart_pte_flags; 1547 flags |= AMDGPU_PTE_READABLE; 1548 1549 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1550 flags |= AMDGPU_PTE_WRITEABLE; 1551 1552 return flags; 1553 } 1554 1555 /** 1556 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1557 * object. 1558 * 1559 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1560 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1561 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1562 * used to clean out a memory space. 1563 */ 1564 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1565 const struct ttm_place *place) 1566 { 1567 unsigned long num_pages = bo->mem.num_pages; 1568 struct drm_mm_node *node = bo->mem.mm_node; 1569 struct dma_resv_list *flist; 1570 struct dma_fence *f; 1571 int i; 1572 1573 if (bo->type == ttm_bo_type_kernel && 1574 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1575 return false; 1576 1577 /* If bo is a KFD BO, check if the bo belongs to the current process. 1578 * If true, then return false as any KFD process needs all its BOs to 1579 * be resident to run successfully 1580 */ 1581 flist = dma_resv_get_list(bo->base.resv); 1582 if (flist) { 1583 for (i = 0; i < flist->shared_count; ++i) { 1584 f = rcu_dereference_protected(flist->shared[i], 1585 dma_resv_held(bo->base.resv)); 1586 if (amdkfd_fence_check_mm(f, current->mm)) 1587 return false; 1588 } 1589 } 1590 1591 switch (bo->mem.mem_type) { 1592 case TTM_PL_TT: 1593 if (amdgpu_bo_is_amdgpu_bo(bo) && 1594 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1595 return false; 1596 return true; 1597 1598 case TTM_PL_VRAM: 1599 /* Check each drm MM node individually */ 1600 while (num_pages) { 1601 if (place->fpfn < (node->start + node->size) && 1602 !(place->lpfn && place->lpfn <= node->start)) 1603 return true; 1604 1605 num_pages -= node->size; 1606 ++node; 1607 } 1608 return false; 1609 1610 default: 1611 break; 1612 } 1613 1614 return ttm_bo_eviction_valuable(bo, place); 1615 } 1616 1617 /** 1618 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1619 * 1620 * @bo: The buffer object to read/write 1621 * @offset: Offset into buffer object 1622 * @buf: Secondary buffer to write/read from 1623 * @len: Length in bytes of access 1624 * @write: true if writing 1625 * 1626 * This is used to access VRAM that backs a buffer object via MMIO 1627 * access for debugging purposes. 1628 */ 1629 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1630 unsigned long offset, 1631 void *buf, int len, int write) 1632 { 1633 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1634 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1635 struct drm_mm_node *nodes; 1636 uint32_t value = 0; 1637 int ret = 0; 1638 uint64_t pos; 1639 unsigned long flags; 1640 1641 if (bo->mem.mem_type != TTM_PL_VRAM) 1642 return -EIO; 1643 1644 pos = offset; 1645 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos); 1646 pos += (nodes->start << PAGE_SHIFT); 1647 1648 while (len && pos < adev->gmc.mc_vram_size) { 1649 uint64_t aligned_pos = pos & ~(uint64_t)3; 1650 uint64_t bytes = 4 - (pos & 3); 1651 uint32_t shift = (pos & 3) * 8; 1652 uint32_t mask = 0xffffffff << shift; 1653 1654 if (len < bytes) { 1655 mask &= 0xffffffff >> (bytes - len) * 8; 1656 bytes = len; 1657 } 1658 1659 if (mask != 0xffffffff) { 1660 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 1661 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); 1662 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); 1663 if (!write || mask != 0xffffffff) 1664 value = RREG32_NO_KIQ(mmMM_DATA); 1665 if (write) { 1666 value &= ~mask; 1667 value |= (*(uint32_t *)buf << shift) & mask; 1668 WREG32_NO_KIQ(mmMM_DATA, value); 1669 } 1670 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 1671 if (!write) { 1672 value = (value & mask) >> shift; 1673 memcpy(buf, &value, bytes); 1674 } 1675 } else { 1676 bytes = (nodes->start + nodes->size) << PAGE_SHIFT; 1677 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull); 1678 1679 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf, 1680 bytes, write); 1681 } 1682 1683 ret += bytes; 1684 buf = (uint8_t *)buf + bytes; 1685 pos += bytes; 1686 len -= bytes; 1687 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { 1688 ++nodes; 1689 pos = (nodes->start << PAGE_SHIFT); 1690 } 1691 } 1692 1693 return ret; 1694 } 1695 1696 static struct ttm_bo_driver amdgpu_bo_driver = { 1697 .ttm_tt_create = &amdgpu_ttm_tt_create, 1698 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1699 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1700 .ttm_tt_bind = &amdgpu_ttm_backend_bind, 1701 .ttm_tt_unbind = &amdgpu_ttm_backend_unbind, 1702 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1703 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1704 .evict_flags = &amdgpu_evict_flags, 1705 .move = &amdgpu_bo_move, 1706 .verify_access = &amdgpu_verify_access, 1707 .move_notify = &amdgpu_bo_move_notify, 1708 .release_notify = &amdgpu_bo_release_notify, 1709 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, 1710 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1711 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1712 .access_memory = &amdgpu_ttm_access_memory, 1713 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1714 }; 1715 1716 /* 1717 * Firmware Reservation functions 1718 */ 1719 /** 1720 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1721 * 1722 * @adev: amdgpu_device pointer 1723 * 1724 * free fw reserved vram if it has been reserved. 1725 */ 1726 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1727 { 1728 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1729 NULL, &adev->mman.fw_vram_usage_va); 1730 } 1731 1732 /** 1733 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1734 * 1735 * @adev: amdgpu_device pointer 1736 * 1737 * create bo vram reservation from fw. 1738 */ 1739 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1740 { 1741 uint64_t vram_size = adev->gmc.visible_vram_size; 1742 1743 adev->mman.fw_vram_usage_va = NULL; 1744 adev->mman.fw_vram_usage_reserved_bo = NULL; 1745 1746 if (adev->mman.fw_vram_usage_size == 0 || 1747 adev->mman.fw_vram_usage_size > vram_size) 1748 return 0; 1749 1750 return amdgpu_bo_create_kernel_at(adev, 1751 adev->mman.fw_vram_usage_start_offset, 1752 adev->mman.fw_vram_usage_size, 1753 AMDGPU_GEM_DOMAIN_VRAM, 1754 &adev->mman.fw_vram_usage_reserved_bo, 1755 &adev->mman.fw_vram_usage_va); 1756 } 1757 1758 /* 1759 * Memoy training reservation functions 1760 */ 1761 1762 /** 1763 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1764 * 1765 * @adev: amdgpu_device pointer 1766 * 1767 * free memory training reserved vram if it has been reserved. 1768 */ 1769 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1770 { 1771 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1772 1773 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1774 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1775 ctx->c2p_bo = NULL; 1776 1777 return 0; 1778 } 1779 1780 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1781 { 1782 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1783 1784 memset(ctx, 0, sizeof(*ctx)); 1785 1786 ctx->c2p_train_data_offset = 1787 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1788 ctx->p2c_train_data_offset = 1789 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1790 ctx->train_data_size = 1791 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1792 1793 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1794 ctx->train_data_size, 1795 ctx->p2c_train_data_offset, 1796 ctx->c2p_train_data_offset); 1797 } 1798 1799 /* 1800 * reserve TMR memory at the top of VRAM which holds 1801 * IP Discovery data and is protected by PSP. 1802 */ 1803 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1804 { 1805 int ret; 1806 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1807 bool mem_train_support = false; 1808 1809 if (!amdgpu_sriov_vf(adev)) { 1810 ret = amdgpu_mem_train_support(adev); 1811 if (ret == 1) 1812 mem_train_support = true; 1813 else if (ret == -1) 1814 return -EINVAL; 1815 else 1816 DRM_DEBUG("memory training does not support!\n"); 1817 } 1818 1819 /* 1820 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1821 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1822 * 1823 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1824 * discovery data and G6 memory training data respectively 1825 */ 1826 adev->mman.discovery_tmr_size = 1827 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1828 if (!adev->mman.discovery_tmr_size) 1829 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1830 1831 if (mem_train_support) { 1832 /* reserve vram for mem train according to TMR location */ 1833 amdgpu_ttm_training_data_block_init(adev); 1834 ret = amdgpu_bo_create_kernel_at(adev, 1835 ctx->c2p_train_data_offset, 1836 ctx->train_data_size, 1837 AMDGPU_GEM_DOMAIN_VRAM, 1838 &ctx->c2p_bo, 1839 NULL); 1840 if (ret) { 1841 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1842 amdgpu_ttm_training_reserve_vram_fini(adev); 1843 return ret; 1844 } 1845 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1846 } 1847 1848 ret = amdgpu_bo_create_kernel_at(adev, 1849 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1850 adev->mman.discovery_tmr_size, 1851 AMDGPU_GEM_DOMAIN_VRAM, 1852 &adev->mman.discovery_memory, 1853 NULL); 1854 if (ret) { 1855 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1856 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1857 return ret; 1858 } 1859 1860 return 0; 1861 } 1862 1863 /** 1864 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1865 * gtt/vram related fields. 1866 * 1867 * This initializes all of the memory space pools that the TTM layer 1868 * will need such as the GTT space (system memory mapped to the device), 1869 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1870 * can be mapped per VMID. 1871 */ 1872 int amdgpu_ttm_init(struct amdgpu_device *adev) 1873 { 1874 uint64_t gtt_size; 1875 int r; 1876 u64 vis_vram_limit; 1877 1878 mutex_init(&adev->mman.gtt_window_lock); 1879 1880 /* No others user of address space so set it to 0 */ 1881 r = ttm_bo_device_init(&adev->mman.bdev, 1882 &amdgpu_bo_driver, 1883 adev_to_drm(adev)->anon_inode->i_mapping, 1884 adev_to_drm(adev)->vma_offset_manager, 1885 dma_addressing_limited(adev->dev)); 1886 if (r) { 1887 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1888 return r; 1889 } 1890 adev->mman.initialized = true; 1891 1892 /* We opt to avoid OOM on system pages allocations */ 1893 adev->mman.bdev.no_retry = true; 1894 1895 /* Initialize VRAM pool with all of VRAM divided into pages */ 1896 r = amdgpu_vram_mgr_init(adev); 1897 if (r) { 1898 DRM_ERROR("Failed initializing VRAM heap.\n"); 1899 return r; 1900 } 1901 1902 /* Reduce size of CPU-visible VRAM if requested */ 1903 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1904 if (amdgpu_vis_vram_limit > 0 && 1905 vis_vram_limit <= adev->gmc.visible_vram_size) 1906 adev->gmc.visible_vram_size = vis_vram_limit; 1907 1908 /* Change the size here instead of the init above so only lpfn is affected */ 1909 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1910 #ifdef CONFIG_64BIT 1911 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1912 adev->gmc.visible_vram_size); 1913 #endif 1914 1915 /* 1916 *The reserved vram for firmware must be pinned to the specified 1917 *place on the VRAM, so reserve it early. 1918 */ 1919 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1920 if (r) { 1921 return r; 1922 } 1923 1924 /* 1925 * only NAVI10 and onwards ASIC support for IP discovery. 1926 * If IP discovery enabled, a block of memory should be 1927 * reserved for IP discovey. 1928 */ 1929 if (adev->mman.discovery_bin) { 1930 r = amdgpu_ttm_reserve_tmr(adev); 1931 if (r) 1932 return r; 1933 } 1934 1935 /* allocate memory as required for VGA 1936 * This is used for VGA emulation and pre-OS scanout buffers to 1937 * avoid display artifacts while transitioning between pre-OS 1938 * and driver. */ 1939 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1940 AMDGPU_GEM_DOMAIN_VRAM, 1941 &adev->mman.stolen_vga_memory, 1942 NULL); 1943 if (r) 1944 return r; 1945 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1946 adev->mman.stolen_extended_size, 1947 AMDGPU_GEM_DOMAIN_VRAM, 1948 &adev->mman.stolen_extended_memory, 1949 NULL); 1950 if (r) 1951 return r; 1952 1953 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1954 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1955 1956 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1957 * or whatever the user passed on module init */ 1958 if (amdgpu_gtt_size == -1) { 1959 struct sysinfo si; 1960 1961 si_meminfo(&si); 1962 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1963 adev->gmc.mc_vram_size), 1964 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1965 } 1966 else 1967 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1968 1969 /* Initialize GTT memory pool */ 1970 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1971 if (r) { 1972 DRM_ERROR("Failed initializing GTT heap.\n"); 1973 return r; 1974 } 1975 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1976 (unsigned)(gtt_size / (1024 * 1024))); 1977 1978 /* Initialize various on-chip memory pools */ 1979 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1980 if (r) { 1981 DRM_ERROR("Failed initializing GDS heap.\n"); 1982 return r; 1983 } 1984 1985 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1986 if (r) { 1987 DRM_ERROR("Failed initializing gws heap.\n"); 1988 return r; 1989 } 1990 1991 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1992 if (r) { 1993 DRM_ERROR("Failed initializing oa heap.\n"); 1994 return r; 1995 } 1996 1997 return 0; 1998 } 1999 2000 /** 2001 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm 2002 */ 2003 void amdgpu_ttm_late_init(struct amdgpu_device *adev) 2004 { 2005 /* return the VGA stolen memory (if any) back to VRAM */ 2006 if (!adev->mman.keep_stolen_vga_memory) 2007 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 2008 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 2009 } 2010 2011 /** 2012 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2013 */ 2014 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2015 { 2016 if (!adev->mman.initialized) 2017 return; 2018 2019 amdgpu_ttm_training_reserve_vram_fini(adev); 2020 /* return the stolen vga memory back to VRAM */ 2021 if (adev->mman.keep_stolen_vga_memory) 2022 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 2023 /* return the IP Discovery TMR memory back to VRAM */ 2024 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 2025 amdgpu_ttm_fw_reserve_vram_fini(adev); 2026 2027 if (adev->mman.aper_base_kaddr) 2028 iounmap(adev->mman.aper_base_kaddr); 2029 adev->mman.aper_base_kaddr = NULL; 2030 2031 amdgpu_vram_mgr_fini(adev); 2032 amdgpu_gtt_mgr_fini(adev); 2033 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 2034 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2035 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2036 ttm_bo_device_release(&adev->mman.bdev); 2037 adev->mman.initialized = false; 2038 DRM_INFO("amdgpu: ttm finalized\n"); 2039 } 2040 2041 /** 2042 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 2043 * 2044 * @adev: amdgpu_device pointer 2045 * @enable: true when we can use buffer functions. 2046 * 2047 * Enable/disable use of buffer functions during suspend/resume. This should 2048 * only be called at bootup or when userspace isn't running. 2049 */ 2050 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 2051 { 2052 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2053 uint64_t size; 2054 int r; 2055 2056 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 2057 adev->mman.buffer_funcs_enabled == enable) 2058 return; 2059 2060 if (enable) { 2061 struct amdgpu_ring *ring; 2062 struct drm_gpu_scheduler *sched; 2063 2064 ring = adev->mman.buffer_funcs_ring; 2065 sched = &ring->sched; 2066 r = drm_sched_entity_init(&adev->mman.entity, 2067 DRM_SCHED_PRIORITY_KERNEL, &sched, 2068 1, NULL); 2069 if (r) { 2070 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 2071 r); 2072 return; 2073 } 2074 } else { 2075 drm_sched_entity_destroy(&adev->mman.entity); 2076 dma_fence_put(man->move); 2077 man->move = NULL; 2078 } 2079 2080 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2081 if (enable) 2082 size = adev->gmc.real_vram_size; 2083 else 2084 size = adev->gmc.visible_vram_size; 2085 man->size = size >> PAGE_SHIFT; 2086 adev->mman.buffer_funcs_enabled = enable; 2087 } 2088 2089 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) 2090 { 2091 struct drm_file *file_priv = filp->private_data; 2092 struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); 2093 2094 if (adev == NULL) 2095 return -EINVAL; 2096 2097 return ttm_bo_mmap(filp, vma, &adev->mman.bdev); 2098 } 2099 2100 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 2101 uint64_t dst_offset, uint32_t byte_count, 2102 struct dma_resv *resv, 2103 struct dma_fence **fence, bool direct_submit, 2104 bool vm_needs_flush, bool tmz) 2105 { 2106 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 2107 AMDGPU_IB_POOL_DELAYED; 2108 struct amdgpu_device *adev = ring->adev; 2109 struct amdgpu_job *job; 2110 2111 uint32_t max_bytes; 2112 unsigned num_loops, num_dw; 2113 unsigned i; 2114 int r; 2115 2116 if (direct_submit && !ring->sched.ready) { 2117 DRM_ERROR("Trying to move memory with ring turned off.\n"); 2118 return -EINVAL; 2119 } 2120 2121 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2122 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2123 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2124 2125 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 2126 if (r) 2127 return r; 2128 2129 if (vm_needs_flush) { 2130 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 2131 job->vm_needs_flush = true; 2132 } 2133 if (resv) { 2134 r = amdgpu_sync_resv(adev, &job->sync, resv, 2135 AMDGPU_SYNC_ALWAYS, 2136 AMDGPU_FENCE_OWNER_UNDEFINED); 2137 if (r) { 2138 DRM_ERROR("sync failed (%d).\n", r); 2139 goto error_free; 2140 } 2141 } 2142 2143 for (i = 0; i < num_loops; i++) { 2144 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2145 2146 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2147 dst_offset, cur_size_in_bytes, tmz); 2148 2149 src_offset += cur_size_in_bytes; 2150 dst_offset += cur_size_in_bytes; 2151 byte_count -= cur_size_in_bytes; 2152 } 2153 2154 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2155 WARN_ON(job->ibs[0].length_dw > num_dw); 2156 if (direct_submit) 2157 r = amdgpu_job_submit_direct(job, ring, fence); 2158 else 2159 r = amdgpu_job_submit(job, &adev->mman.entity, 2160 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2161 if (r) 2162 goto error_free; 2163 2164 return r; 2165 2166 error_free: 2167 amdgpu_job_free(job); 2168 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2169 return r; 2170 } 2171 2172 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2173 uint32_t src_data, 2174 struct dma_resv *resv, 2175 struct dma_fence **fence) 2176 { 2177 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2178 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2179 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2180 2181 struct drm_mm_node *mm_node; 2182 unsigned long num_pages; 2183 unsigned int num_loops, num_dw; 2184 2185 struct amdgpu_job *job; 2186 int r; 2187 2188 if (!adev->mman.buffer_funcs_enabled) { 2189 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2190 return -EINVAL; 2191 } 2192 2193 if (bo->tbo.mem.mem_type == TTM_PL_TT) { 2194 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2195 if (r) 2196 return r; 2197 } 2198 2199 num_pages = bo->tbo.num_pages; 2200 mm_node = bo->tbo.mem.mm_node; 2201 num_loops = 0; 2202 while (num_pages) { 2203 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2204 2205 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes); 2206 num_pages -= mm_node->size; 2207 ++mm_node; 2208 } 2209 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2210 2211 /* for IB padding */ 2212 num_dw += 64; 2213 2214 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2215 &job); 2216 if (r) 2217 return r; 2218 2219 if (resv) { 2220 r = amdgpu_sync_resv(adev, &job->sync, resv, 2221 AMDGPU_SYNC_ALWAYS, 2222 AMDGPU_FENCE_OWNER_UNDEFINED); 2223 if (r) { 2224 DRM_ERROR("sync failed (%d).\n", r); 2225 goto error_free; 2226 } 2227 } 2228 2229 num_pages = bo->tbo.num_pages; 2230 mm_node = bo->tbo.mem.mm_node; 2231 2232 while (num_pages) { 2233 uint64_t byte_count = mm_node->size << PAGE_SHIFT; 2234 uint64_t dst_addr; 2235 2236 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); 2237 while (byte_count) { 2238 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count, 2239 max_bytes); 2240 2241 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 2242 dst_addr, cur_size_in_bytes); 2243 2244 dst_addr += cur_size_in_bytes; 2245 byte_count -= cur_size_in_bytes; 2246 } 2247 2248 num_pages -= mm_node->size; 2249 ++mm_node; 2250 } 2251 2252 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2253 WARN_ON(job->ibs[0].length_dw > num_dw); 2254 r = amdgpu_job_submit(job, &adev->mman.entity, 2255 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2256 if (r) 2257 goto error_free; 2258 2259 return 0; 2260 2261 error_free: 2262 amdgpu_job_free(job); 2263 return r; 2264 } 2265 2266 #if defined(CONFIG_DEBUG_FS) 2267 2268 static int amdgpu_mm_dump_table(struct seq_file *m, void *data) 2269 { 2270 struct drm_info_node *node = (struct drm_info_node *)m->private; 2271 unsigned ttm_pl = (uintptr_t)node->info_ent->data; 2272 struct drm_device *dev = node->minor->dev; 2273 struct amdgpu_device *adev = drm_to_adev(dev); 2274 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); 2275 struct drm_printer p = drm_seq_file_printer(m); 2276 2277 man->func->debug(man, &p); 2278 return 0; 2279 } 2280 2281 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { 2282 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, 2283 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, 2284 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, 2285 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, 2286 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, 2287 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 2288 #ifdef CONFIG_SWIOTLB 2289 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 2290 #endif 2291 }; 2292 2293 /** 2294 * amdgpu_ttm_vram_read - Linear read access to VRAM 2295 * 2296 * Accesses VRAM via MMIO for debugging purposes. 2297 */ 2298 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2299 size_t size, loff_t *pos) 2300 { 2301 struct amdgpu_device *adev = file_inode(f)->i_private; 2302 ssize_t result = 0; 2303 2304 if (size & 0x3 || *pos & 0x3) 2305 return -EINVAL; 2306 2307 if (*pos >= adev->gmc.mc_vram_size) 2308 return -ENXIO; 2309 2310 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2311 while (size) { 2312 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2313 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2314 2315 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2316 if (copy_to_user(buf, value, bytes)) 2317 return -EFAULT; 2318 2319 result += bytes; 2320 buf += bytes; 2321 *pos += bytes; 2322 size -= bytes; 2323 } 2324 2325 return result; 2326 } 2327 2328 /** 2329 * amdgpu_ttm_vram_write - Linear write access to VRAM 2330 * 2331 * Accesses VRAM via MMIO for debugging purposes. 2332 */ 2333 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2334 size_t size, loff_t *pos) 2335 { 2336 struct amdgpu_device *adev = file_inode(f)->i_private; 2337 ssize_t result = 0; 2338 int r; 2339 2340 if (size & 0x3 || *pos & 0x3) 2341 return -EINVAL; 2342 2343 if (*pos >= adev->gmc.mc_vram_size) 2344 return -ENXIO; 2345 2346 while (size) { 2347 unsigned long flags; 2348 uint32_t value; 2349 2350 if (*pos >= adev->gmc.mc_vram_size) 2351 return result; 2352 2353 r = get_user(value, (uint32_t *)buf); 2354 if (r) 2355 return r; 2356 2357 spin_lock_irqsave(&adev->mmio_idx_lock, flags); 2358 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); 2359 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); 2360 WREG32_NO_KIQ(mmMM_DATA, value); 2361 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); 2362 2363 result += 4; 2364 buf += 4; 2365 *pos += 4; 2366 size -= 4; 2367 } 2368 2369 return result; 2370 } 2371 2372 static const struct file_operations amdgpu_ttm_vram_fops = { 2373 .owner = THIS_MODULE, 2374 .read = amdgpu_ttm_vram_read, 2375 .write = amdgpu_ttm_vram_write, 2376 .llseek = default_llseek, 2377 }; 2378 2379 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2380 2381 /** 2382 * amdgpu_ttm_gtt_read - Linear read access to GTT memory 2383 */ 2384 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, 2385 size_t size, loff_t *pos) 2386 { 2387 struct amdgpu_device *adev = file_inode(f)->i_private; 2388 ssize_t result = 0; 2389 int r; 2390 2391 while (size) { 2392 loff_t p = *pos / PAGE_SIZE; 2393 unsigned off = *pos & ~PAGE_MASK; 2394 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 2395 struct page *page; 2396 void *ptr; 2397 2398 if (p >= adev->gart.num_cpu_pages) 2399 return result; 2400 2401 page = adev->gart.pages[p]; 2402 if (page) { 2403 ptr = kmap(page); 2404 ptr += off; 2405 2406 r = copy_to_user(buf, ptr, cur_size); 2407 kunmap(adev->gart.pages[p]); 2408 } else 2409 r = clear_user(buf, cur_size); 2410 2411 if (r) 2412 return -EFAULT; 2413 2414 result += cur_size; 2415 buf += cur_size; 2416 *pos += cur_size; 2417 size -= cur_size; 2418 } 2419 2420 return result; 2421 } 2422 2423 static const struct file_operations amdgpu_ttm_gtt_fops = { 2424 .owner = THIS_MODULE, 2425 .read = amdgpu_ttm_gtt_read, 2426 .llseek = default_llseek 2427 }; 2428 2429 #endif 2430 2431 /** 2432 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2433 * 2434 * This function is used to read memory that has been mapped to the 2435 * GPU and the known addresses are not physical addresses but instead 2436 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2437 */ 2438 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2439 size_t size, loff_t *pos) 2440 { 2441 struct amdgpu_device *adev = file_inode(f)->i_private; 2442 struct iommu_domain *dom; 2443 ssize_t result = 0; 2444 int r; 2445 2446 /* retrieve the IOMMU domain if any for this device */ 2447 dom = iommu_get_domain_for_dev(adev->dev); 2448 2449 while (size) { 2450 phys_addr_t addr = *pos & PAGE_MASK; 2451 loff_t off = *pos & ~PAGE_MASK; 2452 size_t bytes = PAGE_SIZE - off; 2453 unsigned long pfn; 2454 struct page *p; 2455 void *ptr; 2456 2457 bytes = bytes < size ? bytes : size; 2458 2459 /* Translate the bus address to a physical address. If 2460 * the domain is NULL it means there is no IOMMU active 2461 * and the address translation is the identity 2462 */ 2463 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2464 2465 pfn = addr >> PAGE_SHIFT; 2466 if (!pfn_valid(pfn)) 2467 return -EPERM; 2468 2469 p = pfn_to_page(pfn); 2470 if (p->mapping != adev->mman.bdev.dev_mapping) 2471 return -EPERM; 2472 2473 ptr = kmap(p); 2474 r = copy_to_user(buf, ptr + off, bytes); 2475 kunmap(p); 2476 if (r) 2477 return -EFAULT; 2478 2479 size -= bytes; 2480 *pos += bytes; 2481 result += bytes; 2482 } 2483 2484 return result; 2485 } 2486 2487 /** 2488 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2489 * 2490 * This function is used to write memory that has been mapped to the 2491 * GPU and the known addresses are not physical addresses but instead 2492 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2493 */ 2494 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2495 size_t size, loff_t *pos) 2496 { 2497 struct amdgpu_device *adev = file_inode(f)->i_private; 2498 struct iommu_domain *dom; 2499 ssize_t result = 0; 2500 int r; 2501 2502 dom = iommu_get_domain_for_dev(adev->dev); 2503 2504 while (size) { 2505 phys_addr_t addr = *pos & PAGE_MASK; 2506 loff_t off = *pos & ~PAGE_MASK; 2507 size_t bytes = PAGE_SIZE - off; 2508 unsigned long pfn; 2509 struct page *p; 2510 void *ptr; 2511 2512 bytes = bytes < size ? bytes : size; 2513 2514 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2515 2516 pfn = addr >> PAGE_SHIFT; 2517 if (!pfn_valid(pfn)) 2518 return -EPERM; 2519 2520 p = pfn_to_page(pfn); 2521 if (p->mapping != adev->mman.bdev.dev_mapping) 2522 return -EPERM; 2523 2524 ptr = kmap(p); 2525 r = copy_from_user(ptr + off, buf, bytes); 2526 kunmap(p); 2527 if (r) 2528 return -EFAULT; 2529 2530 size -= bytes; 2531 *pos += bytes; 2532 result += bytes; 2533 } 2534 2535 return result; 2536 } 2537 2538 static const struct file_operations amdgpu_ttm_iomem_fops = { 2539 .owner = THIS_MODULE, 2540 .read = amdgpu_iomem_read, 2541 .write = amdgpu_iomem_write, 2542 .llseek = default_llseek 2543 }; 2544 2545 static const struct { 2546 char *name; 2547 const struct file_operations *fops; 2548 int domain; 2549 } ttm_debugfs_entries[] = { 2550 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, 2551 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 2552 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, 2553 #endif 2554 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, 2555 }; 2556 2557 #endif 2558 2559 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2560 { 2561 #if defined(CONFIG_DEBUG_FS) 2562 unsigned count; 2563 2564 struct drm_minor *minor = adev_to_drm(adev)->primary; 2565 struct dentry *ent, *root = minor->debugfs_root; 2566 2567 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { 2568 ent = debugfs_create_file( 2569 ttm_debugfs_entries[count].name, 2570 S_IFREG | S_IRUGO, root, 2571 adev, 2572 ttm_debugfs_entries[count].fops); 2573 if (IS_ERR(ent)) 2574 return PTR_ERR(ent); 2575 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) 2576 i_size_write(ent->d_inode, adev->gmc.mc_vram_size); 2577 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) 2578 i_size_write(ent->d_inode, adev->gmc.gart_size); 2579 adev->mman.debugfs_entries[count] = ent; 2580 } 2581 2582 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); 2583 2584 #ifdef CONFIG_SWIOTLB 2585 if (!(adev->need_swiotlb && swiotlb_nr_tbl())) 2586 --count; 2587 #endif 2588 2589 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); 2590 #else 2591 return 0; 2592 #endif 2593 } 2594