1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/dma-buf.h> 42 #include <linux/sizes.h> 43 #include <linux/module.h> 44 45 #include <drm/drm_drv.h> 46 #include <drm/ttm/ttm_bo.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <drm/ttm/ttm_range_manager.h> 49 #include <drm/ttm/ttm_tt.h> 50 51 #include <drm/amdgpu_drm.h> 52 53 #include "amdgpu.h" 54 #include "amdgpu_object.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_sdma.h" 58 #include "amdgpu_ras.h" 59 #include "amdgpu_hmm.h" 60 #include "amdgpu_atomfirmware.h" 61 #include "amdgpu_res_cursor.h" 62 #include "bif/bif_4_1_d.h" 63 64 MODULE_IMPORT_NS("DMA_BUF"); 65 66 #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) 67 68 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 69 struct ttm_tt *ttm, 70 struct ttm_resource *bo_mem); 71 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 72 struct ttm_tt *ttm); 73 74 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 75 unsigned int type, 76 uint64_t size_in_page) 77 { 78 if (!size_in_page) 79 return 0; 80 81 return ttm_range_man_init(&adev->mman.bdev, type, 82 false, size_in_page); 83 } 84 85 /** 86 * amdgpu_evict_flags - Compute placement flags 87 * 88 * @bo: The buffer object to evict 89 * @placement: Possible destination(s) for evicted BO 90 * 91 * Fill in placement data when ttm_bo_evict() is called 92 */ 93 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 94 struct ttm_placement *placement) 95 { 96 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 97 struct amdgpu_bo *abo; 98 static const struct ttm_place placements = { 99 .fpfn = 0, 100 .lpfn = 0, 101 .mem_type = TTM_PL_SYSTEM, 102 .flags = 0 103 }; 104 105 /* Don't handle scatter gather BOs */ 106 if (bo->type == ttm_bo_type_sg) { 107 placement->num_placement = 0; 108 return; 109 } 110 111 /* Object isn't an AMDGPU object so ignore */ 112 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 113 placement->placement = &placements; 114 placement->num_placement = 1; 115 return; 116 } 117 118 abo = ttm_to_amdgpu_bo(bo); 119 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 120 placement->num_placement = 0; 121 return; 122 } 123 124 switch (bo->resource->mem_type) { 125 case AMDGPU_PL_GDS: 126 case AMDGPU_PL_GWS: 127 case AMDGPU_PL_OA: 128 case AMDGPU_PL_DOORBELL: 129 case AMDGPU_PL_MMIO_REMAP: 130 placement->num_placement = 0; 131 return; 132 133 case TTM_PL_VRAM: 134 if (!adev->mman.buffer_funcs_enabled) { 135 /* Move to system memory */ 136 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 137 138 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 139 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 140 amdgpu_res_cpu_visible(adev, bo->resource)) { 141 142 /* Try evicting to the CPU inaccessible part of VRAM 143 * first, but only set GTT as busy placement, so this 144 * BO will be evicted to GTT rather than causing other 145 * BOs to be evicted from VRAM 146 */ 147 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 148 AMDGPU_GEM_DOMAIN_GTT | 149 AMDGPU_GEM_DOMAIN_CPU); 150 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 151 abo->placements[0].lpfn = 0; 152 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; 153 } else { 154 /* Move to GTT memory */ 155 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 156 AMDGPU_GEM_DOMAIN_CPU); 157 } 158 break; 159 case TTM_PL_TT: 160 case AMDGPU_PL_PREEMPT: 161 default: 162 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 163 break; 164 } 165 *placement = abo->placement; 166 } 167 168 static struct dma_fence * 169 amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, 170 struct amdgpu_job *job, u32 num_dw) 171 { 172 struct amdgpu_ring *ring; 173 174 ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); 175 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 176 WARN_ON(job->ibs[0].length_dw > num_dw); 177 178 lockdep_assert_held(&entity->lock); 179 180 return amdgpu_job_submit(job); 181 } 182 183 /** 184 * amdgpu_ttm_map_buffer - Map memory into the GART windows 185 * @entity: entity to run the window setup job 186 * @bo: buffer object to map 187 * @mem: memory object to map 188 * @mm_cur: range to map 189 * @window: which GART window to use 190 * @tmz: if we should setup a TMZ enabled mapping 191 * @size: in number of bytes to map, out number of bytes mapped 192 * @addr: resulting address inside the MC address space 193 * 194 * Setup one of the GART windows to access a specific piece of memory or return 195 * the physical address for local memory. 196 */ 197 static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity, 198 struct ttm_buffer_object *bo, 199 struct ttm_resource *mem, 200 struct amdgpu_res_cursor *mm_cur, 201 unsigned int window, 202 bool tmz, uint64_t *size, uint64_t *addr) 203 { 204 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 205 unsigned int offset, num_pages, num_dw, num_bytes; 206 uint64_t src_addr, dst_addr; 207 struct amdgpu_job *job; 208 void *cpu_addr; 209 uint64_t flags; 210 int r; 211 const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); 212 213 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 214 GTT_MAX_PAGES * AMDGPU_GPU_PAGES_IN_CPU_PAGE * 8); 215 216 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT)) 217 return -EINVAL; 218 219 /* Map only what can't be accessed directly */ 220 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 221 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 222 mm_cur->start; 223 return 0; 224 } 225 226 227 /* 228 * If start begins at an offset inside the page, then adjust the size 229 * and addr accordingly 230 */ 231 offset = mm_cur->start & ~PAGE_MASK; 232 233 num_pages = PFN_UP(*size + offset); 234 num_pages = min_t(uint32_t, num_pages, GTT_MAX_PAGES); 235 236 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 237 238 *addr = amdgpu_compute_gart_address(&adev->gmc, entity, window); 239 *addr += offset; 240 241 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 242 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 243 244 r = amdgpu_job_alloc_with_ib(adev, &entity->base, 245 AMDGPU_FENCE_OWNER_UNDEFINED, 246 num_dw * 4 + num_bytes, 247 AMDGPU_IB_POOL_DELAYED, 248 AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER, 249 &job); 250 if (r) 251 return r; 252 253 src_addr = num_dw * 4; 254 src_addr += job->ibs[0].gpu_addr; 255 256 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 257 dst_addr += (entity->gart_window_offs[window] >> AMDGPU_GPU_PAGE_SHIFT) * 8; 258 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 259 dst_addr, num_bytes, 0); 260 261 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 262 if (tmz) 263 flags |= AMDGPU_PTE_TMZ; 264 265 cpu_addr = &job->ibs[0].ptr[num_dw]; 266 267 if (mem->mem_type == TTM_PL_TT) { 268 dma_addr_t *dma_addr; 269 270 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 271 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); 272 } else { 273 u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset; 274 275 amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); 276 } 277 278 dma_fence_put(amdgpu_ttm_job_submit(adev, entity, job, num_dw)); 279 return 0; 280 } 281 282 /** 283 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 284 * @adev: amdgpu device 285 * @entity: entity to run the jobs 286 * @src: buffer/address where to read from 287 * @dst: buffer/address where to write to 288 * @size: number of bytes to copy 289 * @tmz: if a secure copy should be used 290 * @resv: resv object to sync to 291 * @f: Returns the last fence if multiple jobs are submitted. 292 * 293 * The function copies @size bytes from {src->mem + src->offset} to 294 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 295 * move and different for a BO to BO copy. 296 * 297 */ 298 __attribute__((nonnull)) 299 static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 300 struct amdgpu_ttm_buffer_entity *entity, 301 const struct amdgpu_copy_mem *src, 302 const struct amdgpu_copy_mem *dst, 303 uint64_t size, bool tmz, 304 struct dma_resv *resv, 305 struct dma_fence **f) 306 { 307 struct amdgpu_res_cursor src_mm, dst_mm; 308 struct dma_fence *fence = NULL; 309 int r = 0; 310 uint32_t copy_flags = 0; 311 struct amdgpu_bo *abo_src, *abo_dst; 312 313 if (!adev->mman.buffer_funcs_enabled) { 314 dev_err(adev->dev, 315 "Trying to move memory with ring turned off.\n"); 316 return -EINVAL; 317 } 318 319 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 320 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 321 322 mutex_lock(&entity->lock); 323 while (src_mm.remaining) { 324 uint64_t from, to, cur_size, tiling_flags; 325 uint32_t num_type, data_format, max_com, write_compress_disable; 326 struct dma_fence *next; 327 328 /* Never copy more than 256MiB at once to avoid a timeout */ 329 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 330 331 /* Map src to window 0 and dst to window 1. */ 332 r = amdgpu_ttm_map_buffer(entity, src->bo, src->mem, &src_mm, 333 0, tmz, &cur_size, &from); 334 if (r) 335 goto error; 336 337 r = amdgpu_ttm_map_buffer(entity, dst->bo, dst->mem, &dst_mm, 338 1, tmz, &cur_size, &to); 339 if (r) 340 goto error; 341 342 abo_src = ttm_to_amdgpu_bo(src->bo); 343 abo_dst = ttm_to_amdgpu_bo(dst->bo); 344 if (tmz) 345 copy_flags |= AMDGPU_COPY_FLAGS_TMZ; 346 if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) && 347 (abo_src->tbo.resource->mem_type == TTM_PL_VRAM)) 348 copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED; 349 if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) && 350 (dst->mem->mem_type == TTM_PL_VRAM)) { 351 copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED; 352 amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags); 353 max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); 354 num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE); 355 data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT); 356 write_compress_disable = 357 AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE); 358 copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) | 359 AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) | 360 AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) | 361 AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE, 362 write_compress_disable)); 363 } 364 365 r = amdgpu_copy_buffer(adev, entity, from, to, cur_size, resv, 366 &next, true, copy_flags); 367 if (r) 368 goto error; 369 370 dma_fence_put(fence); 371 fence = next; 372 373 amdgpu_res_next(&src_mm, cur_size); 374 amdgpu_res_next(&dst_mm, cur_size); 375 } 376 error: 377 mutex_unlock(&entity->lock); 378 *f = fence; 379 return r; 380 } 381 382 /* 383 * amdgpu_move_blit - Copy an entire buffer to another buffer 384 * 385 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 386 * help move buffers to and from VRAM. 387 */ 388 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 389 bool evict, 390 struct ttm_resource *new_mem, 391 struct ttm_resource *old_mem) 392 { 393 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 394 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 395 struct amdgpu_ttm_buffer_entity *entity; 396 struct amdgpu_copy_mem src, dst; 397 struct dma_fence *fence = NULL; 398 int r; 399 u32 e; 400 401 src.bo = bo; 402 dst.bo = bo; 403 src.mem = old_mem; 404 dst.mem = new_mem; 405 src.offset = 0; 406 dst.offset = 0; 407 408 e = atomic_inc_return(&adev->mman.next_move_entity) % 409 adev->mman.num_move_entities; 410 entity = &adev->mman.move_entities[e]; 411 412 r = amdgpu_ttm_copy_mem_to_mem(adev, 413 entity, 414 &src, &dst, 415 new_mem->size, 416 amdgpu_bo_encrypted(abo), 417 bo->base.resv, &fence); 418 if (r) 419 goto error; 420 421 /* clear the space being freed */ 422 if (old_mem->mem_type == TTM_PL_VRAM && 423 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 424 struct dma_fence *wipe_fence = NULL; 425 r = amdgpu_ttm_clear_buffer(entity, abo, NULL, &wipe_fence, 426 false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); 427 if (r) { 428 goto error; 429 } else if (wipe_fence) { 430 amdgpu_vram_mgr_set_cleared(bo->resource); 431 dma_fence_put(fence); 432 fence = wipe_fence; 433 } 434 } 435 436 /* Always block for VM page tables before committing the new location */ 437 if (bo->type == ttm_bo_type_kernel) 438 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 439 else 440 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 441 dma_fence_put(fence); 442 return r; 443 444 error: 445 if (fence) 446 dma_fence_wait(fence, false); 447 dma_fence_put(fence); 448 return r; 449 } 450 451 /** 452 * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU 453 * @adev: amdgpu device 454 * @res: the resource to check 455 * 456 * Returns: true if the full resource is CPU visible, false otherwise. 457 */ 458 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 459 struct ttm_resource *res) 460 { 461 struct amdgpu_res_cursor cursor; 462 463 if (!res) 464 return false; 465 466 if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT || 467 res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL || 468 res->mem_type == AMDGPU_PL_MMIO_REMAP) 469 return true; 470 471 if (res->mem_type != TTM_PL_VRAM) 472 return false; 473 474 amdgpu_res_first(res, 0, res->size, &cursor); 475 while (cursor.remaining) { 476 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size) 477 return false; 478 amdgpu_res_next(&cursor, cursor.size); 479 } 480 481 return true; 482 } 483 484 /* 485 * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy 486 * 487 * Called by amdgpu_bo_move() 488 */ 489 static bool amdgpu_res_copyable(struct amdgpu_device *adev, 490 struct ttm_resource *mem) 491 { 492 if (!amdgpu_res_cpu_visible(adev, mem)) 493 return false; 494 495 /* ttm_resource_ioremap only supports contiguous memory */ 496 if (mem->mem_type == TTM_PL_VRAM && 497 !(mem->placement & TTM_PL_FLAG_CONTIGUOUS)) 498 return false; 499 500 return true; 501 } 502 503 /* 504 * amdgpu_bo_move - Move a buffer object to a new memory location 505 * 506 * Called by ttm_bo_handle_move_mem() 507 */ 508 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 509 struct ttm_operation_ctx *ctx, 510 struct ttm_resource *new_mem, 511 struct ttm_place *hop) 512 { 513 struct amdgpu_device *adev; 514 struct amdgpu_bo *abo; 515 struct ttm_resource *old_mem = bo->resource; 516 int r; 517 518 if (new_mem->mem_type == TTM_PL_TT || 519 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 520 if (old_mem && (old_mem->mem_type == TTM_PL_TT || 521 old_mem->mem_type == AMDGPU_PL_PREEMPT)) { 522 r = ttm_bo_wait_ctx(bo, ctx); 523 if (r) 524 return r; 525 526 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 527 } 528 529 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 530 if (r) 531 return r; 532 } 533 534 abo = ttm_to_amdgpu_bo(bo); 535 adev = amdgpu_ttm_adev(bo->bdev); 536 537 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 538 bo->ttm == NULL)) { 539 amdgpu_bo_move_notify(bo, evict, new_mem); 540 ttm_bo_move_null(bo, new_mem); 541 return 0; 542 } 543 if (old_mem->mem_type == TTM_PL_SYSTEM && 544 (new_mem->mem_type == TTM_PL_TT || 545 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 546 amdgpu_bo_move_notify(bo, evict, new_mem); 547 ttm_bo_move_null(bo, new_mem); 548 return 0; 549 } 550 if ((old_mem->mem_type == TTM_PL_TT || 551 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 552 new_mem->mem_type == TTM_PL_SYSTEM) { 553 r = ttm_bo_wait_ctx(bo, ctx); 554 if (r) 555 return r; 556 557 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 558 amdgpu_bo_move_notify(bo, evict, new_mem); 559 ttm_resource_free(bo, &bo->resource); 560 ttm_bo_assign_mem(bo, new_mem); 561 return 0; 562 } 563 if ((old_mem->mem_type == TTM_PL_TT || 564 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 565 (new_mem->mem_type == TTM_PL_TT || 566 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 567 amdgpu_bo_move_notify(bo, evict, new_mem); 568 ttm_resource_free(bo, &bo->resource); 569 ttm_bo_assign_mem(bo, new_mem); 570 return 0; 571 } 572 573 if (old_mem->mem_type == AMDGPU_PL_GDS || 574 old_mem->mem_type == AMDGPU_PL_GWS || 575 old_mem->mem_type == AMDGPU_PL_OA || 576 old_mem->mem_type == AMDGPU_PL_DOORBELL || 577 old_mem->mem_type == AMDGPU_PL_MMIO_REMAP || 578 new_mem->mem_type == AMDGPU_PL_GDS || 579 new_mem->mem_type == AMDGPU_PL_GWS || 580 new_mem->mem_type == AMDGPU_PL_OA || 581 new_mem->mem_type == AMDGPU_PL_DOORBELL || 582 new_mem->mem_type == AMDGPU_PL_MMIO_REMAP) { 583 /* Nothing to save here */ 584 amdgpu_bo_move_notify(bo, evict, new_mem); 585 ttm_bo_move_null(bo, new_mem); 586 return 0; 587 } 588 589 if (bo->type == ttm_bo_type_device && 590 new_mem->mem_type == TTM_PL_VRAM && 591 old_mem->mem_type != TTM_PL_VRAM) { 592 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 593 * accesses the BO after it's moved. 594 */ 595 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 596 } 597 598 if (adev->mman.buffer_funcs_enabled && 599 ((old_mem->mem_type == TTM_PL_SYSTEM && 600 new_mem->mem_type == TTM_PL_VRAM) || 601 (old_mem->mem_type == TTM_PL_VRAM && 602 new_mem->mem_type == TTM_PL_SYSTEM))) { 603 hop->fpfn = 0; 604 hop->lpfn = 0; 605 hop->mem_type = TTM_PL_TT; 606 hop->flags = TTM_PL_FLAG_TEMPORARY; 607 return -EMULTIHOP; 608 } 609 610 amdgpu_bo_move_notify(bo, evict, new_mem); 611 if (adev->mman.buffer_funcs_enabled) 612 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 613 else 614 r = -ENODEV; 615 616 if (r) { 617 /* Check that all memory is CPU accessible */ 618 if (!amdgpu_res_copyable(adev, old_mem) || 619 !amdgpu_res_copyable(adev, new_mem)) { 620 pr_err("Move buffer fallback to memcpy unavailable\n"); 621 return r; 622 } 623 624 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 625 if (r) 626 return r; 627 } 628 629 /* update statistics after the move */ 630 if (evict) 631 atomic64_inc(&adev->num_evictions); 632 atomic64_add(bo->base.size, &adev->num_bytes_moved); 633 return 0; 634 } 635 636 /* 637 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 638 * 639 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 640 */ 641 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 642 struct ttm_resource *mem) 643 { 644 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 645 646 switch (mem->mem_type) { 647 case TTM_PL_SYSTEM: 648 /* system memory */ 649 return 0; 650 case TTM_PL_TT: 651 case AMDGPU_PL_PREEMPT: 652 break; 653 case TTM_PL_VRAM: 654 mem->bus.offset = mem->start << PAGE_SHIFT; 655 656 if (adev->mman.aper_base_kaddr && 657 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 658 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 659 mem->bus.offset; 660 661 mem->bus.offset += adev->gmc.aper_base; 662 mem->bus.is_iomem = true; 663 break; 664 case AMDGPU_PL_DOORBELL: 665 mem->bus.offset = mem->start << PAGE_SHIFT; 666 mem->bus.offset += adev->doorbell.base; 667 mem->bus.is_iomem = true; 668 mem->bus.caching = ttm_uncached; 669 break; 670 case AMDGPU_PL_MMIO_REMAP: 671 mem->bus.offset = mem->start << PAGE_SHIFT; 672 mem->bus.offset += adev->rmmio_remap.bus_addr; 673 mem->bus.is_iomem = true; 674 mem->bus.caching = ttm_uncached; 675 break; 676 default: 677 return -EINVAL; 678 } 679 return 0; 680 } 681 682 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 683 unsigned long page_offset) 684 { 685 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 686 struct amdgpu_res_cursor cursor; 687 688 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 689 &cursor); 690 691 if (bo->resource->mem_type == AMDGPU_PL_DOORBELL) 692 return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT; 693 else if (bo->resource->mem_type == AMDGPU_PL_MMIO_REMAP) 694 return ((uint64_t)(adev->rmmio_remap.bus_addr + cursor.start)) >> PAGE_SHIFT; 695 696 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 697 } 698 699 /** 700 * amdgpu_ttm_domain_start - Returns GPU start address 701 * @adev: amdgpu device object 702 * @type: type of the memory 703 * 704 * Returns: 705 * GPU start address of a memory domain 706 */ 707 708 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 709 { 710 switch (type) { 711 case TTM_PL_TT: 712 return adev->gmc.gart_start; 713 case TTM_PL_VRAM: 714 return adev->gmc.vram_start; 715 } 716 717 return 0; 718 } 719 720 /* 721 * TTM backend functions. 722 */ 723 struct amdgpu_ttm_tt { 724 struct ttm_tt ttm; 725 struct drm_gem_object *gobj; 726 u64 offset; 727 uint64_t userptr; 728 struct task_struct *usertask; 729 uint32_t userflags; 730 bool bound; 731 int32_t pool_id; 732 }; 733 734 #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) 735 736 #ifdef CONFIG_DRM_AMDGPU_USERPTR 737 /* 738 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 739 * memory and start HMM tracking CPU page table update 740 * 741 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 742 * once afterwards to stop HMM tracking. Its the caller responsibility to ensure 743 * that range is a valid memory and it is freed too. 744 */ 745 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 746 struct amdgpu_hmm_range *range) 747 { 748 struct ttm_tt *ttm = bo->tbo.ttm; 749 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 750 unsigned long start = gtt->userptr; 751 struct vm_area_struct *vma; 752 struct mm_struct *mm; 753 bool readonly; 754 int r = 0; 755 756 mm = bo->notifier.mm; 757 if (unlikely(!mm)) { 758 DRM_DEBUG_DRIVER("BO is not registered?\n"); 759 return -EFAULT; 760 } 761 762 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 763 return -ESRCH; 764 765 mmap_read_lock(mm); 766 vma = vma_lookup(mm, start); 767 if (unlikely(!vma)) { 768 r = -EFAULT; 769 goto out_unlock; 770 } 771 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 772 vma->vm_file)) { 773 r = -EPERM; 774 goto out_unlock; 775 } 776 777 readonly = amdgpu_ttm_tt_is_readonly(ttm); 778 r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages, 779 readonly, NULL, range); 780 out_unlock: 781 mmap_read_unlock(mm); 782 if (r) 783 pr_debug("failed %d to get user pages 0x%lx\n", r, start); 784 785 mmput(mm); 786 787 return r; 788 } 789 790 #endif 791 792 /* 793 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 794 * 795 * Called by amdgpu_cs_list_validate(). This creates the page list 796 * that backs user memory and will ultimately be mapped into the device 797 * address space. 798 */ 799 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range) 800 { 801 unsigned long i; 802 803 for (i = 0; i < ttm->num_pages; ++i) 804 ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; 805 } 806 807 /* 808 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 809 * 810 * Called by amdgpu_ttm_backend_bind() 811 **/ 812 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 813 struct ttm_tt *ttm) 814 { 815 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 816 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 817 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 818 enum dma_data_direction direction = write ? 819 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 820 int r; 821 822 /* Allocate an SG array and squash pages into it */ 823 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 824 (u64)ttm->num_pages << PAGE_SHIFT, 825 GFP_KERNEL); 826 if (r) 827 goto release_sg; 828 829 /* Map SG to device */ 830 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 831 if (r) 832 goto release_sg_table; 833 834 /* convert SG to linear array of pages and dma addresses */ 835 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 836 ttm->num_pages); 837 838 return 0; 839 840 release_sg_table: 841 sg_free_table(ttm->sg); 842 release_sg: 843 kfree(ttm->sg); 844 ttm->sg = NULL; 845 return r; 846 } 847 848 /* 849 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 850 */ 851 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 852 struct ttm_tt *ttm) 853 { 854 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 855 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 856 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 857 enum dma_data_direction direction = write ? 858 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 859 860 /* double check that we don't free the table twice */ 861 if (!ttm->sg || !ttm->sg->sgl) 862 return; 863 864 /* unmap the pages mapped to the device */ 865 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 866 sg_free_table(ttm->sg); 867 } 868 869 /* 870 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ... 871 * MQDn+CtrlStackn where n is the number of XCCs per partition. 872 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD 873 * and uses memory type default, UC. The rest of pages_per_xcc are 874 * Ctrl stack and modify their memory type to NC. 875 */ 876 static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, 877 struct ttm_tt *ttm, uint64_t flags) 878 { 879 struct amdgpu_ttm_tt *gtt = (void *)ttm; 880 uint64_t total_pages = ttm->num_pages; 881 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); 882 uint64_t page_idx, pages_per_xcc; 883 int i; 884 885 pages_per_xcc = total_pages; 886 do_div(pages_per_xcc, num_xcc); 887 888 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { 889 amdgpu_gart_map_gfx9_mqd(adev, 890 gtt->offset + (page_idx << PAGE_SHIFT), 891 pages_per_xcc, >t->ttm.dma_address[page_idx], 892 flags); 893 } 894 } 895 896 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 897 struct ttm_buffer_object *tbo, 898 uint64_t flags) 899 { 900 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 901 struct ttm_tt *ttm = tbo->ttm; 902 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 903 904 if (amdgpu_bo_encrypted(abo)) 905 flags |= AMDGPU_PTE_TMZ; 906 907 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 908 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags); 909 } else { 910 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 911 gtt->ttm.dma_address, flags); 912 } 913 gtt->bound = true; 914 } 915 916 /* 917 * amdgpu_ttm_backend_bind - Bind GTT memory 918 * 919 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 920 * This handles binding GTT memory to the device address space. 921 */ 922 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 923 struct ttm_tt *ttm, 924 struct ttm_resource *bo_mem) 925 { 926 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 927 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 928 uint64_t flags; 929 int r; 930 931 if (!bo_mem) 932 return -EINVAL; 933 934 if (gtt->bound) 935 return 0; 936 937 if (gtt->userptr) { 938 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 939 if (r) { 940 dev_err(adev->dev, "failed to pin userptr\n"); 941 return r; 942 } 943 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { 944 if (!ttm->sg) { 945 struct dma_buf_attachment *attach; 946 struct sg_table *sgt; 947 948 attach = gtt->gobj->import_attach; 949 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 950 if (IS_ERR(sgt)) 951 return PTR_ERR(sgt); 952 953 ttm->sg = sgt; 954 } 955 956 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 957 ttm->num_pages); 958 } 959 960 if (!ttm->num_pages) { 961 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 962 ttm->num_pages, bo_mem, ttm); 963 } 964 965 if (bo_mem->mem_type != TTM_PL_TT || 966 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 967 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 968 return 0; 969 } 970 971 /* compute PTE flags relevant to this BO memory */ 972 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 973 974 /* bind pages into GART page tables */ 975 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 976 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 977 gtt->ttm.dma_address, flags); 978 gtt->bound = true; 979 return 0; 980 } 981 982 /* 983 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 984 * through AGP or GART aperture. 985 * 986 * If bo is accessible through AGP aperture, then use AGP aperture 987 * to access bo; otherwise allocate logical space in GART aperture 988 * and map bo to GART aperture. 989 */ 990 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 991 { 992 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 993 struct ttm_operation_ctx ctx = { false, false }; 994 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 995 struct ttm_placement placement; 996 struct ttm_place placements; 997 struct ttm_resource *tmp; 998 uint64_t addr, flags; 999 int r; 1000 1001 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 1002 return 0; 1003 1004 addr = amdgpu_gmc_agp_addr(bo); 1005 if (addr != AMDGPU_BO_INVALID_OFFSET) 1006 return 0; 1007 1008 /* allocate GART space */ 1009 placement.num_placement = 1; 1010 placement.placement = &placements; 1011 placements.fpfn = 0; 1012 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1013 placements.mem_type = TTM_PL_TT; 1014 placements.flags = bo->resource->placement; 1015 1016 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1017 if (unlikely(r)) 1018 return r; 1019 1020 /* compute PTE flags for this buffer object */ 1021 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 1022 1023 /* Bind pages */ 1024 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 1025 amdgpu_ttm_gart_bind(adev, bo, flags); 1026 amdgpu_gart_invalidate_tlb(adev); 1027 ttm_resource_free(bo, &bo->resource); 1028 ttm_bo_assign_mem(bo, tmp); 1029 1030 return 0; 1031 } 1032 1033 /* 1034 * amdgpu_ttm_recover_gart - Rebind GTT pages 1035 * 1036 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1037 * rebind GTT pages during a GPU reset. 1038 */ 1039 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1040 { 1041 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1042 uint64_t flags; 1043 1044 if (!tbo->ttm) 1045 return; 1046 1047 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1048 amdgpu_ttm_gart_bind(adev, tbo, flags); 1049 } 1050 1051 /* 1052 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1053 * 1054 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1055 * ttm_tt_destroy(). 1056 */ 1057 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1058 struct ttm_tt *ttm) 1059 { 1060 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1061 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1062 1063 /* if the pages have userptr pinning then clear that first */ 1064 if (gtt->userptr) { 1065 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1066 } else if (ttm->sg && drm_gem_is_imported(gtt->gobj)) { 1067 struct dma_buf_attachment *attach; 1068 1069 attach = gtt->gobj->import_attach; 1070 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1071 ttm->sg = NULL; 1072 } 1073 1074 if (!gtt->bound) 1075 return; 1076 1077 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1078 return; 1079 1080 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1081 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1082 gtt->bound = false; 1083 } 1084 1085 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1086 struct ttm_tt *ttm) 1087 { 1088 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1089 1090 if (gtt->usertask) 1091 put_task_struct(gtt->usertask); 1092 1093 ttm_tt_fini(>t->ttm); 1094 kfree(gtt); 1095 } 1096 1097 /** 1098 * amdgpu_ttm_mmio_remap_alloc_sgt - build an sg_table for MMIO_REMAP I/O aperture 1099 * @adev: amdgpu device providing the remap BAR base (adev->rmmio_remap.bus_addr) 1100 * @res: TTM resource of the BO to export; expected to live in AMDGPU_PL_MMIO_REMAP 1101 * @dev: importing device to map for (typically @attach->dev in dma-buf paths) 1102 * @dir: DMA data direction for the importer (passed to dma_map_resource()) 1103 * @sgt: output; on success, set to a newly allocated sg_table describing the I/O span 1104 * 1105 * The HDP flush page (AMDGPU_PL_MMIO_REMAP) is a fixed hardware I/O window in a PCI 1106 * BAR—there are no struct pages to back it. Importers still need a DMA address list, 1107 * so we synthesize a minimal sg_table and populate it from dma_map_resource(), not 1108 * from pages. Using the common amdgpu_res_cursor walker keeps the offset/size math 1109 * consistent with other TTM/manager users. 1110 * 1111 * - @res is assumed to be a small, contiguous I/O region (typically a single 4 KiB 1112 * page) in AMDGPU_PL_MMIO_REMAP. Callers should validate placement before calling. 1113 * - The sg entry is created with sg_set_page(sg, NULL, …) to reflect I/O space. 1114 * - The mapping uses DMA_ATTR_SKIP_CPU_SYNC because this is MMIO, not cacheable RAM. 1115 * - Peer reachability / p2pdma policy checks must be done by the caller. 1116 * 1117 * Return: 1118 * * 0 on success, with *@sgt set to a valid table that must be freed via 1119 * amdgpu_ttm_mmio_remap_free_sgt(). 1120 * * -ENOMEM if allocation of the sg_table fails. 1121 * * -EIO if dma_map_resource() fails. 1122 * 1123 */ 1124 int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev, 1125 struct ttm_resource *res, 1126 struct device *dev, 1127 enum dma_data_direction dir, 1128 struct sg_table **sgt) 1129 { 1130 struct amdgpu_res_cursor cur; 1131 dma_addr_t dma; 1132 resource_size_t phys; 1133 struct scatterlist *sg; 1134 int r; 1135 1136 /* Walk the resource once; MMIO_REMAP is expected to be contiguous+small. */ 1137 amdgpu_res_first(res, 0, res->size, &cur); 1138 1139 /* Translate byte offset in the remap window into a host physical BAR address. */ 1140 phys = adev->rmmio_remap.bus_addr + cur.start; 1141 1142 /* Build a single-entry sg_table mapped as I/O (no struct page backing). */ 1143 *sgt = kzalloc_obj(**sgt); 1144 if (!*sgt) 1145 return -ENOMEM; 1146 r = sg_alloc_table(*sgt, 1, GFP_KERNEL); 1147 if (r) { 1148 kfree(*sgt); 1149 return r; 1150 } 1151 sg = (*sgt)->sgl; 1152 sg_set_page(sg, NULL, cur.size, 0); /* WHY: I/O space → no pages */ 1153 1154 dma = dma_map_resource(dev, phys, cur.size, dir, DMA_ATTR_SKIP_CPU_SYNC); 1155 if (dma_mapping_error(dev, dma)) { 1156 sg_free_table(*sgt); 1157 kfree(*sgt); 1158 return -EIO; 1159 } 1160 sg_dma_address(sg) = dma; 1161 sg_dma_len(sg) = cur.size; 1162 return 0; 1163 } 1164 1165 void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev, 1166 enum dma_data_direction dir, 1167 struct sg_table *sgt) 1168 { 1169 struct scatterlist *sg = sgt->sgl; 1170 1171 dma_unmap_resource(dev, sg_dma_address(sg), sg_dma_len(sg), 1172 dir, DMA_ATTR_SKIP_CPU_SYNC); 1173 sg_free_table(sgt); 1174 kfree(sgt); 1175 } 1176 1177 /** 1178 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1179 * 1180 * @bo: The buffer object to create a GTT ttm_tt object around 1181 * @page_flags: Page flags to be added to the ttm_tt object 1182 * 1183 * Called by ttm_tt_create(). 1184 */ 1185 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1186 uint32_t page_flags) 1187 { 1188 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1189 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1190 struct amdgpu_ttm_tt *gtt; 1191 enum ttm_caching caching; 1192 1193 gtt = kzalloc_obj(struct amdgpu_ttm_tt); 1194 if (!gtt) 1195 return NULL; 1196 1197 gtt->gobj = &bo->base; 1198 if (adev->gmc.mem_partitions && abo->xcp_id >= 0) 1199 gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 1200 else 1201 gtt->pool_id = abo->xcp_id; 1202 1203 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1204 caching = ttm_write_combined; 1205 else 1206 caching = ttm_cached; 1207 1208 /* allocate space for the uninitialized page entries */ 1209 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1210 kfree(gtt); 1211 return NULL; 1212 } 1213 return >t->ttm; 1214 } 1215 1216 /* 1217 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1218 * 1219 * Map the pages of a ttm_tt object to an address space visible 1220 * to the underlying device. 1221 */ 1222 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1223 struct ttm_tt *ttm, 1224 struct ttm_operation_ctx *ctx) 1225 { 1226 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1227 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1228 struct ttm_pool *pool; 1229 pgoff_t i; 1230 int ret; 1231 1232 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1233 if (gtt->userptr) { 1234 ttm->sg = kzalloc_obj(struct sg_table); 1235 if (!ttm->sg) 1236 return -ENOMEM; 1237 return 0; 1238 } 1239 1240 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1241 return 0; 1242 1243 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1244 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1245 else 1246 pool = &adev->mman.bdev.pool; 1247 ret = ttm_pool_alloc(pool, ttm, ctx); 1248 if (ret) 1249 return ret; 1250 1251 for (i = 0; i < ttm->num_pages; ++i) 1252 ttm->pages[i]->mapping = bdev->dev_mapping; 1253 1254 return 0; 1255 } 1256 1257 /* 1258 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1259 * 1260 * Unmaps pages of a ttm_tt object from the device address space and 1261 * unpopulates the page array backing it. 1262 */ 1263 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1264 struct ttm_tt *ttm) 1265 { 1266 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1267 struct amdgpu_device *adev; 1268 struct ttm_pool *pool; 1269 pgoff_t i; 1270 1271 amdgpu_ttm_backend_unbind(bdev, ttm); 1272 1273 if (gtt->userptr) { 1274 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1275 kfree(ttm->sg); 1276 ttm->sg = NULL; 1277 return; 1278 } 1279 1280 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) 1281 return; 1282 1283 for (i = 0; i < ttm->num_pages; ++i) 1284 ttm->pages[i]->mapping = NULL; 1285 1286 adev = amdgpu_ttm_adev(bdev); 1287 1288 if (adev->mman.ttm_pools && gtt->pool_id >= 0) 1289 pool = &adev->mman.ttm_pools[gtt->pool_id]; 1290 else 1291 pool = &adev->mman.bdev.pool; 1292 1293 return ttm_pool_free(pool, ttm); 1294 } 1295 1296 /** 1297 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current 1298 * task 1299 * 1300 * @tbo: The ttm_buffer_object that contains the userptr 1301 * @user_addr: The returned value 1302 */ 1303 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 1304 uint64_t *user_addr) 1305 { 1306 struct amdgpu_ttm_tt *gtt; 1307 1308 if (!tbo->ttm) 1309 return -EINVAL; 1310 1311 gtt = (void *)tbo->ttm; 1312 *user_addr = gtt->userptr; 1313 return 0; 1314 } 1315 1316 /** 1317 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1318 * task 1319 * 1320 * @bo: The ttm_buffer_object to bind this userptr to 1321 * @addr: The address in the current tasks VM space to use 1322 * @flags: Requirements of userptr object. 1323 * 1324 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to 1325 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to 1326 * initialize GPU VM for a KFD process. 1327 */ 1328 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1329 uint64_t addr, uint32_t flags) 1330 { 1331 struct amdgpu_ttm_tt *gtt; 1332 1333 if (!bo->ttm) { 1334 /* TODO: We want a separate TTM object type for userptrs */ 1335 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1336 if (bo->ttm == NULL) 1337 return -ENOMEM; 1338 } 1339 1340 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */ 1341 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 1342 1343 gtt = ttm_to_amdgpu_ttm_tt(bo->ttm); 1344 gtt->userptr = addr; 1345 gtt->userflags = flags; 1346 1347 if (gtt->usertask) 1348 put_task_struct(gtt->usertask); 1349 gtt->usertask = current->group_leader; 1350 get_task_struct(gtt->usertask); 1351 1352 return 0; 1353 } 1354 1355 /* 1356 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1357 */ 1358 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1359 { 1360 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1361 1362 if (gtt == NULL) 1363 return NULL; 1364 1365 if (gtt->usertask == NULL) 1366 return NULL; 1367 1368 return gtt->usertask->mm; 1369 } 1370 1371 /* 1372 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1373 * address range for the current task. 1374 * 1375 */ 1376 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1377 unsigned long end, unsigned long *userptr) 1378 { 1379 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1380 unsigned long size; 1381 1382 if (gtt == NULL || !gtt->userptr) 1383 return false; 1384 1385 /* Return false if no part of the ttm_tt object lies within 1386 * the range 1387 */ 1388 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1389 if (gtt->userptr > end || gtt->userptr + size <= start) 1390 return false; 1391 1392 if (userptr) 1393 *userptr = gtt->userptr; 1394 return true; 1395 } 1396 1397 /* 1398 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1399 */ 1400 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1401 { 1402 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1403 1404 if (gtt == NULL || !gtt->userptr) 1405 return false; 1406 1407 return true; 1408 } 1409 1410 /* 1411 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1412 */ 1413 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1414 { 1415 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); 1416 1417 if (gtt == NULL) 1418 return false; 1419 1420 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1421 } 1422 1423 /** 1424 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1425 * 1426 * @ttm: The ttm_tt object to compute the flags for 1427 * @mem: The memory registry backing this ttm_tt object 1428 * 1429 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1430 */ 1431 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1432 { 1433 uint64_t flags = 0; 1434 1435 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1436 flags |= AMDGPU_PTE_VALID; 1437 1438 if (mem && (mem->mem_type == TTM_PL_TT || 1439 mem->mem_type == AMDGPU_PL_DOORBELL || 1440 mem->mem_type == AMDGPU_PL_PREEMPT || 1441 mem->mem_type == AMDGPU_PL_MMIO_REMAP)) { 1442 flags |= AMDGPU_PTE_SYSTEM; 1443 1444 if (ttm && ttm->caching == ttm_cached) 1445 flags |= AMDGPU_PTE_SNOOPED; 1446 } 1447 1448 if (mem && mem->mem_type == TTM_PL_VRAM && 1449 mem->bus.caching == ttm_cached) 1450 flags |= AMDGPU_PTE_SNOOPED; 1451 1452 return flags; 1453 } 1454 1455 /** 1456 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1457 * 1458 * @adev: amdgpu_device pointer 1459 * @ttm: The ttm_tt object to compute the flags for 1460 * @mem: The memory registry backing this ttm_tt object 1461 * 1462 * Figure out the flags to use for a VM PTE (Page Table Entry). 1463 */ 1464 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1465 struct ttm_resource *mem) 1466 { 1467 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1468 1469 flags |= adev->gart.gart_pte_flags; 1470 flags |= AMDGPU_PTE_READABLE; 1471 1472 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1473 flags |= AMDGPU_PTE_WRITEABLE; 1474 1475 return flags; 1476 } 1477 1478 /* 1479 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1480 * object. 1481 * 1482 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1483 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1484 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1485 * used to clean out a memory space. 1486 */ 1487 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1488 const struct ttm_place *place) 1489 { 1490 struct dma_resv_iter resv_cursor; 1491 struct dma_fence *f; 1492 1493 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1494 return ttm_bo_eviction_valuable(bo, place); 1495 1496 /* Swapout? */ 1497 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1498 return true; 1499 1500 if (bo->type == ttm_bo_type_kernel && 1501 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1502 return false; 1503 1504 /* If bo is a KFD BO, check if the bo belongs to the current process. 1505 * If true, then return false as any KFD process needs all its BOs to 1506 * be resident to run successfully 1507 */ 1508 dma_resv_for_each_fence(&resv_cursor, bo->base.resv, 1509 DMA_RESV_USAGE_BOOKKEEP, f) { 1510 if (amdkfd_fence_check_mm(f, current->mm) && 1511 !(place->flags & TTM_PL_FLAG_CONTIGUOUS)) 1512 return false; 1513 } 1514 1515 /* Preemptible BOs don't own system resources managed by the 1516 * driver (pages, VRAM, GART space). They point to resources 1517 * owned by someone else (e.g. pageable memory in user mode 1518 * or a DMABuf). They are used in a preemptible context so we 1519 * can guarantee no deadlocks and good QoS in case of MMU 1520 * notifiers or DMABuf move notifiers from the resource owner. 1521 */ 1522 if (bo->resource->mem_type == AMDGPU_PL_PREEMPT) 1523 return false; 1524 1525 if (bo->resource->mem_type == TTM_PL_TT && 1526 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1527 return false; 1528 1529 return ttm_bo_eviction_valuable(bo, place); 1530 } 1531 1532 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1533 void *buf, size_t size, bool write) 1534 { 1535 while (size) { 1536 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1537 uint64_t bytes = 4 - (pos & 0x3); 1538 uint32_t shift = (pos & 0x3) * 8; 1539 uint32_t mask = 0xffffffff << shift; 1540 uint32_t value = 0; 1541 1542 if (size < bytes) { 1543 mask &= 0xffffffff >> (bytes - size) * 8; 1544 bytes = size; 1545 } 1546 1547 if (mask != 0xffffffff) { 1548 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1549 if (write) { 1550 value &= ~mask; 1551 value |= (*(uint32_t *)buf << shift) & mask; 1552 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1553 } else { 1554 value = (value & mask) >> shift; 1555 memcpy(buf, &value, bytes); 1556 } 1557 } else { 1558 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1559 } 1560 1561 pos += bytes; 1562 buf += bytes; 1563 size -= bytes; 1564 } 1565 } 1566 1567 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, 1568 unsigned long offset, void *buf, 1569 int len, int write) 1570 { 1571 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1572 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1573 struct amdgpu_res_cursor src_mm; 1574 struct amdgpu_job *job; 1575 struct dma_fence *fence; 1576 uint64_t src_addr, dst_addr; 1577 unsigned int num_dw; 1578 int r, idx; 1579 1580 if (len != PAGE_SIZE) 1581 return -EINVAL; 1582 1583 if (!adev->mman.sdma_access_ptr) 1584 return -EACCES; 1585 1586 if (!adev->mman.buffer_funcs_enabled || !drm_dev_enter(adev_to_drm(adev), &idx)) 1587 return -ENODEV; 1588 1589 if (write) 1590 memcpy(adev->mman.sdma_access_ptr, buf, len); 1591 1592 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 1593 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, 1594 AMDGPU_FENCE_OWNER_UNDEFINED, 1595 num_dw * 4, AMDGPU_IB_POOL_DELAYED, 1596 AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA, 1597 &job); 1598 if (r) 1599 goto out; 1600 1601 mutex_lock(&adev->mman.default_entity.lock); 1602 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); 1603 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + 1604 src_mm.start; 1605 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo); 1606 if (write) 1607 swap(src_addr, dst_addr); 1608 1609 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, 1610 PAGE_SIZE, 0); 1611 1612 fence = amdgpu_ttm_job_submit(adev, &adev->mman.default_entity, job, num_dw); 1613 mutex_unlock(&adev->mman.default_entity.lock); 1614 1615 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) 1616 r = -ETIMEDOUT; 1617 dma_fence_put(fence); 1618 1619 if (!(r || write)) 1620 memcpy(buf, adev->mman.sdma_access_ptr, len); 1621 out: 1622 drm_dev_exit(idx); 1623 return r; 1624 } 1625 1626 /** 1627 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1628 * 1629 * @bo: The buffer object to read/write 1630 * @offset: Offset into buffer object 1631 * @buf: Secondary buffer to write/read from 1632 * @len: Length in bytes of access 1633 * @write: true if writing 1634 * 1635 * This is used to access VRAM that backs a buffer object via MMIO 1636 * access for debugging purposes. 1637 */ 1638 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1639 unsigned long offset, void *buf, int len, 1640 int write) 1641 { 1642 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1643 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1644 struct amdgpu_res_cursor cursor; 1645 int ret = 0; 1646 1647 if (bo->resource->mem_type != TTM_PL_VRAM) 1648 return -EIO; 1649 1650 if (amdgpu_device_has_timeouts_enabled(adev) && 1651 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write)) 1652 return len; 1653 1654 amdgpu_res_first(bo->resource, offset, len, &cursor); 1655 while (cursor.remaining) { 1656 size_t count, size = cursor.size; 1657 loff_t pos = cursor.start; 1658 1659 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1660 size -= count; 1661 if (size) { 1662 /* using MM to access rest vram and handle un-aligned address */ 1663 pos += count; 1664 buf += count; 1665 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1666 } 1667 1668 ret += cursor.size; 1669 buf += cursor.size; 1670 amdgpu_res_next(&cursor, cursor.size); 1671 } 1672 1673 return ret; 1674 } 1675 1676 static void 1677 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1678 { 1679 amdgpu_bo_move_notify(bo, false, NULL); 1680 } 1681 1682 static struct ttm_device_funcs amdgpu_bo_driver = { 1683 .ttm_tt_create = &amdgpu_ttm_tt_create, 1684 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1685 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1686 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1687 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1688 .evict_flags = &amdgpu_evict_flags, 1689 .move = &amdgpu_bo_move, 1690 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1691 .release_notify = &amdgpu_bo_release_notify, 1692 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1693 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1694 .access_memory = &amdgpu_ttm_access_memory, 1695 }; 1696 1697 void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev, 1698 enum amdgpu_resv_region_id id, 1699 uint64_t offset, uint64_t size, 1700 bool needs_cpu_map) 1701 { 1702 struct amdgpu_vram_resv *resv; 1703 1704 if (id >= AMDGPU_RESV_MAX) 1705 return; 1706 1707 resv = &adev->mman.resv_region[id]; 1708 resv->offset = offset; 1709 resv->size = size; 1710 resv->needs_cpu_map = needs_cpu_map; 1711 } 1712 1713 static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev) 1714 { 1715 uint32_t reserve_size = 0; 1716 1717 if (!adev->discovery.reserve_tmr) 1718 return; 1719 1720 /* 1721 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1722 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1723 * 1724 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1725 * discovery data and G6 memory training data respectively 1726 */ 1727 if (adev->bios) 1728 reserve_size = 1729 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1730 1731 if (!adev->bios && 1732 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1733 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1734 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) 1735 reserve_size = max(reserve_size, (uint32_t)280 << 20); 1736 else if (!adev->bios && 1737 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { 1738 reserve_size = max(reserve_size, (uint32_t)150 << 20); 1739 } else if (!reserve_size) 1740 reserve_size = DISCOVERY_TMR_OFFSET; 1741 1742 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1743 adev->gmc.real_vram_size - reserve_size, 1744 reserve_size, false); 1745 } 1746 1747 static void amdgpu_ttm_init_mem_train_resv_region(struct amdgpu_device *adev) 1748 { 1749 uint64_t reserve_size; 1750 uint64_t offset; 1751 1752 if (!adev->discovery.reserve_tmr) 1753 return; 1754 1755 if (!adev->bios || amdgpu_sriov_vf(adev)) 1756 return; 1757 1758 if (!amdgpu_atomfirmware_mem_training_supported(adev)) 1759 return; 1760 1761 reserve_size = adev->mman.resv_region[AMDGPU_RESV_FW].size; 1762 offset = ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1763 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_MEM_TRAIN, 1764 offset, 1765 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES, 1766 false); 1767 } 1768 1769 static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev) 1770 { 1771 uint64_t vram_size = adev->gmc.visible_vram_size; 1772 1773 /* Initialize memory reservations as required for VGA. 1774 * This is used for VGA emulation and pre-OS scanout buffers to 1775 * avoid display artifacts while transitioning between pre-OS 1776 * and driver. 1777 */ 1778 amdgpu_gmc_init_vga_resv_regions(adev); 1779 amdgpu_ttm_init_fw_resv_region(adev); 1780 amdgpu_ttm_init_mem_train_resv_region(adev); 1781 1782 if (adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size > vram_size) 1783 adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size = 0; 1784 1785 if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size > vram_size) 1786 adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0; 1787 } 1788 1789 int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, 1790 enum amdgpu_resv_region_id id) 1791 { 1792 struct amdgpu_vram_resv *resv; 1793 int ret; 1794 1795 if (id >= AMDGPU_RESV_MAX) 1796 return -EINVAL; 1797 1798 resv = &adev->mman.resv_region[id]; 1799 if (!resv->size) 1800 return 0; 1801 1802 ret = amdgpu_bo_create_kernel_at(adev, resv->offset, resv->size, 1803 &resv->bo, 1804 resv->needs_cpu_map ? &resv->cpu_ptr : NULL); 1805 if (ret) { 1806 dev_err(adev->dev, 1807 "reserve vram failed: id=%d offset=0x%llx size=0x%llx ret=%d\n", 1808 id, resv->offset, resv->size, ret); 1809 memset(resv, 0, sizeof(*resv)); 1810 } 1811 1812 return ret; 1813 } 1814 1815 void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, 1816 enum amdgpu_resv_region_id id) 1817 { 1818 struct amdgpu_vram_resv *resv; 1819 1820 if (id >= AMDGPU_RESV_MAX) 1821 return; 1822 1823 resv = &adev->mman.resv_region[id]; 1824 if (!resv->bo) 1825 return; 1826 1827 amdgpu_bo_free_kernel(&resv->bo, NULL, 1828 resv->needs_cpu_map ? &resv->cpu_ptr : NULL); 1829 memset(resv, 0, sizeof(*resv)); 1830 } 1831 1832 /* 1833 * Reserve all regions with non-zero size. Regions whose info is not 1834 * yet available (e.g., fw extended region) may still be reserved 1835 * during runtime. 1836 */ 1837 static int amdgpu_ttm_alloc_vram_resv_regions(struct amdgpu_device *adev) 1838 { 1839 int i, r; 1840 1841 for (i = 0; i < AMDGPU_RESV_MAX; i++) { 1842 r = amdgpu_ttm_mark_vram_reserved(adev, i); 1843 if (r) 1844 return r; 1845 } 1846 1847 return 0; 1848 } 1849 1850 /* 1851 * Memoy training reservation functions 1852 */ 1853 1854 /** 1855 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1856 * 1857 * @adev: amdgpu_device pointer 1858 * 1859 * free memory training reserved vram if it has been reserved. 1860 */ 1861 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1862 { 1863 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1864 1865 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1866 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_MEM_TRAIN); 1867 1868 return 0; 1869 } 1870 1871 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1872 { 1873 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1874 struct amdgpu_vram_resv *resv = 1875 &adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN]; 1876 1877 memset(ctx, 0, sizeof(*ctx)); 1878 1879 ctx->c2p_train_data_offset = resv->offset; 1880 ctx->p2c_train_data_offset = 1881 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1882 ctx->train_data_size = resv->size; 1883 1884 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1885 ctx->train_data_size, 1886 ctx->p2c_train_data_offset, 1887 ctx->c2p_train_data_offset); 1888 } 1889 1890 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) 1891 { 1892 int i; 1893 1894 if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions) 1895 return 0; 1896 1897 adev->mman.ttm_pools = kzalloc_objs(*adev->mman.ttm_pools, 1898 adev->gmc.num_mem_partitions); 1899 if (!adev->mman.ttm_pools) 1900 return -ENOMEM; 1901 1902 for (i = 0; i < adev->gmc.num_mem_partitions; i++) { 1903 ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev, 1904 adev->gmc.mem_partitions[i].numa.node, 1905 TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M))); 1906 } 1907 return 0; 1908 } 1909 1910 static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) 1911 { 1912 int i; 1913 1914 if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools) 1915 return; 1916 1917 for (i = 0; i < adev->gmc.num_mem_partitions; i++) 1918 ttm_pool_fini(&adev->mman.ttm_pools[i]); 1919 1920 kfree(adev->mman.ttm_pools); 1921 adev->mman.ttm_pools = NULL; 1922 } 1923 1924 /** 1925 * amdgpu_ttm_alloc_mmio_remap_bo - Allocate the singleton MMIO_REMAP BO 1926 * @adev: amdgpu device 1927 * 1928 * Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the 1929 * hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host 1930 * PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular 1931 * GEM object (amdgpu_bo_create). 1932 * 1933 * Return: 1934 * * 0 on success or intentional skip (feature not present/unsupported) 1935 * * negative errno on allocation failure 1936 */ 1937 static int amdgpu_ttm_alloc_mmio_remap_bo(struct amdgpu_device *adev) 1938 { 1939 struct ttm_operation_ctx ctx = { false, false }; 1940 struct ttm_placement placement; 1941 struct ttm_buffer_object *tbo; 1942 struct ttm_place placements; 1943 struct amdgpu_bo_param bp; 1944 struct ttm_resource *tmp; 1945 int r; 1946 1947 /* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */ 1948 if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE) 1949 return 0; 1950 1951 /* 1952 * Allocate a BO first and then move it to AMDGPU_PL_MMIO_REMAP. 1953 * The initial TTM resource assigned by amdgpu_bo_create() is 1954 * replaced below with a fixed MMIO_REMAP placement. 1955 */ 1956 memset(&bp, 0, sizeof(bp)); 1957 bp.type = ttm_bo_type_device; 1958 bp.size = AMDGPU_GPU_PAGE_SIZE; 1959 bp.byte_align = AMDGPU_GPU_PAGE_SIZE; 1960 bp.domain = 0; 1961 bp.flags = 0; 1962 bp.resv = NULL; 1963 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 1964 r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo); 1965 if (r) 1966 return r; 1967 1968 r = amdgpu_bo_reserve(adev->rmmio_remap.bo, true); 1969 if (r) 1970 goto err_unref; 1971 1972 tbo = &adev->rmmio_remap.bo->tbo; 1973 1974 /* 1975 * MMIO_REMAP is a fixed I/O placement (AMDGPU_PL_MMIO_REMAP). 1976 */ 1977 placement.num_placement = 1; 1978 placement.placement = &placements; 1979 placements.fpfn = 0; 1980 placements.lpfn = 0; 1981 placements.mem_type = AMDGPU_PL_MMIO_REMAP; 1982 placements.flags = 0; 1983 /* Force the BO into the fixed MMIO_REMAP placement */ 1984 r = ttm_bo_mem_space(tbo, &placement, &tmp, &ctx); 1985 if (unlikely(r)) 1986 goto err_unlock; 1987 1988 ttm_resource_free(tbo, &tbo->resource); 1989 ttm_bo_assign_mem(tbo, tmp); 1990 ttm_bo_pin(tbo); 1991 1992 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 1993 return 0; 1994 1995 err_unlock: 1996 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 1997 1998 err_unref: 1999 amdgpu_bo_unref(&adev->rmmio_remap.bo); 2000 adev->rmmio_remap.bo = NULL; 2001 return r; 2002 } 2003 2004 /** 2005 * amdgpu_ttm_free_mmio_remap_bo - Free the singleton MMIO_REMAP BO 2006 * @adev: amdgpu device 2007 * 2008 * Frees the kernel-owned MMIO_REMAP BO if it was allocated by 2009 * amdgpu_ttm_mmio_remap_bo_init(). 2010 */ 2011 static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) 2012 { 2013 if (!adev->rmmio_remap.bo) 2014 return; 2015 2016 if (!amdgpu_bo_reserve(adev->rmmio_remap.bo, true)) { 2017 ttm_bo_unpin(&adev->rmmio_remap.bo->tbo); 2018 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 2019 } 2020 2021 /* 2022 * At this point we rely on normal DRM teardown ordering: 2023 * no new user ioctls can access the global MMIO_REMAP BO 2024 * once TTM teardown begins. 2025 */ 2026 amdgpu_bo_unref(&adev->rmmio_remap.bo); 2027 adev->rmmio_remap.bo = NULL; 2028 } 2029 2030 static int amdgpu_ttm_buffer_entity_init(struct amdgpu_gtt_mgr *mgr, 2031 struct amdgpu_ttm_buffer_entity *entity, 2032 enum drm_sched_priority prio, 2033 struct drm_gpu_scheduler **scheds, 2034 int num_schedulers, 2035 u32 num_gart_windows) 2036 { 2037 int i, r, num_pages; 2038 const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); 2039 2040 r = drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, NULL); 2041 if (r) 2042 return r; 2043 2044 mutex_init(&entity->lock); 2045 2046 if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) 2047 return -EINVAL; 2048 if (num_gart_windows == 0) 2049 return 0; 2050 2051 num_pages = num_gart_windows * GTT_MAX_PAGES; 2052 r = amdgpu_gtt_mgr_alloc_entries(mgr, &entity->gart_node, num_pages, 2053 DRM_MM_INSERT_BEST); 2054 if (r) { 2055 drm_sched_entity_destroy(&entity->base); 2056 return r; 2057 } 2058 2059 for (i = 0; i < num_gart_windows; i++) { 2060 entity->gart_window_offs[i] = 2061 amdgpu_gtt_node_to_byte_offset(&entity->gart_node) + 2062 i * GTT_MAX_PAGES * PAGE_SIZE; 2063 } 2064 2065 return 0; 2066 } 2067 2068 static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_gtt_mgr *mgr, 2069 struct amdgpu_ttm_buffer_entity *entity) 2070 { 2071 amdgpu_gtt_mgr_free_entries(mgr, &entity->gart_node); 2072 drm_sched_entity_destroy(&entity->base); 2073 } 2074 2075 /* 2076 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 2077 * gtt/vram related fields. 2078 * 2079 * This initializes all of the memory space pools that the TTM layer 2080 * will need such as the GTT space (system memory mapped to the device), 2081 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 2082 * can be mapped per VMID. 2083 */ 2084 int amdgpu_ttm_init(struct amdgpu_device *adev) 2085 { 2086 uint64_t gtt_size; 2087 int r; 2088 2089 dma_set_max_seg_size(adev->dev, UINT_MAX); 2090 /* No others user of address space so set it to 0 */ 2091 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 2092 adev_to_drm(adev)->anon_inode->i_mapping, 2093 adev_to_drm(adev)->vma_offset_manager, 2094 (adev->need_swiotlb ? 2095 TTM_ALLOCATION_POOL_USE_DMA_ALLOC : 0) | 2096 (dma_addressing_limited(adev->dev) ? 2097 TTM_ALLOCATION_POOL_USE_DMA32 : 0) | 2098 TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M))); 2099 if (r) { 2100 dev_err(adev->dev, 2101 "failed initializing buffer object driver(%d).\n", r); 2102 return r; 2103 } 2104 2105 r = amdgpu_ttm_pools_init(adev); 2106 if (r) { 2107 dev_err(adev->dev, "failed to init ttm pools(%d).\n", r); 2108 return r; 2109 } 2110 adev->mman.initialized = true; 2111 2112 if (!adev->gmc.is_app_apu) { 2113 /* Initialize VRAM pool with all of VRAM divided into pages */ 2114 r = amdgpu_vram_mgr_init(adev); 2115 if (r) { 2116 dev_err(adev->dev, "Failed initializing VRAM heap.\n"); 2117 return r; 2118 } 2119 } 2120 2121 /* Change the size here instead of the init above so only lpfn is affected */ 2122 amdgpu_ttm_disable_buffer_funcs(adev); 2123 #ifdef CONFIG_64BIT 2124 if (adev->gmc.xgmi.connected_to_cpu) { 2125 void *kaddr = devm_memremap(adev->dev, adev->gmc.aper_base, 2126 adev->gmc.visible_vram_size, 2127 MEMREMAP_WB); 2128 if (IS_ERR(kaddr)) 2129 return PTR_ERR(kaddr); 2130 adev->mman.aper_base_kaddr = (__force void __iomem *)kaddr; 2131 } else if (adev->gmc.is_app_apu) { 2132 DRM_DEBUG_DRIVER( 2133 "No need to ioremap when real vram size is 0\n"); 2134 } else { 2135 adev->mman.aper_base_kaddr = devm_ioremap_wc(adev->dev, 2136 adev->gmc.aper_base, 2137 adev->gmc.visible_vram_size); 2138 if (!adev->mman.aper_base_kaddr) 2139 return -ENOMEM; 2140 } 2141 #endif 2142 2143 amdgpu_ttm_init_vram_resv_regions(adev); 2144 2145 r = amdgpu_ttm_alloc_vram_resv_regions(adev); 2146 if (r) 2147 return r; 2148 2149 if (adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN].size) { 2150 struct psp_memory_training_context *ctx = 2151 &adev->psp.mem_train_ctx; 2152 2153 amdgpu_ttm_training_data_block_init(adev); 2154 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 2155 } 2156 2157 dev_info(adev->dev, " %uM of VRAM memory ready\n", 2158 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024))); 2159 2160 /* Compute GTT size, either based on TTM limit 2161 * or whatever the user passed on module init. 2162 */ 2163 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT; 2164 if (amdgpu_gtt_size != -1) { 2165 uint64_t configured_size = (uint64_t)amdgpu_gtt_size << 20; 2166 2167 drm_warn(&adev->ddev, 2168 "Configuring gttsize via module parameter is deprecated, please use ttm.pages_limit\n"); 2169 if (gtt_size != configured_size) 2170 drm_warn(&adev->ddev, 2171 "GTT size has been set as %llu but TTM size has been set as %llu, this is unusual\n", 2172 configured_size, gtt_size); 2173 2174 gtt_size = configured_size; 2175 } 2176 2177 /* Initialize GTT memory pool */ 2178 r = amdgpu_gtt_mgr_init(adev, gtt_size); 2179 if (r) { 2180 dev_err(adev->dev, "Failed initializing GTT heap.\n"); 2181 return r; 2182 } 2183 dev_info(adev->dev, " %uM of GTT memory ready.\n", 2184 (unsigned int)(gtt_size / (1024 * 1024))); 2185 2186 if (adev->flags & AMD_IS_APU) { 2187 if (adev->gmc.real_vram_size < gtt_size) 2188 adev->apu_prefer_gtt = true; 2189 } 2190 2191 /* Initialize doorbell pool on PCI BAR */ 2192 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); 2193 if (r) { 2194 dev_err(adev->dev, "Failed initializing doorbell heap.\n"); 2195 return r; 2196 } 2197 2198 /* Create a doorbell page for kernel usages */ 2199 r = amdgpu_doorbell_create_kernel_doorbells(adev); 2200 if (r) { 2201 dev_err(adev->dev, "Failed to initialize kernel doorbells.\n"); 2202 return r; 2203 } 2204 2205 /* Initialize MMIO-remap pool (single page 4K) */ 2206 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_MMIO_REMAP, 1); 2207 if (r) { 2208 dev_err(adev->dev, "Failed initializing MMIO-remap heap.\n"); 2209 return r; 2210 } 2211 2212 /* Allocate the singleton MMIO_REMAP BO if supported */ 2213 r = amdgpu_ttm_alloc_mmio_remap_bo(adev); 2214 if (r) 2215 return r; 2216 2217 /* Initialize preemptible memory pool */ 2218 r = amdgpu_preempt_mgr_init(adev); 2219 if (r) { 2220 dev_err(adev->dev, "Failed initializing PREEMPT heap.\n"); 2221 return r; 2222 } 2223 2224 /* Initialize various on-chip memory pools */ 2225 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 2226 if (r) { 2227 dev_err(adev->dev, "Failed initializing GDS heap.\n"); 2228 return r; 2229 } 2230 2231 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 2232 if (r) { 2233 dev_err(adev->dev, "Failed initializing gws heap.\n"); 2234 return r; 2235 } 2236 2237 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 2238 if (r) { 2239 dev_err(adev->dev, "Failed initializing oa heap.\n"); 2240 return r; 2241 } 2242 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 2243 AMDGPU_GEM_DOMAIN_GTT, 2244 &adev->mman.sdma_access_bo, NULL, 2245 &adev->mman.sdma_access_ptr)) 2246 drm_warn(adev_to_drm(adev), 2247 "Debug VRAM access will use slowpath MM access\n"); 2248 2249 return 0; 2250 } 2251 2252 /* 2253 * amdgpu_ttm_fini - De-initialize the TTM memory pools 2254 */ 2255 void amdgpu_ttm_fini(struct amdgpu_device *adev) 2256 { 2257 if (!adev->mman.initialized) 2258 return; 2259 2260 amdgpu_ttm_pools_fini(adev); 2261 2262 amdgpu_ttm_training_reserve_vram_fini(adev); 2263 /* return the stolen vga memory back to VRAM */ 2264 if (!adev->gmc.is_app_apu) { 2265 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 2266 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 2267 /* return the FW reserved memory back to VRAM */ 2268 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 2269 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 2270 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_RESERVED); 2271 } 2272 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 2273 &adev->mman.sdma_access_ptr); 2274 2275 amdgpu_ttm_free_mmio_remap_bo(adev); 2276 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE); 2277 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); 2278 2279 adev->mman.aper_base_kaddr = NULL; 2280 2281 if (!adev->gmc.is_app_apu) 2282 amdgpu_vram_mgr_fini(adev); 2283 amdgpu_gtt_mgr_fini(adev); 2284 amdgpu_preempt_mgr_fini(adev); 2285 amdgpu_doorbell_fini(adev); 2286 2287 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 2288 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 2289 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 2290 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DOORBELL); 2291 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_MMIO_REMAP); 2292 ttm_device_fini(&adev->mman.bdev); 2293 adev->mman.initialized = false; 2294 dev_info(adev->dev, " ttm finalized\n"); 2295 } 2296 2297 /** 2298 * amdgpu_ttm_enable_buffer_funcs - enable use of buffer functions 2299 * 2300 * @adev: amdgpu_device pointer 2301 * 2302 * Enable use of buffer functions during suspend/resume. This should 2303 * only be called at bootup or when userspace isn't running. 2304 */ 2305 void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev) 2306 { 2307 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2308 u32 num_clear_entities, num_move_entities; 2309 int r, i, j; 2310 2311 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 2312 adev->mman.buffer_funcs_enabled || adev->gmc.is_app_apu) 2313 return; 2314 2315 if (!adev->mman.num_buffer_funcs_scheds) { 2316 dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); 2317 return; 2318 } 2319 2320 /* default_entity doesn't need multiple schedulers so pass only 1. */ 2321 r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, 2322 &adev->mman.default_entity, 2323 DRM_SCHED_PRIORITY_KERNEL, 2324 adev->mman.buffer_funcs_scheds, 1, 0); 2325 if (r < 0) { 2326 dev_err(adev->dev, 2327 "Failed setting up TTM entity (%d)\n", r); 2328 return; 2329 } 2330 2331 num_clear_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); 2332 num_move_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES); 2333 2334 adev->mman.clear_entities = kcalloc(num_clear_entities, 2335 sizeof(struct amdgpu_ttm_buffer_entity), 2336 GFP_KERNEL); 2337 atomic_set(&adev->mman.next_clear_entity, 0); 2338 if (!adev->mman.clear_entities) 2339 goto error_free_default_entity; 2340 2341 adev->mman.num_clear_entities = num_clear_entities; 2342 2343 for (i = 0; i < num_clear_entities; i++) { 2344 r = amdgpu_ttm_buffer_entity_init( 2345 &adev->mman.gtt_mgr, 2346 &adev->mman.clear_entities[i], 2347 DRM_SCHED_PRIORITY_KERNEL, 2348 adev->mman.buffer_funcs_scheds, 2349 adev->mman.num_buffer_funcs_scheds, 1); 2350 2351 if (r < 0) { 2352 for (j = 0; j < i; j++) 2353 amdgpu_ttm_buffer_entity_fini( 2354 &adev->mman.gtt_mgr, &adev->mman.clear_entities[j]); 2355 adev->mman.num_clear_entities = 0; 2356 kfree(adev->mman.clear_entities); 2357 goto error_free_default_entity; 2358 } 2359 } 2360 2361 adev->mman.num_move_entities = num_move_entities; 2362 atomic_set(&adev->mman.next_move_entity, 0); 2363 for (i = 0; i < num_move_entities; i++) { 2364 r = amdgpu_ttm_buffer_entity_init( 2365 &adev->mman.gtt_mgr, 2366 &adev->mman.move_entities[i], 2367 DRM_SCHED_PRIORITY_KERNEL, 2368 adev->mman.buffer_funcs_scheds, 2369 adev->mman.num_buffer_funcs_scheds, 2); 2370 2371 if (r < 0) { 2372 for (j = 0; j < i; j++) 2373 amdgpu_ttm_buffer_entity_fini( 2374 &adev->mman.gtt_mgr, 2375 &adev->mman.move_entities[j]); 2376 adev->mman.num_move_entities = 0; 2377 goto error_free_clear_entities; 2378 } 2379 } 2380 2381 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 2382 man->size = adev->gmc.real_vram_size; 2383 adev->mman.buffer_funcs_enabled = true; 2384 2385 return; 2386 2387 error_free_clear_entities: 2388 for (i = 0; i < adev->mman.num_clear_entities; i++) 2389 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2390 &adev->mman.clear_entities[i]); 2391 kfree(adev->mman.clear_entities); 2392 adev->mman.clear_entities = NULL; 2393 adev->mman.num_clear_entities = 0; 2394 error_free_default_entity: 2395 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2396 &adev->mman.default_entity); 2397 } 2398 2399 /** 2400 * amdgpu_ttm_disable_buffer_funcs - disable use of buffer functions 2401 * 2402 * @adev: amdgpu_device pointer 2403 */ 2404 void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev) 2405 { 2406 struct ttm_resource_manager *man = 2407 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 2408 int i; 2409 2410 if (!adev->mman.buffer_funcs_enabled || amdgpu_in_reset(adev)) 2411 return; 2412 2413 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2414 &adev->mman.default_entity); 2415 for (i = 0; i < adev->mman.num_move_entities; i++) 2416 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2417 &adev->mman.move_entities[i]); 2418 for (i = 0; i < adev->mman.num_clear_entities; i++) 2419 amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2420 &adev->mman.clear_entities[i]); 2421 /* Drop all the old fences since re-creating the scheduler entities 2422 * will allocate new contexts. 2423 */ 2424 ttm_resource_manager_cleanup(man); 2425 2426 kfree(adev->mman.clear_entities); 2427 adev->mman.clear_entities = NULL; 2428 adev->mman.num_clear_entities = 0; 2429 adev->mman.num_move_entities = 0; 2430 2431 man->size = adev->gmc.visible_vram_size; 2432 adev->mman.buffer_funcs_enabled = false; 2433 } 2434 2435 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, 2436 struct amdgpu_ttm_buffer_entity *entity, 2437 unsigned int num_dw, 2438 struct dma_resv *resv, 2439 bool vm_needs_flush, 2440 struct amdgpu_job **job, 2441 u64 k_job_id) 2442 { 2443 enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED; 2444 int r; 2445 r = amdgpu_job_alloc_with_ib(adev, &entity->base, 2446 AMDGPU_FENCE_OWNER_UNDEFINED, 2447 num_dw * 4, pool, k_job_id, job); 2448 if (r) 2449 return r; 2450 2451 if (vm_needs_flush) { 2452 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 2453 adev->gmc.pdb0_bo : 2454 adev->gart.bo); 2455 (*job)->vm_needs_flush = true; 2456 } 2457 if (!resv) 2458 return 0; 2459 2460 return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, 2461 DMA_RESV_USAGE_BOOKKEEP); 2462 } 2463 2464 int amdgpu_copy_buffer(struct amdgpu_device *adev, 2465 struct amdgpu_ttm_buffer_entity *entity, 2466 uint64_t src_offset, 2467 uint64_t dst_offset, uint32_t byte_count, 2468 struct dma_resv *resv, 2469 struct dma_fence **fence, 2470 bool vm_needs_flush, uint32_t copy_flags) 2471 { 2472 unsigned int num_loops, num_dw; 2473 struct amdgpu_ring *ring; 2474 struct amdgpu_job *job; 2475 uint32_t max_bytes; 2476 unsigned int i; 2477 int r; 2478 2479 ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); 2480 2481 if (!ring->sched.ready) { 2482 dev_err(adev->dev, 2483 "Trying to move memory with ring turned off.\n"); 2484 return -EINVAL; 2485 } 2486 2487 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 2488 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 2489 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 2490 r = amdgpu_ttm_prepare_job(adev, entity, num_dw, 2491 resv, vm_needs_flush, &job, 2492 AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); 2493 if (r) 2494 goto error_free; 2495 2496 for (i = 0; i < num_loops; i++) { 2497 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 2498 2499 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 2500 dst_offset, cur_size_in_bytes, copy_flags); 2501 src_offset += cur_size_in_bytes; 2502 dst_offset += cur_size_in_bytes; 2503 byte_count -= cur_size_in_bytes; 2504 } 2505 2506 *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); 2507 2508 return 0; 2509 2510 error_free: 2511 amdgpu_job_free(job); 2512 dev_err(adev->dev, "Error scheduling IBs (%d)\n", r); 2513 return r; 2514 } 2515 2516 static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, 2517 struct amdgpu_ttm_buffer_entity *entity, 2518 uint32_t src_data, 2519 uint64_t dst_addr, uint32_t byte_count, 2520 struct dma_resv *resv, 2521 struct dma_fence **fence, 2522 bool vm_needs_flush, 2523 u64 k_job_id) 2524 { 2525 unsigned int num_loops, num_dw; 2526 struct amdgpu_job *job; 2527 uint32_t max_bytes; 2528 unsigned int i; 2529 int r; 2530 2531 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2532 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); 2533 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); 2534 r = amdgpu_ttm_prepare_job(adev, entity, num_dw, resv, 2535 vm_needs_flush, &job, k_job_id); 2536 if (r) 2537 return r; 2538 2539 for (i = 0; i < num_loops; i++) { 2540 uint32_t cur_size = min(byte_count, max_bytes); 2541 2542 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2543 cur_size); 2544 2545 dst_addr += cur_size; 2546 byte_count -= cur_size; 2547 } 2548 2549 *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); 2550 return 0; 2551 } 2552 2553 /** 2554 * amdgpu_ttm_clear_buffer - fill a buffer with 0 2555 * @entity: entity to use 2556 * @bo: the bo to fill 2557 * @resv: fences contained in this reservation will be used as dependencies. 2558 * @out_fence: the fence from the last clear will be stored here. It might be 2559 * NULL if no job was run. 2560 * @consider_clear_status: true if region reported as cleared by amdgpu_res_cleared() 2561 * are skipped. 2562 * @k_job_id: trace id 2563 * 2564 */ 2565 int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity, 2566 struct amdgpu_bo *bo, 2567 struct dma_resv *resv, 2568 struct dma_fence **out_fence, 2569 bool consider_clear_status, 2570 u64 k_job_id) 2571 { 2572 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2573 struct dma_fence *fence = NULL; 2574 struct amdgpu_res_cursor dst; 2575 int r; 2576 2577 if (!entity) 2578 return -EINVAL; 2579 2580 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); 2581 2582 mutex_lock(&entity->lock); 2583 while (dst.remaining) { 2584 struct dma_fence *next; 2585 uint64_t cur_size, to; 2586 2587 if (consider_clear_status && amdgpu_res_cleared(&dst)) { 2588 amdgpu_res_next(&dst, dst.size); 2589 continue; 2590 } 2591 2592 /* Never fill more than 256MiB at once to avoid timeouts */ 2593 cur_size = min(dst.size, 256ULL << 20); 2594 2595 r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &dst, 2596 0, false, &cur_size, &to); 2597 if (r) 2598 goto error; 2599 2600 r = amdgpu_ttm_fill_mem(adev, entity, 2601 0, to, cur_size, resv, 2602 &next, true, k_job_id); 2603 if (r) 2604 goto error; 2605 2606 dma_fence_put(fence); 2607 fence = next; 2608 2609 amdgpu_res_next(&dst, cur_size); 2610 } 2611 error: 2612 mutex_unlock(&entity->lock); 2613 *out_fence = fence; 2614 return r; 2615 } 2616 2617 struct amdgpu_ttm_buffer_entity * 2618 amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev) 2619 { 2620 struct amdgpu_mman *mman = &adev->mman; 2621 u32 i; 2622 2623 if (mman->num_clear_entities == 0) 2624 return NULL; 2625 2626 i = atomic_inc_return(&mman->next_clear_entity) % 2627 mman->num_clear_entities; 2628 return &mman->clear_entities[i]; 2629 } 2630 2631 /** 2632 * amdgpu_ttm_evict_resources - evict memory buffers 2633 * @adev: amdgpu device object 2634 * @mem_type: evicted BO's memory type 2635 * 2636 * Evicts all @mem_type buffers on the lru list of the memory type. 2637 * 2638 * Returns: 2639 * 0 for success or a negative error code on failure. 2640 */ 2641 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) 2642 { 2643 struct ttm_resource_manager *man; 2644 2645 switch (mem_type) { 2646 case TTM_PL_VRAM: 2647 case TTM_PL_TT: 2648 case AMDGPU_PL_GWS: 2649 case AMDGPU_PL_GDS: 2650 case AMDGPU_PL_OA: 2651 man = ttm_manager_type(&adev->mman.bdev, mem_type); 2652 break; 2653 default: 2654 dev_err(adev->dev, "Trying to evict invalid memory type\n"); 2655 return -EINVAL; 2656 } 2657 2658 return ttm_resource_manager_evict_all(&adev->mman.bdev, man); 2659 } 2660 2661 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 2662 const struct amdgpu_buffer_funcs *buffer_funcs) 2663 { 2664 struct drm_gpu_scheduler *sched; 2665 struct amdgpu_vmhub *hub; 2666 int i, n; 2667 2668 adev->mman.buffer_funcs = buffer_funcs; 2669 2670 for (i = 0, n = 0; i < adev->sdma.num_instances; i++) { 2671 if (adev->sdma.has_page_queue) 2672 sched = &adev->sdma.instance[i].page.sched; 2673 else 2674 sched = &adev->sdma.instance[i].ring.sched; 2675 2676 if (!sched->ready) 2677 continue; 2678 2679 adev->mman.buffer_funcs_scheds[n++] = sched; 2680 } 2681 2682 if (n == 0) { 2683 adev->mman.num_buffer_funcs_scheds = 0; 2684 drm_warn(&adev->ddev, "No working sdma ring available\n"); 2685 return; 2686 } 2687 2688 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 2689 2690 /* 2691 * Allow using multiple SDMA schedulers only on GPUs where 2692 * we are allowed to do concurrent VM flushes. 2693 * This consideration is necessary because all GART windows 2694 * are mapped in VMID 0 (the kernel VMID) so each buffer 2695 * entity would flush VMID 0 concurrently. 2696 * 2697 * Also consider the SDMA invalidation workaround on 2698 * Navi 1x GPUs, which also prevents us from using 2699 * multiple SDMA engines on VMID 0 at the same time. 2700 */ 2701 adev->mman.num_buffer_funcs_scheds = 2702 (adev->vm_manager.concurrent_flush && 2703 !hub->sdma_invalidation_workaround) ? n : 1; 2704 } 2705 2706 #if defined(CONFIG_DEBUG_FS) 2707 2708 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2709 { 2710 struct amdgpu_device *adev = m->private; 2711 2712 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2713 } 2714 2715 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2716 2717 /* 2718 * amdgpu_ttm_vram_read - Linear read access to VRAM 2719 * 2720 * Accesses VRAM via MMIO for debugging purposes. 2721 */ 2722 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2723 size_t size, loff_t *pos) 2724 { 2725 struct amdgpu_device *adev = file_inode(f)->i_private; 2726 ssize_t result = 0; 2727 2728 if (size & 0x3 || *pos & 0x3) 2729 return -EINVAL; 2730 2731 if (*pos >= adev->gmc.mc_vram_size) 2732 return -ENXIO; 2733 2734 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2735 while (size) { 2736 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2737 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2738 2739 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2740 if (copy_to_user(buf, value, bytes)) 2741 return -EFAULT; 2742 2743 result += bytes; 2744 buf += bytes; 2745 *pos += bytes; 2746 size -= bytes; 2747 } 2748 2749 return result; 2750 } 2751 2752 /* 2753 * amdgpu_ttm_vram_write - Linear write access to VRAM 2754 * 2755 * Accesses VRAM via MMIO for debugging purposes. 2756 */ 2757 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2758 size_t size, loff_t *pos) 2759 { 2760 struct amdgpu_device *adev = file_inode(f)->i_private; 2761 ssize_t result = 0; 2762 int r; 2763 2764 if (size & 0x3 || *pos & 0x3) 2765 return -EINVAL; 2766 2767 if (*pos >= adev->gmc.mc_vram_size) 2768 return -ENXIO; 2769 2770 while (size) { 2771 uint32_t value; 2772 2773 if (*pos >= adev->gmc.mc_vram_size) 2774 return result; 2775 2776 r = get_user(value, (uint32_t *)buf); 2777 if (r) 2778 return r; 2779 2780 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2781 2782 result += 4; 2783 buf += 4; 2784 *pos += 4; 2785 size -= 4; 2786 } 2787 2788 return result; 2789 } 2790 2791 static const struct file_operations amdgpu_ttm_vram_fops = { 2792 .owner = THIS_MODULE, 2793 .read = amdgpu_ttm_vram_read, 2794 .write = amdgpu_ttm_vram_write, 2795 .llseek = default_llseek, 2796 }; 2797 2798 /* 2799 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2800 * 2801 * This function is used to read memory that has been mapped to the 2802 * GPU and the known addresses are not physical addresses but instead 2803 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2804 */ 2805 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2806 size_t size, loff_t *pos) 2807 { 2808 struct amdgpu_device *adev = file_inode(f)->i_private; 2809 struct iommu_domain *dom; 2810 ssize_t result = 0; 2811 int r; 2812 2813 /* retrieve the IOMMU domain if any for this device */ 2814 dom = iommu_get_domain_for_dev(adev->dev); 2815 2816 while (size) { 2817 phys_addr_t addr = *pos & PAGE_MASK; 2818 loff_t off = *pos & ~PAGE_MASK; 2819 size_t bytes = PAGE_SIZE - off; 2820 unsigned long pfn; 2821 struct page *p; 2822 void *ptr; 2823 2824 bytes = min(bytes, size); 2825 2826 /* Translate the bus address to a physical address. If 2827 * the domain is NULL it means there is no IOMMU active 2828 * and the address translation is the identity 2829 */ 2830 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2831 2832 pfn = addr >> PAGE_SHIFT; 2833 if (!pfn_valid(pfn)) 2834 return -EPERM; 2835 2836 p = pfn_to_page(pfn); 2837 if (p->mapping != adev->mman.bdev.dev_mapping) 2838 return -EPERM; 2839 2840 ptr = kmap_local_page(p); 2841 r = copy_to_user(buf, ptr + off, bytes); 2842 kunmap_local(ptr); 2843 if (r) 2844 return -EFAULT; 2845 2846 size -= bytes; 2847 *pos += bytes; 2848 result += bytes; 2849 } 2850 2851 return result; 2852 } 2853 2854 /* 2855 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2856 * 2857 * This function is used to write memory that has been mapped to the 2858 * GPU and the known addresses are not physical addresses but instead 2859 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2860 */ 2861 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2862 size_t size, loff_t *pos) 2863 { 2864 struct amdgpu_device *adev = file_inode(f)->i_private; 2865 struct iommu_domain *dom; 2866 ssize_t result = 0; 2867 int r; 2868 2869 dom = iommu_get_domain_for_dev(adev->dev); 2870 2871 while (size) { 2872 phys_addr_t addr = *pos & PAGE_MASK; 2873 loff_t off = *pos & ~PAGE_MASK; 2874 size_t bytes = PAGE_SIZE - off; 2875 unsigned long pfn; 2876 struct page *p; 2877 void *ptr; 2878 2879 bytes = min(bytes, size); 2880 2881 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2882 2883 pfn = addr >> PAGE_SHIFT; 2884 if (!pfn_valid(pfn)) 2885 return -EPERM; 2886 2887 p = pfn_to_page(pfn); 2888 if (p->mapping != adev->mman.bdev.dev_mapping) 2889 return -EPERM; 2890 2891 ptr = kmap_local_page(p); 2892 r = copy_from_user(ptr + off, buf, bytes); 2893 kunmap_local(ptr); 2894 if (r) 2895 return -EFAULT; 2896 2897 size -= bytes; 2898 *pos += bytes; 2899 result += bytes; 2900 } 2901 2902 return result; 2903 } 2904 2905 static const struct file_operations amdgpu_ttm_iomem_fops = { 2906 .owner = THIS_MODULE, 2907 .read = amdgpu_iomem_read, 2908 .write = amdgpu_iomem_write, 2909 .llseek = default_llseek 2910 }; 2911 2912 #endif 2913 2914 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2915 { 2916 #if defined(CONFIG_DEBUG_FS) 2917 struct drm_minor *minor = adev_to_drm(adev)->primary; 2918 struct dentry *root = minor->debugfs_root; 2919 2920 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2921 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2922 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2923 &amdgpu_ttm_iomem_fops); 2924 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2925 &amdgpu_ttm_page_pool_fops); 2926 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2927 TTM_PL_VRAM), 2928 root, "amdgpu_vram_mm"); 2929 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2930 TTM_PL_TT), 2931 root, "amdgpu_gtt_mm"); 2932 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2933 AMDGPU_PL_GDS), 2934 root, "amdgpu_gds_mm"); 2935 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2936 AMDGPU_PL_GWS), 2937 root, "amdgpu_gws_mm"); 2938 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, 2939 AMDGPU_PL_OA), 2940 root, "amdgpu_oa_mm"); 2941 2942 #endif 2943 } 2944