1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_suballoc.h> 31 32 struct amdgpu_device; 33 struct amdgpu_ring; 34 struct amdgpu_ib; 35 struct amdgpu_cs_parser; 36 struct amdgpu_job; 37 struct amdgpu_vm; 38 39 /* max number of rings */ 40 #define AMDGPU_MAX_RINGS 149 41 #define AMDGPU_MAX_HWIP_RINGS 64 42 #define AMDGPU_MAX_GFX_RINGS 2 43 #define AMDGPU_MAX_SW_GFX_RINGS 2 44 #define AMDGPU_MAX_COMPUTE_RINGS 8 45 #define AMDGPU_MAX_VCE_RINGS 3 46 #define AMDGPU_MAX_UVD_ENC_RINGS 2 47 #define AMDGPU_MAX_VPE_RINGS 2 48 49 enum amdgpu_ring_priority_level { 50 AMDGPU_RING_PRIO_0, 51 AMDGPU_RING_PRIO_1, 52 AMDGPU_RING_PRIO_DEFAULT = 1, 53 AMDGPU_RING_PRIO_2, 54 AMDGPU_RING_PRIO_MAX 55 }; 56 57 /* some special values for the owner field */ 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 61 62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 63 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 65 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 66 67 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 68 69 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 70 71 enum amdgpu_ring_type { 72 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 73 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 74 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 75 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 76 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 77 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 78 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 79 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 80 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 81 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE, 82 AMDGPU_RING_TYPE_KIQ, 83 AMDGPU_RING_TYPE_MES, 84 AMDGPU_RING_TYPE_UMSCH_MM, 85 AMDGPU_RING_TYPE_CPER, 86 }; 87 88 enum amdgpu_ib_pool_type { 89 /* Normal submissions to the top of the pipeline. */ 90 AMDGPU_IB_POOL_DELAYED, 91 /* Immediate submissions to the bottom of the pipeline. */ 92 AMDGPU_IB_POOL_IMMEDIATE, 93 /* Direct submission to the ring buffer during init and reset. */ 94 AMDGPU_IB_POOL_DIRECT, 95 96 AMDGPU_IB_POOL_MAX 97 }; 98 99 struct amdgpu_ib { 100 struct drm_suballoc *sa_bo; 101 uint32_t length_dw; 102 uint64_t gpu_addr; 103 uint32_t *ptr; 104 uint32_t flags; 105 }; 106 107 struct amdgpu_sched { 108 u32 num_scheds; 109 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 110 }; 111 112 /* 113 * Fences. 114 */ 115 struct amdgpu_fence_driver { 116 uint64_t gpu_addr; 117 volatile uint32_t *cpu_addr; 118 /* sync_seq is protected by ring emission lock */ 119 uint32_t sync_seq; 120 atomic_t last_seq; 121 bool initialized; 122 struct amdgpu_irq_src *irq_src; 123 unsigned irq_type; 124 struct timer_list fallback_timer; 125 unsigned num_fences_mask; 126 spinlock_t lock; 127 struct dma_fence **fences; 128 }; 129 130 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 131 132 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); 133 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 134 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 135 136 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 137 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 138 struct amdgpu_irq_src *irq_src, 139 unsigned irq_type); 140 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 141 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 142 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 143 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 144 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job, 145 unsigned flags); 146 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 147 uint32_t timeout); 148 bool amdgpu_fence_process(struct amdgpu_ring *ring); 149 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 150 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 151 uint32_t wait_seq, 152 signed long timeout); 153 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 154 155 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 156 157 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 158 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 159 ktime_t timestamp); 160 161 /* 162 * Rings. 163 */ 164 165 /* provided by hw blocks that expose a ring buffer for commands */ 166 struct amdgpu_ring_funcs { 167 /** 168 * @type: 169 * 170 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER 171 * use ring buffers. The type field just identifies which component the 172 * ring buffer is associated with. 173 */ 174 enum amdgpu_ring_type type; 175 uint32_t align_mask; 176 177 /** 178 * @nop: 179 * 180 * Every block in the amdgpu has no-op instructions (e.g., GFX 10 181 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP, 182 * etc). This field receives the specific no-op for the component 183 * that initializes the ring. 184 */ 185 u32 nop; 186 bool support_64bit_ptrs; 187 bool no_user_fence; 188 bool secure_submission_supported; 189 unsigned extra_dw; 190 191 /* ring read/write ptr handling */ 192 u64 (*get_rptr)(struct amdgpu_ring *ring); 193 u64 (*get_wptr)(struct amdgpu_ring *ring); 194 void (*set_wptr)(struct amdgpu_ring *ring); 195 /* validating and patching of IBs */ 196 int (*parse_cs)(struct amdgpu_cs_parser *p, 197 struct amdgpu_job *job, 198 struct amdgpu_ib *ib); 199 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 200 struct amdgpu_job *job, 201 struct amdgpu_ib *ib); 202 /* constants to calculate how many DW are needed for an emit */ 203 unsigned emit_frame_size; 204 unsigned emit_ib_size; 205 /* command emit functions */ 206 void (*emit_ib)(struct amdgpu_ring *ring, 207 struct amdgpu_job *job, 208 struct amdgpu_ib *ib, 209 uint32_t flags); 210 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 211 uint64_t seq, unsigned flags); 212 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 213 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 214 uint64_t pd_addr); 215 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 216 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 217 uint32_t gds_base, uint32_t gds_size, 218 uint32_t gws_base, uint32_t gws_size, 219 uint32_t oa_base, uint32_t oa_size); 220 /* testing functions */ 221 int (*test_ring)(struct amdgpu_ring *ring); 222 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 223 /* insert NOP packets */ 224 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 225 void (*insert_start)(struct amdgpu_ring *ring); 226 void (*insert_end)(struct amdgpu_ring *ring); 227 /* pad the indirect buffer to the necessary number of dw */ 228 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 229 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr); 230 /* note usage for clock and power gating */ 231 void (*begin_use)(struct amdgpu_ring *ring); 232 void (*end_use)(struct amdgpu_ring *ring); 233 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 234 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 235 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 236 u64 gds_va, bool init_shadow, int vmid); 237 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 238 uint32_t reg_val_offs); 239 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 240 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 241 uint32_t val, uint32_t mask); 242 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 243 uint32_t reg0, uint32_t reg1, 244 uint32_t ref, uint32_t mask); 245 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 246 bool secure); 247 /* Try to soft recover the ring to make the fence signal */ 248 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 249 int (*preempt_ib)(struct amdgpu_ring *ring); 250 void (*emit_mem_sync)(struct amdgpu_ring *ring); 251 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 252 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 253 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 254 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 255 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid); 256 void (*emit_cleaner_shader)(struct amdgpu_ring *ring); 257 bool (*is_guilty)(struct amdgpu_ring *ring); 258 }; 259 260 /** 261 * amdgpu_ring - Holds ring information 262 */ 263 struct amdgpu_ring { 264 struct amdgpu_device *adev; 265 const struct amdgpu_ring_funcs *funcs; 266 struct amdgpu_fence_driver fence_drv; 267 struct drm_gpu_scheduler sched; 268 269 struct amdgpu_bo *ring_obj; 270 uint32_t *ring; 271 unsigned rptr_offs; 272 u64 rptr_gpu_addr; 273 volatile u32 *rptr_cpu_addr; 274 275 /** 276 * @wptr: 277 * 278 * This is part of the Ring buffer implementation and represents the 279 * write pointer. The wptr determines where the host has written. 280 */ 281 u64 wptr; 282 283 /** 284 * @wptr_old: 285 * 286 * Before update wptr with the new value, usually the old value is 287 * stored in the wptr_old. 288 */ 289 u64 wptr_old; 290 unsigned ring_size; 291 292 /** 293 * @max_dw: 294 * 295 * Maximum number of DWords for ring allocation. This information is 296 * provided at the ring initialization time, and each IP block can 297 * specify a specific value. Check places that invoke 298 * amdgpu_ring_init() to see the maximum size per block. 299 */ 300 unsigned max_dw; 301 302 /** 303 * @count_dw: 304 * 305 * This value starts with the maximum amount of DWords supported by the 306 * ring. This value is updated based on the ring manipulation. 307 */ 308 int count_dw; 309 uint64_t gpu_addr; 310 311 /** 312 * @ptr_mask: 313 * 314 * Some IPs provide support for 64-bit pointers and others for 32-bit 315 * only; this behavior is component-specific and defined by the field 316 * support_64bit_ptr. If the IP block supports 64-bits, the mask 317 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask. 318 * Notice that this field is used to keep wptr under a valid range. 319 */ 320 uint64_t ptr_mask; 321 322 /** 323 * @buf_mask: 324 * 325 * Buffer mask is a value used to keep wptr count under its 326 * thresholding. Buffer mask initialized during the ring buffer 327 * initialization time, and it is defined as (ring_size / 4) -1. 328 */ 329 uint32_t buf_mask; 330 u32 idx; 331 u32 xcc_id; 332 u32 xcp_id; 333 u32 me; 334 u32 pipe; 335 u32 queue; 336 struct amdgpu_bo *mqd_obj; 337 uint64_t mqd_gpu_addr; 338 void *mqd_ptr; 339 unsigned mqd_size; 340 uint64_t eop_gpu_addr; 341 u32 doorbell_index; 342 bool use_doorbell; 343 bool use_pollmem; 344 unsigned wptr_offs; 345 u64 wptr_gpu_addr; 346 347 /** 348 * @wptr_cpu_addr: 349 * 350 * This is the CPU address pointer in the writeback slot. This is used 351 * to commit changes to the GPU. 352 */ 353 volatile u32 *wptr_cpu_addr; 354 unsigned fence_offs; 355 u64 fence_gpu_addr; 356 volatile u32 *fence_cpu_addr; 357 uint64_t current_ctx; 358 char name[16]; 359 u32 trail_seq; 360 unsigned trail_fence_offs; 361 u64 trail_fence_gpu_addr; 362 volatile u32 *trail_fence_cpu_addr; 363 unsigned cond_exe_offs; 364 u64 cond_exe_gpu_addr; 365 volatile u32 *cond_exe_cpu_addr; 366 unsigned int set_q_mode_offs; 367 u32 *set_q_mode_ptr; 368 u64 set_q_mode_token; 369 unsigned vm_hub; 370 unsigned vm_inv_eng; 371 struct dma_fence *vmid_wait; 372 bool has_compute_vm_bug; 373 bool no_scheduler; 374 bool no_user_submission; 375 int hw_prio; 376 unsigned num_hw_submission; 377 atomic_t *sched_score; 378 379 bool is_sw_ring; 380 unsigned int entry_index; 381 /* store the cached rptr to restore after reset */ 382 uint64_t cached_rptr; 383 }; 384 385 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 386 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 387 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 388 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 389 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 390 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 391 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 392 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 393 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 394 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 395 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 396 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 397 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 398 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 399 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 400 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 401 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 402 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 403 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 404 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 405 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 406 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 407 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a)) 408 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 409 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 410 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 411 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 412 #define amdgpu_ring_reset(r, v) (r)->funcs->reset((r), (v)) 413 414 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 415 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 416 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 417 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 418 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 419 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 420 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 421 422 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 423 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 424 void amdgpu_ring_commit(struct amdgpu_ring *ring); 425 void amdgpu_ring_undo(struct amdgpu_ring *ring); 426 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 427 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 428 unsigned int irq_type, unsigned int hw_prio, 429 atomic_t *sched_score); 430 void amdgpu_ring_fini(struct amdgpu_ring *ring); 431 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 432 uint32_t reg0, uint32_t val0, 433 uint32_t reg1, uint32_t val1); 434 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 435 struct dma_fence *fence); 436 437 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 438 bool cond_exec) 439 { 440 *ring->cond_exe_cpu_addr = cond_exec; 441 } 442 443 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 444 { 445 int i = 0; 446 while (i <= ring->buf_mask) 447 ring->ring[i++] = ring->funcs->nop; 448 449 } 450 451 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 452 { 453 ring->ring[ring->wptr++ & ring->buf_mask] = v; 454 ring->wptr &= ring->ptr_mask; 455 ring->count_dw--; 456 } 457 458 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 459 void *src, int count_dw) 460 { 461 unsigned occupied, chunk1, chunk2; 462 463 occupied = ring->wptr & ring->buf_mask; 464 chunk1 = ring->buf_mask + 1 - occupied; 465 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 466 chunk2 = count_dw - chunk1; 467 chunk1 <<= 2; 468 chunk2 <<= 2; 469 470 if (chunk1) 471 memcpy(&ring->ring[occupied], src, chunk1); 472 473 if (chunk2) { 474 src += chunk1; 475 memcpy(ring->ring, src, chunk2); 476 } 477 478 ring->wptr += count_dw; 479 ring->wptr &= ring->ptr_mask; 480 ring->count_dw -= count_dw; 481 } 482 483 /** 484 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute 485 * @ring: amdgpu_ring structure 486 * @offset: offset returned by amdgpu_ring_init_cond_exec 487 * 488 * Calculate the dw count and patch it into a cond_exec command. 489 */ 490 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, 491 unsigned int offset) 492 { 493 unsigned cur; 494 495 if (!ring->funcs->init_cond_exec) 496 return; 497 498 WARN_ON(offset > ring->buf_mask); 499 WARN_ON(ring->ring[offset] != 0); 500 501 cur = (ring->wptr - 1) & ring->buf_mask; 502 if (cur < offset) 503 cur += ring->ring_size >> 2; 504 ring->ring[offset] = cur - offset; 505 } 506 507 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 508 509 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 510 struct amdgpu_ring *ring); 511 512 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 513 514 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 515 { 516 return ib->ptr[idx]; 517 } 518 519 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 520 uint32_t value) 521 { 522 ib->ptr[idx] = value; 523 } 524 525 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 526 unsigned size, 527 enum amdgpu_ib_pool_type pool, 528 struct amdgpu_ib *ib); 529 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); 530 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 531 struct amdgpu_ib *ibs, struct amdgpu_job *job, 532 struct dma_fence **f); 533 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 534 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 535 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 536 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 537 #endif 538