1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_suballoc.h> 31 32 struct amdgpu_device; 33 struct amdgpu_ring; 34 struct amdgpu_ib; 35 struct amdgpu_cs_parser; 36 struct amdgpu_job; 37 struct amdgpu_vm; 38 39 /* max number of rings */ 40 #define AMDGPU_MAX_RINGS 149 41 #define AMDGPU_MAX_HWIP_RINGS 64 42 #define AMDGPU_MAX_GFX_RINGS 2 43 #define AMDGPU_MAX_SW_GFX_RINGS 2 44 #define AMDGPU_MAX_COMPUTE_RINGS 8 45 #define AMDGPU_MAX_VCE_RINGS 3 46 #define AMDGPU_MAX_UVD_ENC_RINGS 2 47 #define AMDGPU_MAX_VPE_RINGS 2 48 49 enum amdgpu_ring_priority_level { 50 AMDGPU_RING_PRIO_0, 51 AMDGPU_RING_PRIO_1, 52 AMDGPU_RING_PRIO_DEFAULT = 1, 53 AMDGPU_RING_PRIO_2, 54 AMDGPU_RING_PRIO_MAX 55 }; 56 57 /* some special values for the owner field */ 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 61 62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 63 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 65 66 /* Ensure the execution in case of preemption or reset */ 67 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 68 69 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 70 71 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 72 73 enum amdgpu_ring_type { 74 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 75 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 76 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 77 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 78 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 79 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 80 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 81 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 82 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 83 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE, 84 AMDGPU_RING_TYPE_KIQ, 85 AMDGPU_RING_TYPE_MES, 86 AMDGPU_RING_TYPE_UMSCH_MM, 87 AMDGPU_RING_TYPE_CPER, 88 AMDGPU_RING_TYPE_MAX, 89 }; 90 91 enum amdgpu_ib_pool_type { 92 /* Normal submissions to the top of the pipeline. */ 93 AMDGPU_IB_POOL_DELAYED, 94 /* Immediate submissions to the bottom of the pipeline. */ 95 AMDGPU_IB_POOL_IMMEDIATE, 96 /* Direct submission to the ring buffer during init and reset. */ 97 AMDGPU_IB_POOL_DIRECT, 98 99 AMDGPU_IB_POOL_MAX 100 }; 101 102 struct amdgpu_ib { 103 struct drm_suballoc *sa_bo; 104 uint32_t length_dw; 105 uint64_t gpu_addr; 106 uint32_t *ptr; 107 uint32_t flags; 108 }; 109 110 struct amdgpu_sched { 111 u32 num_scheds; 112 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 113 }; 114 115 /* 116 * Fences. 117 */ 118 struct amdgpu_fence_driver { 119 uint64_t gpu_addr; 120 uint32_t *cpu_addr; 121 /* sync_seq is protected by ring emission lock */ 122 uint32_t sync_seq; 123 atomic_t last_seq; 124 u64 signalled_wptr; 125 bool initialized; 126 struct amdgpu_irq_src *irq_src; 127 unsigned irq_type; 128 struct timer_list fallback_timer; 129 unsigned num_fences_mask; 130 spinlock_t lock; 131 struct dma_fence **fences; 132 }; 133 134 /* 135 * Fences mark an event in the GPUs pipeline and are used 136 * for GPU/CPU synchronization. When the fence is written, 137 * it is expected that all buffers associated with that fence 138 * are no longer in use by the associated ring on the GPU and 139 * that the relevant GPU caches have been flushed. 140 */ 141 142 struct amdgpu_fence { 143 struct dma_fence base; 144 145 /* RB, DMA, etc. */ 146 struct amdgpu_ring *ring; 147 ktime_t start_timestamp; 148 149 /* wptr for the fence for resets */ 150 u64 wptr; 151 /* fence context for resets */ 152 u64 context; 153 }; 154 155 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 156 157 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 158 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 159 void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); 160 void amdgpu_fence_save_wptr(struct amdgpu_fence *af); 161 162 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 163 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 164 struct amdgpu_irq_src *irq_src, 165 unsigned irq_type); 166 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 167 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 168 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 169 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 170 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, 171 unsigned int flags); 172 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 173 uint32_t timeout); 174 bool amdgpu_fence_process(struct amdgpu_ring *ring); 175 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 176 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 177 uint32_t wait_seq, 178 signed long timeout); 179 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 180 181 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 182 183 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 184 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 185 ktime_t timestamp); 186 187 /* 188 * Rings. 189 */ 190 191 /* provided by hw blocks that expose a ring buffer for commands */ 192 struct amdgpu_ring_funcs { 193 /** 194 * @type: 195 * 196 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER 197 * use ring buffers. The type field just identifies which component the 198 * ring buffer is associated with. 199 */ 200 enum amdgpu_ring_type type; 201 uint32_t align_mask; 202 203 /** 204 * @nop: 205 * 206 * Every block in the amdgpu has no-op instructions (e.g., GFX 10 207 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP, 208 * etc). This field receives the specific no-op for the component 209 * that initializes the ring. 210 */ 211 u32 nop; 212 bool support_64bit_ptrs; 213 bool no_user_fence; 214 bool secure_submission_supported; 215 216 /** 217 * @extra_bytes: 218 * 219 * Optional extra space in bytes that is added to the ring size 220 * when allocating the BO that holds the contents of the ring. 221 * This space isn't used for command submission to the ring, 222 * but is just there to satisfy some hardware requirements or 223 * implement workarounds. It's up to the implementation of each 224 * specific ring to initialize this space. 225 */ 226 unsigned extra_bytes; 227 228 /* ring read/write ptr handling */ 229 u64 (*get_rptr)(struct amdgpu_ring *ring); 230 u64 (*get_wptr)(struct amdgpu_ring *ring); 231 void (*set_wptr)(struct amdgpu_ring *ring); 232 /* validating and patching of IBs */ 233 int (*parse_cs)(struct amdgpu_cs_parser *p, 234 struct amdgpu_job *job, 235 struct amdgpu_ib *ib); 236 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 237 struct amdgpu_job *job, 238 struct amdgpu_ib *ib); 239 /* constants to calculate how many DW are needed for an emit */ 240 unsigned emit_frame_size; 241 unsigned emit_ib_size; 242 /* command emit functions */ 243 void (*emit_ib)(struct amdgpu_ring *ring, 244 struct amdgpu_job *job, 245 struct amdgpu_ib *ib, 246 uint32_t flags); 247 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 248 uint64_t seq, unsigned flags); 249 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 250 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 251 uint64_t pd_addr); 252 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 253 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 254 uint32_t gds_base, uint32_t gds_size, 255 uint32_t gws_base, uint32_t gws_size, 256 uint32_t oa_base, uint32_t oa_size); 257 /* testing functions */ 258 int (*test_ring)(struct amdgpu_ring *ring); 259 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 260 /* insert NOP packets */ 261 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 262 void (*insert_start)(struct amdgpu_ring *ring); 263 void (*insert_end)(struct amdgpu_ring *ring); 264 /* pad the indirect buffer to the necessary number of dw */ 265 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 266 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr); 267 /* note usage for clock and power gating */ 268 void (*begin_use)(struct amdgpu_ring *ring); 269 void (*end_use)(struct amdgpu_ring *ring); 270 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 271 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 272 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 273 u64 gds_va, bool init_shadow, int vmid); 274 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 275 uint32_t reg_val_offs); 276 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 277 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 278 uint32_t val, uint32_t mask); 279 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 280 uint32_t reg0, uint32_t reg1, 281 uint32_t ref, uint32_t mask); 282 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 283 bool secure); 284 /* Try to soft recover the ring to make the fence signal */ 285 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 286 int (*preempt_ib)(struct amdgpu_ring *ring); 287 void (*emit_mem_sync)(struct amdgpu_ring *ring); 288 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 289 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 290 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 291 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 292 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid, 293 struct amdgpu_fence *timedout_fence); 294 void (*emit_cleaner_shader)(struct amdgpu_ring *ring); 295 }; 296 297 /** 298 * amdgpu_ring - Holds ring information 299 */ 300 struct amdgpu_ring { 301 struct amdgpu_device *adev; 302 const struct amdgpu_ring_funcs *funcs; 303 struct amdgpu_fence_driver fence_drv; 304 struct drm_gpu_scheduler sched; 305 306 struct amdgpu_bo *ring_obj; 307 uint32_t *ring; 308 /* backups for resets */ 309 uint32_t *ring_backup; 310 unsigned int ring_backup_entries_to_copy; 311 unsigned rptr_offs; 312 u64 rptr_gpu_addr; 313 u32 *rptr_cpu_addr; 314 315 /** 316 * @wptr: 317 * 318 * This is part of the Ring buffer implementation and represents the 319 * write pointer. The wptr determines where the host has written. 320 */ 321 u64 wptr; 322 323 /** 324 * @wptr_old: 325 * 326 * Before update wptr with the new value, usually the old value is 327 * stored in the wptr_old. 328 */ 329 u64 wptr_old; 330 unsigned ring_size; 331 332 /** 333 * @max_dw: 334 * 335 * Maximum number of DWords for ring allocation. This information is 336 * provided at the ring initialization time, and each IP block can 337 * specify a specific value. Check places that invoke 338 * amdgpu_ring_init() to see the maximum size per block. 339 */ 340 unsigned max_dw; 341 342 /** 343 * @count_dw: 344 * 345 * This value starts with the maximum amount of DWords supported by the 346 * ring. This value is updated based on the ring manipulation. 347 */ 348 int count_dw; 349 uint64_t gpu_addr; 350 351 /** 352 * @ptr_mask: 353 * 354 * Some IPs provide support for 64-bit pointers and others for 32-bit 355 * only; this behavior is component-specific and defined by the field 356 * support_64bit_ptr. If the IP block supports 64-bits, the mask 357 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask. 358 * Notice that this field is used to keep wptr under a valid range. 359 */ 360 uint64_t ptr_mask; 361 362 /** 363 * @buf_mask: 364 * 365 * Buffer mask is a value used to keep wptr count under its 366 * thresholding. Buffer mask initialized during the ring buffer 367 * initialization time, and it is defined as (ring_size / 4) -1. 368 */ 369 uint32_t buf_mask; 370 u32 idx; 371 u32 xcc_id; 372 u32 xcp_id; 373 u32 me; 374 u32 pipe; 375 u32 queue; 376 struct amdgpu_bo *mqd_obj; 377 uint64_t mqd_gpu_addr; 378 void *mqd_ptr; 379 unsigned mqd_size; 380 uint64_t eop_gpu_addr; 381 u32 doorbell_index; 382 bool use_doorbell; 383 bool use_pollmem; 384 unsigned wptr_offs; 385 u64 wptr_gpu_addr; 386 387 /** 388 * @wptr_cpu_addr: 389 * 390 * This is the CPU address pointer in the writeback slot. This is used 391 * to commit changes to the GPU. 392 */ 393 u32 *wptr_cpu_addr; 394 unsigned fence_offs; 395 u64 fence_gpu_addr; 396 u32 *fence_cpu_addr; 397 uint64_t current_ctx; 398 char name[16]; 399 u32 trail_seq; 400 unsigned trail_fence_offs; 401 u64 trail_fence_gpu_addr; 402 u32 *trail_fence_cpu_addr; 403 unsigned cond_exe_offs; 404 u64 cond_exe_gpu_addr; 405 u32 *cond_exe_cpu_addr; 406 unsigned int set_q_mode_offs; 407 u32 *set_q_mode_ptr; 408 u64 set_q_mode_token; 409 unsigned vm_hub; 410 unsigned vm_inv_eng; 411 struct dma_fence *vmid_wait; 412 bool has_compute_vm_bug; 413 bool no_scheduler; 414 bool no_user_submission; 415 int hw_prio; 416 unsigned num_hw_submission; 417 atomic_t *sched_score; 418 419 bool is_sw_ring; 420 unsigned int entry_index; 421 /* store the cached rptr to restore after reset */ 422 uint64_t cached_rptr; 423 }; 424 425 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 426 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 427 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 428 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 429 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 430 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 431 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 432 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 433 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 434 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 435 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 436 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 437 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 438 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 439 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 440 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 441 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 442 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 443 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 444 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 445 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 446 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 447 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a)) 448 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 449 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 450 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 451 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 452 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f)) 453 454 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 455 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 456 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 457 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 458 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 459 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 460 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 461 462 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 463 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 464 void amdgpu_ring_commit(struct amdgpu_ring *ring); 465 void amdgpu_ring_undo(struct amdgpu_ring *ring); 466 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 467 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 468 unsigned int irq_type, unsigned int hw_prio, 469 atomic_t *sched_score); 470 void amdgpu_ring_fini(struct amdgpu_ring *ring); 471 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 472 uint32_t reg0, uint32_t val0, 473 uint32_t reg1, uint32_t val1); 474 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 475 struct dma_fence *fence); 476 477 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 478 bool cond_exec) 479 { 480 *ring->cond_exe_cpu_addr = cond_exec; 481 } 482 483 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 484 { 485 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); 486 } 487 488 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 489 { 490 ring->ring[ring->wptr++ & ring->buf_mask] = v; 491 ring->wptr &= ring->ptr_mask; 492 ring->count_dw--; 493 } 494 495 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 496 void *src, int count_dw) 497 { 498 unsigned occupied, chunk1, chunk2; 499 500 occupied = ring->wptr & ring->buf_mask; 501 chunk1 = ring->buf_mask + 1 - occupied; 502 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 503 chunk2 = count_dw - chunk1; 504 chunk1 <<= 2; 505 chunk2 <<= 2; 506 507 if (chunk1) 508 memcpy(&ring->ring[occupied], src, chunk1); 509 510 if (chunk2) { 511 src += chunk1; 512 memcpy(ring->ring, src, chunk2); 513 } 514 515 ring->wptr += count_dw; 516 ring->wptr &= ring->ptr_mask; 517 ring->count_dw -= count_dw; 518 } 519 520 /** 521 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute 522 * @ring: amdgpu_ring structure 523 * @offset: offset returned by amdgpu_ring_init_cond_exec 524 * 525 * Calculate the dw count and patch it into a cond_exec command. 526 */ 527 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, 528 unsigned int offset) 529 { 530 unsigned cur; 531 532 if (!ring->funcs->init_cond_exec) 533 return; 534 535 WARN_ON(offset > ring->buf_mask); 536 WARN_ON(ring->ring[offset] != 0); 537 538 cur = (ring->wptr - 1) & ring->buf_mask; 539 if (cur < offset) 540 cur += ring->ring_size >> 2; 541 ring->ring[offset] = cur - offset; 542 } 543 544 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 545 546 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 547 struct amdgpu_ring *ring); 548 549 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 550 551 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 552 { 553 return ib->ptr[idx]; 554 } 555 556 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 557 uint32_t value) 558 { 559 ib->ptr[idx] = value; 560 } 561 562 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 563 unsigned size, 564 enum amdgpu_ib_pool_type pool, 565 struct amdgpu_ib *ib); 566 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); 567 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 568 struct amdgpu_ib *ibs, struct amdgpu_job *job, 569 struct dma_fence **f); 570 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 571 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 572 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 573 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 574 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, 575 struct amdgpu_fence *guilty_fence); 576 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 577 struct amdgpu_fence *guilty_fence); 578 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 579 struct amdgpu_fence *guilty_fence); 580 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 581 u32 reset_type); 582 #endif 583