1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_suballoc.h> 31 32 struct amdgpu_device; 33 struct amdgpu_ring; 34 struct amdgpu_ib; 35 struct amdgpu_cs_parser; 36 struct amdgpu_job; 37 struct amdgpu_vm; 38 39 /* max number of rings */ 40 #define AMDGPU_MAX_RINGS 149 41 #define AMDGPU_MAX_HWIP_RINGS 64 42 #define AMDGPU_MAX_GFX_RINGS 2 43 #define AMDGPU_MAX_SW_GFX_RINGS 2 44 #define AMDGPU_MAX_COMPUTE_RINGS 8 45 #define AMDGPU_MAX_VCE_RINGS 3 46 #define AMDGPU_MAX_UVD_ENC_RINGS 2 47 #define AMDGPU_MAX_VPE_RINGS 2 48 49 enum amdgpu_ring_priority_level { 50 AMDGPU_RING_PRIO_0, 51 AMDGPU_RING_PRIO_1, 52 AMDGPU_RING_PRIO_DEFAULT = 1, 53 AMDGPU_RING_PRIO_2, 54 AMDGPU_RING_PRIO_MAX 55 }; 56 57 /* some special values for the owner field */ 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 61 62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 63 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 65 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 66 67 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 68 69 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 70 71 enum amdgpu_ring_type { 72 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 73 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 74 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 75 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 76 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 77 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 78 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 79 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 80 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 81 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE, 82 AMDGPU_RING_TYPE_KIQ, 83 AMDGPU_RING_TYPE_MES, 84 AMDGPU_RING_TYPE_UMSCH_MM, 85 AMDGPU_RING_TYPE_CPER, 86 }; 87 88 enum amdgpu_ib_pool_type { 89 /* Normal submissions to the top of the pipeline. */ 90 AMDGPU_IB_POOL_DELAYED, 91 /* Immediate submissions to the bottom of the pipeline. */ 92 AMDGPU_IB_POOL_IMMEDIATE, 93 /* Direct submission to the ring buffer during init and reset. */ 94 AMDGPU_IB_POOL_DIRECT, 95 96 AMDGPU_IB_POOL_MAX 97 }; 98 99 struct amdgpu_ib { 100 struct drm_suballoc *sa_bo; 101 uint32_t length_dw; 102 uint64_t gpu_addr; 103 uint32_t *ptr; 104 uint32_t flags; 105 }; 106 107 struct amdgpu_sched { 108 u32 num_scheds; 109 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 110 }; 111 112 /* 113 * Fences. 114 */ 115 struct amdgpu_fence_driver { 116 uint64_t gpu_addr; 117 uint32_t *cpu_addr; 118 /* sync_seq is protected by ring emission lock */ 119 uint32_t sync_seq; 120 atomic_t last_seq; 121 u64 signalled_wptr; 122 bool initialized; 123 struct amdgpu_irq_src *irq_src; 124 unsigned irq_type; 125 struct timer_list fallback_timer; 126 unsigned num_fences_mask; 127 spinlock_t lock; 128 struct dma_fence **fences; 129 }; 130 131 /* 132 * Fences mark an event in the GPUs pipeline and are used 133 * for GPU/CPU synchronization. When the fence is written, 134 * it is expected that all buffers associated with that fence 135 * are no longer in use by the associated ring on the GPU and 136 * that the relevant GPU caches have been flushed. 137 */ 138 139 struct amdgpu_fence { 140 struct dma_fence base; 141 142 /* RB, DMA, etc. */ 143 struct amdgpu_ring *ring; 144 ktime_t start_timestamp; 145 146 /* wptr for the fence for resets */ 147 u64 wptr; 148 /* fence context for resets */ 149 u64 context; 150 }; 151 152 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 153 154 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 155 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 156 void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); 157 void amdgpu_fence_save_wptr(struct amdgpu_fence *af); 158 159 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 160 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 161 struct amdgpu_irq_src *irq_src, 162 unsigned irq_type); 163 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 164 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 165 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 166 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 167 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, 168 unsigned int flags); 169 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 170 uint32_t timeout); 171 bool amdgpu_fence_process(struct amdgpu_ring *ring); 172 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 173 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 174 uint32_t wait_seq, 175 signed long timeout); 176 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 177 178 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 179 180 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 181 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 182 ktime_t timestamp); 183 184 /* 185 * Rings. 186 */ 187 188 /* provided by hw blocks that expose a ring buffer for commands */ 189 struct amdgpu_ring_funcs { 190 /** 191 * @type: 192 * 193 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER 194 * use ring buffers. The type field just identifies which component the 195 * ring buffer is associated with. 196 */ 197 enum amdgpu_ring_type type; 198 uint32_t align_mask; 199 200 /** 201 * @nop: 202 * 203 * Every block in the amdgpu has no-op instructions (e.g., GFX 10 204 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP, 205 * etc). This field receives the specific no-op for the component 206 * that initializes the ring. 207 */ 208 u32 nop; 209 bool support_64bit_ptrs; 210 bool no_user_fence; 211 bool secure_submission_supported; 212 213 /** 214 * @extra_bytes: 215 * 216 * Optional extra space in bytes that is added to the ring size 217 * when allocating the BO that holds the contents of the ring. 218 * This space isn't used for command submission to the ring, 219 * but is just there to satisfy some hardware requirements or 220 * implement workarounds. It's up to the implementation of each 221 * specific ring to initialize this space. 222 */ 223 unsigned extra_bytes; 224 225 /* ring read/write ptr handling */ 226 u64 (*get_rptr)(struct amdgpu_ring *ring); 227 u64 (*get_wptr)(struct amdgpu_ring *ring); 228 void (*set_wptr)(struct amdgpu_ring *ring); 229 /* validating and patching of IBs */ 230 int (*parse_cs)(struct amdgpu_cs_parser *p, 231 struct amdgpu_job *job, 232 struct amdgpu_ib *ib); 233 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 234 struct amdgpu_job *job, 235 struct amdgpu_ib *ib); 236 /* constants to calculate how many DW are needed for an emit */ 237 unsigned emit_frame_size; 238 unsigned emit_ib_size; 239 /* command emit functions */ 240 void (*emit_ib)(struct amdgpu_ring *ring, 241 struct amdgpu_job *job, 242 struct amdgpu_ib *ib, 243 uint32_t flags); 244 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 245 uint64_t seq, unsigned flags); 246 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 247 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 248 uint64_t pd_addr); 249 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 250 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 251 uint32_t gds_base, uint32_t gds_size, 252 uint32_t gws_base, uint32_t gws_size, 253 uint32_t oa_base, uint32_t oa_size); 254 /* testing functions */ 255 int (*test_ring)(struct amdgpu_ring *ring); 256 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 257 /* insert NOP packets */ 258 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 259 void (*insert_start)(struct amdgpu_ring *ring); 260 void (*insert_end)(struct amdgpu_ring *ring); 261 /* pad the indirect buffer to the necessary number of dw */ 262 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 263 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr); 264 /* note usage for clock and power gating */ 265 void (*begin_use)(struct amdgpu_ring *ring); 266 void (*end_use)(struct amdgpu_ring *ring); 267 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 268 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 269 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 270 u64 gds_va, bool init_shadow, int vmid); 271 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 272 uint32_t reg_val_offs); 273 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 274 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 275 uint32_t val, uint32_t mask); 276 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 277 uint32_t reg0, uint32_t reg1, 278 uint32_t ref, uint32_t mask); 279 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 280 bool secure); 281 /* Try to soft recover the ring to make the fence signal */ 282 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 283 int (*preempt_ib)(struct amdgpu_ring *ring); 284 void (*emit_mem_sync)(struct amdgpu_ring *ring); 285 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 286 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 287 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 288 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 289 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid, 290 struct amdgpu_fence *timedout_fence); 291 void (*emit_cleaner_shader)(struct amdgpu_ring *ring); 292 }; 293 294 /** 295 * amdgpu_ring - Holds ring information 296 */ 297 struct amdgpu_ring { 298 struct amdgpu_device *adev; 299 const struct amdgpu_ring_funcs *funcs; 300 struct amdgpu_fence_driver fence_drv; 301 struct drm_gpu_scheduler sched; 302 303 struct amdgpu_bo *ring_obj; 304 uint32_t *ring; 305 /* backups for resets */ 306 uint32_t *ring_backup; 307 unsigned int ring_backup_entries_to_copy; 308 unsigned rptr_offs; 309 u64 rptr_gpu_addr; 310 u32 *rptr_cpu_addr; 311 312 /** 313 * @wptr: 314 * 315 * This is part of the Ring buffer implementation and represents the 316 * write pointer. The wptr determines where the host has written. 317 */ 318 u64 wptr; 319 320 /** 321 * @wptr_old: 322 * 323 * Before update wptr with the new value, usually the old value is 324 * stored in the wptr_old. 325 */ 326 u64 wptr_old; 327 unsigned ring_size; 328 329 /** 330 * @max_dw: 331 * 332 * Maximum number of DWords for ring allocation. This information is 333 * provided at the ring initialization time, and each IP block can 334 * specify a specific value. Check places that invoke 335 * amdgpu_ring_init() to see the maximum size per block. 336 */ 337 unsigned max_dw; 338 339 /** 340 * @count_dw: 341 * 342 * This value starts with the maximum amount of DWords supported by the 343 * ring. This value is updated based on the ring manipulation. 344 */ 345 int count_dw; 346 uint64_t gpu_addr; 347 348 /** 349 * @ptr_mask: 350 * 351 * Some IPs provide support for 64-bit pointers and others for 32-bit 352 * only; this behavior is component-specific and defined by the field 353 * support_64bit_ptr. If the IP block supports 64-bits, the mask 354 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask. 355 * Notice that this field is used to keep wptr under a valid range. 356 */ 357 uint64_t ptr_mask; 358 359 /** 360 * @buf_mask: 361 * 362 * Buffer mask is a value used to keep wptr count under its 363 * thresholding. Buffer mask initialized during the ring buffer 364 * initialization time, and it is defined as (ring_size / 4) -1. 365 */ 366 uint32_t buf_mask; 367 u32 idx; 368 u32 xcc_id; 369 u32 xcp_id; 370 u32 me; 371 u32 pipe; 372 u32 queue; 373 struct amdgpu_bo *mqd_obj; 374 uint64_t mqd_gpu_addr; 375 void *mqd_ptr; 376 unsigned mqd_size; 377 uint64_t eop_gpu_addr; 378 u32 doorbell_index; 379 bool use_doorbell; 380 bool use_pollmem; 381 unsigned wptr_offs; 382 u64 wptr_gpu_addr; 383 384 /** 385 * @wptr_cpu_addr: 386 * 387 * This is the CPU address pointer in the writeback slot. This is used 388 * to commit changes to the GPU. 389 */ 390 u32 *wptr_cpu_addr; 391 unsigned fence_offs; 392 u64 fence_gpu_addr; 393 u32 *fence_cpu_addr; 394 uint64_t current_ctx; 395 char name[16]; 396 u32 trail_seq; 397 unsigned trail_fence_offs; 398 u64 trail_fence_gpu_addr; 399 u32 *trail_fence_cpu_addr; 400 unsigned cond_exe_offs; 401 u64 cond_exe_gpu_addr; 402 u32 *cond_exe_cpu_addr; 403 unsigned int set_q_mode_offs; 404 u32 *set_q_mode_ptr; 405 u64 set_q_mode_token; 406 unsigned vm_hub; 407 unsigned vm_inv_eng; 408 struct dma_fence *vmid_wait; 409 bool has_compute_vm_bug; 410 bool no_scheduler; 411 bool no_user_submission; 412 int hw_prio; 413 unsigned num_hw_submission; 414 atomic_t *sched_score; 415 416 bool is_sw_ring; 417 unsigned int entry_index; 418 /* store the cached rptr to restore after reset */ 419 uint64_t cached_rptr; 420 }; 421 422 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 423 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 424 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 425 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 426 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 427 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 428 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 429 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 430 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 431 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 432 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 433 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 434 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 435 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 436 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 437 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 438 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 439 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 440 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 441 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 442 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 443 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 444 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a)) 445 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 446 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 447 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 448 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 449 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f)) 450 451 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 452 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 453 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 454 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 455 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 456 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 457 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 458 459 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 460 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 461 void amdgpu_ring_commit(struct amdgpu_ring *ring); 462 void amdgpu_ring_undo(struct amdgpu_ring *ring); 463 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 464 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 465 unsigned int irq_type, unsigned int hw_prio, 466 atomic_t *sched_score); 467 void amdgpu_ring_fini(struct amdgpu_ring *ring); 468 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 469 uint32_t reg0, uint32_t val0, 470 uint32_t reg1, uint32_t val1); 471 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 472 struct dma_fence *fence); 473 474 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 475 bool cond_exec) 476 { 477 *ring->cond_exe_cpu_addr = cond_exec; 478 } 479 480 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 481 { 482 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); 483 } 484 485 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 486 { 487 ring->ring[ring->wptr++ & ring->buf_mask] = v; 488 ring->wptr &= ring->ptr_mask; 489 ring->count_dw--; 490 } 491 492 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 493 void *src, int count_dw) 494 { 495 unsigned occupied, chunk1, chunk2; 496 497 occupied = ring->wptr & ring->buf_mask; 498 chunk1 = ring->buf_mask + 1 - occupied; 499 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 500 chunk2 = count_dw - chunk1; 501 chunk1 <<= 2; 502 chunk2 <<= 2; 503 504 if (chunk1) 505 memcpy(&ring->ring[occupied], src, chunk1); 506 507 if (chunk2) { 508 src += chunk1; 509 memcpy(ring->ring, src, chunk2); 510 } 511 512 ring->wptr += count_dw; 513 ring->wptr &= ring->ptr_mask; 514 ring->count_dw -= count_dw; 515 } 516 517 /** 518 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute 519 * @ring: amdgpu_ring structure 520 * @offset: offset returned by amdgpu_ring_init_cond_exec 521 * 522 * Calculate the dw count and patch it into a cond_exec command. 523 */ 524 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, 525 unsigned int offset) 526 { 527 unsigned cur; 528 529 if (!ring->funcs->init_cond_exec) 530 return; 531 532 WARN_ON(offset > ring->buf_mask); 533 WARN_ON(ring->ring[offset] != 0); 534 535 cur = (ring->wptr - 1) & ring->buf_mask; 536 if (cur < offset) 537 cur += ring->ring_size >> 2; 538 ring->ring[offset] = cur - offset; 539 } 540 541 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 542 543 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 544 struct amdgpu_ring *ring); 545 546 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 547 548 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 549 { 550 return ib->ptr[idx]; 551 } 552 553 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 554 uint32_t value) 555 { 556 ib->ptr[idx] = value; 557 } 558 559 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 560 unsigned size, 561 enum amdgpu_ib_pool_type pool, 562 struct amdgpu_ib *ib); 563 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); 564 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 565 struct amdgpu_ib *ibs, struct amdgpu_job *job, 566 struct dma_fence **f); 567 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 568 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 569 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 570 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 571 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, 572 struct amdgpu_fence *guilty_fence); 573 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 574 struct amdgpu_fence *guilty_fence); 575 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 576 struct amdgpu_fence *guilty_fence); 577 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 578 u32 reset_type); 579 #endif 580