1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_suballoc.h> 31 32 struct amdgpu_device; 33 struct amdgpu_ring; 34 struct amdgpu_ib; 35 struct amdgpu_cs_parser; 36 struct amdgpu_job; 37 struct amdgpu_vm; 38 39 /* max number of rings */ 40 #define AMDGPU_MAX_RINGS 149 41 #define AMDGPU_MAX_HWIP_RINGS 64 42 #define AMDGPU_MAX_GFX_RINGS 2 43 #define AMDGPU_MAX_SW_GFX_RINGS 2 44 #define AMDGPU_MAX_COMPUTE_RINGS 8 45 #define AMDGPU_MAX_VCE_RINGS 3 46 #define AMDGPU_MAX_UVD_ENC_RINGS 2 47 #define AMDGPU_MAX_VPE_RINGS 2 48 49 enum amdgpu_ring_priority_level { 50 AMDGPU_RING_PRIO_0, 51 AMDGPU_RING_PRIO_1, 52 AMDGPU_RING_PRIO_DEFAULT = 1, 53 AMDGPU_RING_PRIO_2, 54 AMDGPU_RING_PRIO_MAX 55 }; 56 57 /* some special values for the owner field */ 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 61 62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 63 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 65 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 66 67 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 68 69 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 70 71 enum amdgpu_ring_type { 72 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 73 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 74 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 75 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 76 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 77 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 78 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 79 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 80 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 81 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE, 82 AMDGPU_RING_TYPE_KIQ, 83 AMDGPU_RING_TYPE_MES, 84 AMDGPU_RING_TYPE_UMSCH_MM, 85 AMDGPU_RING_TYPE_CPER, 86 }; 87 88 enum amdgpu_ib_pool_type { 89 /* Normal submissions to the top of the pipeline. */ 90 AMDGPU_IB_POOL_DELAYED, 91 /* Immediate submissions to the bottom of the pipeline. */ 92 AMDGPU_IB_POOL_IMMEDIATE, 93 /* Direct submission to the ring buffer during init and reset. */ 94 AMDGPU_IB_POOL_DIRECT, 95 96 AMDGPU_IB_POOL_MAX 97 }; 98 99 struct amdgpu_ib { 100 struct drm_suballoc *sa_bo; 101 uint32_t length_dw; 102 uint64_t gpu_addr; 103 uint32_t *ptr; 104 uint32_t flags; 105 }; 106 107 struct amdgpu_sched { 108 u32 num_scheds; 109 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 110 }; 111 112 /* 113 * Fences. 114 */ 115 struct amdgpu_fence_driver { 116 uint64_t gpu_addr; 117 uint32_t *cpu_addr; 118 /* sync_seq is protected by ring emission lock */ 119 uint32_t sync_seq; 120 atomic_t last_seq; 121 u64 signalled_wptr; 122 bool initialized; 123 struct amdgpu_irq_src *irq_src; 124 unsigned irq_type; 125 struct timer_list fallback_timer; 126 unsigned num_fences_mask; 127 spinlock_t lock; 128 struct dma_fence **fences; 129 }; 130 131 /* 132 * Fences mark an event in the GPUs pipeline and are used 133 * for GPU/CPU synchronization. When the fence is written, 134 * it is expected that all buffers associated with that fence 135 * are no longer in use by the associated ring on the GPU and 136 * that the relevant GPU caches have been flushed. 137 */ 138 139 struct amdgpu_fence { 140 struct dma_fence base; 141 142 /* RB, DMA, etc. */ 143 struct amdgpu_ring *ring; 144 ktime_t start_timestamp; 145 146 /* wptr for the fence for resets */ 147 u64 wptr; 148 /* fence context for resets */ 149 u64 context; 150 uint32_t seq; 151 }; 152 153 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 154 155 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); 156 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 157 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 158 void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence); 159 void amdgpu_fence_save_wptr(struct dma_fence *fence); 160 161 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 162 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 163 struct amdgpu_irq_src *irq_src, 164 unsigned irq_type); 165 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 166 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 167 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 168 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 169 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 170 struct amdgpu_fence *af, unsigned int flags); 171 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 172 uint32_t timeout); 173 bool amdgpu_fence_process(struct amdgpu_ring *ring); 174 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 175 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 176 uint32_t wait_seq, 177 signed long timeout); 178 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 179 180 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 181 182 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 183 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 184 ktime_t timestamp); 185 186 /* 187 * Rings. 188 */ 189 190 /* provided by hw blocks that expose a ring buffer for commands */ 191 struct amdgpu_ring_funcs { 192 /** 193 * @type: 194 * 195 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER 196 * use ring buffers. The type field just identifies which component the 197 * ring buffer is associated with. 198 */ 199 enum amdgpu_ring_type type; 200 uint32_t align_mask; 201 202 /** 203 * @nop: 204 * 205 * Every block in the amdgpu has no-op instructions (e.g., GFX 10 206 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP, 207 * etc). This field receives the specific no-op for the component 208 * that initializes the ring. 209 */ 210 u32 nop; 211 bool support_64bit_ptrs; 212 bool no_user_fence; 213 bool secure_submission_supported; 214 215 /** 216 * @extra_bytes: 217 * 218 * Optional extra space in bytes that is added to the ring size 219 * when allocating the BO that holds the contents of the ring. 220 * This space isn't used for command submission to the ring, 221 * but is just there to satisfy some hardware requirements or 222 * implement workarounds. It's up to the implementation of each 223 * specific ring to initialize this space. 224 */ 225 unsigned extra_bytes; 226 227 /* ring read/write ptr handling */ 228 u64 (*get_rptr)(struct amdgpu_ring *ring); 229 u64 (*get_wptr)(struct amdgpu_ring *ring); 230 void (*set_wptr)(struct amdgpu_ring *ring); 231 /* validating and patching of IBs */ 232 int (*parse_cs)(struct amdgpu_cs_parser *p, 233 struct amdgpu_job *job, 234 struct amdgpu_ib *ib); 235 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 236 struct amdgpu_job *job, 237 struct amdgpu_ib *ib); 238 /* constants to calculate how many DW are needed for an emit */ 239 unsigned emit_frame_size; 240 unsigned emit_ib_size; 241 /* command emit functions */ 242 void (*emit_ib)(struct amdgpu_ring *ring, 243 struct amdgpu_job *job, 244 struct amdgpu_ib *ib, 245 uint32_t flags); 246 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 247 uint64_t seq, unsigned flags); 248 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 249 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 250 uint64_t pd_addr); 251 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 252 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 253 uint32_t gds_base, uint32_t gds_size, 254 uint32_t gws_base, uint32_t gws_size, 255 uint32_t oa_base, uint32_t oa_size); 256 /* testing functions */ 257 int (*test_ring)(struct amdgpu_ring *ring); 258 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 259 /* insert NOP packets */ 260 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 261 void (*insert_start)(struct amdgpu_ring *ring); 262 void (*insert_end)(struct amdgpu_ring *ring); 263 /* pad the indirect buffer to the necessary number of dw */ 264 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 265 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr); 266 /* note usage for clock and power gating */ 267 void (*begin_use)(struct amdgpu_ring *ring); 268 void (*end_use)(struct amdgpu_ring *ring); 269 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 270 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 271 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 272 u64 gds_va, bool init_shadow, int vmid); 273 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 274 uint32_t reg_val_offs); 275 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 276 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 277 uint32_t val, uint32_t mask); 278 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 279 uint32_t reg0, uint32_t reg1, 280 uint32_t ref, uint32_t mask); 281 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 282 bool secure); 283 /* Try to soft recover the ring to make the fence signal */ 284 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 285 int (*preempt_ib)(struct amdgpu_ring *ring); 286 void (*emit_mem_sync)(struct amdgpu_ring *ring); 287 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 288 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 289 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 290 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 291 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid, 292 struct amdgpu_fence *timedout_fence); 293 void (*emit_cleaner_shader)(struct amdgpu_ring *ring); 294 }; 295 296 /** 297 * amdgpu_ring - Holds ring information 298 */ 299 struct amdgpu_ring { 300 struct amdgpu_device *adev; 301 const struct amdgpu_ring_funcs *funcs; 302 struct amdgpu_fence_driver fence_drv; 303 struct drm_gpu_scheduler sched; 304 305 struct amdgpu_bo *ring_obj; 306 uint32_t *ring; 307 /* backups for resets */ 308 uint32_t *ring_backup; 309 unsigned int ring_backup_entries_to_copy; 310 unsigned rptr_offs; 311 u64 rptr_gpu_addr; 312 u32 *rptr_cpu_addr; 313 314 /** 315 * @wptr: 316 * 317 * This is part of the Ring buffer implementation and represents the 318 * write pointer. The wptr determines where the host has written. 319 */ 320 u64 wptr; 321 322 /** 323 * @wptr_old: 324 * 325 * Before update wptr with the new value, usually the old value is 326 * stored in the wptr_old. 327 */ 328 u64 wptr_old; 329 unsigned ring_size; 330 331 /** 332 * @max_dw: 333 * 334 * Maximum number of DWords for ring allocation. This information is 335 * provided at the ring initialization time, and each IP block can 336 * specify a specific value. Check places that invoke 337 * amdgpu_ring_init() to see the maximum size per block. 338 */ 339 unsigned max_dw; 340 341 /** 342 * @count_dw: 343 * 344 * This value starts with the maximum amount of DWords supported by the 345 * ring. This value is updated based on the ring manipulation. 346 */ 347 int count_dw; 348 uint64_t gpu_addr; 349 350 /** 351 * @ptr_mask: 352 * 353 * Some IPs provide support for 64-bit pointers and others for 32-bit 354 * only; this behavior is component-specific and defined by the field 355 * support_64bit_ptr. If the IP block supports 64-bits, the mask 356 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask. 357 * Notice that this field is used to keep wptr under a valid range. 358 */ 359 uint64_t ptr_mask; 360 361 /** 362 * @buf_mask: 363 * 364 * Buffer mask is a value used to keep wptr count under its 365 * thresholding. Buffer mask initialized during the ring buffer 366 * initialization time, and it is defined as (ring_size / 4) -1. 367 */ 368 uint32_t buf_mask; 369 u32 idx; 370 u32 xcc_id; 371 u32 xcp_id; 372 u32 me; 373 u32 pipe; 374 u32 queue; 375 struct amdgpu_bo *mqd_obj; 376 uint64_t mqd_gpu_addr; 377 void *mqd_ptr; 378 unsigned mqd_size; 379 uint64_t eop_gpu_addr; 380 u32 doorbell_index; 381 bool use_doorbell; 382 bool use_pollmem; 383 unsigned wptr_offs; 384 u64 wptr_gpu_addr; 385 386 /** 387 * @wptr_cpu_addr: 388 * 389 * This is the CPU address pointer in the writeback slot. This is used 390 * to commit changes to the GPU. 391 */ 392 u32 *wptr_cpu_addr; 393 unsigned fence_offs; 394 u64 fence_gpu_addr; 395 u32 *fence_cpu_addr; 396 uint64_t current_ctx; 397 char name[16]; 398 u32 trail_seq; 399 unsigned trail_fence_offs; 400 u64 trail_fence_gpu_addr; 401 u32 *trail_fence_cpu_addr; 402 unsigned cond_exe_offs; 403 u64 cond_exe_gpu_addr; 404 u32 *cond_exe_cpu_addr; 405 unsigned int set_q_mode_offs; 406 u32 *set_q_mode_ptr; 407 u64 set_q_mode_token; 408 unsigned vm_hub; 409 unsigned vm_inv_eng; 410 struct dma_fence *vmid_wait; 411 bool has_compute_vm_bug; 412 bool no_scheduler; 413 bool no_user_submission; 414 int hw_prio; 415 unsigned num_hw_submission; 416 atomic_t *sched_score; 417 418 bool is_sw_ring; 419 unsigned int entry_index; 420 /* store the cached rptr to restore after reset */ 421 uint64_t cached_rptr; 422 }; 423 424 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 425 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 426 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 427 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 428 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 429 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 430 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 431 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 432 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 433 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 434 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 435 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 436 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 437 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 438 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 439 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 440 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 441 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 442 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 443 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 444 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 445 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 446 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a)) 447 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 448 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 449 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 450 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 451 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f)) 452 453 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 454 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 455 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 456 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 457 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 458 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 459 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 460 461 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 462 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 463 void amdgpu_ring_commit(struct amdgpu_ring *ring); 464 void amdgpu_ring_undo(struct amdgpu_ring *ring); 465 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 466 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 467 unsigned int irq_type, unsigned int hw_prio, 468 atomic_t *sched_score); 469 void amdgpu_ring_fini(struct amdgpu_ring *ring); 470 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 471 uint32_t reg0, uint32_t val0, 472 uint32_t reg1, uint32_t val1); 473 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 474 struct dma_fence *fence); 475 476 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 477 bool cond_exec) 478 { 479 *ring->cond_exe_cpu_addr = cond_exec; 480 } 481 482 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 483 { 484 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); 485 } 486 487 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 488 { 489 ring->ring[ring->wptr++ & ring->buf_mask] = v; 490 ring->wptr &= ring->ptr_mask; 491 ring->count_dw--; 492 } 493 494 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 495 void *src, int count_dw) 496 { 497 unsigned occupied, chunk1, chunk2; 498 499 occupied = ring->wptr & ring->buf_mask; 500 chunk1 = ring->buf_mask + 1 - occupied; 501 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 502 chunk2 = count_dw - chunk1; 503 chunk1 <<= 2; 504 chunk2 <<= 2; 505 506 if (chunk1) 507 memcpy(&ring->ring[occupied], src, chunk1); 508 509 if (chunk2) { 510 src += chunk1; 511 memcpy(ring->ring, src, chunk2); 512 } 513 514 ring->wptr += count_dw; 515 ring->wptr &= ring->ptr_mask; 516 ring->count_dw -= count_dw; 517 } 518 519 /** 520 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute 521 * @ring: amdgpu_ring structure 522 * @offset: offset returned by amdgpu_ring_init_cond_exec 523 * 524 * Calculate the dw count and patch it into a cond_exec command. 525 */ 526 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, 527 unsigned int offset) 528 { 529 unsigned cur; 530 531 if (!ring->funcs->init_cond_exec) 532 return; 533 534 WARN_ON(offset > ring->buf_mask); 535 WARN_ON(ring->ring[offset] != 0); 536 537 cur = (ring->wptr - 1) & ring->buf_mask; 538 if (cur < offset) 539 cur += ring->ring_size >> 2; 540 ring->ring[offset] = cur - offset; 541 } 542 543 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 544 545 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 546 struct amdgpu_ring *ring); 547 548 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 549 550 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 551 { 552 return ib->ptr[idx]; 553 } 554 555 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 556 uint32_t value) 557 { 558 ib->ptr[idx] = value; 559 } 560 561 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 562 unsigned size, 563 enum amdgpu_ib_pool_type pool, 564 struct amdgpu_ib *ib); 565 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); 566 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 567 struct amdgpu_ib *ibs, struct amdgpu_job *job, 568 struct dma_fence **f); 569 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 570 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 571 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 572 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 573 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, 574 struct amdgpu_fence *guilty_fence); 575 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 576 struct amdgpu_fence *guilty_fence); 577 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 578 struct amdgpu_fence *guilty_fence); 579 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 580 u32 reset_type); 581 #endif 582