1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/debugfs.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include "amdgpu.h" 36 #include "amdgpu_ras_mgr.h" 37 #include "atom.h" 38 39 /* 40 * Rings 41 * Most engines on the GPU are fed via ring buffers. Ring 42 * buffers are areas of GPU accessible memory that the host 43 * writes commands into and the GPU reads commands out of. 44 * There is a rptr (read pointer) that determines where the 45 * GPU is currently reading, and a wptr (write pointer) 46 * which determines where the host has written. When the 47 * pointers are equal, the ring is idle. When the host 48 * writes commands to the ring buffer, it increments the 49 * wptr. The GPU then starts fetching commands and executes 50 * them until the pointers are equal again. 51 */ 52 53 /** 54 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission. 55 * 56 * @type: ring type for which to return the limit. 57 */ 58 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type) 59 { 60 switch (type) { 61 case AMDGPU_RING_TYPE_GFX: 62 /* Need to keep at least 192 on GFX7+ for old radv. */ 63 return 192; 64 case AMDGPU_RING_TYPE_COMPUTE: 65 return 125; 66 case AMDGPU_RING_TYPE_VCN_JPEG: 67 return 16; 68 default: 69 return 49; 70 } 71 } 72 73 /** 74 * amdgpu_ring_alloc - allocate space on the ring buffer 75 * 76 * @ring: amdgpu_ring structure holding ring information 77 * @ndw: number of dwords to allocate in the ring buffer 78 * 79 * Allocate @ndw dwords in the ring buffer. The number of dwords should be the 80 * sum of all commands written to the ring. 81 * 82 * Returns: 83 * 0 on success, otherwise -ENOMEM if it tries to allocate more than the 84 * maximum dword allowed for one submission. 85 */ 86 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) 87 { 88 /* Align requested size with padding so unlock_commit can 89 * pad safely */ 90 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 91 92 /* Make sure we aren't trying to allocate more space 93 * than the maximum for one submission. Skip for reemit 94 * since we may be reemitting several submissions. 95 */ 96 if (!ring->reemit) { 97 if (WARN_ON_ONCE(ndw > ring->max_dw)) 98 return -ENOMEM; 99 } 100 101 ring->count_dw = ndw; 102 ring->wptr_old = ring->wptr; 103 104 if (ring->funcs->begin_use) 105 ring->funcs->begin_use(ring); 106 107 return 0; 108 } 109 110 /** 111 * amdgpu_ring_insert_nop - insert NOP packets 112 * 113 * @ring: amdgpu_ring structure holding ring information 114 * @count: the number of NOP packets to insert 115 * 116 * This is the generic insert_nop function for rings except SDMA 117 */ 118 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 119 { 120 uint32_t occupied, chunk1, chunk2; 121 122 occupied = ring->wptr & ring->buf_mask; 123 chunk1 = ring->buf_mask + 1 - occupied; 124 chunk1 = (chunk1 >= count) ? count : chunk1; 125 chunk2 = count - chunk1; 126 127 if (chunk1) 128 memset32(&ring->ring[occupied], ring->funcs->nop, chunk1); 129 130 if (chunk2) 131 memset32(ring->ring, ring->funcs->nop, chunk2); 132 133 ring->wptr += count; 134 ring->wptr &= ring->ptr_mask; 135 ring->count_dw -= count; 136 } 137 138 /** 139 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets 140 * 141 * @ring: amdgpu_ring structure holding ring information 142 * @ib: IB to add NOP packets to 143 * 144 * This is the generic pad_ib function for rings except SDMA 145 */ 146 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 147 { 148 u32 align_mask = ring->funcs->align_mask; 149 u32 count = ib->length_dw & align_mask; 150 151 if (count) { 152 count = align_mask + 1 - count; 153 154 memset32(&ib->ptr[ib->length_dw], ring->funcs->nop, count); 155 156 ib->length_dw += count; 157 } 158 } 159 160 /** 161 * amdgpu_ring_commit - tell the GPU to execute the new 162 * commands on the ring buffer 163 * 164 * @ring: amdgpu_ring structure holding ring information 165 * 166 * Update the wptr (write pointer) to tell the GPU to 167 * execute new commands on the ring buffer (all asics). 168 */ 169 void amdgpu_ring_commit(struct amdgpu_ring *ring) 170 { 171 uint32_t count; 172 173 if (ring->count_dw < 0) 174 drm_err(adev_to_drm(ring->adev), "writing more dwords to the ring than expected!\n"); 175 176 /* We pad to match fetch size */ 177 count = ring->funcs->align_mask + 1 - 178 (ring->wptr & ring->funcs->align_mask); 179 count &= ring->funcs->align_mask; 180 181 if (count != 0) 182 ring->funcs->insert_nop(ring, count); 183 184 mb(); 185 amdgpu_ring_set_wptr(ring); 186 187 if (ring->funcs->end_use) 188 ring->funcs->end_use(ring); 189 } 190 191 /** 192 * amdgpu_ring_undo - reset the wptr 193 * 194 * @ring: amdgpu_ring structure holding ring information 195 * 196 * Reset the driver's copy of the wptr (all asics). 197 */ 198 void amdgpu_ring_undo(struct amdgpu_ring *ring) 199 { 200 ring->wptr = ring->wptr_old; 201 202 if (ring->funcs->end_use) 203 ring->funcs->end_use(ring); 204 } 205 206 #define amdgpu_ring_get_gpu_addr(ring, offset) \ 207 (ring->adev->wb.gpu_addr + offset * 4) 208 209 #define amdgpu_ring_get_cpu_addr(ring, offset) \ 210 (&ring->adev->wb.wb[offset]) 211 212 /** 213 * amdgpu_ring_init - init driver ring struct. 214 * 215 * @adev: amdgpu_device pointer 216 * @ring: amdgpu_ring structure holding ring information 217 * @max_dw: maximum number of dw for ring alloc 218 * @irq_src: interrupt source to use for this ring 219 * @irq_type: interrupt type to use for this ring 220 * @hw_prio: ring priority (NORMAL/HIGH) 221 * @sched_score: optional score atomic shared with other schedulers 222 * 223 * Initialize the driver information for the selected ring (all asics). 224 * Returns 0 on success, error on failure. 225 */ 226 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 227 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 228 unsigned int irq_type, unsigned int hw_prio, 229 atomic_t *sched_score) 230 { 231 int r; 232 int sched_hw_submission = amdgpu_sched_hw_submission; 233 u32 *num_sched; 234 u32 hw_ip; 235 unsigned int max_ibs_dw; 236 237 /* Set the hw submission limit higher for KIQ because 238 * it's used for a number of gfx/compute tasks by both 239 * KFD and KGD which may have outstanding fences and 240 * it doesn't really use the gpu scheduler anyway; 241 * KIQ tasks get submitted directly to the ring. 242 */ 243 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 244 sched_hw_submission = max(sched_hw_submission, 256); 245 if (ring->funcs->type == AMDGPU_RING_TYPE_MES) 246 sched_hw_submission = 8; 247 else if (ring == &adev->sdma.instance[0].page) 248 sched_hw_submission = 256; 249 250 if (ring->adev == NULL) { 251 if (adev->num_rings >= AMDGPU_MAX_RINGS) 252 return -EINVAL; 253 254 ring->adev = adev; 255 ring->num_hw_submission = sched_hw_submission; 256 ring->sched_score = sched_score; 257 ring->vmid_wait = dma_fence_get_stub(); 258 259 ring->idx = adev->num_rings++; 260 adev->rings[ring->idx] = ring; 261 262 r = amdgpu_fence_driver_init_ring(ring); 263 if (r) 264 return r; 265 } 266 267 r = amdgpu_device_wb_get(adev, &ring->rptr_offs); 268 if (r) { 269 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); 270 return r; 271 } 272 273 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); 274 if (r) { 275 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); 276 return r; 277 } 278 279 r = amdgpu_device_wb_get(adev, &ring->fence_offs); 280 if (r) { 281 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); 282 return r; 283 } 284 285 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs); 286 if (r) { 287 dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r); 288 return r; 289 } 290 291 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); 292 if (r) { 293 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); 294 return r; 295 } 296 297 ring->fence_gpu_addr = 298 amdgpu_ring_get_gpu_addr(ring, ring->fence_offs); 299 ring->fence_cpu_addr = 300 amdgpu_ring_get_cpu_addr(ring, ring->fence_offs); 301 302 ring->rptr_gpu_addr = 303 amdgpu_ring_get_gpu_addr(ring, ring->rptr_offs); 304 ring->rptr_cpu_addr = 305 amdgpu_ring_get_cpu_addr(ring, ring->rptr_offs); 306 307 ring->wptr_gpu_addr = 308 amdgpu_ring_get_gpu_addr(ring, ring->wptr_offs); 309 ring->wptr_cpu_addr = 310 amdgpu_ring_get_cpu_addr(ring, ring->wptr_offs); 311 312 ring->trail_fence_gpu_addr = 313 amdgpu_ring_get_gpu_addr(ring, ring->trail_fence_offs); 314 ring->trail_fence_cpu_addr = 315 amdgpu_ring_get_cpu_addr(ring, ring->trail_fence_offs); 316 317 ring->cond_exe_gpu_addr = 318 amdgpu_ring_get_gpu_addr(ring, ring->cond_exe_offs); 319 ring->cond_exe_cpu_addr = 320 amdgpu_ring_get_cpu_addr(ring, ring->cond_exe_offs); 321 322 /* always set cond_exec_polling to CONTINUE */ 323 *ring->cond_exe_cpu_addr = 1; 324 325 if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) { 326 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); 327 if (r) { 328 dev_err(adev->dev, "failed initializing fences (%d).\n", r); 329 return r; 330 } 331 332 max_ibs_dw = ring->funcs->emit_frame_size + 333 amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size; 334 max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 335 336 if (WARN_ON(max_ibs_dw > max_dw)) 337 max_dw = max_ibs_dw; 338 339 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); 340 } else { 341 ring->ring_size = roundup_pow_of_two(max_dw * 4); 342 ring->count_dw = (ring->ring_size - 4) >> 2; 343 /* ring buffer is empty now */ 344 ring->wptr = *ring->rptr_cpu_addr = 0; 345 } 346 347 ring->buf_mask = (ring->ring_size / 4) - 1; 348 ring->ptr_mask = ring->funcs->support_64bit_ptrs ? 349 0xffffffffffffffff : ring->buf_mask; 350 /* Initialize cached_rptr to 0 */ 351 ring->cached_rptr = 0; 352 353 if (!ring->ring_backup) { 354 ring->ring_backup = kvzalloc(ring->ring_size, GFP_KERNEL); 355 if (!ring->ring_backup) 356 return -ENOMEM; 357 } 358 359 /* Allocate ring buffer */ 360 if (ring->ring_obj == NULL) { 361 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_bytes, 362 PAGE_SIZE, 363 AMDGPU_GEM_DOMAIN_GTT, 364 &ring->ring_obj, 365 &ring->gpu_addr, 366 (void **)&ring->ring); 367 if (r) { 368 dev_err(adev->dev, "(%d) ring create failed\n", r); 369 kvfree(ring->ring_backup); 370 return r; 371 } 372 amdgpu_ring_clear_ring(ring); 373 } 374 375 ring->max_dw = max_dw; 376 ring->hw_prio = hw_prio; 377 378 if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM) { 379 hw_ip = ring->funcs->type; 380 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds; 381 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] = 382 &ring->sched; 383 } 384 385 return 0; 386 } 387 388 /** 389 * amdgpu_ring_fini - tear down the driver ring struct. 390 * 391 * @ring: amdgpu_ring structure holding ring information 392 * 393 * Tear down the driver information for the selected ring (all asics). 394 */ 395 void amdgpu_ring_fini(struct amdgpu_ring *ring) 396 { 397 398 /* Not to finish a ring which is not initialized */ 399 if (!(ring->adev) || !(ring->adev->rings[ring->idx])) 400 return; 401 402 ring->sched.ready = false; 403 404 amdgpu_device_wb_free(ring->adev, ring->rptr_offs); 405 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); 406 407 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); 408 amdgpu_device_wb_free(ring->adev, ring->fence_offs); 409 410 amdgpu_bo_free_kernel(&ring->ring_obj, 411 &ring->gpu_addr, 412 (void **)&ring->ring); 413 kvfree(ring->ring_backup); 414 ring->ring_backup = NULL; 415 416 dma_fence_put(ring->vmid_wait); 417 ring->vmid_wait = NULL; 418 ring->me = 0; 419 } 420 421 /** 422 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper 423 * 424 * @ring: ring to write to 425 * @reg0: register to write 426 * @reg1: register to wait on 427 * @ref: reference value to write/wait on 428 * @mask: mask to wait on 429 * 430 * Helper for rings that don't support write and wait in a 431 * single oneshot packet. 432 */ 433 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 434 uint32_t reg0, uint32_t reg1, 435 uint32_t ref, uint32_t mask) 436 { 437 amdgpu_ring_emit_wreg(ring, reg0, ref); 438 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 439 } 440 441 /** 442 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup 443 * 444 * @ring: ring to try the recovery on 445 * @vmid: VMID we try to get going again 446 * @fence: timedout fence 447 * 448 * Tries to get a ring proceeding again when it is stuck. 449 */ 450 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 451 struct dma_fence *fence) 452 { 453 unsigned long flags; 454 ktime_t deadline; 455 bool ret; 456 457 deadline = ktime_add_us(ktime_get(), 10000); 458 459 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) 460 return false; 461 462 dma_fence_lock_irqsave(fence, flags); 463 if (!dma_fence_is_signaled_locked(fence)) 464 dma_fence_set_error(fence, -ENODATA); 465 dma_fence_unlock_irqrestore(fence, flags); 466 467 while (!dma_fence_is_signaled(fence) && 468 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) 469 ring->funcs->soft_recovery(ring, vmid); 470 471 ret = dma_fence_is_signaled(fence); 472 /* increment the counter only if soft reset worked */ 473 if (ret) 474 atomic_inc(&ring->adev->gpu_reset_counter); 475 476 return ret; 477 } 478 479 /* 480 * Debugfs info 481 */ 482 #if defined(CONFIG_DEBUG_FS) 483 484 static ssize_t amdgpu_ras_cper_debugfs_read(struct file *f, char __user *buf, 485 size_t size, loff_t *offset) 486 { 487 const u8 ring_header_size = 12; 488 struct amdgpu_ring *ring = file_inode(f)->i_private; 489 struct ras_cmd_cper_snapshot_req *snapshot_req __free(kfree) = 490 kzalloc_obj(struct ras_cmd_cper_snapshot_req); 491 struct ras_cmd_cper_snapshot_rsp *snapshot_rsp __free(kfree) = 492 kzalloc_obj(struct ras_cmd_cper_snapshot_rsp); 493 struct ras_cmd_cper_record_req *record_req __free(kfree) = 494 kzalloc_obj(struct ras_cmd_cper_record_req); 495 struct ras_cmd_cper_record_rsp *record_rsp __free(kfree) = 496 kzalloc_obj(struct ras_cmd_cper_record_rsp); 497 u32 *ring_header __free(kfree) = 498 kzalloc(ring_header_size, GFP_KERNEL); 499 char __user *data_buf = buf; 500 size_t data_size = size; 501 u32 total_cper_num; 502 u64 start_cper_id; 503 u64 cper_offset; 504 size_t chunk_size; 505 size_t total_data_size = 0; 506 bool read_header; 507 int r; 508 509 if (!snapshot_req || !snapshot_rsp || !record_req || !record_rsp || 510 !ring_header) 511 return -ENOMEM; 512 513 read_header = !(*offset); 514 cper_offset = read_header ? 0 : *offset - 1; 515 516 if (read_header) { 517 /* Need at least 12 bytes for the header on the first read */ 518 if (size < ring_header_size) 519 return -EINVAL; 520 data_buf += ring_header_size; 521 data_size -= ring_header_size; 522 } 523 524 r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, 525 RAS_CMD__GET_CPER_SNAPSHOT, 526 snapshot_req, sizeof(struct ras_cmd_cper_snapshot_req), 527 snapshot_rsp, sizeof(struct ras_cmd_cper_snapshot_rsp)); 528 if (r) 529 return r; 530 531 if (!snapshot_rsp->total_cper_num) { 532 if (!read_header) 533 return 0; 534 535 if (copy_to_user(buf, ring_header, ring_header_size)) 536 return -EFAULT; 537 538 *offset = 1; 539 return ring_header_size; 540 } 541 542 start_cper_id = snapshot_rsp->start_cper_id; 543 total_cper_num = snapshot_rsp->total_cper_num; 544 if (read_header && !data_size) { 545 if (copy_to_user(buf, ring_header, ring_header_size)) 546 return -EFAULT; 547 548 *offset = cper_offset + 1; 549 return ring_header_size; 550 } 551 552 if (!data_size) 553 return 0; 554 555 while (data_size && cper_offset < total_cper_num) { 556 memset(record_req, 0, sizeof(*record_req)); 557 memset(record_rsp, 0, sizeof(*record_rsp)); 558 chunk_size = min_t(size_t, data_size, RAS_CMD_MAX_CPER_BUF_SZ); 559 560 record_req->buf_ptr = (u64)(uintptr_t)data_buf; 561 record_req->buf_size = chunk_size; 562 record_req->cper_start_id = start_cper_id + cper_offset; 563 record_req->cper_num = total_cper_num - cper_offset; 564 r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, 565 RAS_CMD__GET_CPER_RECORD, 566 record_req, 567 sizeof(struct ras_cmd_cper_record_req), 568 record_rsp, 569 sizeof(struct ras_cmd_cper_record_rsp)); 570 if (r) 571 return r; 572 573 if (!record_rsp->real_data_size || !record_rsp->real_cper_num) 574 break; 575 if (record_rsp->real_data_size > data_size) 576 return -EIO; 577 578 data_buf += record_rsp->real_data_size; 579 data_size -= record_rsp->real_data_size; 580 total_data_size += record_rsp->real_data_size; 581 cper_offset += record_rsp->real_cper_num; 582 } 583 584 if (read_header) { 585 ring_header[1] = total_data_size >> 2; 586 ring_header[2] = ring_header[1]; 587 588 if (copy_to_user(buf, ring_header, ring_header_size)) 589 return -EFAULT; 590 } 591 592 r = read_header ? total_data_size + ring_header_size : total_data_size; 593 *offset = cper_offset + 1; 594 595 return r; 596 } 597 598 /* Layout of file is 12 bytes consisting of 599 * - rptr 600 * - wptr 601 * - driver's copy of wptr 602 * 603 * followed by n-words of ring data 604 */ 605 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, 606 size_t size, loff_t *pos) 607 { 608 struct amdgpu_ring *ring = file_inode(f)->i_private; 609 u32 value, result, early[3] = { 0 }; 610 uint64_t p; 611 u32 avail_dw, start_dw, read_dw; 612 loff_t i; 613 int r; 614 615 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER && amdgpu_uniras_enabled(ring->adev)) 616 return amdgpu_ras_cper_debugfs_read(f, buf, size, pos); 617 618 if (*pos & 3 || size & 3) 619 return -EINVAL; 620 621 result = 0; 622 623 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 624 mutex_lock(&ring->adev->cper.ring_lock); 625 626 if (*pos < 12) { 627 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; 628 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; 629 early[2] = ring->wptr & ring->buf_mask; 630 for (i = *pos / 4; i < 3 && size; i++) { 631 r = put_user(early[i], (uint32_t *)buf); 632 if (r) { 633 result = r; 634 goto out; 635 } 636 buf += 4; 637 result += 4; 638 size -= 4; 639 *pos += 4; 640 } 641 } 642 643 if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) { 644 while (size) { 645 if (*pos >= (ring->ring_size + 12)) 646 return result; 647 648 value = ring->ring[(*pos - 12)/4]; 649 r = put_user(value, (uint32_t *)buf); 650 if (r) 651 return r; 652 buf += 4; 653 result += 4; 654 size -= 4; 655 *pos += 4; 656 } 657 } else { 658 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; 659 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; 660 661 p = early[0]; 662 if (early[0] <= early[1]) 663 avail_dw = early[1] - early[0]; 664 else 665 avail_dw = ring->buf_mask + 1 - (early[0] - early[1]); 666 667 start_dw = (*pos > 12) ? ((*pos - 12) >> 2) : 0; 668 if (start_dw >= avail_dw) 669 goto out; 670 671 p = (p + start_dw) & ring->ptr_mask; 672 avail_dw -= start_dw; 673 read_dw = min_t(u32, avail_dw, size >> 2); 674 675 while (read_dw) { 676 if (p == early[1]) 677 goto out; 678 679 value = ring->ring[p]; 680 r = put_user(value, (uint32_t *)buf); 681 if (r) { 682 result = r; 683 goto out; 684 } 685 686 buf += 4; 687 result += 4; 688 read_dw--; 689 p++; 690 p &= ring->ptr_mask; 691 *pos += 4; 692 } 693 } 694 695 out: 696 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 697 mutex_unlock(&ring->adev->cper.ring_lock); 698 699 return result; 700 } 701 702 static ssize_t amdgpu_debugfs_virt_ring_read(struct file *f, char __user *buf, 703 size_t size, loff_t *pos) 704 { 705 struct amdgpu_ring *ring = file_inode(f)->i_private; 706 707 if (*pos & 3 || size & 3) 708 return -EINVAL; 709 710 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 711 amdgpu_virt_req_ras_cper_dump(ring->adev, false); 712 713 return amdgpu_debugfs_ring_read(f, buf, size, pos); 714 } 715 716 static const struct file_operations amdgpu_debugfs_ring_fops = { 717 .owner = THIS_MODULE, 718 .read = amdgpu_debugfs_ring_read, 719 .llseek = default_llseek 720 }; 721 722 static const struct file_operations amdgpu_debugfs_virt_ring_fops = { 723 .owner = THIS_MODULE, 724 .read = amdgpu_debugfs_virt_ring_read, 725 .llseek = default_llseek 726 }; 727 728 static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf, 729 size_t size, loff_t *pos) 730 { 731 struct amdgpu_ring *ring = file_inode(f)->i_private; 732 ssize_t bytes = min_t(ssize_t, ring->mqd_size - *pos, size); 733 void *from = ((u8 *)ring->mqd_ptr) + *pos; 734 735 if (*pos > ring->mqd_size) 736 return 0; 737 738 if (copy_to_user(buf, from, bytes)) 739 return -EFAULT; 740 741 *pos += bytes; 742 return bytes; 743 } 744 745 static const struct file_operations amdgpu_debugfs_mqd_fops = { 746 .owner = THIS_MODULE, 747 .read = amdgpu_debugfs_mqd_read, 748 .llseek = default_llseek 749 }; 750 751 static int amdgpu_debugfs_ring_error(void *data, u64 val) 752 { 753 struct amdgpu_ring *ring = data; 754 755 amdgpu_fence_driver_set_error(ring, val); 756 return 0; 757 } 758 759 DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, 760 amdgpu_debugfs_ring_error, "%lld\n"); 761 762 #endif 763 764 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 765 struct amdgpu_ring *ring) 766 { 767 #if defined(CONFIG_DEBUG_FS) 768 struct drm_minor *minor = adev_to_drm(adev)->primary; 769 struct dentry *root = minor->debugfs_root; 770 char name[32]; 771 772 sprintf(name, "amdgpu_ring_%s", ring->name); 773 if (amdgpu_sriov_vf(adev)) 774 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 775 &amdgpu_debugfs_virt_ring_fops, 776 ring->ring_size + 12); 777 else 778 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 779 &amdgpu_debugfs_ring_fops, 780 ring->ring_size + 12); 781 782 if (ring->mqd_obj) { 783 sprintf(name, "amdgpu_mqd_%s", ring->name); 784 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 785 &amdgpu_debugfs_mqd_fops, 786 ring->mqd_size); 787 } 788 789 sprintf(name, "amdgpu_error_%s", ring->name); 790 debugfs_create_file(name, 0200, root, ring, 791 &amdgpu_debugfs_error_fops); 792 793 #endif 794 } 795 796 /** 797 * amdgpu_ring_test_helper - tests ring and set sched readiness status 798 * 799 * @ring: ring to try the recovery on 800 * 801 * Tests ring and set sched readiness status 802 * 803 * Returns 0 on success, error on failure. 804 */ 805 int amdgpu_ring_test_helper(struct amdgpu_ring *ring) 806 { 807 struct amdgpu_device *adev = ring->adev; 808 int r; 809 810 r = amdgpu_ring_test_ring(ring); 811 if (r) 812 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n", 813 ring->name, r); 814 else 815 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n", 816 ring->name); 817 818 ring->sched.ready = !r; 819 820 return r; 821 } 822 823 static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, 824 struct amdgpu_mqd_prop *prop) 825 { 826 struct amdgpu_device *adev = ring->adev; 827 bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && 828 amdgpu_gfx_is_high_priority_compute_queue(adev, ring); 829 bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX && 830 amdgpu_gfx_is_high_priority_graphics_queue(adev, ring); 831 832 memset(prop, 0, sizeof(*prop)); 833 834 prop->mqd_gpu_addr = ring->mqd_gpu_addr; 835 prop->hqd_base_gpu_addr = ring->gpu_addr; 836 prop->rptr_gpu_addr = ring->rptr_gpu_addr; 837 prop->wptr_gpu_addr = ring->wptr_gpu_addr; 838 prop->queue_size = ring->ring_size; 839 prop->eop_gpu_addr = ring->eop_gpu_addr; 840 prop->use_doorbell = ring->use_doorbell; 841 prop->doorbell_index = ring->doorbell_index; 842 prop->kernel_queue = true; 843 844 /* map_queues packet doesn't need activate the queue, 845 * so only kiq need set this field. 846 */ 847 prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; 848 849 prop->allow_tunneling = is_high_prio_compute; 850 if (is_high_prio_compute || is_high_prio_gfx) { 851 prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 852 prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 853 } 854 } 855 856 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring) 857 { 858 struct amdgpu_device *adev = ring->adev; 859 struct amdgpu_mqd *mqd_mgr; 860 struct amdgpu_mqd_prop prop; 861 862 amdgpu_ring_to_mqd_prop(ring, &prop); 863 864 ring->wptr = 0; 865 866 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 867 mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE]; 868 else 869 mqd_mgr = &adev->mqds[ring->funcs->type]; 870 871 return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop); 872 } 873 874 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring) 875 { 876 if (ring->is_sw_ring) 877 amdgpu_sw_ring_ib_begin(ring); 878 } 879 880 void amdgpu_ring_ib_end(struct amdgpu_ring *ring) 881 { 882 if (ring->is_sw_ring) 883 amdgpu_sw_ring_ib_end(ring); 884 } 885 886 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring) 887 { 888 if (ring->is_sw_ring) 889 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL); 890 } 891 892 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring) 893 { 894 if (ring->is_sw_ring) 895 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE); 896 } 897 898 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring) 899 { 900 if (ring->is_sw_ring) 901 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); 902 } 903 904 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) 905 { 906 if (!ring) 907 return false; 908 909 if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched)) 910 return false; 911 912 return true; 913 } 914 915 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 916 struct amdgpu_fence *guilty_fence) 917 { 918 /* back up the non-guilty commands */ 919 amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence); 920 } 921 922 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 923 struct amdgpu_fence *guilty_fence) 924 { 925 int r; 926 927 /* verify that the ring is functional */ 928 r = amdgpu_ring_test_ring(ring); 929 if (r) 930 return r; 931 932 /* set an error on all fences from the context and reemit */ 933 amdgpu_ring_set_fence_errors_and_reemit(ring, guilty_fence); 934 935 return 0; 936 } 937 938 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 939 u32 reset_type) 940 { 941 switch (ring->funcs->type) { 942 case AMDGPU_RING_TYPE_GFX: 943 if (ring->adev->gfx.gfx_supported_reset & reset_type) 944 return true; 945 break; 946 case AMDGPU_RING_TYPE_COMPUTE: 947 if (ring->adev->gfx.compute_supported_reset & reset_type) 948 return true; 949 break; 950 case AMDGPU_RING_TYPE_SDMA: 951 if (ring->adev->sdma.supported_reset & reset_type) 952 return true; 953 break; 954 case AMDGPU_RING_TYPE_VCN_DEC: 955 case AMDGPU_RING_TYPE_VCN_ENC: 956 if (ring->adev->vcn.supported_reset & reset_type) 957 return true; 958 break; 959 case AMDGPU_RING_TYPE_VCN_JPEG: 960 if (ring->adev->jpeg.supported_reset & reset_type) 961 return true; 962 break; 963 default: 964 break; 965 } 966 return false; 967 } 968