1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/debugfs.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include "amdgpu.h" 36 #include "atom.h" 37 38 /* 39 * Rings 40 * Most engines on the GPU are fed via ring buffers. Ring 41 * buffers are areas of GPU accessible memory that the host 42 * writes commands into and the GPU reads commands out of. 43 * There is a rptr (read pointer) that determines where the 44 * GPU is currently reading, and a wptr (write pointer) 45 * which determines where the host has written. When the 46 * pointers are equal, the ring is idle. When the host 47 * writes commands to the ring buffer, it increments the 48 * wptr. The GPU then starts fetching commands and executes 49 * them until the pointers are equal again. 50 */ 51 52 /** 53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission. 54 * 55 * @type: ring type for which to return the limit. 56 */ 57 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type) 58 { 59 switch (type) { 60 case AMDGPU_RING_TYPE_GFX: 61 /* Need to keep at least 192 on GFX7+ for old radv. */ 62 return 192; 63 case AMDGPU_RING_TYPE_COMPUTE: 64 return 125; 65 case AMDGPU_RING_TYPE_VCN_JPEG: 66 return 16; 67 default: 68 return 49; 69 } 70 } 71 72 /** 73 * amdgpu_ring_alloc - allocate space on the ring buffer 74 * 75 * @ring: amdgpu_ring structure holding ring information 76 * @ndw: number of dwords to allocate in the ring buffer 77 * 78 * Allocate @ndw dwords in the ring buffer (all asics). 79 * Returns 0 on success, error on failure. 80 */ 81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) 82 { 83 /* Align requested size with padding so unlock_commit can 84 * pad safely */ 85 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 86 87 /* Make sure we aren't trying to allocate more space 88 * than the maximum for one submission 89 */ 90 if (WARN_ON_ONCE(ndw > ring->max_dw)) 91 return -ENOMEM; 92 93 ring->count_dw = ndw; 94 ring->wptr_old = ring->wptr; 95 96 if (ring->funcs->begin_use) 97 ring->funcs->begin_use(ring); 98 99 return 0; 100 } 101 102 /** amdgpu_ring_insert_nop - insert NOP packets 103 * 104 * @ring: amdgpu_ring structure holding ring information 105 * @count: the number of NOP packets to insert 106 * 107 * This is the generic insert_nop function for rings except SDMA 108 */ 109 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 110 { 111 uint32_t occupied, chunk1, chunk2; 112 113 occupied = ring->wptr & ring->buf_mask; 114 chunk1 = ring->buf_mask + 1 - occupied; 115 chunk1 = (chunk1 >= count) ? count : chunk1; 116 chunk2 = count - chunk1; 117 118 if (chunk1) 119 memset32(&ring->ring[occupied], ring->funcs->nop, chunk1); 120 121 if (chunk2) 122 memset32(ring->ring, ring->funcs->nop, chunk2); 123 124 ring->wptr += count; 125 ring->wptr &= ring->ptr_mask; 126 ring->count_dw -= count; 127 } 128 129 /** 130 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets 131 * 132 * @ring: amdgpu_ring structure holding ring information 133 * @ib: IB to add NOP packets to 134 * 135 * This is the generic pad_ib function for rings except SDMA 136 */ 137 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 138 { 139 while (ib->length_dw & ring->funcs->align_mask) 140 ib->ptr[ib->length_dw++] = ring->funcs->nop; 141 } 142 143 /** 144 * amdgpu_ring_commit - tell the GPU to execute the new 145 * commands on the ring buffer 146 * 147 * @ring: amdgpu_ring structure holding ring information 148 * 149 * Update the wptr (write pointer) to tell the GPU to 150 * execute new commands on the ring buffer (all asics). 151 */ 152 void amdgpu_ring_commit(struct amdgpu_ring *ring) 153 { 154 uint32_t count; 155 156 if (ring->count_dw < 0) 157 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 158 159 /* We pad to match fetch size */ 160 count = ring->funcs->align_mask + 1 - 161 (ring->wptr & ring->funcs->align_mask); 162 count &= ring->funcs->align_mask; 163 164 if (count != 0) 165 ring->funcs->insert_nop(ring, count); 166 167 mb(); 168 amdgpu_ring_set_wptr(ring); 169 170 if (ring->funcs->end_use) 171 ring->funcs->end_use(ring); 172 } 173 174 /** 175 * amdgpu_ring_undo - reset the wptr 176 * 177 * @ring: amdgpu_ring structure holding ring information 178 * 179 * Reset the driver's copy of the wptr (all asics). 180 */ 181 void amdgpu_ring_undo(struct amdgpu_ring *ring) 182 { 183 ring->wptr = ring->wptr_old; 184 185 if (ring->funcs->end_use) 186 ring->funcs->end_use(ring); 187 } 188 189 #define amdgpu_ring_get_gpu_addr(ring, offset) \ 190 (ring->adev->wb.gpu_addr + offset * 4) 191 192 #define amdgpu_ring_get_cpu_addr(ring, offset) \ 193 (&ring->adev->wb.wb[offset]) 194 195 /** 196 * amdgpu_ring_init - init driver ring struct. 197 * 198 * @adev: amdgpu_device pointer 199 * @ring: amdgpu_ring structure holding ring information 200 * @max_dw: maximum number of dw for ring alloc 201 * @irq_src: interrupt source to use for this ring 202 * @irq_type: interrupt type to use for this ring 203 * @hw_prio: ring priority (NORMAL/HIGH) 204 * @sched_score: optional score atomic shared with other schedulers 205 * 206 * Initialize the driver information for the selected ring (all asics). 207 * Returns 0 on success, error on failure. 208 */ 209 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 210 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 211 unsigned int irq_type, unsigned int hw_prio, 212 atomic_t *sched_score) 213 { 214 int r; 215 int sched_hw_submission = amdgpu_sched_hw_submission; 216 u32 *num_sched; 217 u32 hw_ip; 218 unsigned int max_ibs_dw; 219 220 /* Set the hw submission limit higher for KIQ because 221 * it's used for a number of gfx/compute tasks by both 222 * KFD and KGD which may have outstanding fences and 223 * it doesn't really use the gpu scheduler anyway; 224 * KIQ tasks get submitted directly to the ring. 225 */ 226 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 227 sched_hw_submission = max(sched_hw_submission, 256); 228 if (ring->funcs->type == AMDGPU_RING_TYPE_MES) 229 sched_hw_submission = 8; 230 else if (ring == &adev->sdma.instance[0].page) 231 sched_hw_submission = 256; 232 233 if (ring->adev == NULL) { 234 if (adev->num_rings >= AMDGPU_MAX_RINGS) 235 return -EINVAL; 236 237 ring->adev = adev; 238 ring->num_hw_submission = sched_hw_submission; 239 ring->sched_score = sched_score; 240 ring->vmid_wait = dma_fence_get_stub(); 241 242 ring->idx = adev->num_rings++; 243 adev->rings[ring->idx] = ring; 244 245 r = amdgpu_fence_driver_init_ring(ring); 246 if (r) 247 return r; 248 } 249 250 r = amdgpu_device_wb_get(adev, &ring->rptr_offs); 251 if (r) { 252 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); 253 return r; 254 } 255 256 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); 257 if (r) { 258 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); 259 return r; 260 } 261 262 r = amdgpu_device_wb_get(adev, &ring->fence_offs); 263 if (r) { 264 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); 265 return r; 266 } 267 268 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs); 269 if (r) { 270 dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r); 271 return r; 272 } 273 274 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); 275 if (r) { 276 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); 277 return r; 278 } 279 280 ring->fence_gpu_addr = 281 amdgpu_ring_get_gpu_addr(ring, ring->fence_offs); 282 ring->fence_cpu_addr = 283 amdgpu_ring_get_cpu_addr(ring, ring->fence_offs); 284 285 ring->rptr_gpu_addr = 286 amdgpu_ring_get_gpu_addr(ring, ring->rptr_offs); 287 ring->rptr_cpu_addr = 288 amdgpu_ring_get_cpu_addr(ring, ring->rptr_offs); 289 290 ring->wptr_gpu_addr = 291 amdgpu_ring_get_gpu_addr(ring, ring->wptr_offs); 292 ring->wptr_cpu_addr = 293 amdgpu_ring_get_cpu_addr(ring, ring->wptr_offs); 294 295 ring->trail_fence_gpu_addr = 296 amdgpu_ring_get_gpu_addr(ring, ring->trail_fence_offs); 297 ring->trail_fence_cpu_addr = 298 amdgpu_ring_get_cpu_addr(ring, ring->trail_fence_offs); 299 300 ring->cond_exe_gpu_addr = 301 amdgpu_ring_get_gpu_addr(ring, ring->cond_exe_offs); 302 ring->cond_exe_cpu_addr = 303 amdgpu_ring_get_cpu_addr(ring, ring->cond_exe_offs); 304 305 /* always set cond_exec_polling to CONTINUE */ 306 *ring->cond_exe_cpu_addr = 1; 307 308 if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) { 309 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); 310 if (r) { 311 dev_err(adev->dev, "failed initializing fences (%d).\n", r); 312 return r; 313 } 314 315 max_ibs_dw = ring->funcs->emit_frame_size + 316 amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size; 317 max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 318 319 if (WARN_ON(max_ibs_dw > max_dw)) 320 max_dw = max_ibs_dw; 321 322 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); 323 } else { 324 ring->ring_size = roundup_pow_of_two(max_dw * 4); 325 ring->count_dw = (ring->ring_size - 4) >> 2; 326 /* ring buffer is empty now */ 327 ring->wptr = *ring->rptr_cpu_addr = 0; 328 } 329 330 ring->buf_mask = (ring->ring_size / 4) - 1; 331 ring->ptr_mask = ring->funcs->support_64bit_ptrs ? 332 0xffffffffffffffff : ring->buf_mask; 333 /* Initialize cached_rptr to 0 */ 334 ring->cached_rptr = 0; 335 336 /* Allocate ring buffer */ 337 if (ring->ring_obj == NULL) { 338 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE, 339 AMDGPU_GEM_DOMAIN_GTT, 340 &ring->ring_obj, 341 &ring->gpu_addr, 342 (void **)&ring->ring); 343 if (r) { 344 dev_err(adev->dev, "(%d) ring create failed\n", r); 345 return r; 346 } 347 amdgpu_ring_clear_ring(ring); 348 } 349 350 ring->max_dw = max_dw; 351 ring->hw_prio = hw_prio; 352 353 if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM) { 354 hw_ip = ring->funcs->type; 355 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds; 356 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] = 357 &ring->sched; 358 } 359 360 return 0; 361 } 362 363 /** 364 * amdgpu_ring_fini - tear down the driver ring struct. 365 * 366 * @ring: amdgpu_ring structure holding ring information 367 * 368 * Tear down the driver information for the selected ring (all asics). 369 */ 370 void amdgpu_ring_fini(struct amdgpu_ring *ring) 371 { 372 373 /* Not to finish a ring which is not initialized */ 374 if (!(ring->adev) || !(ring->adev->rings[ring->idx])) 375 return; 376 377 ring->sched.ready = false; 378 379 amdgpu_device_wb_free(ring->adev, ring->rptr_offs); 380 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); 381 382 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); 383 amdgpu_device_wb_free(ring->adev, ring->fence_offs); 384 385 amdgpu_bo_free_kernel(&ring->ring_obj, 386 &ring->gpu_addr, 387 (void **)&ring->ring); 388 389 dma_fence_put(ring->vmid_wait); 390 ring->vmid_wait = NULL; 391 ring->me = 0; 392 393 ring->adev->rings[ring->idx] = NULL; 394 } 395 396 /** 397 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper 398 * 399 * @ring: ring to write to 400 * @reg0: register to write 401 * @reg1: register to wait on 402 * @ref: reference value to write/wait on 403 * @mask: mask to wait on 404 * 405 * Helper for rings that don't support write and wait in a 406 * single oneshot packet. 407 */ 408 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 409 uint32_t reg0, uint32_t reg1, 410 uint32_t ref, uint32_t mask) 411 { 412 amdgpu_ring_emit_wreg(ring, reg0, ref); 413 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 414 } 415 416 /** 417 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup 418 * 419 * @ring: ring to try the recovery on 420 * @vmid: VMID we try to get going again 421 * @fence: timedout fence 422 * 423 * Tries to get a ring proceeding again when it is stuck. 424 */ 425 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 426 struct dma_fence *fence) 427 { 428 unsigned long flags; 429 ktime_t deadline; 430 bool ret; 431 432 if (unlikely(ring->adev->debug_disable_soft_recovery)) 433 return false; 434 435 deadline = ktime_add_us(ktime_get(), 10000); 436 437 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) 438 return false; 439 440 spin_lock_irqsave(fence->lock, flags); 441 if (!dma_fence_is_signaled_locked(fence)) 442 dma_fence_set_error(fence, -ENODATA); 443 spin_unlock_irqrestore(fence->lock, flags); 444 445 while (!dma_fence_is_signaled(fence) && 446 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) 447 ring->funcs->soft_recovery(ring, vmid); 448 449 ret = dma_fence_is_signaled(fence); 450 /* increment the counter only if soft reset worked */ 451 if (ret) 452 atomic_inc(&ring->adev->gpu_reset_counter); 453 454 return ret; 455 } 456 457 /* 458 * Debugfs info 459 */ 460 #if defined(CONFIG_DEBUG_FS) 461 462 /* Layout of file is 12 bytes consisting of 463 * - rptr 464 * - wptr 465 * - driver's copy of wptr 466 * 467 * followed by n-words of ring data 468 */ 469 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, 470 size_t size, loff_t *pos) 471 { 472 struct amdgpu_ring *ring = file_inode(f)->i_private; 473 uint32_t value, result, early[3]; 474 uint64_t p; 475 loff_t i; 476 int r; 477 478 if (*pos & 3 || size & 3) 479 return -EINVAL; 480 481 result = 0; 482 483 if (*pos < 12) { 484 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 485 mutex_lock(&ring->adev->cper.ring_lock); 486 487 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; 488 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; 489 early[2] = ring->wptr & ring->buf_mask; 490 for (i = *pos / 4; i < 3 && size; i++) { 491 r = put_user(early[i], (uint32_t *)buf); 492 if (r) { 493 result = r; 494 goto out; 495 } 496 buf += 4; 497 result += 4; 498 size -= 4; 499 *pos += 4; 500 } 501 } 502 503 if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) { 504 while (size) { 505 if (*pos >= (ring->ring_size + 12)) 506 return result; 507 508 value = ring->ring[(*pos - 12)/4]; 509 r = put_user(value, (uint32_t *)buf); 510 if (r) 511 return r; 512 buf += 4; 513 result += 4; 514 size -= 4; 515 *pos += 4; 516 } 517 } else { 518 p = early[0]; 519 if (early[0] <= early[1]) 520 size = (early[1] - early[0]); 521 else 522 size = ring->ring_size - (early[0] - early[1]); 523 524 while (size) { 525 if (p == early[1]) 526 goto out; 527 528 value = ring->ring[p]; 529 r = put_user(value, (uint32_t *)buf); 530 if (r) { 531 result = r; 532 goto out; 533 } 534 535 buf += 4; 536 result += 4; 537 size--; 538 p++; 539 p &= ring->ptr_mask; 540 } 541 } 542 543 out: 544 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 545 mutex_unlock(&ring->adev->cper.ring_lock); 546 547 return result; 548 } 549 550 static ssize_t amdgpu_debugfs_virt_ring_read(struct file *f, char __user *buf, 551 size_t size, loff_t *pos) 552 { 553 struct amdgpu_ring *ring = file_inode(f)->i_private; 554 555 if (*pos & 3 || size & 3) 556 return -EINVAL; 557 558 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 559 amdgpu_virt_req_ras_cper_dump(ring->adev, false); 560 561 return amdgpu_debugfs_ring_read(f, buf, size, pos); 562 } 563 564 static const struct file_operations amdgpu_debugfs_ring_fops = { 565 .owner = THIS_MODULE, 566 .read = amdgpu_debugfs_ring_read, 567 .llseek = default_llseek 568 }; 569 570 static const struct file_operations amdgpu_debugfs_virt_ring_fops = { 571 .owner = THIS_MODULE, 572 .read = amdgpu_debugfs_virt_ring_read, 573 .llseek = default_llseek 574 }; 575 576 static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf, 577 size_t size, loff_t *pos) 578 { 579 struct amdgpu_ring *ring = file_inode(f)->i_private; 580 ssize_t bytes = min_t(ssize_t, ring->mqd_size - *pos, size); 581 void *from = ((u8 *)ring->mqd_ptr) + *pos; 582 583 if (*pos > ring->mqd_size) 584 return 0; 585 586 if (copy_to_user(buf, from, bytes)) 587 return -EFAULT; 588 589 *pos += bytes; 590 return bytes; 591 } 592 593 static const struct file_operations amdgpu_debugfs_mqd_fops = { 594 .owner = THIS_MODULE, 595 .read = amdgpu_debugfs_mqd_read, 596 .llseek = default_llseek 597 }; 598 599 static int amdgpu_debugfs_ring_error(void *data, u64 val) 600 { 601 struct amdgpu_ring *ring = data; 602 603 amdgpu_fence_driver_set_error(ring, val); 604 return 0; 605 } 606 607 DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, 608 amdgpu_debugfs_ring_error, "%lld\n"); 609 610 #endif 611 612 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 613 struct amdgpu_ring *ring) 614 { 615 #if defined(CONFIG_DEBUG_FS) 616 struct drm_minor *minor = adev_to_drm(adev)->primary; 617 struct dentry *root = minor->debugfs_root; 618 char name[32]; 619 620 sprintf(name, "amdgpu_ring_%s", ring->name); 621 if (amdgpu_sriov_vf(adev)) 622 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 623 &amdgpu_debugfs_virt_ring_fops, 624 ring->ring_size + 12); 625 else 626 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 627 &amdgpu_debugfs_ring_fops, 628 ring->ring_size + 12); 629 630 if (ring->mqd_obj) { 631 sprintf(name, "amdgpu_mqd_%s", ring->name); 632 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 633 &amdgpu_debugfs_mqd_fops, 634 ring->mqd_size); 635 } 636 637 sprintf(name, "amdgpu_error_%s", ring->name); 638 debugfs_create_file(name, 0200, root, ring, 639 &amdgpu_debugfs_error_fops); 640 641 #endif 642 } 643 644 /** 645 * amdgpu_ring_test_helper - tests ring and set sched readiness status 646 * 647 * @ring: ring to try the recovery on 648 * 649 * Tests ring and set sched readiness status 650 * 651 * Returns 0 on success, error on failure. 652 */ 653 int amdgpu_ring_test_helper(struct amdgpu_ring *ring) 654 { 655 struct amdgpu_device *adev = ring->adev; 656 int r; 657 658 r = amdgpu_ring_test_ring(ring); 659 if (r) 660 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n", 661 ring->name, r); 662 else 663 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n", 664 ring->name); 665 666 ring->sched.ready = !r; 667 668 return r; 669 } 670 671 static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, 672 struct amdgpu_mqd_prop *prop) 673 { 674 struct amdgpu_device *adev = ring->adev; 675 bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && 676 amdgpu_gfx_is_high_priority_compute_queue(adev, ring); 677 bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX && 678 amdgpu_gfx_is_high_priority_graphics_queue(adev, ring); 679 680 memset(prop, 0, sizeof(*prop)); 681 682 prop->mqd_gpu_addr = ring->mqd_gpu_addr; 683 prop->hqd_base_gpu_addr = ring->gpu_addr; 684 prop->rptr_gpu_addr = ring->rptr_gpu_addr; 685 prop->wptr_gpu_addr = ring->wptr_gpu_addr; 686 prop->queue_size = ring->ring_size; 687 prop->eop_gpu_addr = ring->eop_gpu_addr; 688 prop->use_doorbell = ring->use_doorbell; 689 prop->doorbell_index = ring->doorbell_index; 690 691 /* map_queues packet doesn't need activate the queue, 692 * so only kiq need set this field. 693 */ 694 prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; 695 696 prop->allow_tunneling = is_high_prio_compute; 697 if (is_high_prio_compute || is_high_prio_gfx) { 698 prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 699 prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 700 } 701 } 702 703 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring) 704 { 705 struct amdgpu_device *adev = ring->adev; 706 struct amdgpu_mqd *mqd_mgr; 707 struct amdgpu_mqd_prop prop; 708 709 amdgpu_ring_to_mqd_prop(ring, &prop); 710 711 ring->wptr = 0; 712 713 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 714 mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE]; 715 else 716 mqd_mgr = &adev->mqds[ring->funcs->type]; 717 718 return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop); 719 } 720 721 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring) 722 { 723 if (ring->is_sw_ring) 724 amdgpu_sw_ring_ib_begin(ring); 725 } 726 727 void amdgpu_ring_ib_end(struct amdgpu_ring *ring) 728 { 729 if (ring->is_sw_ring) 730 amdgpu_sw_ring_ib_end(ring); 731 } 732 733 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring) 734 { 735 if (ring->is_sw_ring) 736 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL); 737 } 738 739 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring) 740 { 741 if (ring->is_sw_ring) 742 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE); 743 } 744 745 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring) 746 { 747 if (ring->is_sw_ring) 748 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); 749 } 750 751 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) 752 { 753 if (!ring) 754 return false; 755 756 if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched)) 757 return false; 758 759 return true; 760 } 761