1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_RESET_H__ 25 #define __AMDGPU_RESET_H__ 26 27 #include "amdgpu.h" 28 29 #define AMDGPU_RESET_MAX_HANDLERS 5 30 31 enum AMDGPU_RESET_FLAGS { 32 33 AMDGPU_NEED_FULL_RESET = 0, 34 AMDGPU_SKIP_HW_RESET = 1, 35 AMDGPU_SKIP_COREDUMP = 2, 36 AMDGPU_HOST_FLR = 3, 37 }; 38 39 enum AMDGPU_RESET_SRCS { 40 AMDGPU_RESET_SRC_UNKNOWN, 41 AMDGPU_RESET_SRC_JOB, 42 AMDGPU_RESET_SRC_RAS, 43 AMDGPU_RESET_SRC_MES, 44 AMDGPU_RESET_SRC_HWS, 45 AMDGPU_RESET_SRC_USER, 46 AMDGPU_RESET_SRC_USERQ, 47 }; 48 49 /** 50 * enum amd_reset_method - Methods for resetting AMD GPU devices 51 * 52 * @AMD_RESET_METHOD_NONE: The device will not be reset. 53 * @AMD_RESET_METHOD_LEGACY: Method reserved for SI, CIK and VI ASICs. 54 * @AMD_RESET_METHOD_MODE0: Reset the entire ASIC. Not currently available for 55 * the any device. 56 * @AMD_RESET_METHOD_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, 57 * etc.) individually. Suitable only for some discrete GPU, 58 * not available for all ASICs. 59 * @AMD_RESET_METHOD_MODE2: Resets a lesser level of IPs compared to MODE1. 60 * Which IPs are reset depends on the ASIC. Notably doesn't 61 * reset IPs shared with the CPU on APUs or the memory 62 * controllers (so VRAM is not lost). Not available on all 63 * ASICs. 64 * @AMD_RESET_METHOD_LINK: Triggers SW-UP link reset on other GPUs 65 * @AMD_RESET_METHOD_BACO: BACO (Bus Alive, Chip Off) method powers off and on 66 * the card but without powering off the PCI bus. Suitable 67 * only for discrete GPUs. 68 * @AMD_RESET_METHOD_PCI: Does a full bus reset using core Linux subsystem 69 * PCI reset and does a secondary bus reset or FLR, 70 * depending on what the underlying hardware supports. 71 * @AMD_RESET_METHOD_ON_INIT: Does a device reset during the driver init 72 * sequence. 73 * 74 * Methods available for AMD GPU driver for resetting the device. Not all 75 * methods are suitable for every device. User can override the method using 76 * module parameter `reset_method`. 77 */ 78 enum amd_reset_method { 79 AMD_RESET_METHOD_NONE = -1, 80 AMD_RESET_METHOD_LEGACY = 0, 81 AMD_RESET_METHOD_MODE0, 82 AMD_RESET_METHOD_MODE1, 83 AMD_RESET_METHOD_MODE2, 84 AMD_RESET_METHOD_LINK, 85 AMD_RESET_METHOD_BACO, 86 AMD_RESET_METHOD_PCI, 87 AMD_RESET_METHOD_ON_INIT, 88 }; 89 90 struct amdgpu_reset_context { 91 enum amd_reset_method method; 92 struct amdgpu_device *reset_req_dev; 93 struct amdgpu_job *job; 94 struct amdgpu_hive_info *hive; 95 struct list_head *reset_device_list; 96 unsigned long flags; 97 enum AMDGPU_RESET_SRCS src; 98 }; 99 100 struct amdgpu_reset_control { 101 void *handle; 102 struct work_struct reset_work; 103 struct mutex reset_lock; 104 struct amdgpu_reset_handler *( 105 *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS]; 106 atomic_t in_reset; 107 enum amd_reset_method active_reset; 108 struct amdgpu_reset_handler *(*get_reset_handler)( 109 struct amdgpu_reset_control *reset_ctl, 110 struct amdgpu_reset_context *context); 111 void (*async_reset)(struct work_struct *work); 112 }; 113 114 struct amdgpu_reset_handler { 115 enum amd_reset_method reset_method; 116 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl, 117 struct amdgpu_reset_context *context); 118 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl, 119 struct amdgpu_reset_context *context); 120 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl, 121 struct amdgpu_reset_context *context); 122 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl, 123 struct amdgpu_reset_context *context); 124 int (*restore_env)(struct amdgpu_reset_control *reset_ctl, 125 struct amdgpu_reset_context *context); 126 127 int (*do_reset)(struct amdgpu_device *adev); 128 }; 129 130 131 enum amdgpu_reset_domain_type { 132 SINGLE_DEVICE, 133 XGMI_HIVE 134 }; 135 136 struct amdgpu_reset_domain { 137 struct kref refcount; 138 struct workqueue_struct *wq; 139 enum amdgpu_reset_domain_type type; 140 struct rw_semaphore sem; 141 atomic_t in_gpu_reset; 142 atomic_t reset_res; 143 }; 144 145 int amdgpu_reset_init(struct amdgpu_device *adev); 146 int amdgpu_reset_fini(struct amdgpu_device *adev); 147 148 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev, 149 struct amdgpu_reset_context *reset_context); 150 151 int amdgpu_reset_perform_reset(struct amdgpu_device *adev, 152 struct amdgpu_reset_context *reset_context); 153 154 int amdgpu_reset_prepare_env(struct amdgpu_device *adev, 155 struct amdgpu_reset_context *reset_context); 156 int amdgpu_reset_restore_env(struct amdgpu_device *adev, 157 struct amdgpu_reset_context *reset_context); 158 159 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, 160 char *wq_name); 161 162 void amdgpu_reset_destroy_reset_domain(struct kref *ref); 163 164 static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain) 165 { 166 return kref_get_unless_zero(&domain->refcount) != 0; 167 } 168 169 static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain) 170 { 171 if (domain) 172 kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain); 173 } 174 175 static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain, 176 struct work_struct *work) 177 { 178 return queue_work(domain->wq, work); 179 } 180 181 static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain) 182 { 183 lockdep_assert_held(&domain->sem); 184 return rwsem_is_contended(&domain->sem); 185 } 186 187 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain); 188 189 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain); 190 191 void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf, 192 size_t len); 193 194 #define for_each_handler(i, handler, reset_ctl) \ 195 for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) && \ 196 (handler = (*reset_ctl->reset_handlers)[i]); \ 197 ++i) 198 199 extern struct amdgpu_reset_handler xgmi_reset_on_init_handler; 200 int amdgpu_reset_do_xgmi_reset_on_init( 201 struct amdgpu_reset_context *reset_context); 202 203 bool amdgpu_reset_in_recovery(struct amdgpu_device *adev); 204 205 static inline void amdgpu_reset_set_dpc_status(struct amdgpu_device *adev, 206 bool status) 207 { 208 adev->pcie_reset_ctx.occurs_dpc = status; 209 adev->no_hw_access = status; 210 } 211 212 static inline bool amdgpu_reset_in_dpc(struct amdgpu_device *adev) 213 { 214 return adev->pcie_reset_ctx.occurs_dpc; 215 } 216 217 #endif 218