1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_RESET_H__ 25 #define __AMDGPU_RESET_H__ 26 27 #include "amdgpu.h" 28 29 #define AMDGPU_RESET_MAX_HANDLERS 5 30 31 enum AMDGPU_RESET_FLAGS { 32 33 AMDGPU_NEED_FULL_RESET = 0, 34 AMDGPU_SKIP_HW_RESET = 1, 35 AMDGPU_SKIP_COREDUMP = 2, 36 AMDGPU_HOST_FLR = 3, 37 }; 38 39 struct amdgpu_reset_context { 40 enum amd_reset_method method; 41 struct amdgpu_device *reset_req_dev; 42 struct amdgpu_job *job; 43 struct amdgpu_hive_info *hive; 44 struct list_head *reset_device_list; 45 unsigned long flags; 46 }; 47 48 struct amdgpu_reset_handler { 49 enum amd_reset_method reset_method; 50 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl, 51 struct amdgpu_reset_context *context); 52 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl, 53 struct amdgpu_reset_context *context); 54 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl, 55 struct amdgpu_reset_context *context); 56 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl, 57 struct amdgpu_reset_context *context); 58 int (*restore_env)(struct amdgpu_reset_control *reset_ctl, 59 struct amdgpu_reset_context *context); 60 61 int (*do_reset)(struct amdgpu_device *adev); 62 }; 63 64 struct amdgpu_reset_control { 65 void *handle; 66 struct work_struct reset_work; 67 struct mutex reset_lock; 68 struct amdgpu_reset_handler *( 69 *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS]; 70 atomic_t in_reset; 71 enum amd_reset_method active_reset; 72 struct amdgpu_reset_handler *(*get_reset_handler)( 73 struct amdgpu_reset_control *reset_ctl, 74 struct amdgpu_reset_context *context); 75 void (*async_reset)(struct work_struct *work); 76 }; 77 78 79 enum amdgpu_reset_domain_type { 80 SINGLE_DEVICE, 81 XGMI_HIVE 82 }; 83 84 struct amdgpu_reset_domain { 85 struct kref refcount; 86 struct workqueue_struct *wq; 87 enum amdgpu_reset_domain_type type; 88 struct rw_semaphore sem; 89 atomic_t in_gpu_reset; 90 atomic_t reset_res; 91 }; 92 93 int amdgpu_reset_init(struct amdgpu_device *adev); 94 int amdgpu_reset_fini(struct amdgpu_device *adev); 95 96 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev, 97 struct amdgpu_reset_context *reset_context); 98 99 int amdgpu_reset_perform_reset(struct amdgpu_device *adev, 100 struct amdgpu_reset_context *reset_context); 101 102 int amdgpu_reset_prepare_env(struct amdgpu_device *adev, 103 struct amdgpu_reset_context *reset_context); 104 int amdgpu_reset_restore_env(struct amdgpu_device *adev, 105 struct amdgpu_reset_context *reset_context); 106 107 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, 108 char *wq_name); 109 110 void amdgpu_reset_destroy_reset_domain(struct kref *ref); 111 112 static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain) 113 { 114 return kref_get_unless_zero(&domain->refcount) != 0; 115 } 116 117 static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain) 118 { 119 if (domain) 120 kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain); 121 } 122 123 static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain, 124 struct work_struct *work) 125 { 126 return queue_work(domain->wq, work); 127 } 128 129 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain); 130 131 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain); 132 133 #define for_each_handler(i, handler, reset_ctl) \ 134 for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) && \ 135 (handler = (*reset_ctl->reset_handlers)[i]); \ 136 ++i) 137 #endif 138