xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c (revision d639d9fa162aadec1ae9980c4dcf6e50bd2f8290) 
1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "amdgpu_reset.h"
25 #include "aldebaran.h"
26 #include "sienna_cichlid.h"
27 #include "smu_v13_0_10.h"
28 
29 static int amdgpu_reset_xgmi_reset_on_init_suspend(struct amdgpu_device *adev)
30 {
31 	int i;
32 
33 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
34 		if (!adev->ip_blocks[i].status.valid)
35 			continue;
36 		if (!adev->ip_blocks[i].status.hw)
37 			continue;
38 		/* displays are handled in phase1 */
39 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
40 			continue;
41 
42 		/* XXX handle errors */
43 		amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
44 		adev->ip_blocks[i].status.hw = false;
45 	}
46 
47 	/* VCN FW shared region is in frambuffer, there are some flags
48 	 * initialized in that region during sw_init. Make sure the region is
49 	 * backed up.
50 	 */
51 	amdgpu_vcn_save_vcpu_bo(adev);
52 
53 	return 0;
54 }
55 
56 static int amdgpu_reset_xgmi_reset_on_init_prep_hwctxt(
57 	struct amdgpu_reset_control *reset_ctl,
58 	struct amdgpu_reset_context *reset_context)
59 {
60 	struct list_head *reset_device_list = reset_context->reset_device_list;
61 	struct amdgpu_device *tmp_adev;
62 	int r;
63 
64 	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
65 		amdgpu_unregister_gpu_instance(tmp_adev);
66 		r = amdgpu_reset_xgmi_reset_on_init_suspend(tmp_adev);
67 		if (r) {
68 			dev_err(tmp_adev->dev,
69 				"xgmi reset on init: prepare for reset failed");
70 			return r;
71 		}
72 	}
73 
74 	return r;
75 }
76 
77 static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt(
78 	struct amdgpu_reset_control *reset_ctl,
79 	struct amdgpu_reset_context *reset_context)
80 {
81 	struct list_head *reset_device_list = reset_context->reset_device_list;
82 	struct amdgpu_device *tmp_adev = NULL;
83 	int r;
84 
85 	r = amdgpu_device_reinit_after_reset(reset_context);
86 	if (r)
87 		return r;
88 	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
89 		if (!tmp_adev->kfd.init_complete) {
90 			kgd2kfd_init_zone_device(tmp_adev);
91 			amdgpu_amdkfd_device_init(tmp_adev);
92 			amdgpu_amdkfd_drm_client_create(tmp_adev);
93 			amdgpu_ptl_sysfs_init(tmp_adev);
94 		}
95 	}
96 
97 	return r;
98 }
99 
100 static int amdgpu_reset_xgmi_reset_on_init_perform_reset(
101 	struct amdgpu_reset_control *reset_ctl,
102 	struct amdgpu_reset_context *reset_context)
103 {
104 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
105 	struct list_head *reset_device_list = reset_context->reset_device_list;
106 	struct amdgpu_device *tmp_adev = NULL;
107 	int r;
108 
109 	dev_dbg(adev->dev, "xgmi roi - hw reset\n");
110 
111 	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
112 		mutex_lock(&tmp_adev->reset_cntl->reset_lock);
113 		tmp_adev->reset_cntl->active_reset =
114 			amdgpu_asic_reset_method(adev);
115 	}
116 	r = 0;
117 	/* Mode1 reset needs to be triggered on all devices together */
118 	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
119 		/* For XGMI run all resets in parallel to speed up the process */
120 		if (!queue_work(system_dfl_wq, &tmp_adev->xgmi_reset_work))
121 			r = -EALREADY;
122 		if (r) {
123 			dev_err(tmp_adev->dev,
124 				"xgmi reset on init: reset failed with error, %d",
125 				r);
126 			break;
127 		}
128 	}
129 
130 	/* For XGMI wait for all resets to complete before proceed */
131 	if (!r) {
132 		list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
133 			flush_work(&tmp_adev->xgmi_reset_work);
134 			r = tmp_adev->asic_reset_res;
135 			if (r)
136 				break;
137 		}
138 	}
139 
140 	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
141 		mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
142 		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
143 	}
144 
145 	return r;
146 }
147 
148 int amdgpu_reset_do_xgmi_reset_on_init(
149 	struct amdgpu_reset_context *reset_context)
150 {
151 	struct list_head *reset_device_list = reset_context->reset_device_list;
152 	struct amdgpu_device *adev;
153 	int r;
154 
155 	if (!reset_device_list || list_empty(reset_device_list) ||
156 	    list_is_singular(reset_device_list))
157 		return -EINVAL;
158 
159 	adev = list_first_entry(reset_device_list, struct amdgpu_device,
160 				reset_list);
161 	r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
162 	if (r)
163 		return r;
164 
165 	r = amdgpu_reset_perform_reset(adev, reset_context);
166 
167 	return r;
168 }
169 
170 struct amdgpu_reset_handler xgmi_reset_on_init_handler = {
171 	.reset_method = AMD_RESET_METHOD_ON_INIT,
172 	.prepare_env = NULL,
173 	.prepare_hwcontext = amdgpu_reset_xgmi_reset_on_init_prep_hwctxt,
174 	.perform_reset = amdgpu_reset_xgmi_reset_on_init_perform_reset,
175 	.restore_hwcontext = amdgpu_reset_xgmi_reset_on_init_restore_hwctxt,
176 	.restore_env = NULL,
177 	.do_reset = NULL,
178 };
179 
180 int amdgpu_reset_init(struct amdgpu_device *adev)
181 {
182 	int ret = 0;
183 
184 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
185 	case IP_VERSION(13, 0, 2):
186 	case IP_VERSION(13, 0, 6):
187 	case IP_VERSION(13, 0, 12):
188 	case IP_VERSION(13, 0, 14):
189 		ret = aldebaran_reset_init(adev);
190 		break;
191 	case IP_VERSION(11, 0, 7):
192 		ret = sienna_cichlid_reset_init(adev);
193 		break;
194 	case IP_VERSION(13, 0, 10):
195 		ret = smu_v13_0_10_reset_init(adev);
196 		break;
197 	default:
198 		break;
199 	}
200 
201 	return ret;
202 }
203 
204 int amdgpu_reset_fini(struct amdgpu_device *adev)
205 {
206 	int ret = 0;
207 
208 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
209 	case IP_VERSION(13, 0, 2):
210 	case IP_VERSION(13, 0, 6):
211 	case IP_VERSION(13, 0, 12):
212 	case IP_VERSION(13, 0, 14):
213 		ret = aldebaran_reset_fini(adev);
214 		break;
215 	case IP_VERSION(11, 0, 7):
216 		ret = sienna_cichlid_reset_fini(adev);
217 		break;
218 	case IP_VERSION(13, 0, 10):
219 		ret = smu_v13_0_10_reset_fini(adev);
220 		break;
221 	default:
222 		break;
223 	}
224 
225 	return ret;
226 }
227 
228 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
229 				   struct amdgpu_reset_context *reset_context)
230 {
231 	struct amdgpu_reset_handler *reset_handler = NULL;
232 
233 	if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
234 		reset_handler = adev->reset_cntl->get_reset_handler(
235 			adev->reset_cntl, reset_context);
236 	if (!reset_handler)
237 		return -EOPNOTSUPP;
238 
239 	return reset_handler->prepare_hwcontext(adev->reset_cntl,
240 						reset_context);
241 }
242 
243 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
244 			       struct amdgpu_reset_context *reset_context)
245 {
246 	int ret;
247 	struct amdgpu_reset_handler *reset_handler = NULL;
248 
249 	if (adev->reset_cntl)
250 		reset_handler = adev->reset_cntl->get_reset_handler(
251 			adev->reset_cntl, reset_context);
252 	if (!reset_handler)
253 		return -EOPNOTSUPP;
254 
255 	ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
256 	if (ret)
257 		return ret;
258 
259 	return reset_handler->restore_hwcontext(adev->reset_cntl,
260 						reset_context);
261 }
262 
263 
264 void amdgpu_reset_destroy_reset_domain(struct kref *ref)
265 {
266 	struct amdgpu_reset_domain *reset_domain = container_of(ref,
267 								struct amdgpu_reset_domain,
268 								refcount);
269 	if (reset_domain->wq)
270 		destroy_workqueue(reset_domain->wq);
271 
272 	kvfree(reset_domain);
273 }
274 
275 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
276 							     char *wq_name)
277 {
278 	struct amdgpu_reset_domain *reset_domain;
279 
280 	reset_domain = kvzalloc_obj(struct amdgpu_reset_domain);
281 	if (!reset_domain) {
282 		DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
283 		return NULL;
284 	}
285 
286 	reset_domain->type = type;
287 	kref_init(&reset_domain->refcount);
288 
289 	reset_domain->wq = create_singlethread_workqueue(wq_name);
290 	if (!reset_domain->wq) {
291 		DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
292 		amdgpu_reset_put_reset_domain(reset_domain);
293 		return NULL;
294 
295 	}
296 
297 	atomic_set(&reset_domain->in_gpu_reset, 0);
298 	atomic_set(&reset_domain->reset_res, 0);
299 	init_rwsem(&reset_domain->sem);
300 
301 	return reset_domain;
302 }
303 
304 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
305 {
306 	atomic_set(&reset_domain->in_gpu_reset, 1);
307 	down_write(&reset_domain->sem);
308 }
309 
310 
311 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
312 {
313 	atomic_set(&reset_domain->in_gpu_reset, 0);
314 	up_write(&reset_domain->sem);
315 }
316 
317 void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,
318 			   size_t len)
319 {
320 	if (!buf || !len)
321 		return;
322 
323 	switch (rst_ctxt->src) {
324 	case AMDGPU_RESET_SRC_JOB:
325 		if (rst_ctxt->job) {
326 			snprintf(buf, len, "job hang on ring:%s",
327 				 rst_ctxt->job->base.sched->name);
328 		} else {
329 			strscpy(buf, "job hang", len);
330 		}
331 		break;
332 	case AMDGPU_RESET_SRC_RAS:
333 		strscpy(buf, "RAS error", len);
334 		break;
335 	case AMDGPU_RESET_SRC_MES:
336 		strscpy(buf, "MES hang", len);
337 		break;
338 	case AMDGPU_RESET_SRC_HWS:
339 		strscpy(buf, "HWS hang", len);
340 		break;
341 	case AMDGPU_RESET_SRC_USER:
342 		strscpy(buf, "user trigger", len);
343 		break;
344 	case AMDGPU_RESET_SRC_USERQ:
345 		strscpy(buf, "user queue trigger", len);
346 		break;
347 	default:
348 		strscpy(buf, "unknown", len);
349 	}
350 }
351 
352 bool amdgpu_reset_in_recovery(struct amdgpu_device *adev)
353 {
354 	return (adev->init_lvl->level == AMDGPU_INIT_LEVEL_RESET_RECOVERY);
355 }
356