1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __AMDGPU_REG_ACCESS_H__ 25 #define __AMDGPU_REG_ACCESS_H__ 26 27 #include <linux/types.h> 28 #include <linux/spinlock.h> 29 30 #include "amdgpu_ip.h" 31 32 struct amdgpu_device; 33 34 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); 35 typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); 36 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 37 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); 38 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); 39 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); 40 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); 41 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); 42 43 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, 44 uint32_t); 45 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, 46 uint32_t); 47 typedef uint64_t (*amdgpu_reg_get_smn_base64_t)(struct amdgpu_device *adev, 48 enum amd_hw_ip_block_type block, 49 int die_inst); 50 51 struct amdgpu_reg_ind { 52 spinlock_t lock; 53 amdgpu_rreg_t rreg; 54 amdgpu_wreg_t wreg; 55 }; 56 57 struct amdgpu_reg_ind_blk { 58 spinlock_t lock; 59 amdgpu_block_rreg_t rreg; 60 amdgpu_block_wreg_t wreg; 61 }; 62 63 struct amdgpu_reg_pcie_ind { 64 spinlock_t lock; 65 amdgpu_rreg_t rreg; 66 amdgpu_wreg_t wreg; 67 amdgpu_rreg_ext_t rreg_ext; 68 amdgpu_wreg_ext_t wreg_ext; 69 amdgpu_rreg64_t rreg64; 70 amdgpu_wreg64_t wreg64; 71 amdgpu_rreg64_ext_t rreg64_ext; 72 amdgpu_wreg64_ext_t wreg64_ext; 73 amdgpu_rreg_t port_rreg; 74 amdgpu_wreg_t port_wreg; 75 }; 76 77 struct amdgpu_reg_smn_ext { 78 amdgpu_reg_get_smn_base64_t get_smn_base; 79 }; 80 81 struct amdgpu_reg_access { 82 struct amdgpu_reg_ind smc; 83 struct amdgpu_reg_ind uvd_ctx; 84 struct amdgpu_reg_ind didt; 85 struct amdgpu_reg_ind gc_cac; 86 struct amdgpu_reg_ind se_cac; 87 struct amdgpu_reg_ind_blk audio_endpt; 88 struct amdgpu_reg_pcie_ind pcie; 89 struct amdgpu_reg_smn_ext smn; 90 }; 91 92 /* 93 * ASIC specific register table accessible by UMD 94 */ 95 struct amdgpu_allowed_register_entry { 96 uint32_t reg_offset; 97 bool grbm_indexed; 98 }; 99 100 void amdgpu_reg_access_init(struct amdgpu_device *adev); 101 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); 102 void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 103 uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); 104 void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 105 uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); 106 void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 107 uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 108 void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 109 uint32_t v); 110 uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 111 void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 112 uint32_t v); 113 uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, 114 uint32_t reg); 115 void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, 116 uint32_t reg, uint32_t v); 117 uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg); 118 void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 119 uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg); 120 void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, 121 uint32_t v); 122 uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg); 123 void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v); 124 uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg); 125 void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, 126 uint64_t v); 127 uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); 128 void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, 129 uint32_t v); 130 uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, 131 enum amd_hw_ip_block_type block, 132 int die_inst); 133 uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev, 134 enum amd_hw_ip_block_type block, 135 int die_inst); 136 137 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 138 uint32_t acc_flags); 139 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, 140 uint32_t acc_flags, uint32_t xcc_id); 141 void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 142 uint32_t acc_flags); 143 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, 144 uint32_t v, uint32_t acc_flags, uint32_t xcc_id); 145 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, 146 uint32_t v, uint32_t xcc_id); 147 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, 148 uint8_t value); 149 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 150 151 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr); 152 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr); 153 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr); 154 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr); 155 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, 156 u32 reg_data); 157 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, 158 u32 reg_data); 159 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, 160 u64 reg_data); 161 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, 162 u64 reg_data); 163 164 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg); 165 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 166 167 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, 168 uint32_t reg_addr, char reg_name[], 169 uint32_t expected_value, uint32_t mask); 170 171 uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev, 172 u32 se_num, u32 sh_num, u32 reg_offset); 173 174 #endif /* __AMDGPU_REG_ACCESS_H__ */ 175