157052d29SLijo Lazar /* SPDX-License-Identifier: MIT */ 257052d29SLijo Lazar /* 357052d29SLijo Lazar * Copyright 2025 Advanced Micro Devices, Inc. 457052d29SLijo Lazar * 557052d29SLijo Lazar * Permission is hereby granted, free of charge, to any person obtaining a 657052d29SLijo Lazar * copy of this software and associated documentation files (the "Software"), 757052d29SLijo Lazar * to deal in the Software without restriction, including without limitation 857052d29SLijo Lazar * the rights to use, copy, modify, merge, publish, distribute, sublicense, 957052d29SLijo Lazar * and/or sell copies of the Software, and to permit persons to whom the 1057052d29SLijo Lazar * Software is furnished to do so, subject to the following conditions: 1157052d29SLijo Lazar * 1257052d29SLijo Lazar * The above copyright notice and this permission notice shall be included in 1357052d29SLijo Lazar * all copies or substantial portions of the Software. 1457052d29SLijo Lazar * 1557052d29SLijo Lazar * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1657052d29SLijo Lazar * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1757052d29SLijo Lazar * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1857052d29SLijo Lazar * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1957052d29SLijo Lazar * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2057052d29SLijo Lazar * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2157052d29SLijo Lazar * OTHER DEALINGS IN THE SOFTWARE. 2257052d29SLijo Lazar */ 2357052d29SLijo Lazar 2457052d29SLijo Lazar #ifndef __AMDGPU_REG_ACCESS_H__ 2557052d29SLijo Lazar #define __AMDGPU_REG_ACCESS_H__ 2657052d29SLijo Lazar 2757052d29SLijo Lazar #include <linux/types.h> 28f4eb08f8SLijo Lazar #include <linux/spinlock.h> 2957052d29SLijo Lazar 30467ebfe6SLijo Lazar #include "amdgpu_ip.h" 31467ebfe6SLijo Lazar 3257052d29SLijo Lazar struct amdgpu_device; 3357052d29SLijo Lazar 3457052d29SLijo Lazar typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); 3557052d29SLijo Lazar typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); 365312d68aSLijo Lazar typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 375312d68aSLijo Lazar typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); 3874b9c49eSLijo Lazar typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); 3974b9c49eSLijo Lazar typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); 404a6ab037SLijo Lazar typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); 414a6ab037SLijo Lazar typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); 4257052d29SLijo Lazar 4372cc2e30SLijo Lazar typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, 4472cc2e30SLijo Lazar uint32_t); 4572cc2e30SLijo Lazar typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, 4672cc2e30SLijo Lazar uint32_t); 47467ebfe6SLijo Lazar typedef uint64_t (*amdgpu_reg_get_smn_base64_t)(struct amdgpu_device *adev, 48467ebfe6SLijo Lazar enum amd_hw_ip_block_type block, 49467ebfe6SLijo Lazar int die_inst); 5072cc2e30SLijo Lazar 51f4eb08f8SLijo Lazar struct amdgpu_reg_ind { 52f4eb08f8SLijo Lazar spinlock_t lock; 53f4eb08f8SLijo Lazar amdgpu_rreg_t rreg; 54f4eb08f8SLijo Lazar amdgpu_wreg_t wreg; 55f4eb08f8SLijo Lazar }; 56f4eb08f8SLijo Lazar 5772cc2e30SLijo Lazar struct amdgpu_reg_ind_blk { 5872cc2e30SLijo Lazar spinlock_t lock; 5972cc2e30SLijo Lazar amdgpu_block_rreg_t rreg; 6072cc2e30SLijo Lazar amdgpu_block_wreg_t wreg; 6172cc2e30SLijo Lazar }; 6272cc2e30SLijo Lazar 635d82f451SLijo Lazar struct amdgpu_reg_pcie_ind { 64b2d55124SLijo Lazar spinlock_t lock; 65e84d7e71SLijo Lazar amdgpu_rreg_t rreg; 66e84d7e71SLijo Lazar amdgpu_wreg_t wreg; 675312d68aSLijo Lazar amdgpu_rreg_ext_t rreg_ext; 685312d68aSLijo Lazar amdgpu_wreg_ext_t wreg_ext; 6974b9c49eSLijo Lazar amdgpu_rreg64_t rreg64; 7074b9c49eSLijo Lazar amdgpu_wreg64_t wreg64; 714a6ab037SLijo Lazar amdgpu_rreg64_ext_t rreg64_ext; 724a6ab037SLijo Lazar amdgpu_wreg64_ext_t wreg64_ext; 735d82f451SLijo Lazar amdgpu_rreg_t port_rreg; 745d82f451SLijo Lazar amdgpu_wreg_t port_wreg; 755d82f451SLijo Lazar }; 765d82f451SLijo Lazar 77467ebfe6SLijo Lazar struct amdgpu_reg_smn_ext { 78467ebfe6SLijo Lazar amdgpu_reg_get_smn_base64_t get_smn_base; 79467ebfe6SLijo Lazar }; 80467ebfe6SLijo Lazar 81f4eb08f8SLijo Lazar struct amdgpu_reg_access { 82f4eb08f8SLijo Lazar struct amdgpu_reg_ind smc; 83366201e7SLijo Lazar struct amdgpu_reg_ind uvd_ctx; 844780a26aSLijo Lazar struct amdgpu_reg_ind didt; 85d2de787fSLijo Lazar struct amdgpu_reg_ind gc_cac; 86b1a516a5SLijo Lazar struct amdgpu_reg_ind se_cac; 8772cc2e30SLijo Lazar struct amdgpu_reg_ind_blk audio_endpt; 885d82f451SLijo Lazar struct amdgpu_reg_pcie_ind pcie; 89467ebfe6SLijo Lazar struct amdgpu_reg_smn_ext smn; 90f4eb08f8SLijo Lazar }; 91f4eb08f8SLijo Lazar 92f4eb08f8SLijo Lazar void amdgpu_reg_access_init(struct amdgpu_device *adev); 93f4eb08f8SLijo Lazar uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); 94f4eb08f8SLijo Lazar void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 95366201e7SLijo Lazar uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); 96366201e7SLijo Lazar void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 974780a26aSLijo Lazar uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); 984780a26aSLijo Lazar void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 99d2de787fSLijo Lazar uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 100d2de787fSLijo Lazar void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 101d2de787fSLijo Lazar uint32_t v); 102b1a516a5SLijo Lazar uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 103b1a516a5SLijo Lazar void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 104b1a516a5SLijo Lazar uint32_t v); 10572cc2e30SLijo Lazar uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, 10672cc2e30SLijo Lazar uint32_t reg); 10772cc2e30SLijo Lazar void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, 10872cc2e30SLijo Lazar uint32_t reg, uint32_t v); 109e84d7e71SLijo Lazar uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg); 110e84d7e71SLijo Lazar void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 1115312d68aSLijo Lazar uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg); 1125312d68aSLijo Lazar void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, 1135312d68aSLijo Lazar uint32_t v); 11474b9c49eSLijo Lazar uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg); 11574b9c49eSLijo Lazar void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v); 1164a6ab037SLijo Lazar uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg); 1174a6ab037SLijo Lazar void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, 1184a6ab037SLijo Lazar uint64_t v); 1195d82f451SLijo Lazar uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); 1205d82f451SLijo Lazar void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, 1215d82f451SLijo Lazar uint32_t v); 122467ebfe6SLijo Lazar uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, 123467ebfe6SLijo Lazar enum amd_hw_ip_block_type block, 124467ebfe6SLijo Lazar int die_inst); 125*36a02456SLijo Lazar uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev, 126*36a02456SLijo Lazar enum amd_hw_ip_block_type block, 127*36a02456SLijo Lazar int die_inst); 128f4eb08f8SLijo Lazar 12957052d29SLijo Lazar uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 13057052d29SLijo Lazar uint32_t acc_flags); 13157052d29SLijo Lazar uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, 13257052d29SLijo Lazar uint32_t acc_flags, uint32_t xcc_id); 13357052d29SLijo Lazar void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 13457052d29SLijo Lazar uint32_t acc_flags); 13557052d29SLijo Lazar void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, 13657052d29SLijo Lazar uint32_t v, uint32_t acc_flags, uint32_t xcc_id); 13757052d29SLijo Lazar void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, 13857052d29SLijo Lazar uint32_t v, uint32_t xcc_id); 13957052d29SLijo Lazar void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, 14057052d29SLijo Lazar uint8_t value); 14157052d29SLijo Lazar uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 14257052d29SLijo Lazar 14357052d29SLijo Lazar u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr); 14457052d29SLijo Lazar u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr); 14557052d29SLijo Lazar u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr); 14657052d29SLijo Lazar u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr); 14757052d29SLijo Lazar void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, 14857052d29SLijo Lazar u32 reg_data); 14957052d29SLijo Lazar void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, 15057052d29SLijo Lazar u32 reg_data); 15157052d29SLijo Lazar void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, 15257052d29SLijo Lazar u64 reg_data); 15357052d29SLijo Lazar void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, 15457052d29SLijo Lazar u64 reg_data); 15557052d29SLijo Lazar 15657052d29SLijo Lazar u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg); 15757052d29SLijo Lazar void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 15857052d29SLijo Lazar 15957052d29SLijo Lazar uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, 16057052d29SLijo Lazar uint32_t reg_addr, char reg_name[], 16157052d29SLijo Lazar uint32_t expected_value, uint32_t mask); 16257052d29SLijo Lazar 16357052d29SLijo Lazar #endif /* __AMDGPU_REG_ACCESS_H__ */ 164