xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h (revision daa121128a2d2ac6006159e2c47676e4fcd21eab)
1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  *
23  */
24 #ifndef _AMDGPU_RAS_H
25 #define _AMDGPU_RAS_H
26 
27 #include <linux/debugfs.h>
28 #include <linux/list.h>
29 #include <linux/kfifo.h>
30 #include <linux/radix-tree.h>
31 #include <linux/siphash.h>
32 #include "ta_ras_if.h"
33 #include "amdgpu_ras_eeprom.h"
34 #include "amdgpu_smuio.h"
35 #include "amdgpu_aca.h"
36 
37 struct amdgpu_iv_entry;
38 
39 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x)		AMDGPU_GET_REG_FIELD(x, 0, 0)
40 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x)			AMDGPU_GET_REG_FIELD(x, 1, 1)
41 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 2, 2)
42 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 3, 3)
43 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 4, 4)
44 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x)	AMDGPU_GET_REG_FIELD(x, 5, 5)
45 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x)		AMDGPU_GET_REG_FIELD(x, 6, 6)
46 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x)		AMDGPU_GET_REG_FIELD(x, 7, 7)
47 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x)			AMDGPU_GET_REG_FIELD(x, 10, 8)
48 #define AMDGPU_RAS_GPU_ERR_AID_ID(x)			AMDGPU_GET_REG_FIELD(x, 12, 11)
49 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x)			AMDGPU_GET_REG_FIELD(x, 13, 13)
50 #define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x)		AMDGPU_GET_REG_FIELD(x, 31, 31)
51 
52 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT	1000
53 #define AMDGPU_RAS_BOOT_STEADY_STATUS		0xBA
54 #define AMDGPU_RAS_BOOT_STATUS_MASK		0xFF
55 #define AMDGPU_RAS_BOOT_SUCEESS			0x80000000
56 
57 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS		(0x1 << 0)
58 /* position of instance value in sub_block_index of
59  * ta_ras_trigger_error_input, the sub block uses lower 12 bits
60  */
61 #define AMDGPU_RAS_INST_MASK 0xfffff000
62 #define AMDGPU_RAS_INST_SHIFT 0xc
63 
64 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29
65 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000
66 
67 /* The high three bits indicates socketid */
68 #define AMDGPU_RAS_GET_FEATURES(val)  ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
69 
70 #define RAS_EVENT_LOG(_adev, _id, _fmt, ...)				\
71 do {									\
72 	if (amdgpu_ras_event_id_is_valid((_adev), (_id)))			\
73 	    dev_info((_adev)->dev, "{%llu}" _fmt, (_id), ##__VA_ARGS__);	\
74 	else								\
75 	    dev_info((_adev)->dev, _fmt, ##__VA_ARGS__);			\
76 } while (0)
77 
78 enum amdgpu_ras_block {
79 	AMDGPU_RAS_BLOCK__UMC = 0,
80 	AMDGPU_RAS_BLOCK__SDMA,
81 	AMDGPU_RAS_BLOCK__GFX,
82 	AMDGPU_RAS_BLOCK__MMHUB,
83 	AMDGPU_RAS_BLOCK__ATHUB,
84 	AMDGPU_RAS_BLOCK__PCIE_BIF,
85 	AMDGPU_RAS_BLOCK__HDP,
86 	AMDGPU_RAS_BLOCK__XGMI_WAFL,
87 	AMDGPU_RAS_BLOCK__DF,
88 	AMDGPU_RAS_BLOCK__SMN,
89 	AMDGPU_RAS_BLOCK__SEM,
90 	AMDGPU_RAS_BLOCK__MP0,
91 	AMDGPU_RAS_BLOCK__MP1,
92 	AMDGPU_RAS_BLOCK__FUSE,
93 	AMDGPU_RAS_BLOCK__MCA,
94 	AMDGPU_RAS_BLOCK__VCN,
95 	AMDGPU_RAS_BLOCK__JPEG,
96 	AMDGPU_RAS_BLOCK__IH,
97 	AMDGPU_RAS_BLOCK__MPIO,
98 
99 	AMDGPU_RAS_BLOCK__LAST
100 };
101 
102 enum amdgpu_ras_mca_block {
103 	AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
104 	AMDGPU_RAS_MCA_BLOCK__MP1,
105 	AMDGPU_RAS_MCA_BLOCK__MPIO,
106 	AMDGPU_RAS_MCA_BLOCK__IOHC,
107 
108 	AMDGPU_RAS_MCA_BLOCK__LAST
109 };
110 
111 #define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST
112 #define AMDGPU_RAS_MCA_BLOCK_COUNT	AMDGPU_RAS_MCA_BLOCK__LAST
113 #define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
114 
115 enum amdgpu_ras_gfx_subblock {
116 	/* CPC */
117 	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
118 	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
119 		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
120 	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
121 	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
122 	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
123 	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
124 	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
125 	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
126 	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
127 	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
128 		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
129 	/* CPF */
130 	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
131 	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
132 		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
133 	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
134 	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
135 	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
136 	/* CPG */
137 	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
138 	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
139 		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
140 	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
141 	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
142 	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
143 	/* GDS */
144 	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
145 	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
146 	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
147 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
148 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
149 	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
150 	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
151 		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
152 	/* SPI */
153 	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
154 	/* SQ */
155 	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
156 	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
157 	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
158 	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
159 	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
160 	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
161 	/* SQC (3 ranges) */
162 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
163 	/* SQC range 0 */
164 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
165 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
166 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
167 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
168 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
169 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
170 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
171 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
172 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
173 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
174 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
175 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
176 	/* SQC range 1 */
177 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
178 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
179 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
180 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
181 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
182 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
183 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
184 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
185 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
186 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
187 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
188 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
189 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
190 	/* SQC range 2 */
191 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
192 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
193 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
194 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
195 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
196 	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
197 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
198 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
199 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
200 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
201 	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
202 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
203 		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
204 	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
205 		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
206 	/* TA */
207 	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
208 	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
209 		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
210 	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
211 	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
212 	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
213 	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
214 	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
215 	/* TCA */
216 	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
217 	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
218 		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
219 	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
220 	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
221 		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
222 	/* TCC (5 sub-ranges) */
223 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
224 	/* TCC range 0 */
225 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
226 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
227 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
228 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
229 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
230 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
231 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
232 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
233 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
234 	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
235 	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
236 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
237 		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
238 	/* TCC range 1 */
239 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
240 	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
241 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
242 	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
243 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
244 		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
245 	/* TCC range 2 */
246 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
247 	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
248 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
249 	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
250 	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
251 	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
252 	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
253 	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
254 	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
255 	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
256 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
257 		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
258 	/* TCC range 3 */
259 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
260 	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
261 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
262 	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
263 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
264 		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
265 	/* TCC range 4 */
266 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
267 	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
268 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
269 	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
270 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
271 		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
272 	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
273 		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
274 	/* TCI */
275 	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
276 	/* TCP */
277 	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
278 	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
279 		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
280 	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
281 	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
282 	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
283 	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
284 	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
285 	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
286 	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
287 		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
288 	/* TD */
289 	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
290 	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
291 		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
292 	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
293 	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
294 	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
295 	/* EA (3 sub-ranges) */
296 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
297 	/* EA range 0 */
298 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
299 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
300 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
301 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
302 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
303 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
304 	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
305 	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
306 	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
307 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
308 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
309 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
310 		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
311 	/* EA range 1 */
312 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
313 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
314 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
315 	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
316 	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
317 	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
318 	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
319 	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
320 	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
321 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
322 		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
323 	/* EA range 2 */
324 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
325 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
326 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
327 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
328 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
329 	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
330 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
331 		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
332 	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
333 		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
334 	/* UTC VM L2 bank */
335 	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
336 	/* UTC VM walker */
337 	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
338 	/* UTC ATC L2 2MB cache */
339 	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
340 	/* UTC ATC L2 4KB cache */
341 	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
342 	AMDGPU_RAS_BLOCK__GFX_MAX
343 };
344 
345 enum amdgpu_ras_error_type {
346 	AMDGPU_RAS_ERROR__NONE							= 0,
347 	AMDGPU_RAS_ERROR__PARITY						= 1,
348 	AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE					= 2,
349 	AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE					= 4,
350 	AMDGPU_RAS_ERROR__POISON						= 8,
351 };
352 
353 enum amdgpu_ras_ret {
354 	AMDGPU_RAS_SUCCESS = 0,
355 	AMDGPU_RAS_FAIL,
356 	AMDGPU_RAS_UE,
357 	AMDGPU_RAS_CE,
358 	AMDGPU_RAS_PT,
359 };
360 
361 enum amdgpu_ras_error_query_mode {
362 	AMDGPU_RAS_INVALID_ERROR_QUERY		= 0,
363 	AMDGPU_RAS_DIRECT_ERROR_QUERY		= 1,
364 	AMDGPU_RAS_FIRMWARE_ERROR_QUERY		= 2,
365 };
366 
367 /* ras error status reisger fields */
368 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT	0x0
369 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK	0x00000001L
370 #define ERR_STATUS_LO__MEMORY_ID__SHIFT			0x18
371 #define ERR_STATUS_LO__MEMORY_ID_MASK			0xFF000000L
372 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT	0x2
373 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK		0x00000004L
374 #define ERR_STATUS__ERR_CNT__SHIFT			0x17
375 #define ERR_STATUS__ERR_CNT_MASK			0x03800000L
376 
377 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
378 	ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
379 
380 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
381 	(adev->reg_offset[hwip][ip_inst][segment] + (reg))
382 
383 #define AMDGPU_RAS_ERR_INFO_VALID	(1 << 0)
384 #define AMDGPU_RAS_ERR_STATUS_VALID	(1 << 1)
385 #define AMDGPU_RAS_ERR_ADDRESS_VALID	(1 << 2)
386 
387 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET  (0x1 << 0)
388 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET  (0x1 << 1)
389 
390 struct amdgpu_ras_err_status_reg_entry {
391 	uint32_t hwip;
392 	uint32_t ip_inst;
393 	uint32_t seg_lo;
394 	uint32_t reg_lo;
395 	uint32_t seg_hi;
396 	uint32_t reg_hi;
397 	uint32_t reg_inst;
398 	uint32_t flags;
399 	const char *block_name;
400 };
401 
402 struct amdgpu_ras_memory_id_entry {
403 	uint32_t memory_id;
404 	const char *name;
405 };
406 
407 struct ras_common_if {
408 	enum amdgpu_ras_block block;
409 	enum amdgpu_ras_error_type type;
410 	uint32_t sub_block_index;
411 	char name[32];
412 };
413 
414 #define MAX_UMC_CHANNEL_NUM 32
415 
416 struct ecc_info_per_ch {
417 	uint16_t ce_count_lo_chip;
418 	uint16_t ce_count_hi_chip;
419 	uint64_t mca_umc_status;
420 	uint64_t mca_umc_addr;
421 	uint64_t mca_ceumc_addr;
422 };
423 
424 struct umc_ecc_info {
425 	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
426 
427 	/* Determine smu ecctable whether support
428 	 * record correctable error address
429 	 */
430 	int record_ce_addr_supported;
431 };
432 
433 enum ras_event_type {
434 	RAS_EVENT_TYPE_INVALID = -1,
435 	RAS_EVENT_TYPE_ISR = 0,
436 	RAS_EVENT_TYPE_COUNT,
437 };
438 
439 struct ras_event_manager {
440 	atomic64_t seqnos[RAS_EVENT_TYPE_COUNT];
441 };
442 
443 struct ras_query_context {
444 	enum ras_event_type type;
445 	u64 event_id;
446 };
447 
448 typedef int (*pasid_notify)(struct amdgpu_device *adev,
449 		uint16_t pasid, void *data);
450 
451 struct ras_poison_msg {
452 	enum amdgpu_ras_block block;
453 	uint16_t pasid;
454 	uint32_t reset;
455 	pasid_notify pasid_fn;
456 	void *data;
457 };
458 
459 struct ras_err_pages {
460 	uint32_t count;
461 	uint64_t *pfn;
462 };
463 
464 struct ras_ecc_err {
465 	u64 hash_index;
466 	uint64_t status;
467 	uint64_t ipid;
468 	uint64_t addr;
469 	struct ras_err_pages err_pages;
470 };
471 
472 struct ras_ecc_log_info {
473 	struct mutex lock;
474 	siphash_key_t ecc_key;
475 	struct radix_tree_root de_page_tree;
476 	bool	de_updated;
477 };
478 
479 struct amdgpu_ras {
480 	/* ras infrastructure */
481 	/* for ras itself. */
482 	uint32_t features;
483 	uint32_t schema;
484 	struct list_head head;
485 	/* sysfs */
486 	struct device_attribute features_attr;
487 	struct device_attribute version_attr;
488 	struct device_attribute schema_attr;
489 	struct bin_attribute badpages_attr;
490 	struct dentry *de_ras_eeprom_table;
491 	/* block array */
492 	struct ras_manager *objs;
493 
494 	/* gpu recovery */
495 	struct work_struct recovery_work;
496 	atomic_t in_recovery;
497 	struct amdgpu_device *adev;
498 	/* error handler data */
499 	struct ras_err_handler_data *eh_data;
500 	struct mutex recovery_lock;
501 
502 	uint32_t flags;
503 	bool reboot;
504 	struct amdgpu_ras_eeprom_control eeprom_control;
505 
506 	bool error_query_ready;
507 
508 	/* bad page count threshold */
509 	uint32_t bad_page_cnt_threshold;
510 
511 	/* disable ras error count harvest in recovery */
512 	bool disable_ras_err_cnt_harvest;
513 
514 	/* is poison mode supported */
515 	bool poison_supported;
516 
517 	/* RAS count errors delayed work */
518 	struct delayed_work ras_counte_delay_work;
519 	atomic_t ras_ue_count;
520 	atomic_t ras_ce_count;
521 
522 	/* record umc error info queried from smu */
523 	struct umc_ecc_info umc_ecc;
524 
525 	/* Indicates smu whether need update bad channel info */
526 	bool update_channel_flag;
527 	/* Record status of smu mca debug mode */
528 	bool is_aca_debug_mode;
529 
530 	/* Record special requirements of gpu reset caller */
531 	uint32_t  gpu_reset_flags;
532 
533 	struct task_struct *page_retirement_thread;
534 	wait_queue_head_t page_retirement_wq;
535 	struct mutex page_retirement_lock;
536 	atomic_t page_retirement_req_cnt;
537 	struct mutex page_rsv_lock;
538 	DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128);
539 	struct ras_ecc_log_info  umc_ecc_log;
540 	struct delayed_work page_retirement_dwork;
541 
542 	/* Fatal error detected flag */
543 	atomic_t fed;
544 
545 	/* RAS event manager */
546 	struct ras_event_manager __event_mgr;
547 	struct ras_event_manager *event_mgr;
548 
549 };
550 
551 struct ras_fs_data {
552 	char sysfs_name[48];
553 	char debugfs_name[32];
554 };
555 
556 struct ras_err_addr {
557 	struct list_head node;
558 	uint64_t err_status;
559 	uint64_t err_ipid;
560 	uint64_t err_addr;
561 };
562 
563 struct ras_err_info {
564 	struct amdgpu_smuio_mcm_config_info mcm_info;
565 	u64 ce_count;
566 	u64 ue_count;
567 	u64 de_count;
568 	struct list_head err_addr_list;
569 };
570 
571 struct ras_err_node {
572 	struct list_head node;
573 	struct ras_err_info err_info;
574 };
575 
576 struct ras_err_data {
577 	unsigned long ue_count;
578 	unsigned long ce_count;
579 	unsigned long de_count;
580 	unsigned long err_addr_cnt;
581 	struct eeprom_table_record *err_addr;
582 	unsigned long err_addr_len;
583 	u32 err_list_count;
584 	struct list_head err_node_list;
585 };
586 
587 #define for_each_ras_error(err_node, err_data) \
588 	list_for_each_entry(err_node, &(err_data)->err_node_list, node)
589 
590 struct ras_err_handler_data {
591 	/* point to bad page records array */
592 	struct eeprom_table_record *bps;
593 	/* the count of entries */
594 	int count;
595 	/* the space can place new entries */
596 	int space_left;
597 };
598 
599 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
600 		void *err_data,
601 		struct amdgpu_iv_entry *entry);
602 
603 struct ras_ih_data {
604 	/* interrupt bottom half */
605 	struct work_struct ih_work;
606 	int inuse;
607 	/* IP callback */
608 	ras_ih_cb cb;
609 	/* full of entries */
610 	unsigned char *ring;
611 	unsigned int ring_size;
612 	unsigned int element_size;
613 	unsigned int aligned_element_size;
614 	unsigned int rptr;
615 	unsigned int wptr;
616 };
617 
618 struct ras_manager {
619 	struct ras_common_if head;
620 	/* reference count */
621 	int use;
622 	/* ras block link */
623 	struct list_head node;
624 	/* the device */
625 	struct amdgpu_device *adev;
626 	/* sysfs */
627 	struct device_attribute sysfs_attr;
628 	int attr_inuse;
629 
630 	/* fs node name */
631 	struct ras_fs_data fs_data;
632 
633 	/* IH data */
634 	struct ras_ih_data ih_data;
635 
636 	struct ras_err_data err_data;
637 
638 	struct aca_handle aca_handle;
639 };
640 
641 struct ras_badpage {
642 	unsigned int bp;
643 	unsigned int size;
644 	unsigned int flags;
645 };
646 
647 /* interfaces for IP */
648 struct ras_fs_if {
649 	struct ras_common_if head;
650 	const char* sysfs_name;
651 	char debugfs_name[32];
652 };
653 
654 struct ras_query_if {
655 	struct ras_common_if head;
656 	unsigned long ue_count;
657 	unsigned long ce_count;
658 	unsigned long de_count;
659 };
660 
661 struct ras_inject_if {
662 	struct ras_common_if head;
663 	uint64_t address;
664 	uint64_t value;
665 	uint32_t instance_mask;
666 };
667 
668 struct ras_cure_if {
669 	struct ras_common_if head;
670 	uint64_t address;
671 };
672 
673 struct ras_ih_if {
674 	struct ras_common_if head;
675 	ras_ih_cb cb;
676 };
677 
678 struct ras_dispatch_if {
679 	struct ras_common_if head;
680 	struct amdgpu_iv_entry *entry;
681 };
682 
683 struct ras_debug_if {
684 	union {
685 		struct ras_common_if head;
686 		struct ras_inject_if inject;
687 	};
688 	int op;
689 };
690 
691 struct amdgpu_ras_block_object {
692 	struct ras_common_if  ras_comm;
693 
694 	int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
695 				enum amdgpu_ras_block block, uint32_t sub_block_index);
696 	int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
697 	void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
698 	ras_ih_cb ras_cb;
699 	const struct amdgpu_ras_block_hw_ops *hw_ops;
700 };
701 
702 struct amdgpu_ras_block_hw_ops {
703 	int  (*ras_error_inject)(struct amdgpu_device *adev,
704 			void *inject_if, uint32_t instance_mask);
705 	void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
706 	void (*query_ras_error_status)(struct amdgpu_device *adev);
707 	void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
708 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
709 	void (*reset_ras_error_status)(struct amdgpu_device *adev);
710 	bool (*query_poison_status)(struct amdgpu_device *adev);
711 	bool (*handle_poison_consumption)(struct amdgpu_device *adev);
712 };
713 
714 /* work flow
715  * vbios
716  * 1: ras feature enable (enabled by default)
717  * psp
718  * 2: ras framework init (in ip_init)
719  * IP
720  * 3: IH add
721  * 4: debugfs/sysfs create
722  * 5: query/inject
723  * 6: debugfs/sysfs remove
724  * 7: IH remove
725  * 8: feature disable
726  */
727 
728 
729 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
730 
731 void amdgpu_ras_resume(struct amdgpu_device *adev);
732 void amdgpu_ras_suspend(struct amdgpu_device *adev);
733 
734 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
735 				 unsigned long *ce_count,
736 				 unsigned long *ue_count,
737 				 struct ras_query_if *query_info);
738 
739 /* error handling functions */
740 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
741 		struct eeprom_table_record *bps, int pages);
742 
743 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
744 		unsigned long *new_cnt);
745 
746 static inline enum ta_ras_block
747 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
748 	switch (block) {
749 	case AMDGPU_RAS_BLOCK__UMC:
750 		return TA_RAS_BLOCK__UMC;
751 	case AMDGPU_RAS_BLOCK__SDMA:
752 		return TA_RAS_BLOCK__SDMA;
753 	case AMDGPU_RAS_BLOCK__GFX:
754 		return TA_RAS_BLOCK__GFX;
755 	case AMDGPU_RAS_BLOCK__MMHUB:
756 		return TA_RAS_BLOCK__MMHUB;
757 	case AMDGPU_RAS_BLOCK__ATHUB:
758 		return TA_RAS_BLOCK__ATHUB;
759 	case AMDGPU_RAS_BLOCK__PCIE_BIF:
760 		return TA_RAS_BLOCK__PCIE_BIF;
761 	case AMDGPU_RAS_BLOCK__HDP:
762 		return TA_RAS_BLOCK__HDP;
763 	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
764 		return TA_RAS_BLOCK__XGMI_WAFL;
765 	case AMDGPU_RAS_BLOCK__DF:
766 		return TA_RAS_BLOCK__DF;
767 	case AMDGPU_RAS_BLOCK__SMN:
768 		return TA_RAS_BLOCK__SMN;
769 	case AMDGPU_RAS_BLOCK__SEM:
770 		return TA_RAS_BLOCK__SEM;
771 	case AMDGPU_RAS_BLOCK__MP0:
772 		return TA_RAS_BLOCK__MP0;
773 	case AMDGPU_RAS_BLOCK__MP1:
774 		return TA_RAS_BLOCK__MP1;
775 	case AMDGPU_RAS_BLOCK__FUSE:
776 		return TA_RAS_BLOCK__FUSE;
777 	case AMDGPU_RAS_BLOCK__MCA:
778 		return TA_RAS_BLOCK__MCA;
779 	case AMDGPU_RAS_BLOCK__VCN:
780 		return TA_RAS_BLOCK__VCN;
781 	case AMDGPU_RAS_BLOCK__JPEG:
782 		return TA_RAS_BLOCK__JPEG;
783 	default:
784 		WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
785 		return TA_RAS_BLOCK__UMC;
786 	}
787 }
788 
789 static inline enum ta_ras_error_type
790 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
791 	switch (error) {
792 	case AMDGPU_RAS_ERROR__NONE:
793 		return TA_RAS_ERROR__NONE;
794 	case AMDGPU_RAS_ERROR__PARITY:
795 		return TA_RAS_ERROR__PARITY;
796 	case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
797 		return TA_RAS_ERROR__SINGLE_CORRECTABLE;
798 	case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
799 		return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
800 	case AMDGPU_RAS_ERROR__POISON:
801 		return TA_RAS_ERROR__POISON;
802 	default:
803 		WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
804 		return TA_RAS_ERROR__NONE;
805 	}
806 }
807 
808 /* called in ip_init and ip_fini */
809 int amdgpu_ras_init(struct amdgpu_device *adev);
810 int amdgpu_ras_late_init(struct amdgpu_device *adev);
811 int amdgpu_ras_fini(struct amdgpu_device *adev);
812 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
813 
814 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
815 			struct ras_common_if *ras_block);
816 
817 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
818 			  struct ras_common_if *ras_block);
819 
820 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
821 		struct ras_common_if *head, bool enable);
822 
823 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
824 		struct ras_common_if *head, bool enable);
825 
826 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
827 		struct ras_common_if *head);
828 
829 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
830 		struct ras_common_if *head);
831 
832 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
833 
834 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
835 		struct ras_query_if *info);
836 
837 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
838 		enum amdgpu_ras_block block);
839 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
840 		enum amdgpu_ras_block block);
841 
842 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
843 		struct ras_inject_if *info);
844 
845 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
846 		struct ras_common_if *head);
847 
848 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
849 		struct ras_common_if *head);
850 
851 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
852 		struct ras_dispatch_if *info);
853 
854 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
855 		struct ras_common_if *head);
856 
857 extern atomic_t amdgpu_ras_in_intr;
858 
859 static inline bool amdgpu_ras_intr_triggered(void)
860 {
861 	return !!atomic_read(&amdgpu_ras_in_intr);
862 }
863 
864 static inline void amdgpu_ras_intr_cleared(void)
865 {
866 	atomic_set(&amdgpu_ras_in_intr, 0);
867 }
868 
869 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
870 
871 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
872 
873 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
874 
875 void amdgpu_release_ras_context(struct amdgpu_device *adev);
876 
877 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
878 
879 const char *get_ras_block_str(struct ras_common_if *ras_block);
880 
881 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
882 
883 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
884 
885 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
886 
887 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
888 
889 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
890 
891 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
892 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable);
893 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev);
894 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
895 				     unsigned int *mode);
896 
897 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
898 				struct amdgpu_ras_block_object *ras_block_obj);
899 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
900 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
901 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
902 					 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
903 					 uint32_t instance,
904 					 uint32_t *memory_id);
905 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
906 				       const struct amdgpu_ras_err_status_reg_entry *reg_entry,
907 				       uint32_t instance,
908 				       unsigned long *err_cnt);
909 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
910 					   const struct amdgpu_ras_err_status_reg_entry *reg_list,
911 					   uint32_t reg_list_size,
912 					   const struct amdgpu_ras_memory_id_entry *mem_list,
913 					   uint32_t mem_list_size,
914 					   uint32_t instance,
915 					   uint32_t err_type,
916 					   unsigned long *err_count);
917 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
918 					   const struct amdgpu_ras_err_status_reg_entry *reg_list,
919 					   uint32_t reg_list_size,
920 					   uint32_t instance);
921 
922 int amdgpu_ras_error_data_init(struct ras_err_data *err_data);
923 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);
924 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
925 		struct amdgpu_smuio_mcm_config_info *mcm_info,
926 		struct ras_err_addr *err_addr, u64 count);
927 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
928 		struct amdgpu_smuio_mcm_config_info *mcm_info,
929 		struct ras_err_addr *err_addr, u64 count);
930 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,
931 		struct amdgpu_smuio_mcm_config_info *mcm_info,
932 		struct ras_err_addr *err_addr, u64 count);
933 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);
934 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
935 			       const struct aca_info *aca_info, void *data);
936 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk);
937 
938 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,
939 				  struct aca_handle *handle, char *buf, void *data);
940 
941 void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info,
942 			struct ras_err_addr *err_addr);
943 
944 void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info,
945 		struct ras_err_addr *mca_err_addr);
946 
947 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
948 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
949 
950 bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id);
951 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);
952 
953 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);
954 
955 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,
956 		enum amdgpu_ras_block block, uint16_t pasid,
957 		pasid_notify pasid_fn, void *data, uint32_t reset);
958 
959 #endif
960