1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include <linux/kfifo.h> 30 #include <linux/radix-tree.h> 31 #include "ta_ras_if.h" 32 #include "amdgpu_ras_eeprom.h" 33 #include "amdgpu_smuio.h" 34 #include "amdgpu_aca.h" 35 36 struct amdgpu_iv_entry; 37 38 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 39 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 40 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 41 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 42 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 43 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 44 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 45 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 46 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 47 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 48 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13) 49 50 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 100 51 #define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA 52 #define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF 53 54 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 55 /* position of instance value in sub_block_index of 56 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 57 */ 58 #define AMDGPU_RAS_INST_MASK 0xfffff000 59 #define AMDGPU_RAS_INST_SHIFT 0xc 60 61 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 62 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 63 64 /* Reserve 8 physical dram row for possible retirement. 65 * In worst cases, it will lose 8 * 2MB memory in vram domain */ 66 #define AMDGPU_RAS_RESERVED_VRAM_SIZE (16ULL << 20) 67 /* The high three bits indicates socketid */ 68 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 69 70 #define RAS_EVENT_INVALID_ID (BIT_ULL(63)) 71 #define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63))) 72 73 #define RAS_EVENT_LOG(adev, id, fmt, ...) \ 74 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__) 75 76 #define amdgpu_ras_mark_ras_event(adev, type) \ 77 (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0))) 78 79 enum amdgpu_ras_block { 80 AMDGPU_RAS_BLOCK__UMC = 0, 81 AMDGPU_RAS_BLOCK__SDMA, 82 AMDGPU_RAS_BLOCK__GFX, 83 AMDGPU_RAS_BLOCK__MMHUB, 84 AMDGPU_RAS_BLOCK__ATHUB, 85 AMDGPU_RAS_BLOCK__PCIE_BIF, 86 AMDGPU_RAS_BLOCK__HDP, 87 AMDGPU_RAS_BLOCK__XGMI_WAFL, 88 AMDGPU_RAS_BLOCK__DF, 89 AMDGPU_RAS_BLOCK__SMN, 90 AMDGPU_RAS_BLOCK__SEM, 91 AMDGPU_RAS_BLOCK__MP0, 92 AMDGPU_RAS_BLOCK__MP1, 93 AMDGPU_RAS_BLOCK__FUSE, 94 AMDGPU_RAS_BLOCK__MCA, 95 AMDGPU_RAS_BLOCK__VCN, 96 AMDGPU_RAS_BLOCK__JPEG, 97 AMDGPU_RAS_BLOCK__IH, 98 AMDGPU_RAS_BLOCK__MPIO, 99 100 AMDGPU_RAS_BLOCK__LAST 101 }; 102 103 enum amdgpu_ras_mca_block { 104 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 105 AMDGPU_RAS_MCA_BLOCK__MP1, 106 AMDGPU_RAS_MCA_BLOCK__MPIO, 107 AMDGPU_RAS_MCA_BLOCK__IOHC, 108 109 AMDGPU_RAS_MCA_BLOCK__LAST 110 }; 111 112 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 113 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 114 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 115 116 enum amdgpu_ras_gfx_subblock { 117 /* CPC */ 118 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 119 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 120 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 121 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 122 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 123 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 124 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 125 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 126 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 127 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 128 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 129 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 130 /* CPF */ 131 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 132 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 133 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 134 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 135 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 136 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 137 /* CPG */ 138 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 139 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 140 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 141 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 142 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 143 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 144 /* GDS */ 145 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 146 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 147 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 148 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 149 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 150 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 151 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 152 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 153 /* SPI */ 154 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 155 /* SQ */ 156 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 157 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 158 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 159 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 160 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 161 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 162 /* SQC (3 ranges) */ 163 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 164 /* SQC range 0 */ 165 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 166 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 167 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 168 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 169 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 170 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 171 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 172 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 174 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 175 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 176 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 177 /* SQC range 1 */ 178 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 179 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 180 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 181 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 182 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 183 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 184 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 185 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 186 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 187 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 188 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 189 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 190 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 191 /* SQC range 2 */ 192 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 193 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 194 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 195 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 196 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 197 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 198 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 199 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 200 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 201 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 202 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 203 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 204 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 205 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 206 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 207 /* TA */ 208 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 209 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 210 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 211 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 212 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 213 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 214 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 215 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 216 /* TCA */ 217 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 218 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 219 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 220 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 221 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 222 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 223 /* TCC (5 sub-ranges) */ 224 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 225 /* TCC range 0 */ 226 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 227 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 228 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 230 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 231 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 232 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 233 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 234 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 235 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 236 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 237 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 238 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 239 /* TCC range 1 */ 240 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 241 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 242 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 243 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 244 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 245 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 246 /* TCC range 2 */ 247 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 248 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 249 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 250 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 251 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 252 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 253 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 254 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 255 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 256 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 257 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 258 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 259 /* TCC range 3 */ 260 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 261 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 262 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 263 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 264 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 265 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 266 /* TCC range 4 */ 267 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 268 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 269 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 270 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 271 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 272 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 273 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 274 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 275 /* TCI */ 276 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 277 /* TCP */ 278 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 279 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 280 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 281 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 282 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 283 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 284 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 285 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 286 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 287 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 288 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 289 /* TD */ 290 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 291 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 292 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 293 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 294 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 295 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 296 /* EA (3 sub-ranges) */ 297 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 298 /* EA range 0 */ 299 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 300 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 301 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 302 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 303 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 304 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 305 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 306 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 307 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 308 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 309 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 310 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 311 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 312 /* EA range 1 */ 313 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 314 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 315 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 316 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 317 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 318 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 319 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 320 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 321 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 322 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 323 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 324 /* EA range 2 */ 325 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 326 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 327 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 328 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 329 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 330 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 331 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 332 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 333 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 334 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 335 /* UTC VM L2 bank */ 336 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 337 /* UTC VM walker */ 338 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 339 /* UTC ATC L2 2MB cache */ 340 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 341 /* UTC ATC L2 4KB cache */ 342 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 343 AMDGPU_RAS_BLOCK__GFX_MAX 344 }; 345 346 enum amdgpu_ras_error_type { 347 AMDGPU_RAS_ERROR__NONE = 0, 348 AMDGPU_RAS_ERROR__PARITY = 1, 349 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 350 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 351 AMDGPU_RAS_ERROR__POISON = 8, 352 }; 353 354 enum amdgpu_ras_ret { 355 AMDGPU_RAS_SUCCESS = 0, 356 AMDGPU_RAS_FAIL, 357 AMDGPU_RAS_UE, 358 AMDGPU_RAS_CE, 359 AMDGPU_RAS_PT, 360 }; 361 362 enum amdgpu_ras_error_query_mode { 363 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 364 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 365 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 366 }; 367 368 /* ras error status reisger fields */ 369 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 370 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 371 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 372 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 373 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 374 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 375 #define ERR_STATUS__ERR_CNT__SHIFT 0x17 376 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L 377 378 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 379 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 380 381 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 382 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 383 384 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 385 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 386 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 387 388 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 389 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 390 391 struct amdgpu_ras_err_status_reg_entry { 392 uint32_t hwip; 393 uint32_t ip_inst; 394 uint32_t seg_lo; 395 uint32_t reg_lo; 396 uint32_t seg_hi; 397 uint32_t reg_hi; 398 uint32_t reg_inst; 399 uint32_t flags; 400 const char *block_name; 401 }; 402 403 struct amdgpu_ras_memory_id_entry { 404 uint32_t memory_id; 405 const char *name; 406 }; 407 408 struct ras_common_if { 409 enum amdgpu_ras_block block; 410 enum amdgpu_ras_error_type type; 411 uint32_t sub_block_index; 412 char name[32]; 413 }; 414 415 #define MAX_UMC_CHANNEL_NUM 32 416 417 struct ecc_info_per_ch { 418 uint16_t ce_count_lo_chip; 419 uint16_t ce_count_hi_chip; 420 uint64_t mca_umc_status; 421 uint64_t mca_umc_addr; 422 uint64_t mca_ceumc_addr; 423 }; 424 425 struct umc_ecc_info { 426 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 427 428 /* Determine smu ecctable whether support 429 * record correctable error address 430 */ 431 int record_ce_addr_supported; 432 }; 433 434 enum ras_event_type { 435 RAS_EVENT_TYPE_INVALID = 0, 436 RAS_EVENT_TYPE_FATAL, 437 RAS_EVENT_TYPE_POISON_CREATION, 438 RAS_EVENT_TYPE_POISON_CONSUMPTION, 439 RAS_EVENT_TYPE_COUNT, 440 }; 441 442 struct ras_event_state { 443 u64 last_seqno; 444 atomic64_t count; 445 }; 446 447 struct ras_event_manager { 448 atomic64_t seqno; 449 struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT]; 450 }; 451 452 struct ras_event_id { 453 enum ras_event_type type; 454 u64 event_id; 455 }; 456 457 struct ras_query_context { 458 struct ras_event_id evid; 459 }; 460 461 typedef int (*pasid_notify)(struct amdgpu_device *adev, 462 uint16_t pasid, void *data); 463 464 struct ras_poison_msg { 465 enum amdgpu_ras_block block; 466 uint16_t pasid; 467 uint32_t reset; 468 pasid_notify pasid_fn; 469 void *data; 470 }; 471 472 struct ras_err_pages { 473 uint32_t count; 474 uint64_t *pfn; 475 }; 476 477 struct ras_ecc_err { 478 uint64_t status; 479 uint64_t ipid; 480 uint64_t addr; 481 uint64_t pa_pfn; 482 struct ras_err_pages err_pages; 483 }; 484 485 struct ras_ecc_log_info { 486 struct mutex lock; 487 struct radix_tree_root de_page_tree; 488 uint64_t de_queried_count; 489 uint64_t prev_de_queried_count; 490 }; 491 492 struct amdgpu_ras { 493 /* ras infrastructure */ 494 /* for ras itself. */ 495 uint32_t features; 496 uint32_t schema; 497 struct list_head head; 498 /* sysfs */ 499 struct device_attribute features_attr; 500 struct device_attribute version_attr; 501 struct device_attribute schema_attr; 502 struct device_attribute event_state_attr; 503 struct bin_attribute badpages_attr; 504 struct dentry *de_ras_eeprom_table; 505 /* block array */ 506 struct ras_manager *objs; 507 508 /* gpu recovery */ 509 struct work_struct recovery_work; 510 atomic_t in_recovery; 511 struct amdgpu_device *adev; 512 /* error handler data */ 513 struct ras_err_handler_data *eh_data; 514 struct mutex recovery_lock; 515 516 uint32_t flags; 517 bool reboot; 518 struct amdgpu_ras_eeprom_control eeprom_control; 519 520 bool error_query_ready; 521 522 /* bad page count threshold */ 523 uint32_t bad_page_cnt_threshold; 524 525 /* disable ras error count harvest in recovery */ 526 bool disable_ras_err_cnt_harvest; 527 528 /* is poison mode supported */ 529 bool poison_supported; 530 531 /* RAS count errors delayed work */ 532 struct delayed_work ras_counte_delay_work; 533 atomic_t ras_ue_count; 534 atomic_t ras_ce_count; 535 536 /* record umc error info queried from smu */ 537 struct umc_ecc_info umc_ecc; 538 539 /* Indicates smu whether need update bad channel info */ 540 bool update_channel_flag; 541 /* Record status of smu mca debug mode */ 542 bool is_aca_debug_mode; 543 bool is_rma; 544 545 /* Record special requirements of gpu reset caller */ 546 uint32_t gpu_reset_flags; 547 548 struct task_struct *page_retirement_thread; 549 wait_queue_head_t page_retirement_wq; 550 struct mutex page_retirement_lock; 551 atomic_t page_retirement_req_cnt; 552 atomic_t poison_creation_count; 553 struct mutex page_rsv_lock; 554 DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128); 555 struct ras_ecc_log_info umc_ecc_log; 556 struct delayed_work page_retirement_dwork; 557 558 /* Fatal error detected flag */ 559 atomic_t fed; 560 561 /* RAS event manager */ 562 struct ras_event_manager __event_mgr; 563 struct ras_event_manager *event_mgr; 564 565 uint64_t reserved_pages_in_bytes; 566 }; 567 568 struct ras_fs_data { 569 char sysfs_name[48]; 570 char debugfs_name[32]; 571 }; 572 573 struct ras_err_addr { 574 uint64_t err_status; 575 uint64_t err_ipid; 576 uint64_t err_addr; 577 }; 578 579 struct ras_err_info { 580 struct amdgpu_smuio_mcm_config_info mcm_info; 581 u64 ce_count; 582 u64 ue_count; 583 u64 de_count; 584 }; 585 586 struct ras_err_node { 587 struct list_head node; 588 struct ras_err_info err_info; 589 }; 590 591 struct ras_err_data { 592 unsigned long ue_count; 593 unsigned long ce_count; 594 unsigned long de_count; 595 unsigned long err_addr_cnt; 596 struct eeprom_table_record *err_addr; 597 unsigned long err_addr_len; 598 u32 err_list_count; 599 struct list_head err_node_list; 600 }; 601 602 #define for_each_ras_error(err_node, err_data) \ 603 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 604 605 struct ras_err_handler_data { 606 /* point to bad page records array */ 607 struct eeprom_table_record *bps; 608 /* the count of entries */ 609 int count; 610 /* the space can place new entries */ 611 int space_left; 612 }; 613 614 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 615 void *err_data, 616 struct amdgpu_iv_entry *entry); 617 618 struct ras_ih_data { 619 /* interrupt bottom half */ 620 struct work_struct ih_work; 621 int inuse; 622 /* IP callback */ 623 ras_ih_cb cb; 624 /* full of entries */ 625 unsigned char *ring; 626 unsigned int ring_size; 627 unsigned int element_size; 628 unsigned int aligned_element_size; 629 unsigned int rptr; 630 unsigned int wptr; 631 }; 632 633 struct ras_manager { 634 struct ras_common_if head; 635 /* reference count */ 636 int use; 637 /* ras block link */ 638 struct list_head node; 639 /* the device */ 640 struct amdgpu_device *adev; 641 /* sysfs */ 642 struct device_attribute sysfs_attr; 643 int attr_inuse; 644 645 /* fs node name */ 646 struct ras_fs_data fs_data; 647 648 /* IH data */ 649 struct ras_ih_data ih_data; 650 651 struct ras_err_data err_data; 652 653 struct aca_handle aca_handle; 654 }; 655 656 struct ras_badpage { 657 unsigned int bp; 658 unsigned int size; 659 unsigned int flags; 660 }; 661 662 /* interfaces for IP */ 663 struct ras_fs_if { 664 struct ras_common_if head; 665 const char* sysfs_name; 666 char debugfs_name[32]; 667 }; 668 669 struct ras_query_if { 670 struct ras_common_if head; 671 unsigned long ue_count; 672 unsigned long ce_count; 673 unsigned long de_count; 674 }; 675 676 struct ras_inject_if { 677 struct ras_common_if head; 678 uint64_t address; 679 uint64_t value; 680 uint32_t instance_mask; 681 }; 682 683 struct ras_cure_if { 684 struct ras_common_if head; 685 uint64_t address; 686 }; 687 688 struct ras_ih_if { 689 struct ras_common_if head; 690 ras_ih_cb cb; 691 }; 692 693 struct ras_dispatch_if { 694 struct ras_common_if head; 695 struct amdgpu_iv_entry *entry; 696 }; 697 698 struct ras_debug_if { 699 union { 700 struct ras_common_if head; 701 struct ras_inject_if inject; 702 }; 703 int op; 704 }; 705 706 struct amdgpu_ras_block_object { 707 struct ras_common_if ras_comm; 708 709 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 710 enum amdgpu_ras_block block, uint32_t sub_block_index); 711 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 712 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 713 ras_ih_cb ras_cb; 714 const struct amdgpu_ras_block_hw_ops *hw_ops; 715 }; 716 717 struct amdgpu_ras_block_hw_ops { 718 int (*ras_error_inject)(struct amdgpu_device *adev, 719 void *inject_if, uint32_t instance_mask); 720 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 721 void (*query_ras_error_status)(struct amdgpu_device *adev); 722 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 723 void (*reset_ras_error_count)(struct amdgpu_device *adev); 724 void (*reset_ras_error_status)(struct amdgpu_device *adev); 725 bool (*query_poison_status)(struct amdgpu_device *adev); 726 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 727 }; 728 729 /* work flow 730 * vbios 731 * 1: ras feature enable (enabled by default) 732 * psp 733 * 2: ras framework init (in ip_init) 734 * IP 735 * 3: IH add 736 * 4: debugfs/sysfs create 737 * 5: query/inject 738 * 6: debugfs/sysfs remove 739 * 7: IH remove 740 * 8: feature disable 741 */ 742 743 744 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 745 746 void amdgpu_ras_resume(struct amdgpu_device *adev); 747 void amdgpu_ras_suspend(struct amdgpu_device *adev); 748 749 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 750 unsigned long *ce_count, 751 unsigned long *ue_count, 752 struct ras_query_if *query_info); 753 754 /* error handling functions */ 755 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 756 struct eeprom_table_record *bps, int pages); 757 758 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 759 unsigned long *new_cnt); 760 761 static inline enum ta_ras_block 762 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 763 switch (block) { 764 case AMDGPU_RAS_BLOCK__UMC: 765 return TA_RAS_BLOCK__UMC; 766 case AMDGPU_RAS_BLOCK__SDMA: 767 return TA_RAS_BLOCK__SDMA; 768 case AMDGPU_RAS_BLOCK__GFX: 769 return TA_RAS_BLOCK__GFX; 770 case AMDGPU_RAS_BLOCK__MMHUB: 771 return TA_RAS_BLOCK__MMHUB; 772 case AMDGPU_RAS_BLOCK__ATHUB: 773 return TA_RAS_BLOCK__ATHUB; 774 case AMDGPU_RAS_BLOCK__PCIE_BIF: 775 return TA_RAS_BLOCK__PCIE_BIF; 776 case AMDGPU_RAS_BLOCK__HDP: 777 return TA_RAS_BLOCK__HDP; 778 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 779 return TA_RAS_BLOCK__XGMI_WAFL; 780 case AMDGPU_RAS_BLOCK__DF: 781 return TA_RAS_BLOCK__DF; 782 case AMDGPU_RAS_BLOCK__SMN: 783 return TA_RAS_BLOCK__SMN; 784 case AMDGPU_RAS_BLOCK__SEM: 785 return TA_RAS_BLOCK__SEM; 786 case AMDGPU_RAS_BLOCK__MP0: 787 return TA_RAS_BLOCK__MP0; 788 case AMDGPU_RAS_BLOCK__MP1: 789 return TA_RAS_BLOCK__MP1; 790 case AMDGPU_RAS_BLOCK__FUSE: 791 return TA_RAS_BLOCK__FUSE; 792 case AMDGPU_RAS_BLOCK__MCA: 793 return TA_RAS_BLOCK__MCA; 794 case AMDGPU_RAS_BLOCK__VCN: 795 return TA_RAS_BLOCK__VCN; 796 case AMDGPU_RAS_BLOCK__JPEG: 797 return TA_RAS_BLOCK__JPEG; 798 default: 799 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 800 return TA_RAS_BLOCK__UMC; 801 } 802 } 803 804 static inline enum ta_ras_error_type 805 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 806 switch (error) { 807 case AMDGPU_RAS_ERROR__NONE: 808 return TA_RAS_ERROR__NONE; 809 case AMDGPU_RAS_ERROR__PARITY: 810 return TA_RAS_ERROR__PARITY; 811 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 812 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 813 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 814 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 815 case AMDGPU_RAS_ERROR__POISON: 816 return TA_RAS_ERROR__POISON; 817 default: 818 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 819 return TA_RAS_ERROR__NONE; 820 } 821 } 822 823 /* called in ip_init and ip_fini */ 824 int amdgpu_ras_init(struct amdgpu_device *adev); 825 int amdgpu_ras_late_init(struct amdgpu_device *adev); 826 int amdgpu_ras_fini(struct amdgpu_device *adev); 827 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 828 829 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 830 struct ras_common_if *ras_block); 831 832 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 833 struct ras_common_if *ras_block); 834 835 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 836 struct ras_common_if *head, bool enable); 837 838 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 839 struct ras_common_if *head, bool enable); 840 841 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 842 struct ras_common_if *head); 843 844 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 845 struct ras_common_if *head); 846 847 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 848 849 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 850 struct ras_query_if *info); 851 852 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 853 enum amdgpu_ras_block block); 854 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 855 enum amdgpu_ras_block block); 856 857 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 858 struct ras_inject_if *info); 859 860 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 861 struct ras_common_if *head); 862 863 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 864 struct ras_common_if *head); 865 866 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 867 struct ras_dispatch_if *info); 868 869 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 870 struct ras_common_if *head); 871 872 extern atomic_t amdgpu_ras_in_intr; 873 874 static inline bool amdgpu_ras_intr_triggered(void) 875 { 876 return !!atomic_read(&amdgpu_ras_in_intr); 877 } 878 879 static inline void amdgpu_ras_intr_cleared(void) 880 { 881 atomic_set(&amdgpu_ras_in_intr, 0); 882 } 883 884 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 885 886 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 887 888 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 889 890 void amdgpu_release_ras_context(struct amdgpu_device *adev); 891 892 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 893 894 const char *get_ras_block_str(struct ras_common_if *ras_block); 895 896 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 897 898 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 899 900 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 901 902 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 903 904 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 905 906 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 907 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); 908 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); 909 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 910 unsigned int *mode); 911 912 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 913 struct amdgpu_ras_block_object *ras_block_obj); 914 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 915 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 916 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 917 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 918 uint32_t instance, 919 uint32_t *memory_id); 920 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 921 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 922 uint32_t instance, 923 unsigned long *err_cnt); 924 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 925 const struct amdgpu_ras_err_status_reg_entry *reg_list, 926 uint32_t reg_list_size, 927 const struct amdgpu_ras_memory_id_entry *mem_list, 928 uint32_t mem_list_size, 929 uint32_t instance, 930 uint32_t err_type, 931 unsigned long *err_count); 932 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 933 const struct amdgpu_ras_err_status_reg_entry *reg_list, 934 uint32_t reg_list_size, 935 uint32_t instance); 936 937 int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 938 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 939 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 940 struct amdgpu_smuio_mcm_config_info *mcm_info, 941 struct ras_err_addr *err_addr, u64 count); 942 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 943 struct amdgpu_smuio_mcm_config_info *mcm_info, 944 struct ras_err_addr *err_addr, u64 count); 945 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 946 struct amdgpu_smuio_mcm_config_info *mcm_info, 947 struct ras_err_addr *err_addr, u64 count); 948 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 949 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 950 const struct aca_info *aca_info, void *data); 951 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); 952 953 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 954 struct aca_handle *handle, char *buf, void *data); 955 956 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); 957 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); 958 959 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); 960 int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, 961 const void *caller); 962 963 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); 964 965 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, 966 enum amdgpu_ras_block block, uint16_t pasid, 967 pasid_notify pasid_fn, void *data, uint32_t reset); 968 969 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev); 970 971 __printf(3, 4) 972 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, 973 const char *fmt, ...); 974 975 #endif 976