1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include <linux/kfifo.h> 30 #include <linux/radix-tree.h> 31 #include "ta_ras_if.h" 32 #include "amdgpu_ras_eeprom.h" 33 #include "amdgpu_smuio.h" 34 35 struct amdgpu_iv_entry; 36 37 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 38 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 39 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 40 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 41 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 42 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 43 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 44 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 45 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 46 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 47 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13) 48 #define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x) AMDGPU_GET_REG_FIELD(x, 29, 29) 49 #define AMDGPU_RAS_GPU_ERR_GENERIC(x) AMDGPU_GET_REG_FIELD(x, 30, 30) 50 51 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 100 52 #define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA 53 #define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF 54 55 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 56 /* position of instance value in sub_block_index of 57 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 58 */ 59 #define AMDGPU_RAS_INST_MASK 0xfffff000 60 #define AMDGPU_RAS_INST_SHIFT 0xc 61 62 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 63 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 64 65 /* Reserve 8 physical dram row for possible retirement. 66 * In worst cases, it will lose 8 * 2MB memory in vram domain */ 67 #define AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT (16ULL << 20) 68 /* The high three bits indicates socketid */ 69 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 70 71 #define RAS_EVENT_INVALID_ID (BIT_ULL(63)) 72 #define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63))) 73 74 #define RAS_EVENT_LOG(adev, id, fmt, ...) \ 75 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__) 76 77 #define amdgpu_ras_mark_ras_event(adev, type) \ 78 (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0))) 79 80 enum amdgpu_ras_block { 81 AMDGPU_RAS_BLOCK__UMC = 0, 82 AMDGPU_RAS_BLOCK__SDMA, 83 AMDGPU_RAS_BLOCK__GFX, 84 AMDGPU_RAS_BLOCK__MMHUB, 85 AMDGPU_RAS_BLOCK__ATHUB, 86 AMDGPU_RAS_BLOCK__PCIE_BIF, 87 AMDGPU_RAS_BLOCK__HDP, 88 AMDGPU_RAS_BLOCK__XGMI_WAFL, 89 AMDGPU_RAS_BLOCK__DF, 90 AMDGPU_RAS_BLOCK__SMN, 91 AMDGPU_RAS_BLOCK__SEM, 92 AMDGPU_RAS_BLOCK__MP0, 93 AMDGPU_RAS_BLOCK__MP1, 94 AMDGPU_RAS_BLOCK__FUSE, 95 AMDGPU_RAS_BLOCK__MCA, 96 AMDGPU_RAS_BLOCK__VCN, 97 AMDGPU_RAS_BLOCK__JPEG, 98 AMDGPU_RAS_BLOCK__IH, 99 AMDGPU_RAS_BLOCK__MPIO, 100 AMDGPU_RAS_BLOCK__MMSCH, 101 102 AMDGPU_RAS_BLOCK__LAST, 103 AMDGPU_RAS_BLOCK__ANY = -1 104 }; 105 106 enum amdgpu_ras_mca_block { 107 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 108 AMDGPU_RAS_MCA_BLOCK__MP1, 109 AMDGPU_RAS_MCA_BLOCK__MPIO, 110 AMDGPU_RAS_MCA_BLOCK__IOHC, 111 112 AMDGPU_RAS_MCA_BLOCK__LAST 113 }; 114 115 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 116 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 117 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 118 119 enum amdgpu_ras_gfx_subblock { 120 /* CPC */ 121 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 122 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 123 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 124 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 125 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 126 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 127 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 128 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 129 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 130 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 131 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 132 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 133 /* CPF */ 134 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 135 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 136 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 137 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 138 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 139 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 140 /* CPG */ 141 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 142 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 143 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 144 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 145 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 146 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 147 /* GDS */ 148 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 149 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 150 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 151 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 152 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 153 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 154 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 155 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 156 /* SPI */ 157 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 158 /* SQ */ 159 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 160 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 161 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 162 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 163 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 164 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 165 /* SQC (3 ranges) */ 166 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 167 /* SQC range 0 */ 168 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 169 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 170 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 171 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 172 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 174 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 175 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 176 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 177 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 178 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 179 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 180 /* SQC range 1 */ 181 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 182 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 183 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 184 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 185 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 186 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 187 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 188 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 189 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 190 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 191 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 192 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 193 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 194 /* SQC range 2 */ 195 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 196 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 197 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 198 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 199 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 200 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 201 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 202 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 203 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 204 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 205 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 206 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 207 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 208 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 209 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 210 /* TA */ 211 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 212 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 213 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 214 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 215 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 216 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 217 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 218 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 219 /* TCA */ 220 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 221 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 222 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 223 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 224 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 225 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 226 /* TCC (5 sub-ranges) */ 227 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 228 /* TCC range 0 */ 229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 230 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 231 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 232 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 233 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 234 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 235 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 236 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 237 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 238 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 239 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 240 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 241 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 242 /* TCC range 1 */ 243 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 244 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 245 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 246 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 247 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 248 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 249 /* TCC range 2 */ 250 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 251 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 252 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 253 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 254 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 255 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 256 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 257 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 258 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 259 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 260 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 261 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 262 /* TCC range 3 */ 263 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 264 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 265 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 266 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 267 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 268 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 269 /* TCC range 4 */ 270 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 271 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 272 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 273 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 274 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 275 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 276 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 277 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 278 /* TCI */ 279 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 280 /* TCP */ 281 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 282 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 283 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 284 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 285 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 286 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 287 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 288 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 289 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 290 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 291 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 292 /* TD */ 293 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 294 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 295 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 296 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 297 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 298 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 299 /* EA (3 sub-ranges) */ 300 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 301 /* EA range 0 */ 302 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 303 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 304 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 305 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 306 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 307 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 308 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 309 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 310 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 311 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 312 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 313 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 314 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 315 /* EA range 1 */ 316 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 317 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 318 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 319 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 320 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 321 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 322 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 323 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 324 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 325 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 326 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 327 /* EA range 2 */ 328 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 329 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 330 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 331 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 332 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 333 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 334 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 335 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 336 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 337 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 338 /* UTC VM L2 bank */ 339 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 340 /* UTC VM walker */ 341 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 342 /* UTC ATC L2 2MB cache */ 343 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 344 /* UTC ATC L2 4KB cache */ 345 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 346 AMDGPU_RAS_BLOCK__GFX_MAX 347 }; 348 349 enum amdgpu_ras_error_type { 350 AMDGPU_RAS_ERROR__NONE = 0, 351 AMDGPU_RAS_ERROR__PARITY = 1, 352 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 353 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 354 AMDGPU_RAS_ERROR__POISON = 8, 355 }; 356 357 enum amdgpu_ras_ret { 358 AMDGPU_RAS_SUCCESS = 0, 359 AMDGPU_RAS_FAIL, 360 AMDGPU_RAS_UE, 361 AMDGPU_RAS_CE, 362 AMDGPU_RAS_PT, 363 }; 364 365 enum amdgpu_ras_error_query_mode { 366 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 367 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 368 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 369 AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY = 3, 370 }; 371 372 /* ras error status reisger fields */ 373 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 374 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 375 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 376 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 377 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 378 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 379 #define ERR_STATUS__ERR_CNT__SHIFT 0x17 380 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L 381 382 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 383 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 384 385 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 386 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 387 388 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 389 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 390 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 391 392 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 393 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 394 395 struct amdgpu_ras_err_status_reg_entry { 396 uint32_t hwip; 397 uint32_t ip_inst; 398 uint32_t seg_lo; 399 uint32_t reg_lo; 400 uint32_t seg_hi; 401 uint32_t reg_hi; 402 uint32_t reg_inst; 403 uint32_t flags; 404 const char *block_name; 405 }; 406 407 struct amdgpu_ras_memory_id_entry { 408 uint32_t memory_id; 409 const char *name; 410 }; 411 412 struct ras_common_if { 413 enum amdgpu_ras_block block; 414 enum amdgpu_ras_error_type type; 415 uint32_t sub_block_index; 416 char name[32]; 417 }; 418 419 #define MAX_UMC_CHANNEL_NUM 32 420 421 struct ecc_info_per_ch { 422 uint16_t ce_count_lo_chip; 423 uint16_t ce_count_hi_chip; 424 uint64_t mca_umc_status; 425 uint64_t mca_umc_addr; 426 uint64_t mca_ceumc_addr; 427 }; 428 429 struct umc_ecc_info { 430 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 431 432 /* Determine smu ecctable whether support 433 * record correctable error address 434 */ 435 int record_ce_addr_supported; 436 }; 437 438 enum ras_event_type { 439 RAS_EVENT_TYPE_INVALID = 0, 440 RAS_EVENT_TYPE_FATAL, 441 RAS_EVENT_TYPE_POISON_CREATION, 442 RAS_EVENT_TYPE_POISON_CONSUMPTION, 443 RAS_EVENT_TYPE_COUNT, 444 }; 445 446 struct ras_event_state { 447 u64 last_seqno; 448 atomic64_t count; 449 }; 450 451 struct ras_event_manager { 452 atomic64_t seqno; 453 struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT]; 454 }; 455 456 struct ras_event_id { 457 enum ras_event_type type; 458 u64 event_id; 459 }; 460 461 struct ras_query_context { 462 struct ras_event_id evid; 463 }; 464 465 typedef int (*pasid_notify)(struct amdgpu_device *adev, 466 uint16_t pasid, void *data); 467 468 struct ras_err_pages { 469 uint32_t count; 470 uint64_t *pfn; 471 }; 472 473 struct ras_ecc_err { 474 uint64_t status; 475 uint64_t ipid; 476 uint64_t addr; 477 uint64_t pa_pfn; 478 /* save global channel index across all UMC instances */ 479 uint32_t channel_idx; 480 struct ras_err_pages err_pages; 481 }; 482 483 struct ras_ecc_log_info { 484 struct mutex lock; 485 struct radix_tree_root de_page_tree; 486 }; 487 488 struct ras_critical_region { 489 struct list_head node; 490 struct amdgpu_bo *bo; 491 uint64_t start; 492 uint64_t size; 493 }; 494 495 struct ras_eeprom_table_version { 496 uint32_t minor : 16; 497 uint32_t major : 16; 498 }; 499 500 struct ras_eeprom_smu_funcs { 501 int (*get_ras_table_version)(struct amdgpu_device *adev, 502 uint32_t *table_version); 503 int (*get_badpage_count)(struct amdgpu_device *adev, uint32_t *count, uint32_t timeout); 504 int (*get_badpage_mca_addr)(struct amdgpu_device *adev, uint16_t index, uint64_t *mca_addr); 505 int (*set_timestamp)(struct amdgpu_device *adev, uint64_t timestamp); 506 int (*get_timestamp)(struct amdgpu_device *adev, 507 uint16_t index, uint64_t *timestamp); 508 int (*get_badpage_ipid)(struct amdgpu_device *adev, uint16_t index, uint64_t *ipid); 509 int (*erase_ras_table)(struct amdgpu_device *adev, uint32_t *result); 510 }; 511 512 enum ras_smu_feature_flags { 513 RAS_SMU_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), 514 }; 515 516 struct ras_smu_drv { 517 const struct ras_eeprom_smu_funcs *smu_eeprom_funcs; 518 void (*ras_smu_feature_flags)(struct amdgpu_device *adev, uint64_t *flags); 519 }; 520 521 struct amdgpu_ras { 522 void *ras_mgr; 523 /* ras infrastructure */ 524 /* for ras itself. */ 525 uint32_t features; 526 uint32_t schema; 527 struct list_head head; 528 /* sysfs */ 529 struct device_attribute features_attr; 530 struct device_attribute version_attr; 531 struct device_attribute schema_attr; 532 struct device_attribute event_state_attr; 533 struct bin_attribute badpages_attr; 534 struct dentry *de_ras_eeprom_table; 535 /* block array */ 536 struct ras_manager *objs; 537 538 /* gpu recovery */ 539 struct work_struct recovery_work; 540 atomic_t in_recovery; 541 struct amdgpu_device *adev; 542 /* error handler data */ 543 struct ras_err_handler_data *eh_data; 544 struct mutex recovery_lock; 545 546 uint32_t flags; 547 bool reboot; 548 struct amdgpu_ras_eeprom_control eeprom_control; 549 550 bool error_query_ready; 551 552 /* bad page count threshold */ 553 uint32_t bad_page_cnt_threshold; 554 555 /* disable ras error count harvest in recovery */ 556 bool disable_ras_err_cnt_harvest; 557 558 /* is poison mode supported */ 559 bool poison_supported; 560 561 /* RAS count errors delayed work */ 562 struct delayed_work ras_counte_delay_work; 563 atomic_t ras_ue_count; 564 atomic_t ras_ce_count; 565 566 /* record umc error info queried from smu */ 567 struct umc_ecc_info umc_ecc; 568 569 /* Indicates smu whether need update bad channel info */ 570 bool update_channel_flag; 571 /* Record status of smu mca debug mode */ 572 bool is_mca_debug_mode; 573 bool is_rma; 574 575 /* Record special requirements of gpu reset caller */ 576 uint32_t gpu_reset_flags; 577 578 struct mutex page_retirement_lock; 579 struct mutex page_rsv_lock; 580 struct ras_ecc_log_info umc_ecc_log; 581 582 /* ras errors detected */ 583 unsigned long ras_err_state; 584 585 /* RAS event manager */ 586 struct ras_event_manager __event_mgr; 587 struct ras_event_manager *event_mgr; 588 589 uint64_t reserved_pages_in_bytes; 590 591 pid_t init_task_pid; 592 char init_task_comm[TASK_COMM_LEN]; 593 594 int bad_page_num; 595 596 struct list_head critical_region_head; 597 struct mutex critical_region_lock; 598 599 /* Disable/Enable uniras switch */ 600 bool uniras_enabled; 601 const struct ras_smu_drv *ras_smu_drv; 602 }; 603 604 struct ras_fs_data { 605 char sysfs_name[48]; 606 char debugfs_name[32]; 607 }; 608 609 struct ras_err_info { 610 struct amdgpu_smuio_mcm_config_info mcm_info; 611 u64 ce_count; 612 u64 ue_count; 613 u64 de_count; 614 }; 615 616 struct ras_err_node { 617 struct list_head node; 618 struct ras_err_info err_info; 619 }; 620 621 struct ras_err_data { 622 unsigned long ue_count; 623 unsigned long ce_count; 624 unsigned long de_count; 625 unsigned long err_addr_cnt; 626 struct eeprom_table_record *err_addr; 627 unsigned long err_addr_len; 628 u32 err_list_count; 629 struct list_head err_node_list; 630 }; 631 632 #define for_each_ras_error(err_node, err_data) \ 633 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 634 635 struct ras_err_handler_data { 636 /* point to bad page records array */ 637 struct eeprom_table_record *bps; 638 /* the count of entries */ 639 int count; 640 int count_saved; 641 /* the space can place new entries */ 642 int space_left; 643 }; 644 645 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 646 void *err_data, 647 struct amdgpu_iv_entry *entry); 648 649 struct ras_ih_data { 650 /* interrupt bottom half */ 651 struct work_struct ih_work; 652 int inuse; 653 /* IP callback */ 654 ras_ih_cb cb; 655 /* full of entries */ 656 unsigned char *ring; 657 unsigned int ring_size; 658 unsigned int element_size; 659 unsigned int aligned_element_size; 660 unsigned int rptr; 661 unsigned int wptr; 662 }; 663 664 struct ras_manager { 665 struct ras_common_if head; 666 /* reference count */ 667 int use; 668 /* ras block link */ 669 struct list_head node; 670 /* the device */ 671 struct amdgpu_device *adev; 672 /* sysfs */ 673 struct device_attribute sysfs_attr; 674 int attr_inuse; 675 676 /* fs node name */ 677 struct ras_fs_data fs_data; 678 679 /* IH data */ 680 struct ras_ih_data ih_data; 681 682 struct ras_err_data err_data; 683 }; 684 685 struct ras_badpage { 686 unsigned int bp; 687 unsigned int size; 688 unsigned int flags; 689 }; 690 691 /* interfaces for IP */ 692 struct ras_fs_if { 693 struct ras_common_if head; 694 const char* sysfs_name; 695 char debugfs_name[32]; 696 }; 697 698 struct ras_query_if { 699 struct ras_common_if head; 700 unsigned long ue_count; 701 unsigned long ce_count; 702 unsigned long de_count; 703 }; 704 705 struct ras_inject_if { 706 struct ras_common_if head; 707 uint64_t address; 708 uint64_t value; 709 uint32_t instance_mask; 710 }; 711 712 struct ras_cure_if { 713 struct ras_common_if head; 714 uint64_t address; 715 }; 716 717 struct ras_ih_if { 718 struct ras_common_if head; 719 ras_ih_cb cb; 720 }; 721 722 struct ras_dispatch_if { 723 struct ras_common_if head; 724 struct amdgpu_iv_entry *entry; 725 }; 726 727 struct ras_debug_if { 728 union { 729 struct ras_common_if head; 730 struct ras_inject_if inject; 731 }; 732 int op; 733 }; 734 735 struct amdgpu_ras_block_object { 736 struct ras_common_if ras_comm; 737 738 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 739 enum amdgpu_ras_block block, uint32_t sub_block_index); 740 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 741 void (*ras_suspend)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 742 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 743 ras_ih_cb ras_cb; 744 const struct amdgpu_ras_block_hw_ops *hw_ops; 745 }; 746 747 struct amdgpu_ras_block_hw_ops { 748 int (*ras_error_inject)(struct amdgpu_device *adev, 749 void *inject_if, uint32_t instance_mask); 750 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 751 void (*query_ras_error_status)(struct amdgpu_device *adev); 752 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 753 void (*reset_ras_error_count)(struct amdgpu_device *adev); 754 void (*reset_ras_error_status)(struct amdgpu_device *adev); 755 bool (*query_poison_status)(struct amdgpu_device *adev); 756 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 757 }; 758 759 /* work flow 760 * vbios 761 * 1: ras feature enable (enabled by default) 762 * psp 763 * 2: ras framework init (in ip_init) 764 * IP 765 * 3: IH add 766 * 4: debugfs/sysfs create 767 * 5: query/inject 768 * 6: debugfs/sysfs remove 769 * 7: IH remove 770 * 8: feature disable 771 */ 772 773 int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev); 774 int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info); 775 776 void amdgpu_ras_resume(struct amdgpu_device *adev); 777 void amdgpu_ras_suspend(struct amdgpu_device *adev); 778 779 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 780 unsigned long *ce_count, 781 unsigned long *ue_count, 782 struct ras_query_if *query_info); 783 784 /* error handling functions */ 785 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 786 struct eeprom_table_record *bps, int pages, bool from_rom); 787 788 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 789 unsigned long *new_cnt); 790 791 static inline enum ta_ras_block 792 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 793 switch (block) { 794 case AMDGPU_RAS_BLOCK__UMC: 795 return TA_RAS_BLOCK__UMC; 796 case AMDGPU_RAS_BLOCK__SDMA: 797 return TA_RAS_BLOCK__SDMA; 798 case AMDGPU_RAS_BLOCK__GFX: 799 return TA_RAS_BLOCK__GFX; 800 case AMDGPU_RAS_BLOCK__MMHUB: 801 return TA_RAS_BLOCK__MMHUB; 802 case AMDGPU_RAS_BLOCK__ATHUB: 803 return TA_RAS_BLOCK__ATHUB; 804 case AMDGPU_RAS_BLOCK__PCIE_BIF: 805 return TA_RAS_BLOCK__PCIE_BIF; 806 case AMDGPU_RAS_BLOCK__HDP: 807 return TA_RAS_BLOCK__HDP; 808 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 809 return TA_RAS_BLOCK__XGMI_WAFL; 810 case AMDGPU_RAS_BLOCK__DF: 811 return TA_RAS_BLOCK__DF; 812 case AMDGPU_RAS_BLOCK__SMN: 813 return TA_RAS_BLOCK__SMN; 814 case AMDGPU_RAS_BLOCK__SEM: 815 return TA_RAS_BLOCK__SEM; 816 case AMDGPU_RAS_BLOCK__MP0: 817 return TA_RAS_BLOCK__MP0; 818 case AMDGPU_RAS_BLOCK__MP1: 819 return TA_RAS_BLOCK__MP1; 820 case AMDGPU_RAS_BLOCK__FUSE: 821 return TA_RAS_BLOCK__FUSE; 822 case AMDGPU_RAS_BLOCK__MCA: 823 return TA_RAS_BLOCK__MCA; 824 case AMDGPU_RAS_BLOCK__VCN: 825 return TA_RAS_BLOCK__VCN; 826 case AMDGPU_RAS_BLOCK__JPEG: 827 return TA_RAS_BLOCK__JPEG; 828 case AMDGPU_RAS_BLOCK__IH: 829 return TA_RAS_BLOCK__IH; 830 case AMDGPU_RAS_BLOCK__MPIO: 831 return TA_RAS_BLOCK__MPIO; 832 case AMDGPU_RAS_BLOCK__MMSCH: 833 return TA_RAS_BLOCK__MMSCH; 834 default: 835 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 836 return TA_RAS_BLOCK__UMC; 837 } 838 } 839 840 static inline enum ta_ras_error_type 841 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 842 switch (error) { 843 case AMDGPU_RAS_ERROR__NONE: 844 return TA_RAS_ERROR__NONE; 845 case AMDGPU_RAS_ERROR__PARITY: 846 return TA_RAS_ERROR__PARITY; 847 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 848 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 849 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 850 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 851 case AMDGPU_RAS_ERROR__POISON: 852 return TA_RAS_ERROR__POISON; 853 default: 854 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 855 return TA_RAS_ERROR__NONE; 856 } 857 } 858 859 /* called in ip_init and ip_fini */ 860 int amdgpu_ras_init(struct amdgpu_device *adev); 861 int amdgpu_ras_late_init(struct amdgpu_device *adev); 862 int amdgpu_ras_fini(struct amdgpu_device *adev); 863 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 864 865 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 866 struct ras_common_if *ras_block); 867 868 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 869 struct ras_common_if *ras_block); 870 871 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 872 struct ras_common_if *head, bool enable); 873 874 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 875 struct ras_common_if *head, bool enable); 876 877 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 878 struct ras_common_if *head); 879 880 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 881 struct ras_common_if *head); 882 883 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 884 885 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 886 struct ras_query_if *info); 887 888 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 889 enum amdgpu_ras_block block); 890 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 891 enum amdgpu_ras_block block); 892 893 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 894 struct ras_inject_if *info); 895 896 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 897 struct ras_common_if *head); 898 899 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 900 struct ras_common_if *head); 901 902 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 903 struct ras_dispatch_if *info); 904 905 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 906 struct ras_common_if *head); 907 908 extern atomic_t amdgpu_ras_in_intr; 909 910 static inline bool amdgpu_ras_intr_triggered(void) 911 { 912 return !!atomic_read(&amdgpu_ras_in_intr); 913 } 914 915 static inline void amdgpu_ras_intr_cleared(void) 916 { 917 atomic_set(&amdgpu_ras_in_intr, 0); 918 } 919 920 int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 921 922 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 923 924 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 925 926 void amdgpu_release_ras_context(struct amdgpu_device *adev); 927 928 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 929 930 const char *get_ras_block_str(struct ras_common_if *ras_block); 931 932 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 933 934 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 935 936 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 937 938 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 939 940 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 941 942 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 943 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev); 944 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 945 unsigned int *mode); 946 947 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 948 struct amdgpu_ras_block_object *ras_block_obj); 949 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 950 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 951 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 952 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 953 uint32_t instance, 954 uint32_t *memory_id); 955 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 956 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 957 uint32_t instance, 958 unsigned long *err_cnt); 959 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 960 const struct amdgpu_ras_err_status_reg_entry *reg_list, 961 uint32_t reg_list_size, 962 const struct amdgpu_ras_memory_id_entry *mem_list, 963 uint32_t mem_list_size, 964 uint32_t instance, 965 uint32_t err_type, 966 unsigned long *err_count); 967 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 968 const struct amdgpu_ras_err_status_reg_entry *reg_list, 969 uint32_t reg_list_size, 970 uint32_t instance); 971 972 int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 973 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 974 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 975 struct amdgpu_smuio_mcm_config_info *mcm_info, 976 u64 count); 977 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 978 struct amdgpu_smuio_mcm_config_info *mcm_info, 979 u64 count); 980 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 981 struct amdgpu_smuio_mcm_config_info *mcm_info, 982 u64 count); 983 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 984 985 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); 986 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); 987 void amdgpu_ras_set_err_poison(struct amdgpu_device *adev, 988 enum amdgpu_ras_block block); 989 void amdgpu_ras_clear_err_state(struct amdgpu_device *adev); 990 bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block); 991 992 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); 993 int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, 994 const void *caller); 995 996 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); 997 998 int amdgpu_ras_add_critical_region(struct amdgpu_device *adev, struct amdgpu_bo *bo); 999 bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr); 1000 1001 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev); 1002 1003 __printf(3, 4) 1004 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, 1005 const char *fmt, ...); 1006 1007 bool amdgpu_ras_is_rma(struct amdgpu_device *adev); 1008 1009 void amdgpu_ras_pre_reset(struct amdgpu_device *adev, 1010 struct list_head *device_list); 1011 void amdgpu_ras_post_reset(struct amdgpu_device *adev, 1012 struct list_head *device_list); 1013 void amdgpu_ras_resume_after_reset(struct amdgpu_device *adev); 1014 #endif 1015