1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include <linux/kfifo.h> 30 #include <linux/radix-tree.h> 31 #include "ta_ras_if.h" 32 #include "amdgpu_ras_eeprom.h" 33 #include "amdgpu_smuio.h" 34 #include "amdgpu_aca.h" 35 36 struct amdgpu_iv_entry; 37 38 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 39 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 40 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 41 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 42 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 43 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 44 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 45 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 46 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 47 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 48 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13) 49 #define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x) AMDGPU_GET_REG_FIELD(x, 29, 29) 50 #define AMDGPU_RAS_GPU_ERR_UNKNOWN(x) AMDGPU_GET_REG_FIELD(x, 30, 30) 51 52 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 100 53 #define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA 54 #define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF 55 56 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 57 /* position of instance value in sub_block_index of 58 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 59 */ 60 #define AMDGPU_RAS_INST_MASK 0xfffff000 61 #define AMDGPU_RAS_INST_SHIFT 0xc 62 63 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 64 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 65 66 /* Reserve 8 physical dram row for possible retirement. 67 * In worst cases, it will lose 8 * 2MB memory in vram domain */ 68 #define AMDGPU_RAS_RESERVED_VRAM_SIZE (16ULL << 20) 69 /* The high three bits indicates socketid */ 70 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 71 72 #define RAS_EVENT_INVALID_ID (BIT_ULL(63)) 73 #define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63))) 74 75 #define RAS_EVENT_LOG(adev, id, fmt, ...) \ 76 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__) 77 78 #define amdgpu_ras_mark_ras_event(adev, type) \ 79 (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0))) 80 81 enum amdgpu_ras_block { 82 AMDGPU_RAS_BLOCK__UMC = 0, 83 AMDGPU_RAS_BLOCK__SDMA, 84 AMDGPU_RAS_BLOCK__GFX, 85 AMDGPU_RAS_BLOCK__MMHUB, 86 AMDGPU_RAS_BLOCK__ATHUB, 87 AMDGPU_RAS_BLOCK__PCIE_BIF, 88 AMDGPU_RAS_BLOCK__HDP, 89 AMDGPU_RAS_BLOCK__XGMI_WAFL, 90 AMDGPU_RAS_BLOCK__DF, 91 AMDGPU_RAS_BLOCK__SMN, 92 AMDGPU_RAS_BLOCK__SEM, 93 AMDGPU_RAS_BLOCK__MP0, 94 AMDGPU_RAS_BLOCK__MP1, 95 AMDGPU_RAS_BLOCK__FUSE, 96 AMDGPU_RAS_BLOCK__MCA, 97 AMDGPU_RAS_BLOCK__VCN, 98 AMDGPU_RAS_BLOCK__JPEG, 99 AMDGPU_RAS_BLOCK__IH, 100 AMDGPU_RAS_BLOCK__MPIO, 101 102 AMDGPU_RAS_BLOCK__LAST 103 }; 104 105 enum amdgpu_ras_mca_block { 106 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 107 AMDGPU_RAS_MCA_BLOCK__MP1, 108 AMDGPU_RAS_MCA_BLOCK__MPIO, 109 AMDGPU_RAS_MCA_BLOCK__IOHC, 110 111 AMDGPU_RAS_MCA_BLOCK__LAST 112 }; 113 114 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 115 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 116 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 117 118 enum amdgpu_ras_gfx_subblock { 119 /* CPC */ 120 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 121 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 122 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 123 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 124 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 125 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 126 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 127 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 128 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 129 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 130 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 131 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 132 /* CPF */ 133 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 134 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 135 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 136 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 137 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 138 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 139 /* CPG */ 140 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 141 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 142 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 143 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 144 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 145 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 146 /* GDS */ 147 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 148 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 149 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 150 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 151 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 152 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 153 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 154 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 155 /* SPI */ 156 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 157 /* SQ */ 158 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 159 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 160 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 161 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 162 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 163 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 164 /* SQC (3 ranges) */ 165 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 166 /* SQC range 0 */ 167 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 168 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 169 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 170 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 171 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 172 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 174 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 175 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 176 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 177 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 178 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 179 /* SQC range 1 */ 180 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 181 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 182 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 183 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 184 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 185 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 186 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 187 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 188 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 189 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 190 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 191 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 192 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 193 /* SQC range 2 */ 194 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 195 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 196 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 197 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 198 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 199 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 200 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 201 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 202 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 203 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 204 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 205 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 206 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 207 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 208 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 209 /* TA */ 210 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 211 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 212 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 213 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 214 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 215 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 216 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 217 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 218 /* TCA */ 219 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 220 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 221 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 222 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 223 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 224 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 225 /* TCC (5 sub-ranges) */ 226 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 227 /* TCC range 0 */ 228 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 230 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 231 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 232 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 233 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 234 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 235 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 236 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 237 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 238 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 239 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 240 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 241 /* TCC range 1 */ 242 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 243 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 244 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 245 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 246 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 247 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 248 /* TCC range 2 */ 249 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 250 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 251 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 252 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 253 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 254 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 255 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 256 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 257 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 258 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 259 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 260 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 261 /* TCC range 3 */ 262 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 263 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 264 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 265 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 266 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 267 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 268 /* TCC range 4 */ 269 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 270 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 271 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 272 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 273 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 274 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 275 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 276 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 277 /* TCI */ 278 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 279 /* TCP */ 280 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 281 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 282 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 283 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 284 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 285 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 286 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 287 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 288 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 289 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 290 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 291 /* TD */ 292 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 293 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 294 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 295 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 296 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 297 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 298 /* EA (3 sub-ranges) */ 299 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 300 /* EA range 0 */ 301 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 302 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 303 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 304 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 305 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 306 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 307 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 308 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 309 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 310 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 311 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 312 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 313 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 314 /* EA range 1 */ 315 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 316 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 317 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 318 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 319 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 320 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 321 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 322 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 323 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 324 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 325 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 326 /* EA range 2 */ 327 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 328 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 329 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 330 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 331 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 332 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 333 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 334 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 335 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 336 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 337 /* UTC VM L2 bank */ 338 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 339 /* UTC VM walker */ 340 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 341 /* UTC ATC L2 2MB cache */ 342 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 343 /* UTC ATC L2 4KB cache */ 344 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 345 AMDGPU_RAS_BLOCK__GFX_MAX 346 }; 347 348 enum amdgpu_ras_error_type { 349 AMDGPU_RAS_ERROR__NONE = 0, 350 AMDGPU_RAS_ERROR__PARITY = 1, 351 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 352 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 353 AMDGPU_RAS_ERROR__POISON = 8, 354 }; 355 356 enum amdgpu_ras_ret { 357 AMDGPU_RAS_SUCCESS = 0, 358 AMDGPU_RAS_FAIL, 359 AMDGPU_RAS_UE, 360 AMDGPU_RAS_CE, 361 AMDGPU_RAS_PT, 362 }; 363 364 enum amdgpu_ras_error_query_mode { 365 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 366 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 367 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 368 AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY = 3, 369 }; 370 371 /* ras error status reisger fields */ 372 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 373 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 374 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 375 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 376 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 377 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 378 #define ERR_STATUS__ERR_CNT__SHIFT 0x17 379 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L 380 381 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 382 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 383 384 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 385 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 386 387 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 388 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 389 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 390 391 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 392 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 393 394 struct amdgpu_ras_err_status_reg_entry { 395 uint32_t hwip; 396 uint32_t ip_inst; 397 uint32_t seg_lo; 398 uint32_t reg_lo; 399 uint32_t seg_hi; 400 uint32_t reg_hi; 401 uint32_t reg_inst; 402 uint32_t flags; 403 const char *block_name; 404 }; 405 406 struct amdgpu_ras_memory_id_entry { 407 uint32_t memory_id; 408 const char *name; 409 }; 410 411 struct ras_common_if { 412 enum amdgpu_ras_block block; 413 enum amdgpu_ras_error_type type; 414 uint32_t sub_block_index; 415 char name[32]; 416 }; 417 418 #define MAX_UMC_CHANNEL_NUM 32 419 420 struct ecc_info_per_ch { 421 uint16_t ce_count_lo_chip; 422 uint16_t ce_count_hi_chip; 423 uint64_t mca_umc_status; 424 uint64_t mca_umc_addr; 425 uint64_t mca_ceumc_addr; 426 }; 427 428 struct umc_ecc_info { 429 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 430 431 /* Determine smu ecctable whether support 432 * record correctable error address 433 */ 434 int record_ce_addr_supported; 435 }; 436 437 enum ras_event_type { 438 RAS_EVENT_TYPE_INVALID = 0, 439 RAS_EVENT_TYPE_FATAL, 440 RAS_EVENT_TYPE_POISON_CREATION, 441 RAS_EVENT_TYPE_POISON_CONSUMPTION, 442 RAS_EVENT_TYPE_COUNT, 443 }; 444 445 struct ras_event_state { 446 u64 last_seqno; 447 atomic64_t count; 448 }; 449 450 struct ras_event_manager { 451 atomic64_t seqno; 452 struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT]; 453 }; 454 455 struct ras_event_id { 456 enum ras_event_type type; 457 u64 event_id; 458 }; 459 460 struct ras_query_context { 461 struct ras_event_id evid; 462 }; 463 464 typedef int (*pasid_notify)(struct amdgpu_device *adev, 465 uint16_t pasid, void *data); 466 467 struct ras_poison_msg { 468 enum amdgpu_ras_block block; 469 uint16_t pasid; 470 uint32_t reset; 471 pasid_notify pasid_fn; 472 void *data; 473 }; 474 475 struct ras_err_pages { 476 uint32_t count; 477 uint64_t *pfn; 478 }; 479 480 struct ras_ecc_err { 481 uint64_t status; 482 uint64_t ipid; 483 uint64_t addr; 484 uint64_t pa_pfn; 485 struct ras_err_pages err_pages; 486 }; 487 488 struct ras_ecc_log_info { 489 struct mutex lock; 490 struct radix_tree_root de_page_tree; 491 uint64_t de_queried_count; 492 uint64_t prev_de_queried_count; 493 }; 494 495 struct amdgpu_ras { 496 /* ras infrastructure */ 497 /* for ras itself. */ 498 uint32_t features; 499 uint32_t schema; 500 struct list_head head; 501 /* sysfs */ 502 struct device_attribute features_attr; 503 struct device_attribute version_attr; 504 struct device_attribute schema_attr; 505 struct device_attribute event_state_attr; 506 struct bin_attribute badpages_attr; 507 struct dentry *de_ras_eeprom_table; 508 /* block array */ 509 struct ras_manager *objs; 510 511 /* gpu recovery */ 512 struct work_struct recovery_work; 513 atomic_t in_recovery; 514 struct amdgpu_device *adev; 515 /* error handler data */ 516 struct ras_err_handler_data *eh_data; 517 struct mutex recovery_lock; 518 519 uint32_t flags; 520 bool reboot; 521 struct amdgpu_ras_eeprom_control eeprom_control; 522 523 bool error_query_ready; 524 525 /* bad page count threshold */ 526 uint32_t bad_page_cnt_threshold; 527 528 /* disable ras error count harvest in recovery */ 529 bool disable_ras_err_cnt_harvest; 530 531 /* is poison mode supported */ 532 bool poison_supported; 533 534 /* RAS count errors delayed work */ 535 struct delayed_work ras_counte_delay_work; 536 atomic_t ras_ue_count; 537 atomic_t ras_ce_count; 538 539 /* record umc error info queried from smu */ 540 struct umc_ecc_info umc_ecc; 541 542 /* Indicates smu whether need update bad channel info */ 543 bool update_channel_flag; 544 /* Record status of smu mca debug mode */ 545 bool is_aca_debug_mode; 546 bool is_rma; 547 548 /* Record special requirements of gpu reset caller */ 549 uint32_t gpu_reset_flags; 550 551 struct task_struct *page_retirement_thread; 552 wait_queue_head_t page_retirement_wq; 553 struct mutex page_retirement_lock; 554 atomic_t page_retirement_req_cnt; 555 atomic_t poison_creation_count; 556 struct mutex page_rsv_lock; 557 DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128); 558 struct ras_ecc_log_info umc_ecc_log; 559 struct delayed_work page_retirement_dwork; 560 561 /* Fatal error detected flag */ 562 atomic_t fed; 563 564 /* RAS event manager */ 565 struct ras_event_manager __event_mgr; 566 struct ras_event_manager *event_mgr; 567 568 uint64_t reserved_pages_in_bytes; 569 }; 570 571 struct ras_fs_data { 572 char sysfs_name[48]; 573 char debugfs_name[32]; 574 }; 575 576 struct ras_err_info { 577 struct amdgpu_smuio_mcm_config_info mcm_info; 578 u64 ce_count; 579 u64 ue_count; 580 u64 de_count; 581 }; 582 583 struct ras_err_node { 584 struct list_head node; 585 struct ras_err_info err_info; 586 }; 587 588 struct ras_err_data { 589 unsigned long ue_count; 590 unsigned long ce_count; 591 unsigned long de_count; 592 unsigned long err_addr_cnt; 593 struct eeprom_table_record *err_addr; 594 unsigned long err_addr_len; 595 u32 err_list_count; 596 struct list_head err_node_list; 597 }; 598 599 #define for_each_ras_error(err_node, err_data) \ 600 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 601 602 struct ras_err_handler_data { 603 /* point to bad page records array */ 604 struct eeprom_table_record *bps; 605 /* the count of entries */ 606 int count; 607 /* the space can place new entries */ 608 int space_left; 609 }; 610 611 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 612 void *err_data, 613 struct amdgpu_iv_entry *entry); 614 615 struct ras_ih_data { 616 /* interrupt bottom half */ 617 struct work_struct ih_work; 618 int inuse; 619 /* IP callback */ 620 ras_ih_cb cb; 621 /* full of entries */ 622 unsigned char *ring; 623 unsigned int ring_size; 624 unsigned int element_size; 625 unsigned int aligned_element_size; 626 unsigned int rptr; 627 unsigned int wptr; 628 }; 629 630 struct ras_manager { 631 struct ras_common_if head; 632 /* reference count */ 633 int use; 634 /* ras block link */ 635 struct list_head node; 636 /* the device */ 637 struct amdgpu_device *adev; 638 /* sysfs */ 639 struct device_attribute sysfs_attr; 640 int attr_inuse; 641 642 /* fs node name */ 643 struct ras_fs_data fs_data; 644 645 /* IH data */ 646 struct ras_ih_data ih_data; 647 648 struct ras_err_data err_data; 649 650 struct aca_handle aca_handle; 651 }; 652 653 struct ras_badpage { 654 unsigned int bp; 655 unsigned int size; 656 unsigned int flags; 657 }; 658 659 /* interfaces for IP */ 660 struct ras_fs_if { 661 struct ras_common_if head; 662 const char* sysfs_name; 663 char debugfs_name[32]; 664 }; 665 666 struct ras_query_if { 667 struct ras_common_if head; 668 unsigned long ue_count; 669 unsigned long ce_count; 670 unsigned long de_count; 671 }; 672 673 struct ras_inject_if { 674 struct ras_common_if head; 675 uint64_t address; 676 uint64_t value; 677 uint32_t instance_mask; 678 }; 679 680 struct ras_cure_if { 681 struct ras_common_if head; 682 uint64_t address; 683 }; 684 685 struct ras_ih_if { 686 struct ras_common_if head; 687 ras_ih_cb cb; 688 }; 689 690 struct ras_dispatch_if { 691 struct ras_common_if head; 692 struct amdgpu_iv_entry *entry; 693 }; 694 695 struct ras_debug_if { 696 union { 697 struct ras_common_if head; 698 struct ras_inject_if inject; 699 }; 700 int op; 701 }; 702 703 struct amdgpu_ras_block_object { 704 struct ras_common_if ras_comm; 705 706 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 707 enum amdgpu_ras_block block, uint32_t sub_block_index); 708 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 709 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 710 ras_ih_cb ras_cb; 711 const struct amdgpu_ras_block_hw_ops *hw_ops; 712 }; 713 714 struct amdgpu_ras_block_hw_ops { 715 int (*ras_error_inject)(struct amdgpu_device *adev, 716 void *inject_if, uint32_t instance_mask); 717 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 718 void (*query_ras_error_status)(struct amdgpu_device *adev); 719 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 720 void (*reset_ras_error_count)(struct amdgpu_device *adev); 721 void (*reset_ras_error_status)(struct amdgpu_device *adev); 722 bool (*query_poison_status)(struct amdgpu_device *adev); 723 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 724 }; 725 726 /* work flow 727 * vbios 728 * 1: ras feature enable (enabled by default) 729 * psp 730 * 2: ras framework init (in ip_init) 731 * IP 732 * 3: IH add 733 * 4: debugfs/sysfs create 734 * 5: query/inject 735 * 6: debugfs/sysfs remove 736 * 7: IH remove 737 * 8: feature disable 738 */ 739 740 int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev); 741 int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info); 742 743 void amdgpu_ras_resume(struct amdgpu_device *adev); 744 void amdgpu_ras_suspend(struct amdgpu_device *adev); 745 746 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 747 unsigned long *ce_count, 748 unsigned long *ue_count, 749 struct ras_query_if *query_info); 750 751 /* error handling functions */ 752 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 753 struct eeprom_table_record *bps, int pages); 754 755 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 756 unsigned long *new_cnt); 757 758 static inline enum ta_ras_block 759 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 760 switch (block) { 761 case AMDGPU_RAS_BLOCK__UMC: 762 return TA_RAS_BLOCK__UMC; 763 case AMDGPU_RAS_BLOCK__SDMA: 764 return TA_RAS_BLOCK__SDMA; 765 case AMDGPU_RAS_BLOCK__GFX: 766 return TA_RAS_BLOCK__GFX; 767 case AMDGPU_RAS_BLOCK__MMHUB: 768 return TA_RAS_BLOCK__MMHUB; 769 case AMDGPU_RAS_BLOCK__ATHUB: 770 return TA_RAS_BLOCK__ATHUB; 771 case AMDGPU_RAS_BLOCK__PCIE_BIF: 772 return TA_RAS_BLOCK__PCIE_BIF; 773 case AMDGPU_RAS_BLOCK__HDP: 774 return TA_RAS_BLOCK__HDP; 775 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 776 return TA_RAS_BLOCK__XGMI_WAFL; 777 case AMDGPU_RAS_BLOCK__DF: 778 return TA_RAS_BLOCK__DF; 779 case AMDGPU_RAS_BLOCK__SMN: 780 return TA_RAS_BLOCK__SMN; 781 case AMDGPU_RAS_BLOCK__SEM: 782 return TA_RAS_BLOCK__SEM; 783 case AMDGPU_RAS_BLOCK__MP0: 784 return TA_RAS_BLOCK__MP0; 785 case AMDGPU_RAS_BLOCK__MP1: 786 return TA_RAS_BLOCK__MP1; 787 case AMDGPU_RAS_BLOCK__FUSE: 788 return TA_RAS_BLOCK__FUSE; 789 case AMDGPU_RAS_BLOCK__MCA: 790 return TA_RAS_BLOCK__MCA; 791 case AMDGPU_RAS_BLOCK__VCN: 792 return TA_RAS_BLOCK__VCN; 793 case AMDGPU_RAS_BLOCK__JPEG: 794 return TA_RAS_BLOCK__JPEG; 795 default: 796 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 797 return TA_RAS_BLOCK__UMC; 798 } 799 } 800 801 static inline enum ta_ras_error_type 802 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 803 switch (error) { 804 case AMDGPU_RAS_ERROR__NONE: 805 return TA_RAS_ERROR__NONE; 806 case AMDGPU_RAS_ERROR__PARITY: 807 return TA_RAS_ERROR__PARITY; 808 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 809 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 810 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 811 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 812 case AMDGPU_RAS_ERROR__POISON: 813 return TA_RAS_ERROR__POISON; 814 default: 815 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 816 return TA_RAS_ERROR__NONE; 817 } 818 } 819 820 /* called in ip_init and ip_fini */ 821 int amdgpu_ras_init(struct amdgpu_device *adev); 822 int amdgpu_ras_late_init(struct amdgpu_device *adev); 823 int amdgpu_ras_fini(struct amdgpu_device *adev); 824 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 825 826 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 827 struct ras_common_if *ras_block); 828 829 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 830 struct ras_common_if *ras_block); 831 832 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 833 struct ras_common_if *head, bool enable); 834 835 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 836 struct ras_common_if *head, bool enable); 837 838 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 839 struct ras_common_if *head); 840 841 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 842 struct ras_common_if *head); 843 844 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 845 846 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 847 struct ras_query_if *info); 848 849 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 850 enum amdgpu_ras_block block); 851 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 852 enum amdgpu_ras_block block); 853 854 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 855 struct ras_inject_if *info); 856 857 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 858 struct ras_common_if *head); 859 860 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 861 struct ras_common_if *head); 862 863 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 864 struct ras_dispatch_if *info); 865 866 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 867 struct ras_common_if *head); 868 869 extern atomic_t amdgpu_ras_in_intr; 870 871 static inline bool amdgpu_ras_intr_triggered(void) 872 { 873 return !!atomic_read(&amdgpu_ras_in_intr); 874 } 875 876 static inline void amdgpu_ras_intr_cleared(void) 877 { 878 atomic_set(&amdgpu_ras_in_intr, 0); 879 } 880 881 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 882 883 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 884 885 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 886 887 void amdgpu_release_ras_context(struct amdgpu_device *adev); 888 889 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 890 891 const char *get_ras_block_str(struct ras_common_if *ras_block); 892 893 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 894 895 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 896 897 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 898 899 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 900 901 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 902 903 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 904 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); 905 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); 906 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 907 unsigned int *mode); 908 909 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 910 struct amdgpu_ras_block_object *ras_block_obj); 911 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 912 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 913 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 914 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 915 uint32_t instance, 916 uint32_t *memory_id); 917 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 918 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 919 uint32_t instance, 920 unsigned long *err_cnt); 921 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 922 const struct amdgpu_ras_err_status_reg_entry *reg_list, 923 uint32_t reg_list_size, 924 const struct amdgpu_ras_memory_id_entry *mem_list, 925 uint32_t mem_list_size, 926 uint32_t instance, 927 uint32_t err_type, 928 unsigned long *err_count); 929 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 930 const struct amdgpu_ras_err_status_reg_entry *reg_list, 931 uint32_t reg_list_size, 932 uint32_t instance); 933 934 int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 935 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 936 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 937 struct amdgpu_smuio_mcm_config_info *mcm_info, 938 u64 count); 939 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 940 struct amdgpu_smuio_mcm_config_info *mcm_info, 941 u64 count); 942 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 943 struct amdgpu_smuio_mcm_config_info *mcm_info, 944 u64 count); 945 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 946 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 947 const struct aca_info *aca_info, void *data); 948 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); 949 950 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 951 struct aca_handle *handle, char *buf, void *data); 952 953 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); 954 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); 955 956 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); 957 int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, 958 const void *caller); 959 960 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); 961 962 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, 963 enum amdgpu_ras_block block, uint16_t pasid, 964 pasid_notify pasid_fn, void *data, uint32_t reset); 965 966 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev); 967 968 __printf(3, 4) 969 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, 970 const char *fmt, ...); 971 972 bool amdgpu_ras_is_rma(struct amdgpu_device *adev); 973 #endif 974