1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "ta_ras_if.h" 30 #include "amdgpu_ras_eeprom.h" 31 #include "amdgpu_smuio.h" 32 #include "amdgpu_aca.h" 33 34 struct amdgpu_iv_entry; 35 36 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 37 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 38 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 39 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 40 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 41 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 42 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 43 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 44 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 45 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 46 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 13, 13) 47 #define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x) AMDGPU_GET_REG_FIELD(x, 31, 31) 48 49 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 1000 50 #define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA 51 #define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF 52 #define AMDGPU_RAS_BOOT_SUCEESS 0x80000000 53 54 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 55 /* position of instance value in sub_block_index of 56 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 57 */ 58 #define AMDGPU_RAS_INST_MASK 0xfffff000 59 #define AMDGPU_RAS_INST_SHIFT 0xc 60 61 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 62 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 63 64 /* The high three bits indicates socketid */ 65 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 66 67 #define RAS_EVENT_LOG(_adev, _id, _fmt, ...) \ 68 do { \ 69 if (amdgpu_ras_event_id_is_valid((_adev), (_id))) \ 70 dev_info((_adev)->dev, "{%llu}" _fmt, (_id), ##__VA_ARGS__); \ 71 else \ 72 dev_info((_adev)->dev, _fmt, ##__VA_ARGS__); \ 73 } while (0) 74 75 enum amdgpu_ras_block { 76 AMDGPU_RAS_BLOCK__UMC = 0, 77 AMDGPU_RAS_BLOCK__SDMA, 78 AMDGPU_RAS_BLOCK__GFX, 79 AMDGPU_RAS_BLOCK__MMHUB, 80 AMDGPU_RAS_BLOCK__ATHUB, 81 AMDGPU_RAS_BLOCK__PCIE_BIF, 82 AMDGPU_RAS_BLOCK__HDP, 83 AMDGPU_RAS_BLOCK__XGMI_WAFL, 84 AMDGPU_RAS_BLOCK__DF, 85 AMDGPU_RAS_BLOCK__SMN, 86 AMDGPU_RAS_BLOCK__SEM, 87 AMDGPU_RAS_BLOCK__MP0, 88 AMDGPU_RAS_BLOCK__MP1, 89 AMDGPU_RAS_BLOCK__FUSE, 90 AMDGPU_RAS_BLOCK__MCA, 91 AMDGPU_RAS_BLOCK__VCN, 92 AMDGPU_RAS_BLOCK__JPEG, 93 AMDGPU_RAS_BLOCK__IH, 94 AMDGPU_RAS_BLOCK__MPIO, 95 96 AMDGPU_RAS_BLOCK__LAST 97 }; 98 99 enum amdgpu_ras_mca_block { 100 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 101 AMDGPU_RAS_MCA_BLOCK__MP1, 102 AMDGPU_RAS_MCA_BLOCK__MPIO, 103 AMDGPU_RAS_MCA_BLOCK__IOHC, 104 105 AMDGPU_RAS_MCA_BLOCK__LAST 106 }; 107 108 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 109 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 110 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 111 112 enum amdgpu_ras_gfx_subblock { 113 /* CPC */ 114 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 115 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 116 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 117 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 118 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 119 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 120 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 121 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 122 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 123 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 124 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 125 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 126 /* CPF */ 127 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 128 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 129 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 130 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 131 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 132 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 133 /* CPG */ 134 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 135 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 136 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 137 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 138 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 139 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 140 /* GDS */ 141 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 142 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 143 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 144 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 145 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 146 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 147 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 148 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 149 /* SPI */ 150 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 151 /* SQ */ 152 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 153 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 154 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 155 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 156 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 157 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 158 /* SQC (3 ranges) */ 159 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 160 /* SQC range 0 */ 161 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 162 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 163 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 164 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 165 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 166 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 167 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 168 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 169 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 170 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 171 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 172 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 173 /* SQC range 1 */ 174 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 175 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 176 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 177 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 178 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 179 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 180 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 181 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 182 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 183 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 184 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 185 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 186 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 187 /* SQC range 2 */ 188 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 189 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 190 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 191 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 192 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 193 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 194 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 195 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 196 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 197 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 198 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 199 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 200 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 201 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 202 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 203 /* TA */ 204 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 205 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 206 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 207 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 208 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 209 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 210 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 211 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 212 /* TCA */ 213 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 214 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 215 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 216 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 217 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 218 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 219 /* TCC (5 sub-ranges) */ 220 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 221 /* TCC range 0 */ 222 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 223 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 224 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 225 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 226 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 227 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 228 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 229 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 230 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 231 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 232 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 233 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 234 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 235 /* TCC range 1 */ 236 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 237 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 238 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 239 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 240 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 241 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 242 /* TCC range 2 */ 243 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 244 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 245 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 246 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 247 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 248 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 249 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 250 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 251 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 252 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 253 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 254 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 255 /* TCC range 3 */ 256 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 257 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 258 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 259 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 260 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 261 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 262 /* TCC range 4 */ 263 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 264 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 265 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 266 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 267 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 268 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 269 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 270 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 271 /* TCI */ 272 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 273 /* TCP */ 274 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 275 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 276 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 277 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 278 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 279 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 280 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 281 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 282 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 283 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 284 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 285 /* TD */ 286 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 287 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 288 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 289 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 290 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 291 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 292 /* EA (3 sub-ranges) */ 293 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 294 /* EA range 0 */ 295 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 296 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 297 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 298 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 299 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 300 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 301 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 302 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 303 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 304 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 305 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 306 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 307 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 308 /* EA range 1 */ 309 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 310 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 311 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 312 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 313 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 314 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 315 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 316 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 317 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 318 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 319 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 320 /* EA range 2 */ 321 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 322 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 323 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 324 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 325 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 326 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 327 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 328 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 329 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 330 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 331 /* UTC VM L2 bank */ 332 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 333 /* UTC VM walker */ 334 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 335 /* UTC ATC L2 2MB cache */ 336 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 337 /* UTC ATC L2 4KB cache */ 338 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 339 AMDGPU_RAS_BLOCK__GFX_MAX 340 }; 341 342 enum amdgpu_ras_error_type { 343 AMDGPU_RAS_ERROR__NONE = 0, 344 AMDGPU_RAS_ERROR__PARITY = 1, 345 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 346 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 347 AMDGPU_RAS_ERROR__POISON = 8, 348 }; 349 350 enum amdgpu_ras_ret { 351 AMDGPU_RAS_SUCCESS = 0, 352 AMDGPU_RAS_FAIL, 353 AMDGPU_RAS_UE, 354 AMDGPU_RAS_CE, 355 AMDGPU_RAS_PT, 356 }; 357 358 enum amdgpu_ras_error_query_mode { 359 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 360 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 361 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 362 }; 363 364 /* ras error status reisger fields */ 365 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 366 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 367 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 368 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 369 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 370 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 371 #define ERR_STATUS__ERR_CNT__SHIFT 0x17 372 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L 373 374 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 375 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 376 377 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 378 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 379 380 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 381 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 382 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 383 384 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 385 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 386 387 struct amdgpu_ras_err_status_reg_entry { 388 uint32_t hwip; 389 uint32_t ip_inst; 390 uint32_t seg_lo; 391 uint32_t reg_lo; 392 uint32_t seg_hi; 393 uint32_t reg_hi; 394 uint32_t reg_inst; 395 uint32_t flags; 396 const char *block_name; 397 }; 398 399 struct amdgpu_ras_memory_id_entry { 400 uint32_t memory_id; 401 const char *name; 402 }; 403 404 struct ras_common_if { 405 enum amdgpu_ras_block block; 406 enum amdgpu_ras_error_type type; 407 uint32_t sub_block_index; 408 char name[32]; 409 }; 410 411 #define MAX_UMC_CHANNEL_NUM 32 412 413 struct ecc_info_per_ch { 414 uint16_t ce_count_lo_chip; 415 uint16_t ce_count_hi_chip; 416 uint64_t mca_umc_status; 417 uint64_t mca_umc_addr; 418 uint64_t mca_ceumc_addr; 419 }; 420 421 struct umc_ecc_info { 422 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 423 424 /* Determine smu ecctable whether support 425 * record correctable error address 426 */ 427 int record_ce_addr_supported; 428 }; 429 430 enum ras_event_type { 431 RAS_EVENT_TYPE_INVALID = -1, 432 RAS_EVENT_TYPE_ISR = 0, 433 RAS_EVENT_TYPE_COUNT, 434 }; 435 436 struct ras_event_manager { 437 atomic64_t seqnos[RAS_EVENT_TYPE_COUNT]; 438 }; 439 440 struct ras_query_context { 441 enum ras_event_type type; 442 u64 event_id; 443 }; 444 445 struct amdgpu_ras { 446 /* ras infrastructure */ 447 /* for ras itself. */ 448 uint32_t features; 449 uint32_t schema; 450 struct list_head head; 451 /* sysfs */ 452 struct device_attribute features_attr; 453 struct device_attribute version_attr; 454 struct device_attribute schema_attr; 455 struct bin_attribute badpages_attr; 456 struct dentry *de_ras_eeprom_table; 457 /* block array */ 458 struct ras_manager *objs; 459 460 /* gpu recovery */ 461 struct work_struct recovery_work; 462 atomic_t in_recovery; 463 struct amdgpu_device *adev; 464 /* error handler data */ 465 struct ras_err_handler_data *eh_data; 466 struct mutex recovery_lock; 467 468 uint32_t flags; 469 bool reboot; 470 struct amdgpu_ras_eeprom_control eeprom_control; 471 472 bool error_query_ready; 473 474 /* bad page count threshold */ 475 uint32_t bad_page_cnt_threshold; 476 477 /* disable ras error count harvest in recovery */ 478 bool disable_ras_err_cnt_harvest; 479 480 /* is poison mode supported */ 481 bool poison_supported; 482 483 /* RAS count errors delayed work */ 484 struct delayed_work ras_counte_delay_work; 485 atomic_t ras_ue_count; 486 atomic_t ras_ce_count; 487 488 /* record umc error info queried from smu */ 489 struct umc_ecc_info umc_ecc; 490 491 /* Indicates smu whether need update bad channel info */ 492 bool update_channel_flag; 493 /* Record status of smu mca debug mode */ 494 bool is_aca_debug_mode; 495 496 /* Record special requirements of gpu reset caller */ 497 uint32_t gpu_reset_flags; 498 499 struct task_struct *page_retirement_thread; 500 wait_queue_head_t page_retirement_wq; 501 struct mutex page_retirement_lock; 502 atomic_t page_retirement_req_cnt; 503 /* Fatal error detected flag */ 504 atomic_t fed; 505 506 /* RAS event manager */ 507 struct ras_event_manager __event_mgr; 508 struct ras_event_manager *event_mgr; 509 510 }; 511 512 struct ras_fs_data { 513 char sysfs_name[48]; 514 char debugfs_name[32]; 515 }; 516 517 struct ras_err_addr { 518 struct list_head node; 519 uint64_t err_status; 520 uint64_t err_ipid; 521 uint64_t err_addr; 522 }; 523 524 struct ras_err_info { 525 struct amdgpu_smuio_mcm_config_info mcm_info; 526 u64 ce_count; 527 u64 ue_count; 528 u64 de_count; 529 struct list_head err_addr_list; 530 }; 531 532 struct ras_err_node { 533 struct list_head node; 534 struct ras_err_info err_info; 535 }; 536 537 struct ras_err_data { 538 unsigned long ue_count; 539 unsigned long ce_count; 540 unsigned long de_count; 541 unsigned long err_addr_cnt; 542 struct eeprom_table_record *err_addr; 543 u32 err_list_count; 544 struct list_head err_node_list; 545 }; 546 547 #define for_each_ras_error(err_node, err_data) \ 548 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 549 550 struct ras_err_handler_data { 551 /* point to bad page records array */ 552 struct eeprom_table_record *bps; 553 /* the count of entries */ 554 int count; 555 /* the space can place new entries */ 556 int space_left; 557 }; 558 559 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 560 void *err_data, 561 struct amdgpu_iv_entry *entry); 562 563 struct ras_ih_data { 564 /* interrupt bottom half */ 565 struct work_struct ih_work; 566 int inuse; 567 /* IP callback */ 568 ras_ih_cb cb; 569 /* full of entries */ 570 unsigned char *ring; 571 unsigned int ring_size; 572 unsigned int element_size; 573 unsigned int aligned_element_size; 574 unsigned int rptr; 575 unsigned int wptr; 576 }; 577 578 struct ras_manager { 579 struct ras_common_if head; 580 /* reference count */ 581 int use; 582 /* ras block link */ 583 struct list_head node; 584 /* the device */ 585 struct amdgpu_device *adev; 586 /* sysfs */ 587 struct device_attribute sysfs_attr; 588 int attr_inuse; 589 590 /* fs node name */ 591 struct ras_fs_data fs_data; 592 593 /* IH data */ 594 struct ras_ih_data ih_data; 595 596 struct ras_err_data err_data; 597 598 struct aca_handle aca_handle; 599 }; 600 601 struct ras_badpage { 602 unsigned int bp; 603 unsigned int size; 604 unsigned int flags; 605 }; 606 607 /* interfaces for IP */ 608 struct ras_fs_if { 609 struct ras_common_if head; 610 const char* sysfs_name; 611 char debugfs_name[32]; 612 }; 613 614 struct ras_query_if { 615 struct ras_common_if head; 616 unsigned long ue_count; 617 unsigned long ce_count; 618 unsigned long de_count; 619 }; 620 621 struct ras_inject_if { 622 struct ras_common_if head; 623 uint64_t address; 624 uint64_t value; 625 uint32_t instance_mask; 626 }; 627 628 struct ras_cure_if { 629 struct ras_common_if head; 630 uint64_t address; 631 }; 632 633 struct ras_ih_if { 634 struct ras_common_if head; 635 ras_ih_cb cb; 636 }; 637 638 struct ras_dispatch_if { 639 struct ras_common_if head; 640 struct amdgpu_iv_entry *entry; 641 }; 642 643 struct ras_debug_if { 644 union { 645 struct ras_common_if head; 646 struct ras_inject_if inject; 647 }; 648 int op; 649 }; 650 651 struct amdgpu_ras_block_object { 652 struct ras_common_if ras_comm; 653 654 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 655 enum amdgpu_ras_block block, uint32_t sub_block_index); 656 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 657 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 658 ras_ih_cb ras_cb; 659 const struct amdgpu_ras_block_hw_ops *hw_ops; 660 }; 661 662 struct amdgpu_ras_block_hw_ops { 663 int (*ras_error_inject)(struct amdgpu_device *adev, 664 void *inject_if, uint32_t instance_mask); 665 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 666 void (*query_ras_error_status)(struct amdgpu_device *adev); 667 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 668 void (*reset_ras_error_count)(struct amdgpu_device *adev); 669 void (*reset_ras_error_status)(struct amdgpu_device *adev); 670 bool (*query_poison_status)(struct amdgpu_device *adev); 671 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 672 }; 673 674 /* work flow 675 * vbios 676 * 1: ras feature enable (enabled by default) 677 * psp 678 * 2: ras framework init (in ip_init) 679 * IP 680 * 3: IH add 681 * 4: debugfs/sysfs create 682 * 5: query/inject 683 * 6: debugfs/sysfs remove 684 * 7: IH remove 685 * 8: feature disable 686 */ 687 688 689 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 690 691 void amdgpu_ras_resume(struct amdgpu_device *adev); 692 void amdgpu_ras_suspend(struct amdgpu_device *adev); 693 694 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 695 unsigned long *ce_count, 696 unsigned long *ue_count, 697 struct ras_query_if *query_info); 698 699 /* error handling functions */ 700 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 701 struct eeprom_table_record *bps, int pages); 702 703 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 704 unsigned long *new_cnt); 705 706 static inline enum ta_ras_block 707 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 708 switch (block) { 709 case AMDGPU_RAS_BLOCK__UMC: 710 return TA_RAS_BLOCK__UMC; 711 case AMDGPU_RAS_BLOCK__SDMA: 712 return TA_RAS_BLOCK__SDMA; 713 case AMDGPU_RAS_BLOCK__GFX: 714 return TA_RAS_BLOCK__GFX; 715 case AMDGPU_RAS_BLOCK__MMHUB: 716 return TA_RAS_BLOCK__MMHUB; 717 case AMDGPU_RAS_BLOCK__ATHUB: 718 return TA_RAS_BLOCK__ATHUB; 719 case AMDGPU_RAS_BLOCK__PCIE_BIF: 720 return TA_RAS_BLOCK__PCIE_BIF; 721 case AMDGPU_RAS_BLOCK__HDP: 722 return TA_RAS_BLOCK__HDP; 723 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 724 return TA_RAS_BLOCK__XGMI_WAFL; 725 case AMDGPU_RAS_BLOCK__DF: 726 return TA_RAS_BLOCK__DF; 727 case AMDGPU_RAS_BLOCK__SMN: 728 return TA_RAS_BLOCK__SMN; 729 case AMDGPU_RAS_BLOCK__SEM: 730 return TA_RAS_BLOCK__SEM; 731 case AMDGPU_RAS_BLOCK__MP0: 732 return TA_RAS_BLOCK__MP0; 733 case AMDGPU_RAS_BLOCK__MP1: 734 return TA_RAS_BLOCK__MP1; 735 case AMDGPU_RAS_BLOCK__FUSE: 736 return TA_RAS_BLOCK__FUSE; 737 case AMDGPU_RAS_BLOCK__MCA: 738 return TA_RAS_BLOCK__MCA; 739 case AMDGPU_RAS_BLOCK__VCN: 740 return TA_RAS_BLOCK__VCN; 741 case AMDGPU_RAS_BLOCK__JPEG: 742 return TA_RAS_BLOCK__JPEG; 743 default: 744 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 745 return TA_RAS_BLOCK__UMC; 746 } 747 } 748 749 static inline enum ta_ras_error_type 750 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 751 switch (error) { 752 case AMDGPU_RAS_ERROR__NONE: 753 return TA_RAS_ERROR__NONE; 754 case AMDGPU_RAS_ERROR__PARITY: 755 return TA_RAS_ERROR__PARITY; 756 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 757 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 758 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 759 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 760 case AMDGPU_RAS_ERROR__POISON: 761 return TA_RAS_ERROR__POISON; 762 default: 763 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 764 return TA_RAS_ERROR__NONE; 765 } 766 } 767 768 /* called in ip_init and ip_fini */ 769 int amdgpu_ras_init(struct amdgpu_device *adev); 770 int amdgpu_ras_late_init(struct amdgpu_device *adev); 771 int amdgpu_ras_fini(struct amdgpu_device *adev); 772 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 773 774 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 775 struct ras_common_if *ras_block); 776 777 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 778 struct ras_common_if *ras_block); 779 780 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 781 struct ras_common_if *head, bool enable); 782 783 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 784 struct ras_common_if *head, bool enable); 785 786 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 787 struct ras_common_if *head); 788 789 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 790 struct ras_common_if *head); 791 792 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 793 794 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 795 struct ras_query_if *info); 796 797 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 798 enum amdgpu_ras_block block); 799 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 800 enum amdgpu_ras_block block); 801 802 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 803 struct ras_inject_if *info); 804 805 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 806 struct ras_common_if *head); 807 808 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 809 struct ras_common_if *head); 810 811 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 812 struct ras_dispatch_if *info); 813 814 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 815 struct ras_common_if *head); 816 817 extern atomic_t amdgpu_ras_in_intr; 818 819 static inline bool amdgpu_ras_intr_triggered(void) 820 { 821 return !!atomic_read(&amdgpu_ras_in_intr); 822 } 823 824 static inline void amdgpu_ras_intr_cleared(void) 825 { 826 atomic_set(&amdgpu_ras_in_intr, 0); 827 } 828 829 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 830 831 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 832 833 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 834 835 void amdgpu_release_ras_context(struct amdgpu_device *adev); 836 837 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 838 839 const char *get_ras_block_str(struct ras_common_if *ras_block); 840 841 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 842 843 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 844 845 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 846 847 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 848 849 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 850 851 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 852 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); 853 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); 854 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 855 unsigned int *mode); 856 857 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 858 struct amdgpu_ras_block_object *ras_block_obj); 859 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 860 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 861 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 862 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 863 uint32_t instance, 864 uint32_t *memory_id); 865 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 866 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 867 uint32_t instance, 868 unsigned long *err_cnt); 869 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 870 const struct amdgpu_ras_err_status_reg_entry *reg_list, 871 uint32_t reg_list_size, 872 const struct amdgpu_ras_memory_id_entry *mem_list, 873 uint32_t mem_list_size, 874 uint32_t instance, 875 uint32_t err_type, 876 unsigned long *err_count); 877 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 878 const struct amdgpu_ras_err_status_reg_entry *reg_list, 879 uint32_t reg_list_size, 880 uint32_t instance); 881 882 int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 883 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 884 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 885 struct amdgpu_smuio_mcm_config_info *mcm_info, 886 struct ras_err_addr *err_addr, u64 count); 887 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 888 struct amdgpu_smuio_mcm_config_info *mcm_info, 889 struct ras_err_addr *err_addr, u64 count); 890 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 891 struct amdgpu_smuio_mcm_config_info *mcm_info, 892 struct ras_err_addr *err_addr, u64 count); 893 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 894 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 895 const struct aca_info *aca_info, void *data); 896 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); 897 898 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 899 struct aca_handle *handle, char *buf, void *data); 900 901 void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, 902 struct ras_err_addr *err_addr); 903 904 void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, 905 struct ras_err_addr *mca_err_addr); 906 907 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); 908 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); 909 910 bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id); 911 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); 912 #endif 913