1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "ta_ras_if.h" 30 #include "amdgpu_ras_eeprom.h" 31 #include "amdgpu_smuio.h" 32 #include "amdgpu_aca.h" 33 34 struct amdgpu_iv_entry; 35 36 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 37 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 38 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 39 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 40 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 41 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 42 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 43 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 44 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 45 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 46 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 13, 13) 47 #define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x) AMDGPU_GET_REG_FIELD(x, 31, 31) 48 49 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 50 /* position of instance value in sub_block_index of 51 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 52 */ 53 #define AMDGPU_RAS_INST_MASK 0xfffff000 54 #define AMDGPU_RAS_INST_SHIFT 0xc 55 56 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 57 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 58 59 /* The high three bits indicates socketid */ 60 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 61 62 enum amdgpu_ras_block { 63 AMDGPU_RAS_BLOCK__UMC = 0, 64 AMDGPU_RAS_BLOCK__SDMA, 65 AMDGPU_RAS_BLOCK__GFX, 66 AMDGPU_RAS_BLOCK__MMHUB, 67 AMDGPU_RAS_BLOCK__ATHUB, 68 AMDGPU_RAS_BLOCK__PCIE_BIF, 69 AMDGPU_RAS_BLOCK__HDP, 70 AMDGPU_RAS_BLOCK__XGMI_WAFL, 71 AMDGPU_RAS_BLOCK__DF, 72 AMDGPU_RAS_BLOCK__SMN, 73 AMDGPU_RAS_BLOCK__SEM, 74 AMDGPU_RAS_BLOCK__MP0, 75 AMDGPU_RAS_BLOCK__MP1, 76 AMDGPU_RAS_BLOCK__FUSE, 77 AMDGPU_RAS_BLOCK__MCA, 78 AMDGPU_RAS_BLOCK__VCN, 79 AMDGPU_RAS_BLOCK__JPEG, 80 AMDGPU_RAS_BLOCK__IH, 81 AMDGPU_RAS_BLOCK__MPIO, 82 83 AMDGPU_RAS_BLOCK__LAST 84 }; 85 86 enum amdgpu_ras_mca_block { 87 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 88 AMDGPU_RAS_MCA_BLOCK__MP1, 89 AMDGPU_RAS_MCA_BLOCK__MPIO, 90 AMDGPU_RAS_MCA_BLOCK__IOHC, 91 92 AMDGPU_RAS_MCA_BLOCK__LAST 93 }; 94 95 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 96 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 97 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 98 99 enum amdgpu_ras_gfx_subblock { 100 /* CPC */ 101 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 102 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 103 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 104 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 105 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 106 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 107 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 108 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 109 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 110 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 111 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 112 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 113 /* CPF */ 114 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 115 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 116 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 117 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 118 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 119 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 120 /* CPG */ 121 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 122 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 123 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 124 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 125 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 126 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 127 /* GDS */ 128 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 129 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 130 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 131 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 132 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 133 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 134 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 135 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 136 /* SPI */ 137 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 138 /* SQ */ 139 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 140 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 141 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 142 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 143 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 144 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 145 /* SQC (3 ranges) */ 146 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 147 /* SQC range 0 */ 148 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 149 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 150 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 151 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 152 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 153 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 154 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 155 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 156 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 157 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 158 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 159 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 160 /* SQC range 1 */ 161 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 162 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 163 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 164 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 165 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 166 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 167 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 168 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 169 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 170 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 171 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 172 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 174 /* SQC range 2 */ 175 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 176 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 177 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 178 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 179 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 180 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 181 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 182 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 183 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 184 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 185 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 186 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 187 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 188 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 189 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 190 /* TA */ 191 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 192 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 193 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 194 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 195 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 196 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 197 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 198 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 199 /* TCA */ 200 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 201 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 202 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 203 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 204 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 205 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 206 /* TCC (5 sub-ranges) */ 207 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 208 /* TCC range 0 */ 209 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 210 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 211 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 212 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 213 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 214 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 215 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 216 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 217 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 218 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 219 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 220 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 221 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 222 /* TCC range 1 */ 223 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 224 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 225 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 226 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 227 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 228 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 229 /* TCC range 2 */ 230 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 231 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 232 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 233 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 234 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 235 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 236 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 237 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 238 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 239 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 240 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 241 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 242 /* TCC range 3 */ 243 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 244 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 245 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 246 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 247 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 248 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 249 /* TCC range 4 */ 250 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 251 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 252 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 253 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 254 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 255 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 256 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 257 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 258 /* TCI */ 259 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 260 /* TCP */ 261 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 262 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 263 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 264 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 265 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 266 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 267 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 268 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 269 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 270 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 271 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 272 /* TD */ 273 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 274 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 275 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 276 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 277 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 278 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 279 /* EA (3 sub-ranges) */ 280 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 281 /* EA range 0 */ 282 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 283 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 284 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 285 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 286 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 287 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 288 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 289 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 290 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 291 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 292 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 293 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 294 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 295 /* EA range 1 */ 296 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 297 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 298 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 299 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 300 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 301 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 302 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 303 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 304 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 305 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 306 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 307 /* EA range 2 */ 308 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 309 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 310 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 311 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 312 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 313 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 314 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 315 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 316 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 317 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 318 /* UTC VM L2 bank */ 319 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 320 /* UTC VM walker */ 321 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 322 /* UTC ATC L2 2MB cache */ 323 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 324 /* UTC ATC L2 4KB cache */ 325 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 326 AMDGPU_RAS_BLOCK__GFX_MAX 327 }; 328 329 enum amdgpu_ras_error_type { 330 AMDGPU_RAS_ERROR__NONE = 0, 331 AMDGPU_RAS_ERROR__PARITY = 1, 332 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 333 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 334 AMDGPU_RAS_ERROR__POISON = 8, 335 }; 336 337 enum amdgpu_ras_ret { 338 AMDGPU_RAS_SUCCESS = 0, 339 AMDGPU_RAS_FAIL, 340 AMDGPU_RAS_UE, 341 AMDGPU_RAS_CE, 342 AMDGPU_RAS_PT, 343 }; 344 345 enum amdgpu_ras_error_query_mode { 346 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 347 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 348 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 349 }; 350 351 /* ras error status reisger fields */ 352 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 353 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 354 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 355 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 356 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 357 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 358 #define ERR_STATUS__ERR_CNT__SHIFT 0x17 359 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L 360 361 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 362 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 363 364 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 365 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 366 367 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 368 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 369 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 370 371 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 372 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 373 374 struct amdgpu_ras_err_status_reg_entry { 375 uint32_t hwip; 376 uint32_t ip_inst; 377 uint32_t seg_lo; 378 uint32_t reg_lo; 379 uint32_t seg_hi; 380 uint32_t reg_hi; 381 uint32_t reg_inst; 382 uint32_t flags; 383 const char *block_name; 384 }; 385 386 struct amdgpu_ras_memory_id_entry { 387 uint32_t memory_id; 388 const char *name; 389 }; 390 391 struct ras_common_if { 392 enum amdgpu_ras_block block; 393 enum amdgpu_ras_error_type type; 394 uint32_t sub_block_index; 395 char name[32]; 396 }; 397 398 #define MAX_UMC_CHANNEL_NUM 32 399 400 struct ecc_info_per_ch { 401 uint16_t ce_count_lo_chip; 402 uint16_t ce_count_hi_chip; 403 uint64_t mca_umc_status; 404 uint64_t mca_umc_addr; 405 uint64_t mca_ceumc_addr; 406 }; 407 408 struct umc_ecc_info { 409 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 410 411 /* Determine smu ecctable whether support 412 * record correctable error address 413 */ 414 int record_ce_addr_supported; 415 }; 416 417 struct amdgpu_ras { 418 /* ras infrastructure */ 419 /* for ras itself. */ 420 uint32_t features; 421 uint32_t schema; 422 struct list_head head; 423 /* sysfs */ 424 struct device_attribute features_attr; 425 struct device_attribute version_attr; 426 struct device_attribute schema_attr; 427 struct bin_attribute badpages_attr; 428 struct dentry *de_ras_eeprom_table; 429 /* block array */ 430 struct ras_manager *objs; 431 432 /* gpu recovery */ 433 struct work_struct recovery_work; 434 atomic_t in_recovery; 435 struct amdgpu_device *adev; 436 /* error handler data */ 437 struct ras_err_handler_data *eh_data; 438 struct mutex recovery_lock; 439 440 uint32_t flags; 441 bool reboot; 442 struct amdgpu_ras_eeprom_control eeprom_control; 443 444 bool error_query_ready; 445 446 /* bad page count threshold */ 447 uint32_t bad_page_cnt_threshold; 448 449 /* disable ras error count harvest in recovery */ 450 bool disable_ras_err_cnt_harvest; 451 452 /* is poison mode supported */ 453 bool poison_supported; 454 455 /* RAS count errors delayed work */ 456 struct delayed_work ras_counte_delay_work; 457 atomic_t ras_ue_count; 458 atomic_t ras_ce_count; 459 460 /* record umc error info queried from smu */ 461 struct umc_ecc_info umc_ecc; 462 463 /* Indicates smu whether need update bad channel info */ 464 bool update_channel_flag; 465 /* Record status of smu mca debug mode */ 466 bool is_aca_debug_mode; 467 468 /* Record special requirements of gpu reset caller */ 469 uint32_t gpu_reset_flags; 470 471 struct task_struct *page_retirement_thread; 472 wait_queue_head_t page_retirement_wq; 473 struct mutex page_retirement_lock; 474 atomic_t page_retirement_req_cnt; 475 }; 476 477 struct ras_fs_data { 478 char sysfs_name[48]; 479 char debugfs_name[32]; 480 }; 481 482 struct ras_err_addr { 483 struct list_head node; 484 uint64_t err_status; 485 uint64_t err_ipid; 486 uint64_t err_addr; 487 }; 488 489 struct ras_err_info { 490 struct amdgpu_smuio_mcm_config_info mcm_info; 491 u64 ce_count; 492 u64 ue_count; 493 u64 de_count; 494 struct list_head err_addr_list; 495 }; 496 497 struct ras_err_node { 498 struct list_head node; 499 struct ras_err_info err_info; 500 }; 501 502 struct ras_err_data { 503 unsigned long ue_count; 504 unsigned long ce_count; 505 unsigned long de_count; 506 unsigned long err_addr_cnt; 507 struct eeprom_table_record *err_addr; 508 u32 err_list_count; 509 struct list_head err_node_list; 510 }; 511 512 #define for_each_ras_error(err_node, err_data) \ 513 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 514 515 struct ras_err_handler_data { 516 /* point to bad page records array */ 517 struct eeprom_table_record *bps; 518 /* the count of entries */ 519 int count; 520 /* the space can place new entries */ 521 int space_left; 522 }; 523 524 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 525 void *err_data, 526 struct amdgpu_iv_entry *entry); 527 528 struct ras_ih_data { 529 /* interrupt bottom half */ 530 struct work_struct ih_work; 531 int inuse; 532 /* IP callback */ 533 ras_ih_cb cb; 534 /* full of entries */ 535 unsigned char *ring; 536 unsigned int ring_size; 537 unsigned int element_size; 538 unsigned int aligned_element_size; 539 unsigned int rptr; 540 unsigned int wptr; 541 }; 542 543 struct ras_manager { 544 struct ras_common_if head; 545 /* reference count */ 546 int use; 547 /* ras block link */ 548 struct list_head node; 549 /* the device */ 550 struct amdgpu_device *adev; 551 /* sysfs */ 552 struct device_attribute sysfs_attr; 553 int attr_inuse; 554 555 /* fs node name */ 556 struct ras_fs_data fs_data; 557 558 /* IH data */ 559 struct ras_ih_data ih_data; 560 561 struct ras_err_data err_data; 562 563 struct aca_handle aca_handle; 564 }; 565 566 struct ras_badpage { 567 unsigned int bp; 568 unsigned int size; 569 unsigned int flags; 570 }; 571 572 /* interfaces for IP */ 573 struct ras_fs_if { 574 struct ras_common_if head; 575 const char* sysfs_name; 576 char debugfs_name[32]; 577 }; 578 579 struct ras_query_if { 580 struct ras_common_if head; 581 unsigned long ue_count; 582 unsigned long ce_count; 583 unsigned long de_count; 584 }; 585 586 struct ras_inject_if { 587 struct ras_common_if head; 588 uint64_t address; 589 uint64_t value; 590 uint32_t instance_mask; 591 }; 592 593 struct ras_cure_if { 594 struct ras_common_if head; 595 uint64_t address; 596 }; 597 598 struct ras_ih_if { 599 struct ras_common_if head; 600 ras_ih_cb cb; 601 }; 602 603 struct ras_dispatch_if { 604 struct ras_common_if head; 605 struct amdgpu_iv_entry *entry; 606 }; 607 608 struct ras_debug_if { 609 union { 610 struct ras_common_if head; 611 struct ras_inject_if inject; 612 }; 613 int op; 614 }; 615 616 struct amdgpu_ras_block_object { 617 struct ras_common_if ras_comm; 618 619 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 620 enum amdgpu_ras_block block, uint32_t sub_block_index); 621 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 622 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 623 ras_ih_cb ras_cb; 624 const struct amdgpu_ras_block_hw_ops *hw_ops; 625 }; 626 627 struct amdgpu_ras_block_hw_ops { 628 int (*ras_error_inject)(struct amdgpu_device *adev, 629 void *inject_if, uint32_t instance_mask); 630 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 631 void (*query_ras_error_status)(struct amdgpu_device *adev); 632 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 633 void (*reset_ras_error_count)(struct amdgpu_device *adev); 634 void (*reset_ras_error_status)(struct amdgpu_device *adev); 635 bool (*query_poison_status)(struct amdgpu_device *adev); 636 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 637 }; 638 639 /* work flow 640 * vbios 641 * 1: ras feature enable (enabled by default) 642 * psp 643 * 2: ras framework init (in ip_init) 644 * IP 645 * 3: IH add 646 * 4: debugfs/sysfs create 647 * 5: query/inject 648 * 6: debugfs/sysfs remove 649 * 7: IH remove 650 * 8: feature disable 651 */ 652 653 654 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 655 656 void amdgpu_ras_resume(struct amdgpu_device *adev); 657 void amdgpu_ras_suspend(struct amdgpu_device *adev); 658 659 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 660 unsigned long *ce_count, 661 unsigned long *ue_count, 662 struct ras_query_if *query_info); 663 664 /* error handling functions */ 665 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 666 struct eeprom_table_record *bps, int pages); 667 668 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 669 unsigned long *new_cnt); 670 671 static inline enum ta_ras_block 672 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 673 switch (block) { 674 case AMDGPU_RAS_BLOCK__UMC: 675 return TA_RAS_BLOCK__UMC; 676 case AMDGPU_RAS_BLOCK__SDMA: 677 return TA_RAS_BLOCK__SDMA; 678 case AMDGPU_RAS_BLOCK__GFX: 679 return TA_RAS_BLOCK__GFX; 680 case AMDGPU_RAS_BLOCK__MMHUB: 681 return TA_RAS_BLOCK__MMHUB; 682 case AMDGPU_RAS_BLOCK__ATHUB: 683 return TA_RAS_BLOCK__ATHUB; 684 case AMDGPU_RAS_BLOCK__PCIE_BIF: 685 return TA_RAS_BLOCK__PCIE_BIF; 686 case AMDGPU_RAS_BLOCK__HDP: 687 return TA_RAS_BLOCK__HDP; 688 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 689 return TA_RAS_BLOCK__XGMI_WAFL; 690 case AMDGPU_RAS_BLOCK__DF: 691 return TA_RAS_BLOCK__DF; 692 case AMDGPU_RAS_BLOCK__SMN: 693 return TA_RAS_BLOCK__SMN; 694 case AMDGPU_RAS_BLOCK__SEM: 695 return TA_RAS_BLOCK__SEM; 696 case AMDGPU_RAS_BLOCK__MP0: 697 return TA_RAS_BLOCK__MP0; 698 case AMDGPU_RAS_BLOCK__MP1: 699 return TA_RAS_BLOCK__MP1; 700 case AMDGPU_RAS_BLOCK__FUSE: 701 return TA_RAS_BLOCK__FUSE; 702 case AMDGPU_RAS_BLOCK__MCA: 703 return TA_RAS_BLOCK__MCA; 704 case AMDGPU_RAS_BLOCK__VCN: 705 return TA_RAS_BLOCK__VCN; 706 case AMDGPU_RAS_BLOCK__JPEG: 707 return TA_RAS_BLOCK__JPEG; 708 default: 709 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 710 return TA_RAS_BLOCK__UMC; 711 } 712 } 713 714 static inline enum ta_ras_error_type 715 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 716 switch (error) { 717 case AMDGPU_RAS_ERROR__NONE: 718 return TA_RAS_ERROR__NONE; 719 case AMDGPU_RAS_ERROR__PARITY: 720 return TA_RAS_ERROR__PARITY; 721 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 722 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 723 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 724 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 725 case AMDGPU_RAS_ERROR__POISON: 726 return TA_RAS_ERROR__POISON; 727 default: 728 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 729 return TA_RAS_ERROR__NONE; 730 } 731 } 732 733 /* called in ip_init and ip_fini */ 734 int amdgpu_ras_init(struct amdgpu_device *adev); 735 int amdgpu_ras_late_init(struct amdgpu_device *adev); 736 int amdgpu_ras_fini(struct amdgpu_device *adev); 737 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 738 739 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 740 struct ras_common_if *ras_block); 741 742 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 743 struct ras_common_if *ras_block); 744 745 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 746 struct ras_common_if *head, bool enable); 747 748 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 749 struct ras_common_if *head, bool enable); 750 751 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 752 struct ras_common_if *head); 753 754 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 755 struct ras_common_if *head); 756 757 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 758 759 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 760 struct ras_query_if *info); 761 762 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 763 enum amdgpu_ras_block block); 764 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 765 enum amdgpu_ras_block block); 766 767 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 768 struct ras_inject_if *info); 769 770 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 771 struct ras_common_if *head); 772 773 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 774 struct ras_common_if *head); 775 776 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 777 struct ras_dispatch_if *info); 778 779 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 780 struct ras_common_if *head); 781 782 extern atomic_t amdgpu_ras_in_intr; 783 784 static inline bool amdgpu_ras_intr_triggered(void) 785 { 786 return !!atomic_read(&amdgpu_ras_in_intr); 787 } 788 789 static inline void amdgpu_ras_intr_cleared(void) 790 { 791 atomic_set(&amdgpu_ras_in_intr, 0); 792 } 793 794 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 795 796 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 797 798 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 799 800 void amdgpu_release_ras_context(struct amdgpu_device *adev); 801 802 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 803 804 const char *get_ras_block_str(struct ras_common_if *ras_block); 805 806 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 807 808 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 809 810 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 811 812 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 813 814 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 815 816 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 817 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); 818 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); 819 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 820 unsigned int *mode); 821 822 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 823 struct amdgpu_ras_block_object *ras_block_obj); 824 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 825 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 826 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 827 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 828 uint32_t instance, 829 uint32_t *memory_id); 830 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 831 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 832 uint32_t instance, 833 unsigned long *err_cnt); 834 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 835 const struct amdgpu_ras_err_status_reg_entry *reg_list, 836 uint32_t reg_list_size, 837 const struct amdgpu_ras_memory_id_entry *mem_list, 838 uint32_t mem_list_size, 839 uint32_t instance, 840 uint32_t err_type, 841 unsigned long *err_count); 842 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 843 const struct amdgpu_ras_err_status_reg_entry *reg_list, 844 uint32_t reg_list_size, 845 uint32_t instance); 846 847 int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 848 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 849 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 850 struct amdgpu_smuio_mcm_config_info *mcm_info, 851 struct ras_err_addr *err_addr, u64 count); 852 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 853 struct amdgpu_smuio_mcm_config_info *mcm_info, 854 struct ras_err_addr *err_addr, u64 count); 855 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 856 struct amdgpu_smuio_mcm_config_info *mcm_info, 857 struct ras_err_addr *err_addr, u64 count); 858 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 859 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 860 const struct aca_info *aca_info, void *data); 861 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); 862 863 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 864 struct aca_handle *handle, char *buf, void *data); 865 866 void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, 867 struct ras_err_addr *err_addr); 868 869 void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, 870 struct ras_err_addr *mca_err_addr); 871 #endif 872