1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include <linux/kfifo.h> 30 #include <linux/radix-tree.h> 31 #include <linux/siphash.h> 32 #include "ta_ras_if.h" 33 #include "amdgpu_ras_eeprom.h" 34 #include "amdgpu_smuio.h" 35 #include "amdgpu_aca.h" 36 37 struct amdgpu_iv_entry; 38 39 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0) 40 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1) 41 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2) 42 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3) 43 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4) 44 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5) 45 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6) 46 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 47 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 48 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 49 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13) 50 #define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x) AMDGPU_GET_REG_FIELD(x, 31, 31) 51 52 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 1000 53 #define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA 54 #define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF 55 #define AMDGPU_RAS_BOOT_SUCEESS 0x80000000 56 57 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 58 /* position of instance value in sub_block_index of 59 * ta_ras_trigger_error_input, the sub block uses lower 12 bits 60 */ 61 #define AMDGPU_RAS_INST_MASK 0xfffff000 62 #define AMDGPU_RAS_INST_SHIFT 0xc 63 64 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29 65 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000 66 67 /* The high three bits indicates socketid */ 68 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK) 69 70 #define RAS_EVENT_LOG(adev, id, fmt, ...) \ 71 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__); 72 73 enum amdgpu_ras_block { 74 AMDGPU_RAS_BLOCK__UMC = 0, 75 AMDGPU_RAS_BLOCK__SDMA, 76 AMDGPU_RAS_BLOCK__GFX, 77 AMDGPU_RAS_BLOCK__MMHUB, 78 AMDGPU_RAS_BLOCK__ATHUB, 79 AMDGPU_RAS_BLOCK__PCIE_BIF, 80 AMDGPU_RAS_BLOCK__HDP, 81 AMDGPU_RAS_BLOCK__XGMI_WAFL, 82 AMDGPU_RAS_BLOCK__DF, 83 AMDGPU_RAS_BLOCK__SMN, 84 AMDGPU_RAS_BLOCK__SEM, 85 AMDGPU_RAS_BLOCK__MP0, 86 AMDGPU_RAS_BLOCK__MP1, 87 AMDGPU_RAS_BLOCK__FUSE, 88 AMDGPU_RAS_BLOCK__MCA, 89 AMDGPU_RAS_BLOCK__VCN, 90 AMDGPU_RAS_BLOCK__JPEG, 91 AMDGPU_RAS_BLOCK__IH, 92 AMDGPU_RAS_BLOCK__MPIO, 93 94 AMDGPU_RAS_BLOCK__LAST 95 }; 96 97 enum amdgpu_ras_mca_block { 98 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 99 AMDGPU_RAS_MCA_BLOCK__MP1, 100 AMDGPU_RAS_MCA_BLOCK__MPIO, 101 AMDGPU_RAS_MCA_BLOCK__IOHC, 102 103 AMDGPU_RAS_MCA_BLOCK__LAST 104 }; 105 106 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 107 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 108 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 109 110 enum amdgpu_ras_gfx_subblock { 111 /* CPC */ 112 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 113 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 114 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 115 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 116 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 117 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 118 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 119 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 120 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 121 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 122 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 123 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 124 /* CPF */ 125 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 126 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 127 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 128 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 129 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 130 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 131 /* CPG */ 132 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 133 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 134 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 135 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 136 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 137 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 138 /* GDS */ 139 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 140 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 141 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 142 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 143 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 144 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 145 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 146 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 147 /* SPI */ 148 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 149 /* SQ */ 150 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 151 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 152 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 153 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 154 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 155 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 156 /* SQC (3 ranges) */ 157 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 158 /* SQC range 0 */ 159 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 160 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 161 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 162 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 163 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 164 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 165 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 166 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 167 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 168 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 169 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 170 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 171 /* SQC range 1 */ 172 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 173 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 174 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 175 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 176 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 177 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 178 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 179 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 180 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 181 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 182 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 183 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 184 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 185 /* SQC range 2 */ 186 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 187 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 188 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 189 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 190 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 191 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 192 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 193 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 194 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 195 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 196 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 197 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 198 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 199 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 200 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 201 /* TA */ 202 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 203 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 204 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 205 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 206 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 207 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 208 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 209 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 210 /* TCA */ 211 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 212 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 213 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 214 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 215 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 216 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 217 /* TCC (5 sub-ranges) */ 218 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 219 /* TCC range 0 */ 220 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 221 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 222 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 223 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 224 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 225 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 226 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 227 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 228 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 229 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 230 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 231 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 232 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 233 /* TCC range 1 */ 234 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 235 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 236 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 237 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 238 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 239 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 240 /* TCC range 2 */ 241 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 242 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 243 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 244 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 245 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 246 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 247 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 248 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 249 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 250 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 251 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 252 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 253 /* TCC range 3 */ 254 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 255 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 256 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 257 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 258 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 259 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 260 /* TCC range 4 */ 261 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 262 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 263 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 264 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 265 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 266 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 267 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 268 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 269 /* TCI */ 270 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 271 /* TCP */ 272 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 273 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 274 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 275 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 276 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 277 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 278 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 279 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 280 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 281 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 282 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 283 /* TD */ 284 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 285 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 286 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 287 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 288 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 289 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 290 /* EA (3 sub-ranges) */ 291 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 292 /* EA range 0 */ 293 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 294 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 295 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 296 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 297 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 298 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 299 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 300 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 301 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 302 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 303 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 304 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 305 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 306 /* EA range 1 */ 307 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 308 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 309 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 310 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 311 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 312 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 313 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 314 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 315 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 316 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 317 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 318 /* EA range 2 */ 319 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 320 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 321 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 322 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 323 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 324 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 325 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 326 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 327 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 328 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 329 /* UTC VM L2 bank */ 330 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 331 /* UTC VM walker */ 332 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 333 /* UTC ATC L2 2MB cache */ 334 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 335 /* UTC ATC L2 4KB cache */ 336 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 337 AMDGPU_RAS_BLOCK__GFX_MAX 338 }; 339 340 enum amdgpu_ras_error_type { 341 AMDGPU_RAS_ERROR__NONE = 0, 342 AMDGPU_RAS_ERROR__PARITY = 1, 343 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 344 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 345 AMDGPU_RAS_ERROR__POISON = 8, 346 }; 347 348 enum amdgpu_ras_ret { 349 AMDGPU_RAS_SUCCESS = 0, 350 AMDGPU_RAS_FAIL, 351 AMDGPU_RAS_UE, 352 AMDGPU_RAS_CE, 353 AMDGPU_RAS_PT, 354 }; 355 356 enum amdgpu_ras_error_query_mode { 357 AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 358 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 359 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 360 }; 361 362 /* ras error status reisger fields */ 363 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 364 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L 365 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 366 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L 367 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 368 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L 369 #define ERR_STATUS__ERR_CNT__SHIFT 0x17 370 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L 371 372 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \ 373 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi 374 375 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ 376 (adev->reg_offset[hwip][ip_inst][segment] + (reg)) 377 378 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0) 379 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1) 380 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2) 381 382 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0) 383 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1) 384 385 struct amdgpu_ras_err_status_reg_entry { 386 uint32_t hwip; 387 uint32_t ip_inst; 388 uint32_t seg_lo; 389 uint32_t reg_lo; 390 uint32_t seg_hi; 391 uint32_t reg_hi; 392 uint32_t reg_inst; 393 uint32_t flags; 394 const char *block_name; 395 }; 396 397 struct amdgpu_ras_memory_id_entry { 398 uint32_t memory_id; 399 const char *name; 400 }; 401 402 struct ras_common_if { 403 enum amdgpu_ras_block block; 404 enum amdgpu_ras_error_type type; 405 uint32_t sub_block_index; 406 char name[32]; 407 }; 408 409 #define MAX_UMC_CHANNEL_NUM 32 410 411 struct ecc_info_per_ch { 412 uint16_t ce_count_lo_chip; 413 uint16_t ce_count_hi_chip; 414 uint64_t mca_umc_status; 415 uint64_t mca_umc_addr; 416 uint64_t mca_ceumc_addr; 417 }; 418 419 struct umc_ecc_info { 420 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 421 422 /* Determine smu ecctable whether support 423 * record correctable error address 424 */ 425 int record_ce_addr_supported; 426 }; 427 428 enum ras_event_type { 429 RAS_EVENT_TYPE_INVALID = -1, 430 RAS_EVENT_TYPE_ISR = 0, 431 RAS_EVENT_TYPE_COUNT, 432 }; 433 434 struct ras_event_manager { 435 atomic64_t seqnos[RAS_EVENT_TYPE_COUNT]; 436 }; 437 438 struct ras_query_context { 439 enum ras_event_type type; 440 u64 event_id; 441 }; 442 443 typedef int (*pasid_notify)(struct amdgpu_device *adev, 444 uint16_t pasid, void *data); 445 446 struct ras_poison_msg { 447 enum amdgpu_ras_block block; 448 uint16_t pasid; 449 uint32_t reset; 450 pasid_notify pasid_fn; 451 void *data; 452 }; 453 454 struct ras_err_pages { 455 uint32_t count; 456 uint64_t *pfn; 457 }; 458 459 struct ras_ecc_err { 460 u64 hash_index; 461 uint64_t status; 462 uint64_t ipid; 463 uint64_t addr; 464 struct ras_err_pages err_pages; 465 }; 466 467 struct ras_ecc_log_info { 468 struct mutex lock; 469 siphash_key_t ecc_key; 470 struct radix_tree_root de_page_tree; 471 bool de_updated; 472 }; 473 474 struct amdgpu_ras { 475 /* ras infrastructure */ 476 /* for ras itself. */ 477 uint32_t features; 478 uint32_t schema; 479 struct list_head head; 480 /* sysfs */ 481 struct device_attribute features_attr; 482 struct device_attribute version_attr; 483 struct device_attribute schema_attr; 484 struct bin_attribute badpages_attr; 485 struct dentry *de_ras_eeprom_table; 486 /* block array */ 487 struct ras_manager *objs; 488 489 /* gpu recovery */ 490 struct work_struct recovery_work; 491 atomic_t in_recovery; 492 struct amdgpu_device *adev; 493 /* error handler data */ 494 struct ras_err_handler_data *eh_data; 495 struct mutex recovery_lock; 496 497 uint32_t flags; 498 bool reboot; 499 struct amdgpu_ras_eeprom_control eeprom_control; 500 501 bool error_query_ready; 502 503 /* bad page count threshold */ 504 uint32_t bad_page_cnt_threshold; 505 506 /* disable ras error count harvest in recovery */ 507 bool disable_ras_err_cnt_harvest; 508 509 /* is poison mode supported */ 510 bool poison_supported; 511 512 /* RAS count errors delayed work */ 513 struct delayed_work ras_counte_delay_work; 514 atomic_t ras_ue_count; 515 atomic_t ras_ce_count; 516 517 /* record umc error info queried from smu */ 518 struct umc_ecc_info umc_ecc; 519 520 /* Indicates smu whether need update bad channel info */ 521 bool update_channel_flag; 522 /* Record status of smu mca debug mode */ 523 bool is_aca_debug_mode; 524 525 /* Record special requirements of gpu reset caller */ 526 uint32_t gpu_reset_flags; 527 528 struct task_struct *page_retirement_thread; 529 wait_queue_head_t page_retirement_wq; 530 struct mutex page_retirement_lock; 531 atomic_t page_retirement_req_cnt; 532 struct mutex page_rsv_lock; 533 DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128); 534 struct ras_ecc_log_info umc_ecc_log; 535 struct delayed_work page_retirement_dwork; 536 537 /* Fatal error detected flag */ 538 atomic_t fed; 539 540 /* RAS event manager */ 541 struct ras_event_manager __event_mgr; 542 struct ras_event_manager *event_mgr; 543 544 }; 545 546 struct ras_fs_data { 547 char sysfs_name[48]; 548 char debugfs_name[32]; 549 }; 550 551 struct ras_err_addr { 552 struct list_head node; 553 uint64_t err_status; 554 uint64_t err_ipid; 555 uint64_t err_addr; 556 }; 557 558 struct ras_err_info { 559 struct amdgpu_smuio_mcm_config_info mcm_info; 560 u64 ce_count; 561 u64 ue_count; 562 u64 de_count; 563 struct list_head err_addr_list; 564 }; 565 566 struct ras_err_node { 567 struct list_head node; 568 struct ras_err_info err_info; 569 }; 570 571 struct ras_err_data { 572 unsigned long ue_count; 573 unsigned long ce_count; 574 unsigned long de_count; 575 unsigned long err_addr_cnt; 576 struct eeprom_table_record *err_addr; 577 unsigned long err_addr_len; 578 u32 err_list_count; 579 struct list_head err_node_list; 580 }; 581 582 #define for_each_ras_error(err_node, err_data) \ 583 list_for_each_entry(err_node, &(err_data)->err_node_list, node) 584 585 struct ras_err_handler_data { 586 /* point to bad page records array */ 587 struct eeprom_table_record *bps; 588 /* the count of entries */ 589 int count; 590 /* the space can place new entries */ 591 int space_left; 592 }; 593 594 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 595 void *err_data, 596 struct amdgpu_iv_entry *entry); 597 598 struct ras_ih_data { 599 /* interrupt bottom half */ 600 struct work_struct ih_work; 601 int inuse; 602 /* IP callback */ 603 ras_ih_cb cb; 604 /* full of entries */ 605 unsigned char *ring; 606 unsigned int ring_size; 607 unsigned int element_size; 608 unsigned int aligned_element_size; 609 unsigned int rptr; 610 unsigned int wptr; 611 }; 612 613 struct ras_manager { 614 struct ras_common_if head; 615 /* reference count */ 616 int use; 617 /* ras block link */ 618 struct list_head node; 619 /* the device */ 620 struct amdgpu_device *adev; 621 /* sysfs */ 622 struct device_attribute sysfs_attr; 623 int attr_inuse; 624 625 /* fs node name */ 626 struct ras_fs_data fs_data; 627 628 /* IH data */ 629 struct ras_ih_data ih_data; 630 631 struct ras_err_data err_data; 632 633 struct aca_handle aca_handle; 634 }; 635 636 struct ras_badpage { 637 unsigned int bp; 638 unsigned int size; 639 unsigned int flags; 640 }; 641 642 /* interfaces for IP */ 643 struct ras_fs_if { 644 struct ras_common_if head; 645 const char* sysfs_name; 646 char debugfs_name[32]; 647 }; 648 649 struct ras_query_if { 650 struct ras_common_if head; 651 unsigned long ue_count; 652 unsigned long ce_count; 653 unsigned long de_count; 654 }; 655 656 struct ras_inject_if { 657 struct ras_common_if head; 658 uint64_t address; 659 uint64_t value; 660 uint32_t instance_mask; 661 }; 662 663 struct ras_cure_if { 664 struct ras_common_if head; 665 uint64_t address; 666 }; 667 668 struct ras_ih_if { 669 struct ras_common_if head; 670 ras_ih_cb cb; 671 }; 672 673 struct ras_dispatch_if { 674 struct ras_common_if head; 675 struct amdgpu_iv_entry *entry; 676 }; 677 678 struct ras_debug_if { 679 union { 680 struct ras_common_if head; 681 struct ras_inject_if inject; 682 }; 683 int op; 684 }; 685 686 struct amdgpu_ras_block_object { 687 struct ras_common_if ras_comm; 688 689 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 690 enum amdgpu_ras_block block, uint32_t sub_block_index); 691 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 692 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 693 ras_ih_cb ras_cb; 694 const struct amdgpu_ras_block_hw_ops *hw_ops; 695 }; 696 697 struct amdgpu_ras_block_hw_ops { 698 int (*ras_error_inject)(struct amdgpu_device *adev, 699 void *inject_if, uint32_t instance_mask); 700 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 701 void (*query_ras_error_status)(struct amdgpu_device *adev); 702 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 703 void (*reset_ras_error_count)(struct amdgpu_device *adev); 704 void (*reset_ras_error_status)(struct amdgpu_device *adev); 705 bool (*query_poison_status)(struct amdgpu_device *adev); 706 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 707 }; 708 709 /* work flow 710 * vbios 711 * 1: ras feature enable (enabled by default) 712 * psp 713 * 2: ras framework init (in ip_init) 714 * IP 715 * 3: IH add 716 * 4: debugfs/sysfs create 717 * 5: query/inject 718 * 6: debugfs/sysfs remove 719 * 7: IH remove 720 * 8: feature disable 721 */ 722 723 724 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 725 726 void amdgpu_ras_resume(struct amdgpu_device *adev); 727 void amdgpu_ras_suspend(struct amdgpu_device *adev); 728 729 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 730 unsigned long *ce_count, 731 unsigned long *ue_count, 732 struct ras_query_if *query_info); 733 734 /* error handling functions */ 735 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 736 struct eeprom_table_record *bps, int pages); 737 738 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 739 unsigned long *new_cnt); 740 741 static inline enum ta_ras_block 742 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 743 switch (block) { 744 case AMDGPU_RAS_BLOCK__UMC: 745 return TA_RAS_BLOCK__UMC; 746 case AMDGPU_RAS_BLOCK__SDMA: 747 return TA_RAS_BLOCK__SDMA; 748 case AMDGPU_RAS_BLOCK__GFX: 749 return TA_RAS_BLOCK__GFX; 750 case AMDGPU_RAS_BLOCK__MMHUB: 751 return TA_RAS_BLOCK__MMHUB; 752 case AMDGPU_RAS_BLOCK__ATHUB: 753 return TA_RAS_BLOCK__ATHUB; 754 case AMDGPU_RAS_BLOCK__PCIE_BIF: 755 return TA_RAS_BLOCK__PCIE_BIF; 756 case AMDGPU_RAS_BLOCK__HDP: 757 return TA_RAS_BLOCK__HDP; 758 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 759 return TA_RAS_BLOCK__XGMI_WAFL; 760 case AMDGPU_RAS_BLOCK__DF: 761 return TA_RAS_BLOCK__DF; 762 case AMDGPU_RAS_BLOCK__SMN: 763 return TA_RAS_BLOCK__SMN; 764 case AMDGPU_RAS_BLOCK__SEM: 765 return TA_RAS_BLOCK__SEM; 766 case AMDGPU_RAS_BLOCK__MP0: 767 return TA_RAS_BLOCK__MP0; 768 case AMDGPU_RAS_BLOCK__MP1: 769 return TA_RAS_BLOCK__MP1; 770 case AMDGPU_RAS_BLOCK__FUSE: 771 return TA_RAS_BLOCK__FUSE; 772 case AMDGPU_RAS_BLOCK__MCA: 773 return TA_RAS_BLOCK__MCA; 774 case AMDGPU_RAS_BLOCK__VCN: 775 return TA_RAS_BLOCK__VCN; 776 case AMDGPU_RAS_BLOCK__JPEG: 777 return TA_RAS_BLOCK__JPEG; 778 default: 779 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 780 return TA_RAS_BLOCK__UMC; 781 } 782 } 783 784 static inline enum ta_ras_error_type 785 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 786 switch (error) { 787 case AMDGPU_RAS_ERROR__NONE: 788 return TA_RAS_ERROR__NONE; 789 case AMDGPU_RAS_ERROR__PARITY: 790 return TA_RAS_ERROR__PARITY; 791 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 792 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 793 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 794 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 795 case AMDGPU_RAS_ERROR__POISON: 796 return TA_RAS_ERROR__POISON; 797 default: 798 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 799 return TA_RAS_ERROR__NONE; 800 } 801 } 802 803 /* called in ip_init and ip_fini */ 804 int amdgpu_ras_init(struct amdgpu_device *adev); 805 int amdgpu_ras_late_init(struct amdgpu_device *adev); 806 int amdgpu_ras_fini(struct amdgpu_device *adev); 807 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 808 809 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 810 struct ras_common_if *ras_block); 811 812 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 813 struct ras_common_if *ras_block); 814 815 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 816 struct ras_common_if *head, bool enable); 817 818 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 819 struct ras_common_if *head, bool enable); 820 821 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 822 struct ras_common_if *head); 823 824 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 825 struct ras_common_if *head); 826 827 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 828 829 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 830 struct ras_query_if *info); 831 832 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 833 enum amdgpu_ras_block block); 834 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 835 enum amdgpu_ras_block block); 836 837 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 838 struct ras_inject_if *info); 839 840 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 841 struct ras_common_if *head); 842 843 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 844 struct ras_common_if *head); 845 846 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 847 struct ras_dispatch_if *info); 848 849 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 850 struct ras_common_if *head); 851 852 extern atomic_t amdgpu_ras_in_intr; 853 854 static inline bool amdgpu_ras_intr_triggered(void) 855 { 856 return !!atomic_read(&amdgpu_ras_in_intr); 857 } 858 859 static inline void amdgpu_ras_intr_cleared(void) 860 { 861 atomic_set(&amdgpu_ras_in_intr, 0); 862 } 863 864 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 865 866 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 867 868 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 869 870 void amdgpu_release_ras_context(struct amdgpu_device *adev); 871 872 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 873 874 const char *get_ras_block_str(struct ras_common_if *ras_block); 875 876 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 877 878 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 879 880 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 881 882 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 883 884 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 885 886 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 887 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable); 888 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev); 889 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 890 unsigned int *mode); 891 892 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 893 struct amdgpu_ras_block_object *ras_block_obj); 894 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 895 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name); 896 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 897 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 898 uint32_t instance, 899 uint32_t *memory_id); 900 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 901 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 902 uint32_t instance, 903 unsigned long *err_cnt); 904 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 905 const struct amdgpu_ras_err_status_reg_entry *reg_list, 906 uint32_t reg_list_size, 907 const struct amdgpu_ras_memory_id_entry *mem_list, 908 uint32_t mem_list_size, 909 uint32_t instance, 910 uint32_t err_type, 911 unsigned long *err_count); 912 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 913 const struct amdgpu_ras_err_status_reg_entry *reg_list, 914 uint32_t reg_list_size, 915 uint32_t instance); 916 917 int amdgpu_ras_error_data_init(struct ras_err_data *err_data); 918 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data); 919 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 920 struct amdgpu_smuio_mcm_config_info *mcm_info, 921 struct ras_err_addr *err_addr, u64 count); 922 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 923 struct amdgpu_smuio_mcm_config_info *mcm_info, 924 struct ras_err_addr *err_addr, u64 count); 925 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 926 struct amdgpu_smuio_mcm_config_info *mcm_info, 927 struct ras_err_addr *err_addr, u64 count); 928 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances); 929 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 930 const struct aca_info *aca_info, void *data); 931 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk); 932 933 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 934 struct aca_handle *handle, char *buf, void *data); 935 936 void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, 937 struct ras_err_addr *err_addr); 938 939 void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, 940 struct ras_err_addr *mca_err_addr); 941 942 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); 943 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); 944 945 bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id); 946 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); 947 948 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); 949 950 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, 951 enum amdgpu_ras_block block, uint16_t pasid, 952 pasid_notify pasid_fn, void *data, uint32_t reset); 953 954 __printf(3, 4) 955 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, 956 const char *fmt, ...); 957 958 #endif 959