1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _AMDGPU_RAS_H 25 #define _AMDGPU_RAS_H 26 27 #include <linux/debugfs.h> 28 #include <linux/list.h> 29 #include "ta_ras_if.h" 30 #include "amdgpu_ras_eeprom.h" 31 32 struct amdgpu_iv_entry; 33 34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0) 35 36 enum amdgpu_ras_block { 37 AMDGPU_RAS_BLOCK__UMC = 0, 38 AMDGPU_RAS_BLOCK__SDMA, 39 AMDGPU_RAS_BLOCK__GFX, 40 AMDGPU_RAS_BLOCK__MMHUB, 41 AMDGPU_RAS_BLOCK__ATHUB, 42 AMDGPU_RAS_BLOCK__PCIE_BIF, 43 AMDGPU_RAS_BLOCK__HDP, 44 AMDGPU_RAS_BLOCK__XGMI_WAFL, 45 AMDGPU_RAS_BLOCK__DF, 46 AMDGPU_RAS_BLOCK__SMN, 47 AMDGPU_RAS_BLOCK__SEM, 48 AMDGPU_RAS_BLOCK__MP0, 49 AMDGPU_RAS_BLOCK__MP1, 50 AMDGPU_RAS_BLOCK__FUSE, 51 AMDGPU_RAS_BLOCK__MCA, 52 AMDGPU_RAS_BLOCK__VCN, 53 AMDGPU_RAS_BLOCK__JPEG, 54 55 AMDGPU_RAS_BLOCK__LAST 56 }; 57 58 enum amdgpu_ras_mca_block { 59 AMDGPU_RAS_MCA_BLOCK__MP0 = 0, 60 AMDGPU_RAS_MCA_BLOCK__MP1, 61 AMDGPU_RAS_MCA_BLOCK__MPIO, 62 AMDGPU_RAS_MCA_BLOCK__IOHC, 63 64 AMDGPU_RAS_MCA_BLOCK__LAST 65 }; 66 67 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST 68 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST 69 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) 70 71 enum amdgpu_ras_gfx_subblock { 72 /* CPC */ 73 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 74 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = 75 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, 76 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, 77 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, 78 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 79 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, 80 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, 81 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 82 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 83 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = 84 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, 85 /* CPF */ 86 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 87 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = 88 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, 89 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, 90 AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 91 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, 92 /* CPG */ 93 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 94 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = 95 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, 96 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, 97 AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 98 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, 99 /* GDS */ 100 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 101 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, 102 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 103 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 104 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 105 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 106 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = 107 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 108 /* SPI */ 109 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, 110 /* SQ */ 111 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 112 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, 113 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, 114 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, 115 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 116 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, 117 /* SQC (3 ranges) */ 118 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 119 /* SQC range 0 */ 120 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = 121 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, 122 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 123 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, 124 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 125 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 126 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 127 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 128 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 129 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 130 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = 131 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 132 /* SQC range 1 */ 133 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 134 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 135 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, 136 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 137 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 138 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 139 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 140 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 141 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 142 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 143 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 144 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = 145 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 146 /* SQC range 2 */ 147 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 148 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 149 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, 150 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 151 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 152 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 153 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 154 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 155 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 156 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 157 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 158 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = 159 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 160 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = 161 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, 162 /* TA */ 163 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 164 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = 165 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, 166 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, 167 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, 168 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, 169 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 170 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, 171 /* TCA */ 172 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 173 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = 174 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, 175 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 176 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = 177 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, 178 /* TCC (5 sub-ranges) */ 179 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 180 /* TCC range 0 */ 181 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = 182 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, 183 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = 184 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, 185 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 186 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 187 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 188 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 189 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 190 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 191 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 192 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = 193 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 194 /* TCC range 1 */ 195 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 196 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = 197 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, 198 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 199 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = 200 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 201 /* TCC range 2 */ 202 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 203 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = 204 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, 205 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 206 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 207 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 208 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 209 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, 210 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 211 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 212 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = 213 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 214 /* TCC range 3 */ 215 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 216 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = 217 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, 218 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 219 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = 220 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 221 /* TCC range 4 */ 222 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 223 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 224 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, 225 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 226 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = 227 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 228 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = 229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, 230 /* TCI */ 231 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, 232 /* TCP */ 233 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 234 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = 235 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, 236 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 237 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, 238 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, 239 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, 240 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 241 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 242 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = 243 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 244 /* TD */ 245 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 246 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = 247 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, 248 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 249 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 250 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, 251 /* EA (3 sub-ranges) */ 252 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 253 /* EA range 0 */ 254 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = 255 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, 256 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = 257 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, 258 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 259 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 260 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 261 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 262 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 263 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 264 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 265 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = 266 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 267 /* EA range 1 */ 268 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 269 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = 270 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, 271 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 272 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 273 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 274 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 275 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 276 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 277 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = 278 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 279 /* EA range 2 */ 280 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 281 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = 282 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, 283 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, 284 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, 285 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 286 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = 287 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, 288 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = 289 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, 290 /* UTC VM L2 bank */ 291 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, 292 /* UTC VM walker */ 293 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, 294 /* UTC ATC L2 2MB cache */ 295 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 296 /* UTC ATC L2 4KB cache */ 297 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 298 AMDGPU_RAS_BLOCK__GFX_MAX 299 }; 300 301 enum amdgpu_ras_error_type { 302 AMDGPU_RAS_ERROR__NONE = 0, 303 AMDGPU_RAS_ERROR__PARITY = 1, 304 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, 305 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 306 AMDGPU_RAS_ERROR__POISON = 8, 307 }; 308 309 enum amdgpu_ras_ret { 310 AMDGPU_RAS_SUCCESS = 0, 311 AMDGPU_RAS_FAIL, 312 AMDGPU_RAS_UE, 313 AMDGPU_RAS_CE, 314 AMDGPU_RAS_PT, 315 }; 316 317 struct ras_common_if { 318 enum amdgpu_ras_block block; 319 enum amdgpu_ras_error_type type; 320 uint32_t sub_block_index; 321 char name[32]; 322 }; 323 324 #define MAX_UMC_CHANNEL_NUM 32 325 326 struct ecc_info_per_ch { 327 uint16_t ce_count_lo_chip; 328 uint16_t ce_count_hi_chip; 329 uint64_t mca_umc_status; 330 uint64_t mca_umc_addr; 331 }; 332 333 struct umc_ecc_info { 334 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM]; 335 }; 336 337 struct amdgpu_ras { 338 /* ras infrastructure */ 339 /* for ras itself. */ 340 uint32_t features; 341 struct list_head head; 342 /* sysfs */ 343 struct device_attribute features_attr; 344 struct bin_attribute badpages_attr; 345 struct dentry *de_ras_eeprom_table; 346 /* block array */ 347 struct ras_manager *objs; 348 349 /* gpu recovery */ 350 struct work_struct recovery_work; 351 atomic_t in_recovery; 352 struct amdgpu_device *adev; 353 /* error handler data */ 354 struct ras_err_handler_data *eh_data; 355 struct mutex recovery_lock; 356 357 uint32_t flags; 358 bool reboot; 359 struct amdgpu_ras_eeprom_control eeprom_control; 360 361 bool error_query_ready; 362 363 /* bad page count threshold */ 364 uint32_t bad_page_cnt_threshold; 365 366 /* disable ras error count harvest in recovery */ 367 bool disable_ras_err_cnt_harvest; 368 369 /* is poison mode supported */ 370 bool poison_supported; 371 372 /* RAS count errors delayed work */ 373 struct delayed_work ras_counte_delay_work; 374 atomic_t ras_ue_count; 375 atomic_t ras_ce_count; 376 377 /* record umc error info queried from smu */ 378 struct umc_ecc_info umc_ecc; 379 380 /* Indicates smu whether need update bad channel info */ 381 bool update_channel_flag; 382 }; 383 384 struct ras_fs_data { 385 char sysfs_name[32]; 386 char debugfs_name[32]; 387 }; 388 389 struct ras_err_data { 390 unsigned long ue_count; 391 unsigned long ce_count; 392 unsigned long err_addr_cnt; 393 struct eeprom_table_record *err_addr; 394 }; 395 396 struct ras_err_handler_data { 397 /* point to bad page records array */ 398 struct eeprom_table_record *bps; 399 /* the count of entries */ 400 int count; 401 /* the space can place new entries */ 402 int space_left; 403 }; 404 405 typedef int (*ras_ih_cb)(struct amdgpu_device *adev, 406 void *err_data, 407 struct amdgpu_iv_entry *entry); 408 409 struct ras_ih_data { 410 /* interrupt bottom half */ 411 struct work_struct ih_work; 412 int inuse; 413 /* IP callback */ 414 ras_ih_cb cb; 415 /* full of entries */ 416 unsigned char *ring; 417 unsigned int ring_size; 418 unsigned int element_size; 419 unsigned int aligned_element_size; 420 unsigned int rptr; 421 unsigned int wptr; 422 }; 423 424 struct ras_manager { 425 struct ras_common_if head; 426 /* reference count */ 427 int use; 428 /* ras block link */ 429 struct list_head node; 430 /* the device */ 431 struct amdgpu_device *adev; 432 /* sysfs */ 433 struct device_attribute sysfs_attr; 434 int attr_inuse; 435 436 /* fs node name */ 437 struct ras_fs_data fs_data; 438 439 /* IH data */ 440 struct ras_ih_data ih_data; 441 442 struct ras_err_data err_data; 443 }; 444 445 struct ras_badpage { 446 unsigned int bp; 447 unsigned int size; 448 unsigned int flags; 449 }; 450 451 /* interfaces for IP */ 452 struct ras_fs_if { 453 struct ras_common_if head; 454 const char* sysfs_name; 455 char debugfs_name[32]; 456 }; 457 458 struct ras_query_if { 459 struct ras_common_if head; 460 unsigned long ue_count; 461 unsigned long ce_count; 462 }; 463 464 struct ras_inject_if { 465 struct ras_common_if head; 466 uint64_t address; 467 uint64_t value; 468 }; 469 470 struct ras_cure_if { 471 struct ras_common_if head; 472 uint64_t address; 473 }; 474 475 struct ras_ih_if { 476 struct ras_common_if head; 477 ras_ih_cb cb; 478 }; 479 480 struct ras_dispatch_if { 481 struct ras_common_if head; 482 struct amdgpu_iv_entry *entry; 483 }; 484 485 struct ras_debug_if { 486 union { 487 struct ras_common_if head; 488 struct ras_inject_if inject; 489 }; 490 int op; 491 }; 492 493 struct amdgpu_ras_block_object { 494 struct ras_common_if ras_comm; 495 496 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj, 497 enum amdgpu_ras_block block, uint32_t sub_block_index); 498 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 499 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block); 500 ras_ih_cb ras_cb; 501 const struct amdgpu_ras_block_hw_ops *hw_ops; 502 }; 503 504 struct amdgpu_ras_block_hw_ops { 505 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 506 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status); 507 void (*query_ras_error_status)(struct amdgpu_device *adev); 508 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status); 509 void (*reset_ras_error_count)(struct amdgpu_device *adev); 510 void (*reset_ras_error_status)(struct amdgpu_device *adev); 511 bool (*query_poison_status)(struct amdgpu_device *adev); 512 bool (*handle_poison_consumption)(struct amdgpu_device *adev); 513 }; 514 515 /* work flow 516 * vbios 517 * 1: ras feature enable (enabled by default) 518 * psp 519 * 2: ras framework init (in ip_init) 520 * IP 521 * 3: IH add 522 * 4: debugfs/sysfs create 523 * 5: query/inject 524 * 6: debugfs/sysfs remove 525 * 7: IH remove 526 * 8: feature disable 527 */ 528 529 530 int amdgpu_ras_recovery_init(struct amdgpu_device *adev); 531 532 void amdgpu_ras_resume(struct amdgpu_device *adev); 533 void amdgpu_ras_suspend(struct amdgpu_device *adev); 534 535 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 536 unsigned long *ce_count, 537 unsigned long *ue_count); 538 539 /* error handling functions */ 540 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 541 struct eeprom_table_record *bps, int pages); 542 543 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev); 544 545 static inline enum ta_ras_block 546 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) { 547 switch (block) { 548 case AMDGPU_RAS_BLOCK__UMC: 549 return TA_RAS_BLOCK__UMC; 550 case AMDGPU_RAS_BLOCK__SDMA: 551 return TA_RAS_BLOCK__SDMA; 552 case AMDGPU_RAS_BLOCK__GFX: 553 return TA_RAS_BLOCK__GFX; 554 case AMDGPU_RAS_BLOCK__MMHUB: 555 return TA_RAS_BLOCK__MMHUB; 556 case AMDGPU_RAS_BLOCK__ATHUB: 557 return TA_RAS_BLOCK__ATHUB; 558 case AMDGPU_RAS_BLOCK__PCIE_BIF: 559 return TA_RAS_BLOCK__PCIE_BIF; 560 case AMDGPU_RAS_BLOCK__HDP: 561 return TA_RAS_BLOCK__HDP; 562 case AMDGPU_RAS_BLOCK__XGMI_WAFL: 563 return TA_RAS_BLOCK__XGMI_WAFL; 564 case AMDGPU_RAS_BLOCK__DF: 565 return TA_RAS_BLOCK__DF; 566 case AMDGPU_RAS_BLOCK__SMN: 567 return TA_RAS_BLOCK__SMN; 568 case AMDGPU_RAS_BLOCK__SEM: 569 return TA_RAS_BLOCK__SEM; 570 case AMDGPU_RAS_BLOCK__MP0: 571 return TA_RAS_BLOCK__MP0; 572 case AMDGPU_RAS_BLOCK__MP1: 573 return TA_RAS_BLOCK__MP1; 574 case AMDGPU_RAS_BLOCK__FUSE: 575 return TA_RAS_BLOCK__FUSE; 576 case AMDGPU_RAS_BLOCK__MCA: 577 return TA_RAS_BLOCK__MCA; 578 default: 579 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block); 580 return TA_RAS_BLOCK__UMC; 581 } 582 } 583 584 static inline enum ta_ras_error_type 585 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { 586 switch (error) { 587 case AMDGPU_RAS_ERROR__NONE: 588 return TA_RAS_ERROR__NONE; 589 case AMDGPU_RAS_ERROR__PARITY: 590 return TA_RAS_ERROR__PARITY; 591 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 592 return TA_RAS_ERROR__SINGLE_CORRECTABLE; 593 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 594 return TA_RAS_ERROR__MULTI_UNCORRECTABLE; 595 case AMDGPU_RAS_ERROR__POISON: 596 return TA_RAS_ERROR__POISON; 597 default: 598 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error); 599 return TA_RAS_ERROR__NONE; 600 } 601 } 602 603 /* called in ip_init and ip_fini */ 604 int amdgpu_ras_init(struct amdgpu_device *adev); 605 int amdgpu_ras_late_init(struct amdgpu_device *adev); 606 int amdgpu_ras_fini(struct amdgpu_device *adev); 607 int amdgpu_ras_pre_fini(struct amdgpu_device *adev); 608 609 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 610 struct ras_common_if *ras_block); 611 612 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 613 struct ras_common_if *ras_block); 614 615 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 616 struct ras_common_if *head, bool enable); 617 618 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 619 struct ras_common_if *head, bool enable); 620 621 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 622 struct ras_common_if *head); 623 624 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 625 struct ras_common_if *head); 626 627 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev); 628 629 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 630 struct ras_query_if *info); 631 632 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 633 enum amdgpu_ras_block block); 634 635 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 636 struct ras_inject_if *info); 637 638 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 639 struct ras_common_if *head); 640 641 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 642 struct ras_common_if *head); 643 644 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 645 struct ras_dispatch_if *info); 646 647 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 648 struct ras_common_if *head); 649 650 extern atomic_t amdgpu_ras_in_intr; 651 652 static inline bool amdgpu_ras_intr_triggered(void) 653 { 654 return !!atomic_read(&amdgpu_ras_in_intr); 655 } 656 657 static inline void amdgpu_ras_intr_cleared(void) 658 { 659 atomic_set(&amdgpu_ras_in_intr, 0); 660 } 661 662 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); 663 664 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); 665 666 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev); 667 668 void amdgpu_release_ras_context(struct amdgpu_device *adev); 669 670 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev); 671 672 const char *get_ras_block_str(struct ras_common_if *ras_block); 673 674 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev); 675 676 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block); 677 678 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev); 679 680 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev); 681 682 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con); 683 684 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 685 struct amdgpu_ras_block_object *ras_block_obj); 686 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev); 687 #endif 688