1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/debugfs.h> 25 #include <linux/list.h> 26 #include <linux/module.h> 27 #include <linux/uaccess.h> 28 #include <linux/reboot.h> 29 #include <linux/syscalls.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/list_sort.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_atomfirmware.h" 36 #include "amdgpu_xgmi.h" 37 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 38 #include "nbio_v4_3.h" 39 #include "nbif_v6_3_1.h" 40 #include "nbio_v7_9.h" 41 #include "atom.h" 42 #include "amdgpu_reset.h" 43 #include "amdgpu_psp.h" 44 45 #ifdef CONFIG_X86_MCE_AMD 46 #include <asm/mce.h> 47 48 static bool notifier_registered; 49 #endif 50 static const char *RAS_FS_NAME = "ras"; 51 52 const char *ras_error_string[] = { 53 "none", 54 "parity", 55 "single_correctable", 56 "multi_uncorrectable", 57 "poison", 58 }; 59 60 const char *ras_block_string[] = { 61 "umc", 62 "sdma", 63 "gfx", 64 "mmhub", 65 "athub", 66 "pcie_bif", 67 "hdp", 68 "xgmi_wafl", 69 "df", 70 "smn", 71 "sem", 72 "mp0", 73 "mp1", 74 "fuse", 75 "mca", 76 "vcn", 77 "jpeg", 78 "ih", 79 "mpio", 80 }; 81 82 const char *ras_mca_block_string[] = { 83 "mca_mp0", 84 "mca_mp1", 85 "mca_mpio", 86 "mca_iohc", 87 }; 88 89 struct amdgpu_ras_block_list { 90 /* ras block link */ 91 struct list_head node; 92 93 struct amdgpu_ras_block_object *ras_obj; 94 }; 95 96 const char *get_ras_block_str(struct ras_common_if *ras_block) 97 { 98 if (!ras_block) 99 return "NULL"; 100 101 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT || 102 ras_block->block >= ARRAY_SIZE(ras_block_string)) 103 return "OUT OF RANGE"; 104 105 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) 106 return ras_mca_block_string[ras_block->sub_block_index]; 107 108 return ras_block_string[ras_block->block]; 109 } 110 111 #define ras_block_str(_BLOCK_) \ 112 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range") 113 114 #define ras_err_str(i) (ras_error_string[ffs(i)]) 115 116 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) 117 118 /* inject address is 52 bits */ 119 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) 120 121 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ 122 #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) 123 124 #define MAX_UMC_POISON_POLLING_TIME_ASYNC 300 //ms 125 126 #define AMDGPU_RAS_RETIRE_PAGE_INTERVAL 100 //ms 127 128 #define MAX_FLUSH_RETIRE_DWORK_TIMES 100 129 130 enum amdgpu_ras_retire_page_reservation { 131 AMDGPU_RAS_RETIRE_PAGE_RESERVED, 132 AMDGPU_RAS_RETIRE_PAGE_PENDING, 133 AMDGPU_RAS_RETIRE_PAGE_FAULT, 134 }; 135 136 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); 137 138 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, 139 uint64_t addr); 140 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, 141 uint64_t addr); 142 #ifdef CONFIG_X86_MCE_AMD 143 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); 144 struct mce_notifier_adev_list { 145 struct amdgpu_device *devs[MAX_GPU_INSTANCE]; 146 int num_gpu; 147 }; 148 static struct mce_notifier_adev_list mce_adev_list; 149 #endif 150 151 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) 152 { 153 if (adev && amdgpu_ras_get_context(adev)) 154 amdgpu_ras_get_context(adev)->error_query_ready = ready; 155 } 156 157 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) 158 { 159 if (adev && amdgpu_ras_get_context(adev)) 160 return amdgpu_ras_get_context(adev)->error_query_ready; 161 162 return false; 163 } 164 165 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) 166 { 167 struct ras_err_data err_data; 168 struct eeprom_table_record err_rec; 169 int ret; 170 171 if ((address >= adev->gmc.mc_vram_size) || 172 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { 173 dev_warn(adev->dev, 174 "RAS WARN: input address 0x%llx is invalid.\n", 175 address); 176 return -EINVAL; 177 } 178 179 if (amdgpu_ras_check_bad_page(adev, address)) { 180 dev_warn(adev->dev, 181 "RAS WARN: 0x%llx has already been marked as bad page!\n", 182 address); 183 return 0; 184 } 185 186 ret = amdgpu_ras_error_data_init(&err_data); 187 if (ret) 188 return ret; 189 190 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); 191 err_data.err_addr = &err_rec; 192 amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0); 193 194 if (amdgpu_bad_page_threshold != 0) { 195 amdgpu_ras_add_bad_pages(adev, err_data.err_addr, 196 err_data.err_addr_cnt, false); 197 amdgpu_ras_save_bad_pages(adev, NULL); 198 } 199 200 amdgpu_ras_error_data_fini(&err_data); 201 202 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); 203 dev_warn(adev->dev, "Clear EEPROM:\n"); 204 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); 205 206 return 0; 207 } 208 209 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, 210 size_t size, loff_t *pos) 211 { 212 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; 213 struct ras_query_if info = { 214 .head = obj->head, 215 }; 216 ssize_t s; 217 char val[128]; 218 219 if (amdgpu_ras_query_error_status(obj->adev, &info)) 220 return -EINVAL; 221 222 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */ 223 if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && 224 amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { 225 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) 226 dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); 227 } 228 229 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", 230 "ue", info.ue_count, 231 "ce", info.ce_count); 232 if (*pos >= s) 233 return 0; 234 235 s -= *pos; 236 s = min_t(u64, s, size); 237 238 239 if (copy_to_user(buf, &val[*pos], s)) 240 return -EINVAL; 241 242 *pos += s; 243 244 return s; 245 } 246 247 static const struct file_operations amdgpu_ras_debugfs_ops = { 248 .owner = THIS_MODULE, 249 .read = amdgpu_ras_debugfs_read, 250 .write = NULL, 251 .llseek = default_llseek 252 }; 253 254 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) 255 { 256 int i; 257 258 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { 259 *block_id = i; 260 if (strcmp(name, ras_block_string[i]) == 0) 261 return 0; 262 } 263 return -EINVAL; 264 } 265 266 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, 267 const char __user *buf, size_t size, 268 loff_t *pos, struct ras_debug_if *data) 269 { 270 ssize_t s = min_t(u64, 64, size); 271 char str[65]; 272 char block_name[33]; 273 char err[9] = "ue"; 274 int op = -1; 275 int block_id; 276 uint32_t sub_block; 277 u64 address, value; 278 /* default value is 0 if the mask is not set by user */ 279 u32 instance_mask = 0; 280 281 if (*pos) 282 return -EINVAL; 283 *pos = size; 284 285 memset(str, 0, sizeof(str)); 286 memset(data, 0, sizeof(*data)); 287 288 if (copy_from_user(str, buf, s)) 289 return -EINVAL; 290 291 if (sscanf(str, "disable %32s", block_name) == 1) 292 op = 0; 293 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) 294 op = 1; 295 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) 296 op = 2; 297 else if (strstr(str, "retire_page") != NULL) 298 op = 3; 299 else if (str[0] && str[1] && str[2] && str[3]) 300 /* ascii string, but commands are not matched. */ 301 return -EINVAL; 302 303 if (op != -1) { 304 if (op == 3) { 305 if (sscanf(str, "%*s 0x%llx", &address) != 1 && 306 sscanf(str, "%*s %llu", &address) != 1) 307 return -EINVAL; 308 309 data->op = op; 310 data->inject.address = address; 311 312 return 0; 313 } 314 315 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) 316 return -EINVAL; 317 318 data->head.block = block_id; 319 /* only ue, ce and poison errors are supported */ 320 if (!memcmp("ue", err, 2)) 321 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 322 else if (!memcmp("ce", err, 2)) 323 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; 324 else if (!memcmp("poison", err, 6)) 325 data->head.type = AMDGPU_RAS_ERROR__POISON; 326 else 327 return -EINVAL; 328 329 data->op = op; 330 331 if (op == 2) { 332 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x", 333 &sub_block, &address, &value, &instance_mask) != 4 && 334 sscanf(str, "%*s %*s %*s %u %llu %llu %u", 335 &sub_block, &address, &value, &instance_mask) != 4 && 336 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", 337 &sub_block, &address, &value) != 3 && 338 sscanf(str, "%*s %*s %*s %u %llu %llu", 339 &sub_block, &address, &value) != 3) 340 return -EINVAL; 341 data->head.sub_block_index = sub_block; 342 data->inject.address = address; 343 data->inject.value = value; 344 data->inject.instance_mask = instance_mask; 345 } 346 } else { 347 if (size < sizeof(*data)) 348 return -EINVAL; 349 350 if (copy_from_user(data, buf, sizeof(*data))) 351 return -EINVAL; 352 } 353 354 return 0; 355 } 356 357 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev, 358 struct ras_debug_if *data) 359 { 360 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 361 uint32_t mask, inst_mask = data->inject.instance_mask; 362 363 /* no need to set instance mask if there is only one instance */ 364 if (num_xcc <= 1 && inst_mask) { 365 data->inject.instance_mask = 0; 366 dev_dbg(adev->dev, 367 "RAS inject mask(0x%x) isn't supported and force it to 0.\n", 368 inst_mask); 369 370 return; 371 } 372 373 switch (data->head.block) { 374 case AMDGPU_RAS_BLOCK__GFX: 375 mask = GENMASK(num_xcc - 1, 0); 376 break; 377 case AMDGPU_RAS_BLOCK__SDMA: 378 mask = GENMASK(adev->sdma.num_instances - 1, 0); 379 break; 380 case AMDGPU_RAS_BLOCK__VCN: 381 case AMDGPU_RAS_BLOCK__JPEG: 382 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); 383 break; 384 default: 385 mask = inst_mask; 386 break; 387 } 388 389 /* remove invalid bits in instance mask */ 390 data->inject.instance_mask &= mask; 391 if (inst_mask != data->inject.instance_mask) 392 dev_dbg(adev->dev, 393 "Adjust RAS inject mask 0x%x to 0x%x\n", 394 inst_mask, data->inject.instance_mask); 395 } 396 397 /** 398 * DOC: AMDGPU RAS debugfs control interface 399 * 400 * The control interface accepts struct ras_debug_if which has two members. 401 * 402 * First member: ras_debug_if::head or ras_debug_if::inject. 403 * 404 * head is used to indicate which IP block will be under control. 405 * 406 * head has four members, they are block, type, sub_block_index, name. 407 * block: which IP will be under control. 408 * type: what kind of error will be enabled/disabled/injected. 409 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. 410 * name: the name of IP. 411 * 412 * inject has three more members than head, they are address, value and mask. 413 * As their names indicate, inject operation will write the 414 * value to the address. 415 * 416 * The second member: struct ras_debug_if::op. 417 * It has three kinds of operations. 418 * 419 * - 0: disable RAS on the block. Take ::head as its data. 420 * - 1: enable RAS on the block. Take ::head as its data. 421 * - 2: inject errors on the block. Take ::inject as its data. 422 * 423 * How to use the interface? 424 * 425 * In a program 426 * 427 * Copy the struct ras_debug_if in your code and initialize it. 428 * Write the struct to the control interface. 429 * 430 * From shell 431 * 432 * .. code-block:: bash 433 * 434 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl 435 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl 436 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl 437 * 438 * Where N, is the card which you want to affect. 439 * 440 * "disable" requires only the block. 441 * "enable" requires the block and error type. 442 * "inject" requires the block, error type, address, and value. 443 * 444 * The block is one of: umc, sdma, gfx, etc. 445 * see ras_block_string[] for details 446 * 447 * The error type is one of: ue, ce and poison where, 448 * ue is multi-uncorrectable 449 * ce is single-correctable 450 * poison is poison 451 * 452 * The sub-block is a the sub-block index, pass 0 if there is no sub-block. 453 * The address and value are hexadecimal numbers, leading 0x is optional. 454 * The mask means instance mask, is optional, default value is 0x1. 455 * 456 * For instance, 457 * 458 * .. code-block:: bash 459 * 460 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl 461 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl 462 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl 463 * 464 * How to check the result of the operation? 465 * 466 * To check disable/enable, see "ras" features at, 467 * /sys/class/drm/card[0/1/2...]/device/ras/features 468 * 469 * To check inject, see the corresponding error count at, 470 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count 471 * 472 * .. note:: 473 * Operations are only allowed on blocks which are supported. 474 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask 475 * to see which blocks support RAS on a particular asic. 476 * 477 */ 478 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, 479 const char __user *buf, 480 size_t size, loff_t *pos) 481 { 482 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 483 struct ras_debug_if data; 484 int ret = 0; 485 486 if (!amdgpu_ras_get_error_query_ready(adev)) { 487 dev_warn(adev->dev, "RAS WARN: error injection " 488 "currently inaccessible\n"); 489 return size; 490 } 491 492 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); 493 if (ret) 494 return ret; 495 496 if (data.op == 3) { 497 ret = amdgpu_reserve_page_direct(adev, data.inject.address); 498 if (!ret) 499 return size; 500 else 501 return ret; 502 } 503 504 if (!amdgpu_ras_is_supported(adev, data.head.block)) 505 return -EINVAL; 506 507 switch (data.op) { 508 case 0: 509 ret = amdgpu_ras_feature_enable(adev, &data.head, 0); 510 break; 511 case 1: 512 ret = amdgpu_ras_feature_enable(adev, &data.head, 1); 513 break; 514 case 2: 515 if ((data.inject.address >= adev->gmc.mc_vram_size && 516 adev->gmc.mc_vram_size) || 517 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { 518 dev_warn(adev->dev, "RAS WARN: input address " 519 "0x%llx is invalid.", 520 data.inject.address); 521 ret = -EINVAL; 522 break; 523 } 524 525 /* umc ce/ue error injection for a bad page is not allowed */ 526 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && 527 amdgpu_ras_check_bad_page(adev, data.inject.address)) { 528 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " 529 "already been marked as bad!\n", 530 data.inject.address); 531 break; 532 } 533 534 amdgpu_ras_instance_mask_check(adev, &data); 535 536 /* data.inject.address is offset instead of absolute gpu address */ 537 ret = amdgpu_ras_error_inject(adev, &data.inject); 538 break; 539 default: 540 ret = -EINVAL; 541 break; 542 } 543 544 if (ret) 545 return ret; 546 547 return size; 548 } 549 550 /** 551 * DOC: AMDGPU RAS debugfs EEPROM table reset interface 552 * 553 * Some boards contain an EEPROM which is used to persistently store a list of 554 * bad pages which experiences ECC errors in vram. This interface provides 555 * a way to reset the EEPROM, e.g., after testing error injection. 556 * 557 * Usage: 558 * 559 * .. code-block:: bash 560 * 561 * echo 1 > ../ras/ras_eeprom_reset 562 * 563 * will reset EEPROM table to 0 entries. 564 * 565 */ 566 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, 567 const char __user *buf, 568 size_t size, loff_t *pos) 569 { 570 struct amdgpu_device *adev = 571 (struct amdgpu_device *)file_inode(f)->i_private; 572 int ret; 573 574 ret = amdgpu_ras_eeprom_reset_table( 575 &(amdgpu_ras_get_context(adev)->eeprom_control)); 576 577 if (!ret) { 578 /* Something was written to EEPROM. 579 */ 580 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; 581 return size; 582 } else { 583 return ret; 584 } 585 } 586 587 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { 588 .owner = THIS_MODULE, 589 .read = NULL, 590 .write = amdgpu_ras_debugfs_ctrl_write, 591 .llseek = default_llseek 592 }; 593 594 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { 595 .owner = THIS_MODULE, 596 .read = NULL, 597 .write = amdgpu_ras_debugfs_eeprom_write, 598 .llseek = default_llseek 599 }; 600 601 /** 602 * DOC: AMDGPU RAS sysfs Error Count Interface 603 * 604 * It allows the user to read the error count for each IP block on the gpu through 605 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count 606 * 607 * It outputs the multiple lines which report the uncorrected (ue) and corrected 608 * (ce) error counts. 609 * 610 * The format of one line is below, 611 * 612 * [ce|ue]: count 613 * 614 * Example: 615 * 616 * .. code-block:: bash 617 * 618 * ue: 0 619 * ce: 1 620 * 621 */ 622 static ssize_t amdgpu_ras_sysfs_read(struct device *dev, 623 struct device_attribute *attr, char *buf) 624 { 625 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); 626 struct ras_query_if info = { 627 .head = obj->head, 628 }; 629 630 if (!amdgpu_ras_get_error_query_ready(obj->adev)) 631 return sysfs_emit(buf, "Query currently inaccessible\n"); 632 633 if (amdgpu_ras_query_error_status(obj->adev, &info)) 634 return -EINVAL; 635 636 if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && 637 amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { 638 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) 639 dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); 640 } 641 642 if (info.head.block == AMDGPU_RAS_BLOCK__UMC) 643 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count, 644 "ce", info.ce_count, "de", info.de_count); 645 else 646 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, 647 "ce", info.ce_count); 648 } 649 650 /* obj begin */ 651 652 #define get_obj(obj) do { (obj)->use++; } while (0) 653 #define alive_obj(obj) ((obj)->use) 654 655 static inline void put_obj(struct ras_manager *obj) 656 { 657 if (obj && (--obj->use == 0)) { 658 list_del(&obj->node); 659 amdgpu_ras_error_data_fini(&obj->err_data); 660 } 661 662 if (obj && (obj->use < 0)) 663 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); 664 } 665 666 /* make one obj and return it. */ 667 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, 668 struct ras_common_if *head) 669 { 670 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 671 struct ras_manager *obj; 672 673 if (!adev->ras_enabled || !con) 674 return NULL; 675 676 if (head->block >= AMDGPU_RAS_BLOCK_COUNT) 677 return NULL; 678 679 if (head->block == AMDGPU_RAS_BLOCK__MCA) { 680 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) 681 return NULL; 682 683 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; 684 } else 685 obj = &con->objs[head->block]; 686 687 /* already exist. return obj? */ 688 if (alive_obj(obj)) 689 return NULL; 690 691 if (amdgpu_ras_error_data_init(&obj->err_data)) 692 return NULL; 693 694 obj->head = *head; 695 obj->adev = adev; 696 list_add(&obj->node, &con->head); 697 get_obj(obj); 698 699 return obj; 700 } 701 702 /* return an obj equal to head, or the first when head is NULL */ 703 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 704 struct ras_common_if *head) 705 { 706 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 707 struct ras_manager *obj; 708 int i; 709 710 if (!adev->ras_enabled || !con) 711 return NULL; 712 713 if (head) { 714 if (head->block >= AMDGPU_RAS_BLOCK_COUNT) 715 return NULL; 716 717 if (head->block == AMDGPU_RAS_BLOCK__MCA) { 718 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) 719 return NULL; 720 721 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; 722 } else 723 obj = &con->objs[head->block]; 724 725 if (alive_obj(obj)) 726 return obj; 727 } else { 728 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { 729 obj = &con->objs[i]; 730 if (alive_obj(obj)) 731 return obj; 732 } 733 } 734 735 return NULL; 736 } 737 /* obj end */ 738 739 /* feature ctl begin */ 740 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, 741 struct ras_common_if *head) 742 { 743 return adev->ras_hw_enabled & BIT(head->block); 744 } 745 746 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, 747 struct ras_common_if *head) 748 { 749 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 750 751 return con->features & BIT(head->block); 752 } 753 754 /* 755 * if obj is not created, then create one. 756 * set feature enable flag. 757 */ 758 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, 759 struct ras_common_if *head, int enable) 760 { 761 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 762 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 763 764 /* If hardware does not support ras, then do not create obj. 765 * But if hardware support ras, we can create the obj. 766 * Ras framework checks con->hw_supported to see if it need do 767 * corresponding initialization. 768 * IP checks con->support to see if it need disable ras. 769 */ 770 if (!amdgpu_ras_is_feature_allowed(adev, head)) 771 return 0; 772 773 if (enable) { 774 if (!obj) { 775 obj = amdgpu_ras_create_obj(adev, head); 776 if (!obj) 777 return -EINVAL; 778 } else { 779 /* In case we create obj somewhere else */ 780 get_obj(obj); 781 } 782 con->features |= BIT(head->block); 783 } else { 784 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { 785 con->features &= ~BIT(head->block); 786 put_obj(obj); 787 } 788 } 789 790 return 0; 791 } 792 793 /* wrapper of psp_ras_enable_features */ 794 int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 795 struct ras_common_if *head, bool enable) 796 { 797 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 798 union ta_ras_cmd_input *info; 799 int ret; 800 801 if (!con) 802 return -EINVAL; 803 804 /* For non-gfx ip, do not enable ras feature if it is not allowed */ 805 /* For gfx ip, regardless of feature support status, */ 806 /* Force issue enable or disable ras feature commands */ 807 if (head->block != AMDGPU_RAS_BLOCK__GFX && 808 !amdgpu_ras_is_feature_allowed(adev, head)) 809 return 0; 810 811 /* Only enable gfx ras feature from host side */ 812 if (head->block == AMDGPU_RAS_BLOCK__GFX && 813 !amdgpu_sriov_vf(adev) && 814 !amdgpu_ras_intr_triggered()) { 815 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); 816 if (!info) 817 return -ENOMEM; 818 819 if (!enable) { 820 info->disable_features = (struct ta_ras_disable_features_input) { 821 .block_id = amdgpu_ras_block_to_ta(head->block), 822 .error_type = amdgpu_ras_error_to_ta(head->type), 823 }; 824 } else { 825 info->enable_features = (struct ta_ras_enable_features_input) { 826 .block_id = amdgpu_ras_block_to_ta(head->block), 827 .error_type = amdgpu_ras_error_to_ta(head->type), 828 }; 829 } 830 831 ret = psp_ras_enable_features(&adev->psp, info, enable); 832 if (ret) { 833 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", 834 enable ? "enable":"disable", 835 get_ras_block_str(head), 836 amdgpu_ras_is_poison_mode_supported(adev), ret); 837 kfree(info); 838 return ret; 839 } 840 841 kfree(info); 842 } 843 844 /* setup the obj */ 845 __amdgpu_ras_feature_enable(adev, head, enable); 846 847 return 0; 848 } 849 850 /* Only used in device probe stage and called only once. */ 851 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 852 struct ras_common_if *head, bool enable) 853 { 854 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 855 int ret; 856 857 if (!con) 858 return -EINVAL; 859 860 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { 861 if (enable) { 862 /* There is no harm to issue a ras TA cmd regardless of 863 * the currecnt ras state. 864 * If current state == target state, it will do nothing 865 * But sometimes it requests driver to reset and repost 866 * with error code -EAGAIN. 867 */ 868 ret = amdgpu_ras_feature_enable(adev, head, 1); 869 /* With old ras TA, we might fail to enable ras. 870 * Log it and just setup the object. 871 * TODO need remove this WA in the future. 872 */ 873 if (ret == -EINVAL) { 874 ret = __amdgpu_ras_feature_enable(adev, head, 1); 875 if (!ret) 876 dev_info(adev->dev, 877 "RAS INFO: %s setup object\n", 878 get_ras_block_str(head)); 879 } 880 } else { 881 /* setup the object then issue a ras TA disable cmd.*/ 882 ret = __amdgpu_ras_feature_enable(adev, head, 1); 883 if (ret) 884 return ret; 885 886 /* gfx block ras disable cmd must send to ras-ta */ 887 if (head->block == AMDGPU_RAS_BLOCK__GFX) 888 con->features |= BIT(head->block); 889 890 ret = amdgpu_ras_feature_enable(adev, head, 0); 891 892 /* clean gfx block ras features flag */ 893 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) 894 con->features &= ~BIT(head->block); 895 } 896 } else 897 ret = amdgpu_ras_feature_enable(adev, head, enable); 898 899 return ret; 900 } 901 902 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, 903 bool bypass) 904 { 905 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 906 struct ras_manager *obj, *tmp; 907 908 list_for_each_entry_safe(obj, tmp, &con->head, node) { 909 /* bypass psp. 910 * aka just release the obj and corresponding flags 911 */ 912 if (bypass) { 913 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) 914 break; 915 } else { 916 if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) 917 break; 918 } 919 } 920 921 return con->features; 922 } 923 924 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, 925 bool bypass) 926 { 927 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 928 int i; 929 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; 930 931 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { 932 struct ras_common_if head = { 933 .block = i, 934 .type = default_ras_type, 935 .sub_block_index = 0, 936 }; 937 938 if (i == AMDGPU_RAS_BLOCK__MCA) 939 continue; 940 941 if (bypass) { 942 /* 943 * bypass psp. vbios enable ras for us. 944 * so just create the obj 945 */ 946 if (__amdgpu_ras_feature_enable(adev, &head, 1)) 947 break; 948 } else { 949 if (amdgpu_ras_feature_enable(adev, &head, 1)) 950 break; 951 } 952 } 953 954 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { 955 struct ras_common_if head = { 956 .block = AMDGPU_RAS_BLOCK__MCA, 957 .type = default_ras_type, 958 .sub_block_index = i, 959 }; 960 961 if (bypass) { 962 /* 963 * bypass psp. vbios enable ras for us. 964 * so just create the obj 965 */ 966 if (__amdgpu_ras_feature_enable(adev, &head, 1)) 967 break; 968 } else { 969 if (amdgpu_ras_feature_enable(adev, &head, 1)) 970 break; 971 } 972 } 973 974 return con->features; 975 } 976 /* feature ctl end */ 977 978 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, 979 enum amdgpu_ras_block block) 980 { 981 if (!block_obj) 982 return -EINVAL; 983 984 if (block_obj->ras_comm.block == block) 985 return 0; 986 987 return -EINVAL; 988 } 989 990 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev, 991 enum amdgpu_ras_block block, uint32_t sub_block_index) 992 { 993 struct amdgpu_ras_block_list *node, *tmp; 994 struct amdgpu_ras_block_object *obj; 995 996 if (block >= AMDGPU_RAS_BLOCK__LAST) 997 return NULL; 998 999 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { 1000 if (!node->ras_obj) { 1001 dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); 1002 continue; 1003 } 1004 1005 obj = node->ras_obj; 1006 if (obj->ras_block_match) { 1007 if (obj->ras_block_match(obj, block, sub_block_index) == 0) 1008 return obj; 1009 } else { 1010 if (amdgpu_ras_block_match_default(obj, block) == 0) 1011 return obj; 1012 } 1013 } 1014 1015 return NULL; 1016 } 1017 1018 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data) 1019 { 1020 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1021 int ret = 0; 1022 1023 /* 1024 * choosing right query method according to 1025 * whether smu support query error information 1026 */ 1027 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); 1028 if (ret == -EOPNOTSUPP) { 1029 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 1030 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) 1031 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); 1032 1033 /* umc query_ras_error_address is also responsible for clearing 1034 * error status 1035 */ 1036 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 1037 adev->umc.ras->ras_block.hw_ops->query_ras_error_address) 1038 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); 1039 } else if (!ret) { 1040 if (adev->umc.ras && 1041 adev->umc.ras->ecc_info_query_ras_error_count) 1042 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); 1043 1044 if (adev->umc.ras && 1045 adev->umc.ras->ecc_info_query_ras_error_address) 1046 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data); 1047 } 1048 } 1049 1050 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev, 1051 struct ras_manager *ras_mgr, 1052 struct ras_err_data *err_data, 1053 struct ras_query_context *qctx, 1054 const char *blk_name, 1055 bool is_ue, 1056 bool is_de) 1057 { 1058 struct amdgpu_smuio_mcm_config_info *mcm_info; 1059 struct ras_err_node *err_node; 1060 struct ras_err_info *err_info; 1061 u64 event_id = qctx->evid.event_id; 1062 1063 if (is_ue) { 1064 for_each_ras_error(err_node, err_data) { 1065 err_info = &err_node->err_info; 1066 mcm_info = &err_info->mcm_info; 1067 if (err_info->ue_count) { 1068 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, " 1069 "%lld new uncorrectable hardware errors detected in %s block\n", 1070 mcm_info->socket_id, 1071 mcm_info->die_id, 1072 err_info->ue_count, 1073 blk_name); 1074 } 1075 } 1076 1077 for_each_ras_error(err_node, &ras_mgr->err_data) { 1078 err_info = &err_node->err_info; 1079 mcm_info = &err_info->mcm_info; 1080 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, " 1081 "%lld uncorrectable hardware errors detected in total in %s block\n", 1082 mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name); 1083 } 1084 1085 } else { 1086 if (is_de) { 1087 for_each_ras_error(err_node, err_data) { 1088 err_info = &err_node->err_info; 1089 mcm_info = &err_info->mcm_info; 1090 if (err_info->de_count) { 1091 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, " 1092 "%lld new deferred hardware errors detected in %s block\n", 1093 mcm_info->socket_id, 1094 mcm_info->die_id, 1095 err_info->de_count, 1096 blk_name); 1097 } 1098 } 1099 1100 for_each_ras_error(err_node, &ras_mgr->err_data) { 1101 err_info = &err_node->err_info; 1102 mcm_info = &err_info->mcm_info; 1103 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, " 1104 "%lld deferred hardware errors detected in total in %s block\n", 1105 mcm_info->socket_id, mcm_info->die_id, 1106 err_info->de_count, blk_name); 1107 } 1108 } else { 1109 for_each_ras_error(err_node, err_data) { 1110 err_info = &err_node->err_info; 1111 mcm_info = &err_info->mcm_info; 1112 if (err_info->ce_count) { 1113 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, " 1114 "%lld new correctable hardware errors detected in %s block\n", 1115 mcm_info->socket_id, 1116 mcm_info->die_id, 1117 err_info->ce_count, 1118 blk_name); 1119 } 1120 } 1121 1122 for_each_ras_error(err_node, &ras_mgr->err_data) { 1123 err_info = &err_node->err_info; 1124 mcm_info = &err_info->mcm_info; 1125 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, " 1126 "%lld correctable hardware errors detected in total in %s block\n", 1127 mcm_info->socket_id, mcm_info->die_id, 1128 err_info->ce_count, blk_name); 1129 } 1130 } 1131 } 1132 } 1133 1134 static inline bool err_data_has_source_info(struct ras_err_data *data) 1135 { 1136 return !list_empty(&data->err_node_list); 1137 } 1138 1139 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, 1140 struct ras_query_if *query_if, 1141 struct ras_err_data *err_data, 1142 struct ras_query_context *qctx) 1143 { 1144 struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head); 1145 const char *blk_name = get_ras_block_str(&query_if->head); 1146 u64 event_id = qctx->evid.event_id; 1147 1148 if (err_data->ce_count) { 1149 if (err_data_has_source_info(err_data)) { 1150 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx, 1151 blk_name, false, false); 1152 } else if (!adev->aid_mask && 1153 adev->smuio.funcs && 1154 adev->smuio.funcs->get_socket_id && 1155 adev->smuio.funcs->get_die_id) { 1156 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d " 1157 "%ld correctable hardware errors " 1158 "detected in %s block\n", 1159 adev->smuio.funcs->get_socket_id(adev), 1160 adev->smuio.funcs->get_die_id(adev), 1161 ras_mgr->err_data.ce_count, 1162 blk_name); 1163 } else { 1164 RAS_EVENT_LOG(adev, event_id, "%ld correctable hardware errors " 1165 "detected in %s block\n", 1166 ras_mgr->err_data.ce_count, 1167 blk_name); 1168 } 1169 } 1170 1171 if (err_data->ue_count) { 1172 if (err_data_has_source_info(err_data)) { 1173 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx, 1174 blk_name, true, false); 1175 } else if (!adev->aid_mask && 1176 adev->smuio.funcs && 1177 adev->smuio.funcs->get_socket_id && 1178 adev->smuio.funcs->get_die_id) { 1179 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d " 1180 "%ld uncorrectable hardware errors " 1181 "detected in %s block\n", 1182 adev->smuio.funcs->get_socket_id(adev), 1183 adev->smuio.funcs->get_die_id(adev), 1184 ras_mgr->err_data.ue_count, 1185 blk_name); 1186 } else { 1187 RAS_EVENT_LOG(adev, event_id, "%ld uncorrectable hardware errors " 1188 "detected in %s block\n", 1189 ras_mgr->err_data.ue_count, 1190 blk_name); 1191 } 1192 } 1193 1194 if (err_data->de_count) { 1195 if (err_data_has_source_info(err_data)) { 1196 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx, 1197 blk_name, false, true); 1198 } else if (!adev->aid_mask && 1199 adev->smuio.funcs && 1200 adev->smuio.funcs->get_socket_id && 1201 adev->smuio.funcs->get_die_id) { 1202 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d " 1203 "%ld deferred hardware errors " 1204 "detected in %s block\n", 1205 adev->smuio.funcs->get_socket_id(adev), 1206 adev->smuio.funcs->get_die_id(adev), 1207 ras_mgr->err_data.de_count, 1208 blk_name); 1209 } else { 1210 RAS_EVENT_LOG(adev, event_id, "%ld deferred hardware errors " 1211 "detected in %s block\n", 1212 ras_mgr->err_data.de_count, 1213 blk_name); 1214 } 1215 } 1216 } 1217 1218 static void amdgpu_ras_virt_error_generate_report(struct amdgpu_device *adev, 1219 struct ras_query_if *query_if, 1220 struct ras_err_data *err_data, 1221 struct ras_query_context *qctx) 1222 { 1223 unsigned long new_ue, new_ce, new_de; 1224 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &query_if->head); 1225 const char *blk_name = get_ras_block_str(&query_if->head); 1226 u64 event_id = qctx->evid.event_id; 1227 1228 new_ce = err_data->ce_count - obj->err_data.ce_count; 1229 new_ue = err_data->ue_count - obj->err_data.ue_count; 1230 new_de = err_data->de_count - obj->err_data.de_count; 1231 1232 if (new_ce) { 1233 RAS_EVENT_LOG(adev, event_id, "%lu correctable hardware errors " 1234 "detected in %s block\n", 1235 new_ce, 1236 blk_name); 1237 } 1238 1239 if (new_ue) { 1240 RAS_EVENT_LOG(adev, event_id, "%lu uncorrectable hardware errors " 1241 "detected in %s block\n", 1242 new_ue, 1243 blk_name); 1244 } 1245 1246 if (new_de) { 1247 RAS_EVENT_LOG(adev, event_id, "%lu deferred hardware errors " 1248 "detected in %s block\n", 1249 new_de, 1250 blk_name); 1251 } 1252 } 1253 1254 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data) 1255 { 1256 struct ras_err_node *err_node; 1257 struct ras_err_info *err_info; 1258 1259 if (err_data_has_source_info(err_data)) { 1260 for_each_ras_error(err_node, err_data) { 1261 err_info = &err_node->err_info; 1262 amdgpu_ras_error_statistic_de_count(&obj->err_data, 1263 &err_info->mcm_info, err_info->de_count); 1264 amdgpu_ras_error_statistic_ce_count(&obj->err_data, 1265 &err_info->mcm_info, err_info->ce_count); 1266 amdgpu_ras_error_statistic_ue_count(&obj->err_data, 1267 &err_info->mcm_info, err_info->ue_count); 1268 } 1269 } else { 1270 /* for legacy asic path which doesn't has error source info */ 1271 obj->err_data.ue_count += err_data->ue_count; 1272 obj->err_data.ce_count += err_data->ce_count; 1273 obj->err_data.de_count += err_data->de_count; 1274 } 1275 } 1276 1277 static void amdgpu_ras_mgr_virt_error_data_statistics_update(struct ras_manager *obj, 1278 struct ras_err_data *err_data) 1279 { 1280 /* Host reports absolute counts */ 1281 obj->err_data.ue_count = err_data->ue_count; 1282 obj->err_data.ce_count = err_data->ce_count; 1283 obj->err_data.de_count = err_data->de_count; 1284 } 1285 1286 static struct ras_manager *get_ras_manager(struct amdgpu_device *adev, enum amdgpu_ras_block blk) 1287 { 1288 struct ras_common_if head; 1289 1290 memset(&head, 0, sizeof(head)); 1291 head.block = blk; 1292 1293 return amdgpu_ras_find_obj(adev, &head); 1294 } 1295 1296 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 1297 const struct aca_info *aca_info, void *data) 1298 { 1299 struct ras_manager *obj; 1300 1301 /* in resume phase, no need to create aca fs node */ 1302 if (adev->in_suspend || amdgpu_reset_in_recovery(adev)) 1303 return 0; 1304 1305 obj = get_ras_manager(adev, blk); 1306 if (!obj) 1307 return -EINVAL; 1308 1309 return amdgpu_aca_add_handle(adev, &obj->aca_handle, ras_block_str(blk), aca_info, data); 1310 } 1311 1312 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk) 1313 { 1314 struct ras_manager *obj; 1315 1316 obj = get_ras_manager(adev, blk); 1317 if (!obj) 1318 return -EINVAL; 1319 1320 amdgpu_aca_remove_handle(&obj->aca_handle); 1321 1322 return 0; 1323 } 1324 1325 static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 1326 enum aca_error_type type, struct ras_err_data *err_data, 1327 struct ras_query_context *qctx) 1328 { 1329 struct ras_manager *obj; 1330 1331 obj = get_ras_manager(adev, blk); 1332 if (!obj) 1333 return -EINVAL; 1334 1335 return amdgpu_aca_get_error_data(adev, &obj->aca_handle, type, err_data, qctx); 1336 } 1337 1338 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, 1339 struct aca_handle *handle, char *buf, void *data) 1340 { 1341 struct ras_manager *obj = container_of(handle, struct ras_manager, aca_handle); 1342 struct ras_query_if info = { 1343 .head = obj->head, 1344 }; 1345 1346 if (!amdgpu_ras_get_error_query_ready(obj->adev)) 1347 return sysfs_emit(buf, "Query currently inaccessible\n"); 1348 1349 if (amdgpu_ras_query_error_status(obj->adev, &info)) 1350 return -EINVAL; 1351 1352 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count, 1353 "ce", info.ce_count, "de", info.de_count); 1354 } 1355 1356 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, 1357 struct ras_query_if *info, 1358 struct ras_err_data *err_data, 1359 struct ras_query_context *qctx, 1360 unsigned int error_query_mode) 1361 { 1362 enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT; 1363 struct amdgpu_ras_block_object *block_obj = NULL; 1364 int ret; 1365 1366 if (blk == AMDGPU_RAS_BLOCK_COUNT) 1367 return -EINVAL; 1368 1369 if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY) 1370 return -EINVAL; 1371 1372 if (error_query_mode == AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) { 1373 return amdgpu_virt_req_ras_err_count(adev, blk, err_data); 1374 } else if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { 1375 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { 1376 amdgpu_ras_get_ecc_info(adev, err_data); 1377 } else { 1378 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); 1379 if (!block_obj || !block_obj->hw_ops) { 1380 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1381 get_ras_block_str(&info->head)); 1382 return -EINVAL; 1383 } 1384 1385 if (block_obj->hw_ops->query_ras_error_count) 1386 block_obj->hw_ops->query_ras_error_count(adev, err_data); 1387 1388 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || 1389 (info->head.block == AMDGPU_RAS_BLOCK__GFX) || 1390 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { 1391 if (block_obj->hw_ops->query_ras_error_status) 1392 block_obj->hw_ops->query_ras_error_status(adev); 1393 } 1394 } 1395 } else { 1396 if (amdgpu_aca_is_enabled(adev)) { 1397 ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_UE, err_data, qctx); 1398 if (ret) 1399 return ret; 1400 1401 ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data, qctx); 1402 if (ret) 1403 return ret; 1404 1405 ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_DEFERRED, err_data, qctx); 1406 if (ret) 1407 return ret; 1408 } else { 1409 /* FIXME: add code to check return value later */ 1410 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data, qctx); 1411 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data, qctx); 1412 } 1413 } 1414 1415 return 0; 1416 } 1417 1418 /* query/inject/cure begin */ 1419 static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev, 1420 struct ras_query_if *info, 1421 enum ras_event_type type) 1422 { 1423 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); 1424 struct ras_err_data err_data; 1425 struct ras_query_context qctx; 1426 unsigned int error_query_mode; 1427 int ret; 1428 1429 if (!obj) 1430 return -EINVAL; 1431 1432 ret = amdgpu_ras_error_data_init(&err_data); 1433 if (ret) 1434 return ret; 1435 1436 if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode)) 1437 return -EINVAL; 1438 1439 memset(&qctx, 0, sizeof(qctx)); 1440 qctx.evid.type = type; 1441 qctx.evid.event_id = amdgpu_ras_acquire_event_id(adev, type); 1442 1443 if (!down_read_trylock(&adev->reset_domain->sem)) { 1444 ret = -EIO; 1445 goto out_fini_err_data; 1446 } 1447 1448 ret = amdgpu_ras_query_error_status_helper(adev, info, 1449 &err_data, 1450 &qctx, 1451 error_query_mode); 1452 up_read(&adev->reset_domain->sem); 1453 if (ret) 1454 goto out_fini_err_data; 1455 1456 if (error_query_mode != AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) { 1457 amdgpu_rasmgr_error_data_statistic_update(obj, &err_data); 1458 amdgpu_ras_error_generate_report(adev, info, &err_data, &qctx); 1459 } else { 1460 /* Host provides absolute error counts. First generate the report 1461 * using the previous VF internal count against new host count. 1462 * Then Update VF internal count. 1463 */ 1464 amdgpu_ras_virt_error_generate_report(adev, info, &err_data, &qctx); 1465 amdgpu_ras_mgr_virt_error_data_statistics_update(obj, &err_data); 1466 } 1467 1468 info->ue_count = obj->err_data.ue_count; 1469 info->ce_count = obj->err_data.ce_count; 1470 info->de_count = obj->err_data.de_count; 1471 1472 out_fini_err_data: 1473 amdgpu_ras_error_data_fini(&err_data); 1474 1475 return ret; 1476 } 1477 1478 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info) 1479 { 1480 return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID); 1481 } 1482 1483 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, 1484 enum amdgpu_ras_block block) 1485 { 1486 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); 1487 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 1488 const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; 1489 1490 if (!block_obj || !block_obj->hw_ops) { 1491 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1492 ras_block_str(block)); 1493 return -EOPNOTSUPP; 1494 } 1495 1496 if (!amdgpu_ras_is_supported(adev, block) || 1497 !amdgpu_ras_get_aca_debug_mode(adev)) 1498 return -EOPNOTSUPP; 1499 1500 /* skip ras error reset in gpu reset */ 1501 if ((amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) && 1502 ((smu_funcs && smu_funcs->set_debug_mode) || 1503 (mca_funcs && mca_funcs->mca_set_debug_mode))) 1504 return -EOPNOTSUPP; 1505 1506 if (block_obj->hw_ops->reset_ras_error_count) 1507 block_obj->hw_ops->reset_ras_error_count(adev); 1508 1509 return 0; 1510 } 1511 1512 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 1513 enum amdgpu_ras_block block) 1514 { 1515 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); 1516 1517 if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP) 1518 return 0; 1519 1520 if ((block == AMDGPU_RAS_BLOCK__GFX) || 1521 (block == AMDGPU_RAS_BLOCK__MMHUB)) { 1522 if (block_obj->hw_ops->reset_ras_error_status) 1523 block_obj->hw_ops->reset_ras_error_status(adev); 1524 } 1525 1526 return 0; 1527 } 1528 1529 /* wrapper of psp_ras_trigger_error */ 1530 int amdgpu_ras_error_inject(struct amdgpu_device *adev, 1531 struct ras_inject_if *info) 1532 { 1533 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); 1534 struct ta_ras_trigger_error_input block_info = { 1535 .block_id = amdgpu_ras_block_to_ta(info->head.block), 1536 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), 1537 .sub_block_index = info->head.sub_block_index, 1538 .address = info->address, 1539 .value = info->value, 1540 }; 1541 int ret = -EINVAL; 1542 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, 1543 info->head.block, 1544 info->head.sub_block_index); 1545 1546 /* inject on guest isn't allowed, return success directly */ 1547 if (amdgpu_sriov_vf(adev)) 1548 return 0; 1549 1550 if (!obj) 1551 return -EINVAL; 1552 1553 if (!block_obj || !block_obj->hw_ops) { 1554 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1555 get_ras_block_str(&info->head)); 1556 return -EINVAL; 1557 } 1558 1559 /* Calculate XGMI relative offset */ 1560 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1561 info->head.block != AMDGPU_RAS_BLOCK__GFX) { 1562 block_info.address = 1563 amdgpu_xgmi_get_relative_phy_addr(adev, 1564 block_info.address); 1565 } 1566 1567 if (block_obj->hw_ops->ras_error_inject) { 1568 if (info->head.block == AMDGPU_RAS_BLOCK__GFX) 1569 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask); 1570 else /* Special ras_error_inject is defined (e.g: xgmi) */ 1571 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info, 1572 info->instance_mask); 1573 } else { 1574 /* default path */ 1575 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask); 1576 } 1577 1578 if (ret) 1579 dev_err(adev->dev, "ras inject %s failed %d\n", 1580 get_ras_block_str(&info->head), ret); 1581 1582 return ret; 1583 } 1584 1585 /** 1586 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP 1587 * @adev: pointer to AMD GPU device 1588 * @ce_count: pointer to an integer to be set to the count of correctible errors. 1589 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors. 1590 * @query_info: pointer to ras_query_if 1591 * 1592 * Return 0 for query success or do nothing, otherwise return an error 1593 * on failures 1594 */ 1595 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev, 1596 unsigned long *ce_count, 1597 unsigned long *ue_count, 1598 struct ras_query_if *query_info) 1599 { 1600 int ret; 1601 1602 if (!query_info) 1603 /* do nothing if query_info is not specified */ 1604 return 0; 1605 1606 ret = amdgpu_ras_query_error_status(adev, query_info); 1607 if (ret) 1608 return ret; 1609 1610 *ce_count += query_info->ce_count; 1611 *ue_count += query_info->ue_count; 1612 1613 /* some hardware/IP supports read to clear 1614 * no need to explictly reset the err status after the query call */ 1615 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && 1616 amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { 1617 if (amdgpu_ras_reset_error_status(adev, query_info->head.block)) 1618 dev_warn(adev->dev, 1619 "Failed to reset error counter and error status\n"); 1620 } 1621 1622 return 0; 1623 } 1624 1625 /** 1626 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP 1627 * @adev: pointer to AMD GPU device 1628 * @ce_count: pointer to an integer to be set to the count of correctible errors. 1629 * @ue_count: pointer to an integer to be set to the count of uncorrectible 1630 * errors. 1631 * @query_info: pointer to ras_query_if if the query request is only for 1632 * specific ip block; if info is NULL, then the qurey request is for 1633 * all the ip blocks that support query ras error counters/status 1634 * 1635 * If set, @ce_count or @ue_count, count and return the corresponding 1636 * error counts in those integer pointers. Return 0 if the device 1637 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. 1638 */ 1639 int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 1640 unsigned long *ce_count, 1641 unsigned long *ue_count, 1642 struct ras_query_if *query_info) 1643 { 1644 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1645 struct ras_manager *obj; 1646 unsigned long ce, ue; 1647 int ret; 1648 1649 if (!adev->ras_enabled || !con) 1650 return -EOPNOTSUPP; 1651 1652 /* Don't count since no reporting. 1653 */ 1654 if (!ce_count && !ue_count) 1655 return 0; 1656 1657 ce = 0; 1658 ue = 0; 1659 if (!query_info) { 1660 /* query all the ip blocks that support ras query interface */ 1661 list_for_each_entry(obj, &con->head, node) { 1662 struct ras_query_if info = { 1663 .head = obj->head, 1664 }; 1665 1666 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info); 1667 } 1668 } else { 1669 /* query specific ip block */ 1670 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info); 1671 } 1672 1673 if (ret) 1674 return ret; 1675 1676 if (ce_count) 1677 *ce_count = ce; 1678 1679 if (ue_count) 1680 *ue_count = ue; 1681 1682 return 0; 1683 } 1684 /* query/inject/cure end */ 1685 1686 1687 /* sysfs begin */ 1688 1689 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, 1690 struct ras_badpage **bps, unsigned int *count); 1691 1692 static char *amdgpu_ras_badpage_flags_str(unsigned int flags) 1693 { 1694 switch (flags) { 1695 case AMDGPU_RAS_RETIRE_PAGE_RESERVED: 1696 return "R"; 1697 case AMDGPU_RAS_RETIRE_PAGE_PENDING: 1698 return "P"; 1699 case AMDGPU_RAS_RETIRE_PAGE_FAULT: 1700 default: 1701 return "F"; 1702 } 1703 } 1704 1705 /** 1706 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface 1707 * 1708 * It allows user to read the bad pages of vram on the gpu through 1709 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages 1710 * 1711 * It outputs multiple lines, and each line stands for one gpu page. 1712 * 1713 * The format of one line is below, 1714 * gpu pfn : gpu page size : flags 1715 * 1716 * gpu pfn and gpu page size are printed in hex format. 1717 * flags can be one of below character, 1718 * 1719 * R: reserved, this gpu page is reserved and not able to use. 1720 * 1721 * P: pending for reserve, this gpu page is marked as bad, will be reserved 1722 * in next window of page_reserve. 1723 * 1724 * F: unable to reserve. this gpu page can't be reserved due to some reasons. 1725 * 1726 * Examples: 1727 * 1728 * .. code-block:: bash 1729 * 1730 * 0x00000001 : 0x00001000 : R 1731 * 0x00000002 : 0x00001000 : P 1732 * 1733 */ 1734 1735 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, 1736 struct kobject *kobj, const struct bin_attribute *attr, 1737 char *buf, loff_t ppos, size_t count) 1738 { 1739 struct amdgpu_ras *con = 1740 container_of(attr, struct amdgpu_ras, badpages_attr); 1741 struct amdgpu_device *adev = con->adev; 1742 const unsigned int element_size = 1743 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; 1744 unsigned int start = div64_ul(ppos + element_size - 1, element_size); 1745 unsigned int end = div64_ul(ppos + count - 1, element_size); 1746 ssize_t s = 0; 1747 struct ras_badpage *bps = NULL; 1748 unsigned int bps_count = 0; 1749 1750 memset(buf, 0, count); 1751 1752 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) 1753 return 0; 1754 1755 for (; start < end && start < bps_count; start++) 1756 s += scnprintf(&buf[s], element_size + 1, 1757 "0x%08x : 0x%08x : %1s\n", 1758 bps[start].bp, 1759 bps[start].size, 1760 amdgpu_ras_badpage_flags_str(bps[start].flags)); 1761 1762 kfree(bps); 1763 1764 return s; 1765 } 1766 1767 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, 1768 struct device_attribute *attr, char *buf) 1769 { 1770 struct amdgpu_ras *con = 1771 container_of(attr, struct amdgpu_ras, features_attr); 1772 1773 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); 1774 } 1775 1776 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev, 1777 struct device_attribute *attr, char *buf) 1778 { 1779 struct amdgpu_ras *con = 1780 container_of(attr, struct amdgpu_ras, version_attr); 1781 return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version); 1782 } 1783 1784 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev, 1785 struct device_attribute *attr, char *buf) 1786 { 1787 struct amdgpu_ras *con = 1788 container_of(attr, struct amdgpu_ras, schema_attr); 1789 return sysfs_emit(buf, "schema: 0x%x\n", con->schema); 1790 } 1791 1792 static struct { 1793 enum ras_event_type type; 1794 const char *name; 1795 } dump_event[] = { 1796 {RAS_EVENT_TYPE_FATAL, "Fatal Error"}, 1797 {RAS_EVENT_TYPE_POISON_CREATION, "Poison Creation"}, 1798 {RAS_EVENT_TYPE_POISON_CONSUMPTION, "Poison Consumption"}, 1799 }; 1800 1801 static ssize_t amdgpu_ras_sysfs_event_state_show(struct device *dev, 1802 struct device_attribute *attr, char *buf) 1803 { 1804 struct amdgpu_ras *con = 1805 container_of(attr, struct amdgpu_ras, event_state_attr); 1806 struct ras_event_manager *event_mgr = con->event_mgr; 1807 struct ras_event_state *event_state; 1808 int i, size = 0; 1809 1810 if (!event_mgr) 1811 return -EINVAL; 1812 1813 size += sysfs_emit_at(buf, size, "current seqno: %llu\n", atomic64_read(&event_mgr->seqno)); 1814 for (i = 0; i < ARRAY_SIZE(dump_event); i++) { 1815 event_state = &event_mgr->event_state[dump_event[i].type]; 1816 size += sysfs_emit_at(buf, size, "%s: count:%llu, last_seqno:%llu\n", 1817 dump_event[i].name, 1818 atomic64_read(&event_state->count), 1819 event_state->last_seqno); 1820 } 1821 1822 return (ssize_t)size; 1823 } 1824 1825 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) 1826 { 1827 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1828 1829 if (adev->dev->kobj.sd) 1830 sysfs_remove_file_from_group(&adev->dev->kobj, 1831 &con->badpages_attr.attr, 1832 RAS_FS_NAME); 1833 } 1834 1835 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev) 1836 { 1837 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1838 struct attribute *attrs[] = { 1839 &con->features_attr.attr, 1840 &con->version_attr.attr, 1841 &con->schema_attr.attr, 1842 &con->event_state_attr.attr, 1843 NULL 1844 }; 1845 struct attribute_group group = { 1846 .name = RAS_FS_NAME, 1847 .attrs = attrs, 1848 }; 1849 1850 if (adev->dev->kobj.sd) 1851 sysfs_remove_group(&adev->dev->kobj, &group); 1852 1853 return 0; 1854 } 1855 1856 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 1857 struct ras_common_if *head) 1858 { 1859 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 1860 1861 if (amdgpu_aca_is_enabled(adev)) 1862 return 0; 1863 1864 if (!obj || obj->attr_inuse) 1865 return -EINVAL; 1866 1867 get_obj(obj); 1868 1869 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name), 1870 "%s_err_count", head->name); 1871 1872 obj->sysfs_attr = (struct device_attribute){ 1873 .attr = { 1874 .name = obj->fs_data.sysfs_name, 1875 .mode = S_IRUGO, 1876 }, 1877 .show = amdgpu_ras_sysfs_read, 1878 }; 1879 sysfs_attr_init(&obj->sysfs_attr.attr); 1880 1881 if (sysfs_add_file_to_group(&adev->dev->kobj, 1882 &obj->sysfs_attr.attr, 1883 RAS_FS_NAME)) { 1884 put_obj(obj); 1885 return -EINVAL; 1886 } 1887 1888 obj->attr_inuse = 1; 1889 1890 return 0; 1891 } 1892 1893 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 1894 struct ras_common_if *head) 1895 { 1896 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 1897 1898 if (amdgpu_aca_is_enabled(adev)) 1899 return 0; 1900 1901 if (!obj || !obj->attr_inuse) 1902 return -EINVAL; 1903 1904 if (adev->dev->kobj.sd) 1905 sysfs_remove_file_from_group(&adev->dev->kobj, 1906 &obj->sysfs_attr.attr, 1907 RAS_FS_NAME); 1908 obj->attr_inuse = 0; 1909 put_obj(obj); 1910 1911 return 0; 1912 } 1913 1914 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) 1915 { 1916 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1917 struct ras_manager *obj, *tmp; 1918 1919 list_for_each_entry_safe(obj, tmp, &con->head, node) { 1920 amdgpu_ras_sysfs_remove(adev, &obj->head); 1921 } 1922 1923 if (amdgpu_bad_page_threshold != 0) 1924 amdgpu_ras_sysfs_remove_bad_page_node(adev); 1925 1926 amdgpu_ras_sysfs_remove_dev_attr_node(adev); 1927 1928 return 0; 1929 } 1930 /* sysfs end */ 1931 1932 /** 1933 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors 1934 * 1935 * Normally when there is an uncorrectable error, the driver will reset 1936 * the GPU to recover. However, in the event of an unrecoverable error, 1937 * the driver provides an interface to reboot the system automatically 1938 * in that event. 1939 * 1940 * The following file in debugfs provides that interface: 1941 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot 1942 * 1943 * Usage: 1944 * 1945 * .. code-block:: bash 1946 * 1947 * echo true > .../ras/auto_reboot 1948 * 1949 */ 1950 /* debugfs begin */ 1951 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) 1952 { 1953 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1954 struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control; 1955 struct drm_minor *minor = adev_to_drm(adev)->primary; 1956 struct dentry *dir; 1957 1958 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); 1959 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, 1960 &amdgpu_ras_debugfs_ctrl_ops); 1961 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, 1962 &amdgpu_ras_debugfs_eeprom_ops); 1963 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, 1964 &con->bad_page_cnt_threshold); 1965 debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs); 1966 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); 1967 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); 1968 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, 1969 &amdgpu_ras_debugfs_eeprom_size_ops); 1970 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", 1971 S_IRUGO, dir, adev, 1972 &amdgpu_ras_debugfs_eeprom_table_ops); 1973 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); 1974 1975 /* 1976 * After one uncorrectable error happens, usually GPU recovery will 1977 * be scheduled. But due to the known problem in GPU recovery failing 1978 * to bring GPU back, below interface provides one direct way to 1979 * user to reboot system automatically in such case within 1980 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine 1981 * will never be called. 1982 */ 1983 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); 1984 1985 /* 1986 * User could set this not to clean up hardware's error count register 1987 * of RAS IPs during ras recovery. 1988 */ 1989 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, 1990 &con->disable_ras_err_cnt_harvest); 1991 return dir; 1992 } 1993 1994 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 1995 struct ras_fs_if *head, 1996 struct dentry *dir) 1997 { 1998 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); 1999 2000 if (!obj || !dir) 2001 return; 2002 2003 get_obj(obj); 2004 2005 memcpy(obj->fs_data.debugfs_name, 2006 head->debugfs_name, 2007 sizeof(obj->fs_data.debugfs_name)); 2008 2009 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, 2010 obj, &amdgpu_ras_debugfs_ops); 2011 } 2012 2013 static bool amdgpu_ras_aca_is_supported(struct amdgpu_device *adev) 2014 { 2015 bool ret; 2016 2017 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2018 case IP_VERSION(13, 0, 6): 2019 case IP_VERSION(13, 0, 12): 2020 case IP_VERSION(13, 0, 14): 2021 ret = true; 2022 break; 2023 default: 2024 ret = false; 2025 break; 2026 } 2027 2028 return ret; 2029 } 2030 2031 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) 2032 { 2033 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2034 struct dentry *dir; 2035 struct ras_manager *obj; 2036 struct ras_fs_if fs_info; 2037 2038 /* 2039 * it won't be called in resume path, no need to check 2040 * suspend and gpu reset status 2041 */ 2042 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) 2043 return; 2044 2045 dir = amdgpu_ras_debugfs_create_ctrl_node(adev); 2046 2047 list_for_each_entry(obj, &con->head, node) { 2048 if (amdgpu_ras_is_supported(adev, obj->head.block) && 2049 (obj->attr_inuse == 1)) { 2050 sprintf(fs_info.debugfs_name, "%s_err_inject", 2051 get_ras_block_str(&obj->head)); 2052 fs_info.head = obj->head; 2053 amdgpu_ras_debugfs_create(adev, &fs_info, dir); 2054 } 2055 } 2056 2057 if (amdgpu_ras_aca_is_supported(adev)) { 2058 if (amdgpu_aca_is_enabled(adev)) 2059 amdgpu_aca_smu_debugfs_init(adev, dir); 2060 else 2061 amdgpu_mca_smu_debugfs_init(adev, dir); 2062 } 2063 } 2064 2065 /* debugfs end */ 2066 2067 /* ras fs */ 2068 static const BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, 2069 amdgpu_ras_sysfs_badpages_read, NULL, 0); 2070 static DEVICE_ATTR(features, S_IRUGO, 2071 amdgpu_ras_sysfs_features_read, NULL); 2072 static DEVICE_ATTR(version, 0444, 2073 amdgpu_ras_sysfs_version_show, NULL); 2074 static DEVICE_ATTR(schema, 0444, 2075 amdgpu_ras_sysfs_schema_show, NULL); 2076 static DEVICE_ATTR(event_state, 0444, 2077 amdgpu_ras_sysfs_event_state_show, NULL); 2078 static int amdgpu_ras_fs_init(struct amdgpu_device *adev) 2079 { 2080 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2081 struct attribute_group group = { 2082 .name = RAS_FS_NAME, 2083 }; 2084 struct attribute *attrs[] = { 2085 &con->features_attr.attr, 2086 &con->version_attr.attr, 2087 &con->schema_attr.attr, 2088 &con->event_state_attr.attr, 2089 NULL 2090 }; 2091 const struct bin_attribute *bin_attrs[] = { 2092 NULL, 2093 NULL, 2094 }; 2095 int r; 2096 2097 group.attrs = attrs; 2098 2099 /* add features entry */ 2100 con->features_attr = dev_attr_features; 2101 sysfs_attr_init(attrs[0]); 2102 2103 /* add version entry */ 2104 con->version_attr = dev_attr_version; 2105 sysfs_attr_init(attrs[1]); 2106 2107 /* add schema entry */ 2108 con->schema_attr = dev_attr_schema; 2109 sysfs_attr_init(attrs[2]); 2110 2111 /* add event_state entry */ 2112 con->event_state_attr = dev_attr_event_state; 2113 sysfs_attr_init(attrs[3]); 2114 2115 if (amdgpu_bad_page_threshold != 0) { 2116 /* add bad_page_features entry */ 2117 con->badpages_attr = bin_attr_gpu_vram_bad_pages; 2118 sysfs_bin_attr_init(&con->badpages_attr); 2119 bin_attrs[0] = &con->badpages_attr; 2120 group.bin_attrs_new = bin_attrs; 2121 } 2122 2123 r = sysfs_create_group(&adev->dev->kobj, &group); 2124 if (r) 2125 dev_err(adev->dev, "Failed to create RAS sysfs group!"); 2126 2127 return 0; 2128 } 2129 2130 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) 2131 { 2132 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2133 struct ras_manager *con_obj, *ip_obj, *tmp; 2134 2135 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2136 list_for_each_entry_safe(con_obj, tmp, &con->head, node) { 2137 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); 2138 if (ip_obj) 2139 put_obj(ip_obj); 2140 } 2141 } 2142 2143 amdgpu_ras_sysfs_remove_all(adev); 2144 return 0; 2145 } 2146 /* ras fs end */ 2147 2148 /* ih begin */ 2149 2150 /* For the hardware that cannot enable bif ring for both ras_controller_irq 2151 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status 2152 * register to check whether the interrupt is triggered or not, and properly 2153 * ack the interrupt if it is there 2154 */ 2155 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) 2156 { 2157 /* Fatal error events are handled on host side */ 2158 if (amdgpu_sriov_vf(adev)) 2159 return; 2160 /** 2161 * If the current interrupt is caused by a non-fatal RAS error, skip 2162 * check for fatal error. For fatal errors, FED status of all devices 2163 * in XGMI hive gets set when the first device gets fatal error 2164 * interrupt. The error gets propagated to other devices as well, so 2165 * make sure to ack the interrupt regardless of FED status. 2166 */ 2167 if (!amdgpu_ras_get_fed_status(adev) && 2168 amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY)) 2169 return; 2170 2171 if (adev->nbio.ras && 2172 adev->nbio.ras->handle_ras_controller_intr_no_bifring) 2173 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); 2174 2175 if (adev->nbio.ras && 2176 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) 2177 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); 2178 } 2179 2180 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj, 2181 struct amdgpu_iv_entry *entry) 2182 { 2183 bool poison_stat = false; 2184 struct amdgpu_device *adev = obj->adev; 2185 struct amdgpu_ras_block_object *block_obj = 2186 amdgpu_ras_get_ras_block(adev, obj->head.block, 0); 2187 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2188 enum ras_event_type type = RAS_EVENT_TYPE_POISON_CONSUMPTION; 2189 u64 event_id; 2190 int ret; 2191 2192 if (!block_obj || !con) 2193 return; 2194 2195 ret = amdgpu_ras_mark_ras_event(adev, type); 2196 if (ret) 2197 return; 2198 2199 amdgpu_ras_set_err_poison(adev, block_obj->ras_comm.block); 2200 /* both query_poison_status and handle_poison_consumption are optional, 2201 * but at least one of them should be implemented if we need poison 2202 * consumption handler 2203 */ 2204 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) { 2205 poison_stat = block_obj->hw_ops->query_poison_status(adev); 2206 if (!poison_stat) { 2207 /* Not poison consumption interrupt, no need to handle it */ 2208 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n", 2209 block_obj->ras_comm.name); 2210 2211 return; 2212 } 2213 } 2214 2215 amdgpu_umc_poison_handler(adev, obj->head.block, 0); 2216 2217 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) 2218 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev); 2219 2220 /* gpu reset is fallback for failed and default cases. 2221 * For RMA case, amdgpu_umc_poison_handler will handle gpu reset. 2222 */ 2223 if (poison_stat && !amdgpu_ras_is_rma(adev)) { 2224 event_id = amdgpu_ras_acquire_event_id(adev, type); 2225 RAS_EVENT_LOG(adev, event_id, 2226 "GPU reset for %s RAS poison consumption is issued!\n", 2227 block_obj->ras_comm.name); 2228 amdgpu_ras_reset_gpu(adev); 2229 } 2230 2231 if (!poison_stat) 2232 amdgpu_gfx_poison_consumption_handler(adev, entry); 2233 } 2234 2235 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj, 2236 struct amdgpu_iv_entry *entry) 2237 { 2238 struct amdgpu_device *adev = obj->adev; 2239 enum ras_event_type type = RAS_EVENT_TYPE_POISON_CREATION; 2240 u64 event_id; 2241 int ret; 2242 2243 ret = amdgpu_ras_mark_ras_event(adev, type); 2244 if (ret) 2245 return; 2246 2247 event_id = amdgpu_ras_acquire_event_id(adev, type); 2248 RAS_EVENT_LOG(adev, event_id, "Poison is created\n"); 2249 2250 if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) { 2251 struct amdgpu_ras *con = amdgpu_ras_get_context(obj->adev); 2252 2253 atomic_inc(&con->page_retirement_req_cnt); 2254 atomic_inc(&con->poison_creation_count); 2255 2256 wake_up(&con->page_retirement_wq); 2257 } 2258 } 2259 2260 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, 2261 struct amdgpu_iv_entry *entry) 2262 { 2263 struct ras_ih_data *data = &obj->ih_data; 2264 struct ras_err_data err_data; 2265 int ret; 2266 2267 if (!data->cb) 2268 return; 2269 2270 ret = amdgpu_ras_error_data_init(&err_data); 2271 if (ret) 2272 return; 2273 2274 /* Let IP handle its data, maybe we need get the output 2275 * from the callback to update the error type/count, etc 2276 */ 2277 amdgpu_ras_set_fed(obj->adev, true); 2278 ret = data->cb(obj->adev, &err_data, entry); 2279 /* ue will trigger an interrupt, and in that case 2280 * we need do a reset to recovery the whole system. 2281 * But leave IP do that recovery, here we just dispatch 2282 * the error. 2283 */ 2284 if (ret == AMDGPU_RAS_SUCCESS) { 2285 /* these counts could be left as 0 if 2286 * some blocks do not count error number 2287 */ 2288 obj->err_data.ue_count += err_data.ue_count; 2289 obj->err_data.ce_count += err_data.ce_count; 2290 obj->err_data.de_count += err_data.de_count; 2291 } 2292 2293 amdgpu_ras_error_data_fini(&err_data); 2294 } 2295 2296 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) 2297 { 2298 struct ras_ih_data *data = &obj->ih_data; 2299 struct amdgpu_iv_entry entry; 2300 2301 while (data->rptr != data->wptr) { 2302 rmb(); 2303 memcpy(&entry, &data->ring[data->rptr], 2304 data->element_size); 2305 2306 wmb(); 2307 data->rptr = (data->aligned_element_size + 2308 data->rptr) % data->ring_size; 2309 2310 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) { 2311 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) 2312 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry); 2313 else 2314 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry); 2315 } else { 2316 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) 2317 amdgpu_ras_interrupt_umc_handler(obj, &entry); 2318 else 2319 dev_warn(obj->adev->dev, 2320 "No RAS interrupt handler for non-UMC block with poison disabled.\n"); 2321 } 2322 } 2323 } 2324 2325 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) 2326 { 2327 struct ras_ih_data *data = 2328 container_of(work, struct ras_ih_data, ih_work); 2329 struct ras_manager *obj = 2330 container_of(data, struct ras_manager, ih_data); 2331 2332 amdgpu_ras_interrupt_handler(obj); 2333 } 2334 2335 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 2336 struct ras_dispatch_if *info) 2337 { 2338 struct ras_manager *obj; 2339 struct ras_ih_data *data; 2340 2341 obj = amdgpu_ras_find_obj(adev, &info->head); 2342 if (!obj) 2343 return -EINVAL; 2344 2345 data = &obj->ih_data; 2346 2347 if (data->inuse == 0) 2348 return 0; 2349 2350 /* Might be overflow... */ 2351 memcpy(&data->ring[data->wptr], info->entry, 2352 data->element_size); 2353 2354 wmb(); 2355 data->wptr = (data->aligned_element_size + 2356 data->wptr) % data->ring_size; 2357 2358 schedule_work(&data->ih_work); 2359 2360 return 0; 2361 } 2362 2363 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 2364 struct ras_common_if *head) 2365 { 2366 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 2367 struct ras_ih_data *data; 2368 2369 if (!obj) 2370 return -EINVAL; 2371 2372 data = &obj->ih_data; 2373 if (data->inuse == 0) 2374 return 0; 2375 2376 cancel_work_sync(&data->ih_work); 2377 2378 kfree(data->ring); 2379 memset(data, 0, sizeof(*data)); 2380 put_obj(obj); 2381 2382 return 0; 2383 } 2384 2385 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 2386 struct ras_common_if *head) 2387 { 2388 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 2389 struct ras_ih_data *data; 2390 struct amdgpu_ras_block_object *ras_obj; 2391 2392 if (!obj) { 2393 /* in case we registe the IH before enable ras feature */ 2394 obj = amdgpu_ras_create_obj(adev, head); 2395 if (!obj) 2396 return -EINVAL; 2397 } else 2398 get_obj(obj); 2399 2400 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm); 2401 2402 data = &obj->ih_data; 2403 /* add the callback.etc */ 2404 *data = (struct ras_ih_data) { 2405 .inuse = 0, 2406 .cb = ras_obj->ras_cb, 2407 .element_size = sizeof(struct amdgpu_iv_entry), 2408 .rptr = 0, 2409 .wptr = 0, 2410 }; 2411 2412 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); 2413 2414 data->aligned_element_size = ALIGN(data->element_size, 8); 2415 /* the ring can store 64 iv entries. */ 2416 data->ring_size = 64 * data->aligned_element_size; 2417 data->ring = kmalloc(data->ring_size, GFP_KERNEL); 2418 if (!data->ring) { 2419 put_obj(obj); 2420 return -ENOMEM; 2421 } 2422 2423 /* IH is ready */ 2424 data->inuse = 1; 2425 2426 return 0; 2427 } 2428 2429 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) 2430 { 2431 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2432 struct ras_manager *obj, *tmp; 2433 2434 list_for_each_entry_safe(obj, tmp, &con->head, node) { 2435 amdgpu_ras_interrupt_remove_handler(adev, &obj->head); 2436 } 2437 2438 return 0; 2439 } 2440 /* ih end */ 2441 2442 /* traversal all IPs except NBIO to query error counter */ 2443 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev, enum ras_event_type type) 2444 { 2445 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2446 struct ras_manager *obj; 2447 2448 if (!adev->ras_enabled || !con) 2449 return; 2450 2451 list_for_each_entry(obj, &con->head, node) { 2452 struct ras_query_if info = { 2453 .head = obj->head, 2454 }; 2455 2456 /* 2457 * PCIE_BIF IP has one different isr by ras controller 2458 * interrupt, the specific ras counter query will be 2459 * done in that isr. So skip such block from common 2460 * sync flood interrupt isr calling. 2461 */ 2462 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) 2463 continue; 2464 2465 /* 2466 * this is a workaround for aldebaran, skip send msg to 2467 * smu to get ecc_info table due to smu handle get ecc 2468 * info table failed temporarily. 2469 * should be removed until smu fix handle ecc_info table. 2470 */ 2471 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) && 2472 (amdgpu_ip_version(adev, MP1_HWIP, 0) == 2473 IP_VERSION(13, 0, 2))) 2474 continue; 2475 2476 amdgpu_ras_query_error_status_with_event(adev, &info, type); 2477 2478 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != 2479 IP_VERSION(11, 0, 2) && 2480 amdgpu_ip_version(adev, MP0_HWIP, 0) != 2481 IP_VERSION(11, 0, 4) && 2482 amdgpu_ip_version(adev, MP0_HWIP, 0) != 2483 IP_VERSION(13, 0, 0)) { 2484 if (amdgpu_ras_reset_error_status(adev, info.head.block)) 2485 dev_warn(adev->dev, "Failed to reset error counter and error status"); 2486 } 2487 } 2488 } 2489 2490 /* Parse RdRspStatus and WrRspStatus */ 2491 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, 2492 struct ras_query_if *info) 2493 { 2494 struct amdgpu_ras_block_object *block_obj; 2495 /* 2496 * Only two block need to query read/write 2497 * RspStatus at current state 2498 */ 2499 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) && 2500 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB)) 2501 return; 2502 2503 block_obj = amdgpu_ras_get_ras_block(adev, 2504 info->head.block, 2505 info->head.sub_block_index); 2506 2507 if (!block_obj || !block_obj->hw_ops) { 2508 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 2509 get_ras_block_str(&info->head)); 2510 return; 2511 } 2512 2513 if (block_obj->hw_ops->query_ras_error_status) 2514 block_obj->hw_ops->query_ras_error_status(adev); 2515 2516 } 2517 2518 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) 2519 { 2520 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2521 struct ras_manager *obj; 2522 2523 if (!adev->ras_enabled || !con) 2524 return; 2525 2526 list_for_each_entry(obj, &con->head, node) { 2527 struct ras_query_if info = { 2528 .head = obj->head, 2529 }; 2530 2531 amdgpu_ras_error_status_query(adev, &info); 2532 } 2533 } 2534 2535 /* recovery begin */ 2536 2537 /* return 0 on success. 2538 * caller need free bps. 2539 */ 2540 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, 2541 struct ras_badpage **bps, unsigned int *count) 2542 { 2543 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2544 struct ras_err_handler_data *data; 2545 int i = 0; 2546 int ret = 0, status; 2547 2548 if (!con || !con->eh_data || !bps || !count) 2549 return -EINVAL; 2550 2551 mutex_lock(&con->recovery_lock); 2552 data = con->eh_data; 2553 if (!data || data->count == 0) { 2554 *bps = NULL; 2555 ret = -EINVAL; 2556 goto out; 2557 } 2558 2559 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); 2560 if (!*bps) { 2561 ret = -ENOMEM; 2562 goto out; 2563 } 2564 2565 for (; i < data->count; i++) { 2566 (*bps)[i] = (struct ras_badpage){ 2567 .bp = data->bps[i].retired_page, 2568 .size = AMDGPU_GPU_PAGE_SIZE, 2569 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, 2570 }; 2571 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, 2572 data->bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT); 2573 if (status == -EBUSY) 2574 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; 2575 else if (status == -ENOENT) 2576 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; 2577 } 2578 2579 *count = data->count; 2580 out: 2581 mutex_unlock(&con->recovery_lock); 2582 return ret; 2583 } 2584 2585 static void amdgpu_ras_set_fed_all(struct amdgpu_device *adev, 2586 struct amdgpu_hive_info *hive, bool status) 2587 { 2588 struct amdgpu_device *tmp_adev; 2589 2590 if (hive) { 2591 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 2592 amdgpu_ras_set_fed(tmp_adev, status); 2593 } else { 2594 amdgpu_ras_set_fed(adev, status); 2595 } 2596 } 2597 2598 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev) 2599 { 2600 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); 2601 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 2602 int hive_ras_recovery = 0; 2603 2604 if (hive) { 2605 hive_ras_recovery = atomic_read(&hive->ras_recovery); 2606 amdgpu_put_xgmi_hive(hive); 2607 } 2608 2609 if (ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery)) 2610 return true; 2611 2612 return false; 2613 } 2614 2615 static enum ras_event_type amdgpu_ras_get_fatal_error_event(struct amdgpu_device *adev) 2616 { 2617 if (amdgpu_ras_intr_triggered()) 2618 return RAS_EVENT_TYPE_FATAL; 2619 else 2620 return RAS_EVENT_TYPE_POISON_CONSUMPTION; 2621 } 2622 2623 static void amdgpu_ras_do_recovery(struct work_struct *work) 2624 { 2625 struct amdgpu_ras *ras = 2626 container_of(work, struct amdgpu_ras, recovery_work); 2627 struct amdgpu_device *remote_adev = NULL; 2628 struct amdgpu_device *adev = ras->adev; 2629 struct list_head device_list, *device_list_handle = NULL; 2630 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); 2631 enum ras_event_type type; 2632 2633 if (hive) { 2634 atomic_set(&hive->ras_recovery, 1); 2635 2636 /* If any device which is part of the hive received RAS fatal 2637 * error interrupt, set fatal error status on all. This 2638 * condition will need a recovery, and flag will be cleared 2639 * as part of recovery. 2640 */ 2641 list_for_each_entry(remote_adev, &hive->device_list, 2642 gmc.xgmi.head) 2643 if (amdgpu_ras_get_fed_status(remote_adev)) { 2644 amdgpu_ras_set_fed_all(adev, hive, true); 2645 break; 2646 } 2647 } 2648 if (!ras->disable_ras_err_cnt_harvest) { 2649 2650 /* Build list of devices to query RAS related errors */ 2651 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { 2652 device_list_handle = &hive->device_list; 2653 } else { 2654 INIT_LIST_HEAD(&device_list); 2655 list_add_tail(&adev->gmc.xgmi.head, &device_list); 2656 device_list_handle = &device_list; 2657 } 2658 2659 type = amdgpu_ras_get_fatal_error_event(adev); 2660 list_for_each_entry(remote_adev, 2661 device_list_handle, gmc.xgmi.head) { 2662 amdgpu_ras_query_err_status(remote_adev); 2663 amdgpu_ras_log_on_err_counter(remote_adev, type); 2664 } 2665 2666 } 2667 2668 if (amdgpu_device_should_recover_gpu(ras->adev)) { 2669 struct amdgpu_reset_context reset_context; 2670 memset(&reset_context, 0, sizeof(reset_context)); 2671 2672 reset_context.method = AMD_RESET_METHOD_NONE; 2673 reset_context.reset_req_dev = adev; 2674 reset_context.src = AMDGPU_RESET_SRC_RAS; 2675 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2676 2677 /* Perform full reset in fatal error mode */ 2678 if (!amdgpu_ras_is_poison_mode_supported(ras->adev)) 2679 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2680 else { 2681 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2682 2683 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) { 2684 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET; 2685 reset_context.method = AMD_RESET_METHOD_MODE2; 2686 } 2687 2688 /* Fatal error occurs in poison mode, mode1 reset is used to 2689 * recover gpu. 2690 */ 2691 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) { 2692 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET; 2693 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2694 2695 psp_fatal_error_recovery_quirk(&adev->psp); 2696 } 2697 } 2698 2699 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context); 2700 } 2701 atomic_set(&ras->in_recovery, 0); 2702 if (hive) { 2703 atomic_set(&hive->ras_recovery, 0); 2704 amdgpu_put_xgmi_hive(hive); 2705 } 2706 } 2707 2708 /* alloc/realloc bps array */ 2709 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, 2710 struct ras_err_handler_data *data, int pages) 2711 { 2712 unsigned int old_space = data->count + data->space_left; 2713 unsigned int new_space = old_space + pages; 2714 unsigned int align_space = ALIGN(new_space, 512); 2715 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); 2716 2717 if (!bps) { 2718 return -ENOMEM; 2719 } 2720 2721 if (data->bps) { 2722 memcpy(bps, data->bps, 2723 data->count * sizeof(*data->bps)); 2724 kfree(data->bps); 2725 } 2726 2727 data->bps = bps; 2728 data->space_left += align_space - old_space; 2729 return 0; 2730 } 2731 2732 static int amdgpu_ras_mca2pa_by_idx(struct amdgpu_device *adev, 2733 struct eeprom_table_record *bps, 2734 struct ras_err_data *err_data) 2735 { 2736 struct ta_ras_query_address_input addr_in; 2737 uint32_t socket = 0; 2738 int ret = 0; 2739 2740 if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) 2741 socket = adev->smuio.funcs->get_socket_id(adev); 2742 2743 /* reinit err_data */ 2744 err_data->err_addr_cnt = 0; 2745 err_data->err_addr_len = adev->umc.retire_unit; 2746 2747 memset(&addr_in, 0, sizeof(addr_in)); 2748 addr_in.ma.err_addr = bps->address; 2749 addr_in.ma.socket_id = socket; 2750 addr_in.ma.ch_inst = bps->mem_channel; 2751 /* tell RAS TA the node instance is not used */ 2752 addr_in.ma.node_inst = TA_RAS_INV_NODE; 2753 2754 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) 2755 ret = adev->umc.ras->convert_ras_err_addr(adev, err_data, 2756 &addr_in, NULL, false); 2757 2758 return ret; 2759 } 2760 2761 static int amdgpu_ras_mca2pa(struct amdgpu_device *adev, 2762 struct eeprom_table_record *bps, 2763 struct ras_err_data *err_data) 2764 { 2765 struct ta_ras_query_address_input addr_in; 2766 uint32_t die_id, socket = 0; 2767 2768 if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) 2769 socket = adev->smuio.funcs->get_socket_id(adev); 2770 2771 /* although die id is gotten from PA in nps1 mode, the id is 2772 * fitable for any nps mode 2773 */ 2774 if (adev->umc.ras && adev->umc.ras->get_die_id_from_pa) 2775 die_id = adev->umc.ras->get_die_id_from_pa(adev, bps->address, 2776 bps->retired_page << AMDGPU_GPU_PAGE_SHIFT); 2777 else 2778 return -EINVAL; 2779 2780 /* reinit err_data */ 2781 err_data->err_addr_cnt = 0; 2782 err_data->err_addr_len = adev->umc.retire_unit; 2783 2784 memset(&addr_in, 0, sizeof(addr_in)); 2785 addr_in.ma.err_addr = bps->address; 2786 addr_in.ma.ch_inst = bps->mem_channel; 2787 addr_in.ma.umc_inst = bps->mcumc_id; 2788 addr_in.ma.node_inst = die_id; 2789 addr_in.ma.socket_id = socket; 2790 2791 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) 2792 return adev->umc.ras->convert_ras_err_addr(adev, err_data, 2793 &addr_in, NULL, false); 2794 else 2795 return -EINVAL; 2796 } 2797 2798 /* it deal with vram only. */ 2799 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 2800 struct eeprom_table_record *bps, int pages, bool from_rom) 2801 { 2802 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2803 struct ras_err_handler_data *data; 2804 struct ras_err_data err_data; 2805 struct eeprom_table_record *err_rec; 2806 struct amdgpu_ras_eeprom_control *control = 2807 &adev->psp.ras_context.ras->eeprom_control; 2808 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 2809 int ret = 0; 2810 uint32_t i, j, loop_cnt = 1; 2811 bool find_pages_per_pa = false; 2812 2813 if (!con || !con->eh_data || !bps || pages <= 0) 2814 return 0; 2815 2816 if (from_rom) { 2817 err_data.err_addr = 2818 kcalloc(adev->umc.retire_unit, 2819 sizeof(struct eeprom_table_record), GFP_KERNEL); 2820 if (!err_data.err_addr) { 2821 dev_warn(adev->dev, "Failed to alloc UMC error address record in mca2pa conversion!\n"); 2822 ret = -ENOMEM; 2823 goto out; 2824 } 2825 2826 err_rec = err_data.err_addr; 2827 loop_cnt = adev->umc.retire_unit; 2828 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2829 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2830 } 2831 2832 mutex_lock(&con->recovery_lock); 2833 data = con->eh_data; 2834 if (!data) { 2835 /* Returning 0 as the absence of eh_data is acceptable */ 2836 goto free; 2837 } 2838 2839 for (i = 0; i < pages; i++) { 2840 if (from_rom && 2841 control->rec_type == AMDGPU_RAS_EEPROM_REC_MCA) { 2842 if (!find_pages_per_pa) { 2843 if (amdgpu_ras_mca2pa_by_idx(adev, &bps[i], &err_data)) { 2844 if (!i && nps == AMDGPU_NPS1_PARTITION_MODE) { 2845 /* may use old RAS TA, use PA to find pages in 2846 * one row 2847 */ 2848 if (amdgpu_umc_pages_in_a_row(adev, &err_data, 2849 bps[i].retired_page << 2850 AMDGPU_GPU_PAGE_SHIFT)) { 2851 ret = -EINVAL; 2852 goto free; 2853 } else { 2854 find_pages_per_pa = true; 2855 } 2856 } else { 2857 /* unsupported cases */ 2858 ret = -EOPNOTSUPP; 2859 goto free; 2860 } 2861 } 2862 } else { 2863 if (amdgpu_umc_pages_in_a_row(adev, &err_data, 2864 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) { 2865 ret = -EINVAL; 2866 goto free; 2867 } 2868 } 2869 } else { 2870 if (from_rom && !find_pages_per_pa) { 2871 if (bps[i].retired_page & UMC_CHANNEL_IDX_V2) { 2872 /* bad page in any NPS mode in eeprom */ 2873 if (amdgpu_ras_mca2pa_by_idx(adev, &bps[i], &err_data)) { 2874 ret = -EINVAL; 2875 goto free; 2876 } 2877 } else { 2878 /* legacy bad page in eeprom, generated only in 2879 * NPS1 mode 2880 */ 2881 if (amdgpu_ras_mca2pa(adev, &bps[i], &err_data)) { 2882 /* old RAS TA or ASICs which don't support to 2883 * convert addrss via mca address 2884 */ 2885 if (!i && nps == AMDGPU_NPS1_PARTITION_MODE) { 2886 find_pages_per_pa = true; 2887 err_rec = &bps[i]; 2888 loop_cnt = 1; 2889 } else { 2890 /* non-nps1 mode, old RAS TA 2891 * can't support it 2892 */ 2893 ret = -EOPNOTSUPP; 2894 goto free; 2895 } 2896 } 2897 } 2898 2899 if (!find_pages_per_pa) 2900 i += (adev->umc.retire_unit - 1); 2901 } else { 2902 err_rec = &bps[i]; 2903 } 2904 } 2905 2906 for (j = 0; j < loop_cnt; j++) { 2907 if (amdgpu_ras_check_bad_page_unlock(con, 2908 err_rec[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) 2909 continue; 2910 2911 if (!data->space_left && 2912 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { 2913 ret = -ENOMEM; 2914 goto free; 2915 } 2916 2917 amdgpu_ras_reserve_page(adev, err_rec[j].retired_page); 2918 2919 memcpy(&data->bps[data->count], &(err_rec[j]), 2920 sizeof(struct eeprom_table_record)); 2921 data->count++; 2922 data->space_left--; 2923 } 2924 } 2925 2926 free: 2927 if (from_rom) 2928 kfree(err_data.err_addr); 2929 out: 2930 mutex_unlock(&con->recovery_lock); 2931 2932 return ret; 2933 } 2934 2935 /* 2936 * write error record array to eeprom, the function should be 2937 * protected by recovery_lock 2938 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL 2939 */ 2940 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 2941 unsigned long *new_cnt) 2942 { 2943 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2944 struct ras_err_handler_data *data; 2945 struct amdgpu_ras_eeprom_control *control; 2946 int save_count, unit_num, bad_page_num, i; 2947 2948 if (!con || !con->eh_data) { 2949 if (new_cnt) 2950 *new_cnt = 0; 2951 2952 return 0; 2953 } 2954 2955 mutex_lock(&con->recovery_lock); 2956 control = &con->eeprom_control; 2957 data = con->eh_data; 2958 bad_page_num = control->ras_num_bad_pages; 2959 save_count = data->count - bad_page_num; 2960 mutex_unlock(&con->recovery_lock); 2961 2962 unit_num = save_count / adev->umc.retire_unit; 2963 if (new_cnt) 2964 *new_cnt = unit_num; 2965 2966 /* only new entries are saved */ 2967 if (save_count > 0) { 2968 if (control->rec_type == AMDGPU_RAS_EEPROM_REC_PA) { 2969 if (amdgpu_ras_eeprom_append(control, 2970 &data->bps[control->ras_num_recs], 2971 save_count)) { 2972 dev_err(adev->dev, "Failed to save EEPROM table data!"); 2973 return -EIO; 2974 } 2975 } else { 2976 for (i = 0; i < unit_num; i++) { 2977 if (amdgpu_ras_eeprom_append(control, 2978 &data->bps[bad_page_num + i * adev->umc.retire_unit], 2979 1)) { 2980 dev_err(adev->dev, "Failed to save EEPROM table data!"); 2981 return -EIO; 2982 } 2983 } 2984 } 2985 2986 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); 2987 } 2988 2989 return 0; 2990 } 2991 2992 /* 2993 * read error record array in eeprom and reserve enough space for 2994 * storing new bad pages 2995 */ 2996 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) 2997 { 2998 struct amdgpu_ras_eeprom_control *control = 2999 &adev->psp.ras_context.ras->eeprom_control; 3000 struct eeprom_table_record *bps; 3001 int ret; 3002 3003 /* no bad page record, skip eeprom access */ 3004 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) 3005 return 0; 3006 3007 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); 3008 if (!bps) 3009 return -ENOMEM; 3010 3011 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); 3012 if (ret) { 3013 dev_err(adev->dev, "Failed to load EEPROM table records!"); 3014 } else { 3015 if (control->ras_num_recs > 1 && 3016 adev->umc.ras && adev->umc.ras->convert_ras_err_addr) { 3017 if ((bps[0].address == bps[1].address) && 3018 (bps[0].mem_channel == bps[1].mem_channel)) 3019 control->rec_type = AMDGPU_RAS_EEPROM_REC_PA; 3020 else 3021 control->rec_type = AMDGPU_RAS_EEPROM_REC_MCA; 3022 } 3023 3024 ret = amdgpu_ras_eeprom_check(control); 3025 if (ret) 3026 goto out; 3027 3028 /* HW not usable */ 3029 if (amdgpu_ras_is_rma(adev)) { 3030 ret = -EHWPOISON; 3031 goto out; 3032 } 3033 3034 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs, true); 3035 } 3036 3037 out: 3038 kfree(bps); 3039 return ret; 3040 } 3041 3042 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, 3043 uint64_t addr) 3044 { 3045 struct ras_err_handler_data *data = con->eh_data; 3046 int i; 3047 3048 addr >>= AMDGPU_GPU_PAGE_SHIFT; 3049 for (i = 0; i < data->count; i++) 3050 if (addr == data->bps[i].retired_page) 3051 return true; 3052 3053 return false; 3054 } 3055 3056 /* 3057 * check if an address belongs to bad page 3058 * 3059 * Note: this check is only for umc block 3060 */ 3061 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, 3062 uint64_t addr) 3063 { 3064 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3065 bool ret = false; 3066 3067 if (!con || !con->eh_data) 3068 return ret; 3069 3070 mutex_lock(&con->recovery_lock); 3071 ret = amdgpu_ras_check_bad_page_unlock(con, addr); 3072 mutex_unlock(&con->recovery_lock); 3073 return ret; 3074 } 3075 3076 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, 3077 uint32_t max_count) 3078 { 3079 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3080 3081 /* 3082 * Justification of value bad_page_cnt_threshold in ras structure 3083 * 3084 * Generally, 0 <= amdgpu_bad_page_threshold <= max record length 3085 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two 3086 * scenarios accordingly. 3087 * 3088 * Bad page retirement enablement: 3089 * - If amdgpu_bad_page_threshold = -2, 3090 * bad_page_cnt_threshold = typical value by formula. 3091 * 3092 * - When the value from user is 0 < amdgpu_bad_page_threshold < 3093 * max record length in eeprom, use it directly. 3094 * 3095 * Bad page retirement disablement: 3096 * - If amdgpu_bad_page_threshold = 0, bad page retirement 3097 * functionality is disabled, and bad_page_cnt_threshold will 3098 * take no effect. 3099 */ 3100 3101 if (amdgpu_bad_page_threshold < 0) { 3102 u64 val = adev->gmc.mc_vram_size; 3103 3104 do_div(val, RAS_BAD_PAGE_COVER); 3105 con->bad_page_cnt_threshold = min(lower_32_bits(val), 3106 max_count); 3107 } else { 3108 con->bad_page_cnt_threshold = min_t(int, max_count, 3109 amdgpu_bad_page_threshold); 3110 } 3111 } 3112 3113 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, 3114 enum amdgpu_ras_block block, uint16_t pasid, 3115 pasid_notify pasid_fn, void *data, uint32_t reset) 3116 { 3117 int ret = 0; 3118 struct ras_poison_msg poison_msg; 3119 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3120 3121 memset(&poison_msg, 0, sizeof(poison_msg)); 3122 poison_msg.block = block; 3123 poison_msg.pasid = pasid; 3124 poison_msg.reset = reset; 3125 poison_msg.pasid_fn = pasid_fn; 3126 poison_msg.data = data; 3127 3128 ret = kfifo_put(&con->poison_fifo, poison_msg); 3129 if (!ret) { 3130 dev_err(adev->dev, "Poison message fifo is full!\n"); 3131 return -ENOSPC; 3132 } 3133 3134 return 0; 3135 } 3136 3137 static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev, 3138 struct ras_poison_msg *poison_msg) 3139 { 3140 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3141 3142 return kfifo_get(&con->poison_fifo, poison_msg); 3143 } 3144 3145 static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log) 3146 { 3147 mutex_init(&ecc_log->lock); 3148 3149 INIT_RADIX_TREE(&ecc_log->de_page_tree, GFP_KERNEL); 3150 ecc_log->de_queried_count = 0; 3151 ecc_log->prev_de_queried_count = 0; 3152 } 3153 3154 static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log) 3155 { 3156 struct radix_tree_iter iter; 3157 void __rcu **slot; 3158 struct ras_ecc_err *ecc_err; 3159 3160 mutex_lock(&ecc_log->lock); 3161 radix_tree_for_each_slot(slot, &ecc_log->de_page_tree, &iter, 0) { 3162 ecc_err = radix_tree_deref_slot(slot); 3163 kfree(ecc_err->err_pages.pfn); 3164 kfree(ecc_err); 3165 radix_tree_iter_delete(&ecc_log->de_page_tree, &iter, slot); 3166 } 3167 mutex_unlock(&ecc_log->lock); 3168 3169 mutex_destroy(&ecc_log->lock); 3170 ecc_log->de_queried_count = 0; 3171 ecc_log->prev_de_queried_count = 0; 3172 } 3173 3174 static bool amdgpu_ras_schedule_retirement_dwork(struct amdgpu_ras *con, 3175 uint32_t delayed_ms) 3176 { 3177 int ret; 3178 3179 mutex_lock(&con->umc_ecc_log.lock); 3180 ret = radix_tree_tagged(&con->umc_ecc_log.de_page_tree, 3181 UMC_ECC_NEW_DETECTED_TAG); 3182 mutex_unlock(&con->umc_ecc_log.lock); 3183 3184 if (ret) 3185 schedule_delayed_work(&con->page_retirement_dwork, 3186 msecs_to_jiffies(delayed_ms)); 3187 3188 return ret ? true : false; 3189 } 3190 3191 static void amdgpu_ras_do_page_retirement(struct work_struct *work) 3192 { 3193 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, 3194 page_retirement_dwork.work); 3195 struct amdgpu_device *adev = con->adev; 3196 struct ras_err_data err_data; 3197 unsigned long err_cnt; 3198 3199 /* If gpu reset is ongoing, delay retiring the bad pages */ 3200 if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) { 3201 amdgpu_ras_schedule_retirement_dwork(con, 3202 AMDGPU_RAS_RETIRE_PAGE_INTERVAL * 3); 3203 return; 3204 } 3205 3206 amdgpu_ras_error_data_init(&err_data); 3207 3208 amdgpu_umc_handle_bad_pages(adev, &err_data); 3209 err_cnt = err_data.err_addr_cnt; 3210 3211 amdgpu_ras_error_data_fini(&err_data); 3212 3213 if (err_cnt && amdgpu_ras_is_rma(adev)) 3214 amdgpu_ras_reset_gpu(adev); 3215 3216 amdgpu_ras_schedule_retirement_dwork(con, 3217 AMDGPU_RAS_RETIRE_PAGE_INTERVAL); 3218 } 3219 3220 static int amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev, 3221 uint32_t poison_creation_count) 3222 { 3223 int ret = 0; 3224 struct ras_ecc_log_info *ecc_log; 3225 struct ras_query_if info; 3226 uint32_t timeout = 0; 3227 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3228 uint64_t de_queried_count; 3229 uint32_t new_detect_count, total_detect_count; 3230 uint32_t need_query_count = poison_creation_count; 3231 bool query_data_timeout = false; 3232 enum ras_event_type type = RAS_EVENT_TYPE_POISON_CREATION; 3233 3234 memset(&info, 0, sizeof(info)); 3235 info.head.block = AMDGPU_RAS_BLOCK__UMC; 3236 3237 ecc_log = &ras->umc_ecc_log; 3238 total_detect_count = 0; 3239 do { 3240 ret = amdgpu_ras_query_error_status_with_event(adev, &info, type); 3241 if (ret) 3242 return ret; 3243 3244 de_queried_count = ecc_log->de_queried_count; 3245 if (de_queried_count > ecc_log->prev_de_queried_count) { 3246 new_detect_count = de_queried_count - ecc_log->prev_de_queried_count; 3247 ecc_log->prev_de_queried_count = de_queried_count; 3248 timeout = 0; 3249 } else { 3250 new_detect_count = 0; 3251 } 3252 3253 if (new_detect_count) { 3254 total_detect_count += new_detect_count; 3255 } else { 3256 if (!timeout && need_query_count) 3257 timeout = MAX_UMC_POISON_POLLING_TIME_ASYNC; 3258 3259 if (timeout) { 3260 if (!--timeout) { 3261 query_data_timeout = true; 3262 break; 3263 } 3264 msleep(1); 3265 } 3266 } 3267 } while (total_detect_count < need_query_count); 3268 3269 if (query_data_timeout) { 3270 dev_warn(adev->dev, "Can't find deferred error! count: %u\n", 3271 (need_query_count - total_detect_count)); 3272 return -ENOENT; 3273 } 3274 3275 if (total_detect_count) 3276 schedule_delayed_work(&ras->page_retirement_dwork, 0); 3277 3278 return 0; 3279 } 3280 3281 static void amdgpu_ras_clear_poison_fifo(struct amdgpu_device *adev) 3282 { 3283 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3284 struct ras_poison_msg msg; 3285 int ret; 3286 3287 do { 3288 ret = kfifo_get(&con->poison_fifo, &msg); 3289 } while (ret); 3290 } 3291 3292 static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev, 3293 uint32_t msg_count, uint32_t *gpu_reset) 3294 { 3295 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3296 uint32_t reset_flags = 0, reset = 0; 3297 struct ras_poison_msg msg; 3298 int ret, i; 3299 3300 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 3301 3302 for (i = 0; i < msg_count; i++) { 3303 ret = amdgpu_ras_get_poison_req(adev, &msg); 3304 if (!ret) 3305 continue; 3306 3307 if (msg.pasid_fn) 3308 msg.pasid_fn(adev, msg.pasid, msg.data); 3309 3310 reset_flags |= msg.reset; 3311 } 3312 3313 /* for RMA, amdgpu_ras_poison_creation_handler will trigger gpu reset */ 3314 if (reset_flags && !amdgpu_ras_is_rma(adev)) { 3315 if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) 3316 reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; 3317 else if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) 3318 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 3319 else 3320 reset = reset_flags; 3321 3322 flush_delayed_work(&con->page_retirement_dwork); 3323 3324 con->gpu_reset_flags |= reset; 3325 amdgpu_ras_reset_gpu(adev); 3326 3327 *gpu_reset = reset; 3328 3329 /* Wait for gpu recovery to complete */ 3330 flush_work(&con->recovery_work); 3331 } 3332 3333 return 0; 3334 } 3335 3336 static int amdgpu_ras_page_retirement_thread(void *param) 3337 { 3338 struct amdgpu_device *adev = (struct amdgpu_device *)param; 3339 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3340 uint32_t poison_creation_count, msg_count; 3341 uint32_t gpu_reset; 3342 int ret; 3343 3344 while (!kthread_should_stop()) { 3345 3346 wait_event_interruptible(con->page_retirement_wq, 3347 kthread_should_stop() || 3348 atomic_read(&con->page_retirement_req_cnt)); 3349 3350 if (kthread_should_stop()) 3351 break; 3352 3353 gpu_reset = 0; 3354 3355 do { 3356 poison_creation_count = atomic_read(&con->poison_creation_count); 3357 ret = amdgpu_ras_poison_creation_handler(adev, poison_creation_count); 3358 if (ret == -EIO) 3359 break; 3360 3361 if (poison_creation_count) { 3362 atomic_sub(poison_creation_count, &con->poison_creation_count); 3363 atomic_sub(poison_creation_count, &con->page_retirement_req_cnt); 3364 } 3365 } while (atomic_read(&con->poison_creation_count)); 3366 3367 if (ret != -EIO) { 3368 msg_count = kfifo_len(&con->poison_fifo); 3369 if (msg_count) { 3370 ret = amdgpu_ras_poison_consumption_handler(adev, 3371 msg_count, &gpu_reset); 3372 if ((ret != -EIO) && 3373 (gpu_reset != AMDGPU_RAS_GPU_RESET_MODE1_RESET)) 3374 atomic_sub(msg_count, &con->page_retirement_req_cnt); 3375 } 3376 } 3377 3378 if ((ret == -EIO) || (gpu_reset == AMDGPU_RAS_GPU_RESET_MODE1_RESET)) { 3379 /* gpu mode-1 reset is ongoing or just completed ras mode-1 reset */ 3380 /* Clear poison creation request */ 3381 atomic_set(&con->poison_creation_count, 0); 3382 3383 /* Clear poison fifo */ 3384 amdgpu_ras_clear_poison_fifo(adev); 3385 3386 /* Clear all poison requests */ 3387 atomic_set(&con->page_retirement_req_cnt, 0); 3388 3389 if (ret == -EIO) { 3390 /* Wait for mode-1 reset to complete */ 3391 down_read(&adev->reset_domain->sem); 3392 up_read(&adev->reset_domain->sem); 3393 } 3394 3395 /* Wake up work to save bad pages to eeprom */ 3396 schedule_delayed_work(&con->page_retirement_dwork, 0); 3397 } else if (gpu_reset) { 3398 /* gpu just completed mode-2 reset or other reset */ 3399 /* Clear poison consumption messages cached in fifo */ 3400 msg_count = kfifo_len(&con->poison_fifo); 3401 if (msg_count) { 3402 amdgpu_ras_clear_poison_fifo(adev); 3403 atomic_sub(msg_count, &con->page_retirement_req_cnt); 3404 } 3405 3406 /* Wake up work to save bad pages to eeprom */ 3407 schedule_delayed_work(&con->page_retirement_dwork, 0); 3408 } 3409 } 3410 3411 return 0; 3412 } 3413 3414 int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev) 3415 { 3416 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3417 struct amdgpu_ras_eeprom_control *control; 3418 int ret; 3419 3420 if (!con || amdgpu_sriov_vf(adev)) 3421 return 0; 3422 3423 control = &con->eeprom_control; 3424 ret = amdgpu_ras_eeprom_init(control); 3425 if (ret) 3426 return ret; 3427 3428 if (!adev->umc.ras || !adev->umc.ras->convert_ras_err_addr) 3429 control->rec_type = AMDGPU_RAS_EEPROM_REC_PA; 3430 3431 /* default status is MCA storage */ 3432 if (control->ras_num_recs <= 1 && 3433 adev->umc.ras && adev->umc.ras->convert_ras_err_addr) 3434 control->rec_type = AMDGPU_RAS_EEPROM_REC_MCA; 3435 3436 if (control->ras_num_recs) { 3437 ret = amdgpu_ras_load_bad_pages(adev); 3438 if (ret) 3439 return ret; 3440 3441 amdgpu_dpm_send_hbm_bad_pages_num( 3442 adev, control->ras_num_bad_pages); 3443 3444 if (con->update_channel_flag == true) { 3445 amdgpu_dpm_send_hbm_bad_channel_flag( 3446 adev, control->bad_channel_bitmap); 3447 con->update_channel_flag = false; 3448 } 3449 } 3450 3451 return ret; 3452 } 3453 3454 int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) 3455 { 3456 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3457 struct ras_err_handler_data **data; 3458 u32 max_eeprom_records_count = 0; 3459 int ret; 3460 3461 if (!con || amdgpu_sriov_vf(adev)) 3462 return 0; 3463 3464 /* Allow access to RAS EEPROM via debugfs, when the ASIC 3465 * supports RAS and debugfs is enabled, but when 3466 * adev->ras_enabled is unset, i.e. when "ras_enable" 3467 * module parameter is set to 0. 3468 */ 3469 con->adev = adev; 3470 3471 if (!adev->ras_enabled) 3472 return 0; 3473 3474 data = &con->eh_data; 3475 *data = kzalloc(sizeof(**data), GFP_KERNEL); 3476 if (!*data) { 3477 ret = -ENOMEM; 3478 goto out; 3479 } 3480 3481 mutex_init(&con->recovery_lock); 3482 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); 3483 atomic_set(&con->in_recovery, 0); 3484 con->eeprom_control.bad_channel_bitmap = 0; 3485 3486 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); 3487 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); 3488 3489 if (init_bp_info) { 3490 ret = amdgpu_ras_init_badpage_info(adev); 3491 if (ret) 3492 goto free; 3493 } 3494 3495 mutex_init(&con->page_rsv_lock); 3496 INIT_KFIFO(con->poison_fifo); 3497 mutex_init(&con->page_retirement_lock); 3498 init_waitqueue_head(&con->page_retirement_wq); 3499 atomic_set(&con->page_retirement_req_cnt, 0); 3500 atomic_set(&con->poison_creation_count, 0); 3501 con->page_retirement_thread = 3502 kthread_run(amdgpu_ras_page_retirement_thread, adev, "umc_page_retirement"); 3503 if (IS_ERR(con->page_retirement_thread)) { 3504 con->page_retirement_thread = NULL; 3505 dev_warn(adev->dev, "Failed to create umc_page_retirement thread!!!\n"); 3506 } 3507 3508 INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); 3509 amdgpu_ras_ecc_log_init(&con->umc_ecc_log); 3510 #ifdef CONFIG_X86_MCE_AMD 3511 if ((adev->asic_type == CHIP_ALDEBARAN) && 3512 (adev->gmc.xgmi.connected_to_cpu)) 3513 amdgpu_register_bad_pages_mca_notifier(adev); 3514 #endif 3515 return 0; 3516 3517 free: 3518 kfree((*data)->bps); 3519 kfree(*data); 3520 con->eh_data = NULL; 3521 out: 3522 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); 3523 3524 /* 3525 * Except error threshold exceeding case, other failure cases in this 3526 * function would not fail amdgpu driver init. 3527 */ 3528 if (!amdgpu_ras_is_rma(adev)) 3529 ret = 0; 3530 else 3531 ret = -EINVAL; 3532 3533 return ret; 3534 } 3535 3536 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) 3537 { 3538 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3539 struct ras_err_handler_data *data = con->eh_data; 3540 int max_flush_timeout = MAX_FLUSH_RETIRE_DWORK_TIMES; 3541 bool ret; 3542 3543 /* recovery_init failed to init it, fini is useless */ 3544 if (!data) 3545 return 0; 3546 3547 /* Save all cached bad pages to eeprom */ 3548 do { 3549 flush_delayed_work(&con->page_retirement_dwork); 3550 ret = amdgpu_ras_schedule_retirement_dwork(con, 0); 3551 } while (ret && max_flush_timeout--); 3552 3553 if (con->page_retirement_thread) 3554 kthread_stop(con->page_retirement_thread); 3555 3556 atomic_set(&con->page_retirement_req_cnt, 0); 3557 atomic_set(&con->poison_creation_count, 0); 3558 3559 mutex_destroy(&con->page_rsv_lock); 3560 3561 cancel_work_sync(&con->recovery_work); 3562 3563 cancel_delayed_work_sync(&con->page_retirement_dwork); 3564 3565 amdgpu_ras_ecc_log_fini(&con->umc_ecc_log); 3566 3567 mutex_lock(&con->recovery_lock); 3568 con->eh_data = NULL; 3569 kfree(data->bps); 3570 kfree(data); 3571 mutex_unlock(&con->recovery_lock); 3572 3573 return 0; 3574 } 3575 /* recovery end */ 3576 3577 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) 3578 { 3579 if (amdgpu_sriov_vf(adev)) { 3580 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 3581 case IP_VERSION(13, 0, 2): 3582 case IP_VERSION(13, 0, 6): 3583 case IP_VERSION(13, 0, 12): 3584 case IP_VERSION(13, 0, 14): 3585 return true; 3586 default: 3587 return false; 3588 } 3589 } 3590 3591 if (adev->asic_type == CHIP_IP_DISCOVERY) { 3592 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 3593 case IP_VERSION(13, 0, 0): 3594 case IP_VERSION(13, 0, 6): 3595 case IP_VERSION(13, 0, 10): 3596 case IP_VERSION(13, 0, 12): 3597 case IP_VERSION(13, 0, 14): 3598 case IP_VERSION(14, 0, 3): 3599 return true; 3600 default: 3601 return false; 3602 } 3603 } 3604 3605 return adev->asic_type == CHIP_VEGA10 || 3606 adev->asic_type == CHIP_VEGA20 || 3607 adev->asic_type == CHIP_ARCTURUS || 3608 adev->asic_type == CHIP_ALDEBARAN || 3609 adev->asic_type == CHIP_SIENNA_CICHLID; 3610 } 3611 3612 /* 3613 * this is workaround for vega20 workstation sku, 3614 * force enable gfx ras, ignore vbios gfx ras flag 3615 * due to GC EDC can not write 3616 */ 3617 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) 3618 { 3619 struct atom_context *ctx = adev->mode_info.atom_context; 3620 3621 if (!ctx) 3622 return; 3623 3624 if (strnstr(ctx->vbios_pn, "D16406", 3625 sizeof(ctx->vbios_pn)) || 3626 strnstr(ctx->vbios_pn, "D36002", 3627 sizeof(ctx->vbios_pn))) 3628 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); 3629 } 3630 3631 /* Query ras capablity via atomfirmware interface */ 3632 static void amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev) 3633 { 3634 /* mem_ecc cap */ 3635 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { 3636 dev_info(adev->dev, "MEM ECC is active.\n"); 3637 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | 3638 1 << AMDGPU_RAS_BLOCK__DF); 3639 } else { 3640 dev_info(adev->dev, "MEM ECC is not presented.\n"); 3641 } 3642 3643 /* sram_ecc cap */ 3644 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { 3645 dev_info(adev->dev, "SRAM ECC is active.\n"); 3646 if (!amdgpu_sriov_vf(adev)) 3647 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | 3648 1 << AMDGPU_RAS_BLOCK__DF); 3649 else 3650 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | 3651 1 << AMDGPU_RAS_BLOCK__SDMA | 3652 1 << AMDGPU_RAS_BLOCK__GFX); 3653 3654 /* 3655 * VCN/JPEG RAS can be supported on both bare metal and 3656 * SRIOV environment 3657 */ 3658 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) || 3659 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) || 3660 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3)) 3661 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | 3662 1 << AMDGPU_RAS_BLOCK__JPEG); 3663 else 3664 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | 3665 1 << AMDGPU_RAS_BLOCK__JPEG); 3666 3667 /* 3668 * XGMI RAS is not supported if xgmi num physical nodes 3669 * is zero 3670 */ 3671 if (!adev->gmc.xgmi.num_physical_nodes) 3672 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); 3673 } else { 3674 dev_info(adev->dev, "SRAM ECC is not presented.\n"); 3675 } 3676 } 3677 3678 /* Query poison mode from umc/df IP callbacks */ 3679 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) 3680 { 3681 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3682 bool df_poison, umc_poison; 3683 3684 /* poison setting is useless on SRIOV guest */ 3685 if (amdgpu_sriov_vf(adev) || !con) 3686 return; 3687 3688 /* Init poison supported flag, the default value is false */ 3689 if (adev->gmc.xgmi.connected_to_cpu || 3690 adev->gmc.is_app_apu) { 3691 /* enabled by default when GPU is connected to CPU */ 3692 con->poison_supported = true; 3693 } else if (adev->df.funcs && 3694 adev->df.funcs->query_ras_poison_mode && 3695 adev->umc.ras && 3696 adev->umc.ras->query_ras_poison_mode) { 3697 df_poison = 3698 adev->df.funcs->query_ras_poison_mode(adev); 3699 umc_poison = 3700 adev->umc.ras->query_ras_poison_mode(adev); 3701 3702 /* Only poison is set in both DF and UMC, we can support it */ 3703 if (df_poison && umc_poison) 3704 con->poison_supported = true; 3705 else if (df_poison != umc_poison) 3706 dev_warn(adev->dev, 3707 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", 3708 df_poison, umc_poison); 3709 } 3710 } 3711 3712 /* 3713 * check hardware's ras ability which will be saved in hw_supported. 3714 * if hardware does not support ras, we can skip some ras initializtion and 3715 * forbid some ras operations from IP. 3716 * if software itself, say boot parameter, limit the ras ability. We still 3717 * need allow IP do some limited operations, like disable. In such case, 3718 * we have to initialize ras as normal. but need check if operation is 3719 * allowed or not in each function. 3720 */ 3721 static void amdgpu_ras_check_supported(struct amdgpu_device *adev) 3722 { 3723 adev->ras_hw_enabled = adev->ras_enabled = 0; 3724 3725 if (!amdgpu_ras_asic_supported(adev)) 3726 return; 3727 3728 if (amdgpu_sriov_vf(adev)) { 3729 if (amdgpu_virt_get_ras_capability(adev)) 3730 goto init_ras_enabled_flag; 3731 } 3732 3733 /* query ras capability from psp */ 3734 if (amdgpu_psp_get_ras_capability(&adev->psp)) 3735 goto init_ras_enabled_flag; 3736 3737 /* query ras capablity from bios */ 3738 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 3739 amdgpu_ras_query_ras_capablity_from_vbios(adev); 3740 } else { 3741 /* driver only manages a few IP blocks RAS feature 3742 * when GPU is connected cpu through XGMI */ 3743 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | 3744 1 << AMDGPU_RAS_BLOCK__SDMA | 3745 1 << AMDGPU_RAS_BLOCK__MMHUB); 3746 } 3747 3748 /* apply asic specific settings (vega20 only for now) */ 3749 amdgpu_ras_get_quirks(adev); 3750 3751 /* query poison mode from umc/df ip callback */ 3752 amdgpu_ras_query_poison_mode(adev); 3753 3754 init_ras_enabled_flag: 3755 /* hw_supported needs to be aligned with RAS block mask. */ 3756 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; 3757 3758 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : 3759 adev->ras_hw_enabled & amdgpu_ras_mask; 3760 3761 /* aca is disabled by default */ 3762 adev->aca.is_enabled = false; 3763 3764 /* bad page feature is not applicable to specific app platform */ 3765 if (adev->gmc.is_app_apu && 3766 amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(12, 0, 0)) 3767 amdgpu_bad_page_threshold = 0; 3768 } 3769 3770 static void amdgpu_ras_counte_dw(struct work_struct *work) 3771 { 3772 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, 3773 ras_counte_delay_work.work); 3774 struct amdgpu_device *adev = con->adev; 3775 struct drm_device *dev = adev_to_drm(adev); 3776 unsigned long ce_count, ue_count; 3777 int res; 3778 3779 res = pm_runtime_get_sync(dev->dev); 3780 if (res < 0) 3781 goto Out; 3782 3783 /* Cache new values. 3784 */ 3785 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) { 3786 atomic_set(&con->ras_ce_count, ce_count); 3787 atomic_set(&con->ras_ue_count, ue_count); 3788 } 3789 3790 pm_runtime_mark_last_busy(dev->dev); 3791 Out: 3792 pm_runtime_put_autosuspend(dev->dev); 3793 } 3794 3795 static int amdgpu_get_ras_schema(struct amdgpu_device *adev) 3796 { 3797 return amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 | 3798 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE | 3799 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE | 3800 AMDGPU_RAS_ERROR__PARITY; 3801 } 3802 3803 static void ras_event_mgr_init(struct ras_event_manager *mgr) 3804 { 3805 struct ras_event_state *event_state; 3806 int i; 3807 3808 memset(mgr, 0, sizeof(*mgr)); 3809 atomic64_set(&mgr->seqno, 0); 3810 3811 for (i = 0; i < ARRAY_SIZE(mgr->event_state); i++) { 3812 event_state = &mgr->event_state[i]; 3813 event_state->last_seqno = RAS_EVENT_INVALID_ID; 3814 atomic64_set(&event_state->count, 0); 3815 } 3816 } 3817 3818 static void amdgpu_ras_event_mgr_init(struct amdgpu_device *adev) 3819 { 3820 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3821 struct amdgpu_hive_info *hive; 3822 3823 if (!ras) 3824 return; 3825 3826 hive = amdgpu_get_xgmi_hive(adev); 3827 ras->event_mgr = hive ? &hive->event_mgr : &ras->__event_mgr; 3828 3829 /* init event manager with node 0 on xgmi system */ 3830 if (!amdgpu_reset_in_recovery(adev)) { 3831 if (!hive || adev->gmc.xgmi.node_id == 0) 3832 ras_event_mgr_init(ras->event_mgr); 3833 } 3834 3835 if (hive) 3836 amdgpu_put_xgmi_hive(hive); 3837 } 3838 3839 static void amdgpu_ras_init_reserved_vram_size(struct amdgpu_device *adev) 3840 { 3841 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3842 3843 if (!con || (adev->flags & AMD_IS_APU)) 3844 return; 3845 3846 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 3847 case IP_VERSION(13, 0, 2): 3848 case IP_VERSION(13, 0, 6): 3849 case IP_VERSION(13, 0, 12): 3850 case IP_VERSION(13, 0, 14): 3851 con->reserved_pages_in_bytes = AMDGPU_RAS_RESERVED_VRAM_SIZE; 3852 break; 3853 default: 3854 break; 3855 } 3856 } 3857 3858 int amdgpu_ras_init(struct amdgpu_device *adev) 3859 { 3860 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3861 int r; 3862 3863 if (con) 3864 return 0; 3865 3866 con = kzalloc(sizeof(*con) + 3867 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + 3868 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, 3869 GFP_KERNEL); 3870 if (!con) 3871 return -ENOMEM; 3872 3873 con->adev = adev; 3874 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); 3875 atomic_set(&con->ras_ce_count, 0); 3876 atomic_set(&con->ras_ue_count, 0); 3877 3878 con->objs = (struct ras_manager *)(con + 1); 3879 3880 amdgpu_ras_set_context(adev, con); 3881 3882 amdgpu_ras_check_supported(adev); 3883 3884 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { 3885 /* set gfx block ras context feature for VEGA20 Gaming 3886 * send ras disable cmd to ras ta during ras late init. 3887 */ 3888 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { 3889 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); 3890 3891 return 0; 3892 } 3893 3894 r = 0; 3895 goto release_con; 3896 } 3897 3898 con->update_channel_flag = false; 3899 con->features = 0; 3900 con->schema = 0; 3901 INIT_LIST_HEAD(&con->head); 3902 /* Might need get this flag from vbios. */ 3903 con->flags = RAS_DEFAULT_FLAGS; 3904 3905 /* initialize nbio ras function ahead of any other 3906 * ras functions so hardware fatal error interrupt 3907 * can be enabled as early as possible */ 3908 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3909 case IP_VERSION(7, 4, 0): 3910 case IP_VERSION(7, 4, 1): 3911 case IP_VERSION(7, 4, 4): 3912 if (!adev->gmc.xgmi.connected_to_cpu) 3913 adev->nbio.ras = &nbio_v7_4_ras; 3914 break; 3915 case IP_VERSION(4, 3, 0): 3916 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF)) 3917 /* unlike other generation of nbio ras, 3918 * nbio v4_3 only support fatal error interrupt 3919 * to inform software that DF is freezed due to 3920 * system fatal error event. driver should not 3921 * enable nbio ras in such case. Instead, 3922 * check DF RAS */ 3923 adev->nbio.ras = &nbio_v4_3_ras; 3924 break; 3925 case IP_VERSION(6, 3, 1): 3926 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF)) 3927 /* unlike other generation of nbio ras, 3928 * nbif v6_3_1 only support fatal error interrupt 3929 * to inform software that DF is freezed due to 3930 * system fatal error event. driver should not 3931 * enable nbio ras in such case. Instead, 3932 * check DF RAS 3933 */ 3934 adev->nbio.ras = &nbif_v6_3_1_ras; 3935 break; 3936 case IP_VERSION(7, 9, 0): 3937 case IP_VERSION(7, 9, 1): 3938 if (!adev->gmc.is_app_apu) 3939 adev->nbio.ras = &nbio_v7_9_ras; 3940 break; 3941 default: 3942 /* nbio ras is not available */ 3943 break; 3944 } 3945 3946 /* nbio ras block needs to be enabled ahead of other ras blocks 3947 * to handle fatal error */ 3948 r = amdgpu_nbio_ras_sw_init(adev); 3949 if (r) 3950 return r; 3951 3952 if (adev->nbio.ras && 3953 adev->nbio.ras->init_ras_controller_interrupt) { 3954 r = adev->nbio.ras->init_ras_controller_interrupt(adev); 3955 if (r) 3956 goto release_con; 3957 } 3958 3959 if (adev->nbio.ras && 3960 adev->nbio.ras->init_ras_err_event_athub_interrupt) { 3961 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev); 3962 if (r) 3963 goto release_con; 3964 } 3965 3966 /* Packed socket_id to ras feature mask bits[31:29] */ 3967 if (adev->smuio.funcs && 3968 adev->smuio.funcs->get_socket_id) 3969 con->features |= ((adev->smuio.funcs->get_socket_id(adev)) << 3970 AMDGPU_RAS_FEATURES_SOCKETID_SHIFT); 3971 3972 /* Get RAS schema for particular SOC */ 3973 con->schema = amdgpu_get_ras_schema(adev); 3974 3975 amdgpu_ras_init_reserved_vram_size(adev); 3976 3977 if (amdgpu_ras_fs_init(adev)) { 3978 r = -EINVAL; 3979 goto release_con; 3980 } 3981 3982 if (amdgpu_ras_aca_is_supported(adev)) { 3983 if (amdgpu_aca_is_enabled(adev)) 3984 r = amdgpu_aca_init(adev); 3985 else 3986 r = amdgpu_mca_init(adev); 3987 if (r) 3988 goto release_con; 3989 } 3990 3991 dev_info(adev->dev, "RAS INFO: ras initialized successfully, " 3992 "hardware ability[%x] ras_mask[%x]\n", 3993 adev->ras_hw_enabled, adev->ras_enabled); 3994 3995 return 0; 3996 release_con: 3997 amdgpu_ras_set_context(adev, NULL); 3998 kfree(con); 3999 4000 return r; 4001 } 4002 4003 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) 4004 { 4005 if (adev->gmc.xgmi.connected_to_cpu || 4006 adev->gmc.is_app_apu) 4007 return 1; 4008 return 0; 4009 } 4010 4011 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, 4012 struct ras_common_if *ras_block) 4013 { 4014 struct ras_query_if info = { 4015 .head = *ras_block, 4016 }; 4017 4018 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 4019 return 0; 4020 4021 if (amdgpu_ras_query_error_status(adev, &info) != 0) 4022 DRM_WARN("RAS init harvest failure"); 4023 4024 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) 4025 DRM_WARN("RAS init harvest reset failure"); 4026 4027 return 0; 4028 } 4029 4030 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) 4031 { 4032 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4033 4034 if (!con) 4035 return false; 4036 4037 return con->poison_supported; 4038 } 4039 4040 /* helper function to handle common stuff in ip late init phase */ 4041 int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 4042 struct ras_common_if *ras_block) 4043 { 4044 struct amdgpu_ras_block_object *ras_obj = NULL; 4045 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4046 struct ras_query_if *query_info; 4047 unsigned long ue_count, ce_count; 4048 int r; 4049 4050 /* disable RAS feature per IP block if it is not supported */ 4051 if (!amdgpu_ras_is_supported(adev, ras_block->block)) { 4052 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 4053 return 0; 4054 } 4055 4056 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); 4057 if (r) { 4058 if (adev->in_suspend || amdgpu_reset_in_recovery(adev)) { 4059 /* in resume phase, if fail to enable ras, 4060 * clean up all ras fs nodes, and disable ras */ 4061 goto cleanup; 4062 } else 4063 return r; 4064 } 4065 4066 /* check for errors on warm reset edc persisant supported ASIC */ 4067 amdgpu_persistent_edc_harvesting(adev, ras_block); 4068 4069 /* in resume phase, no need to create ras fs node */ 4070 if (adev->in_suspend || amdgpu_reset_in_recovery(adev)) 4071 return 0; 4072 4073 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); 4074 if (ras_obj->ras_cb || (ras_obj->hw_ops && 4075 (ras_obj->hw_ops->query_poison_status || 4076 ras_obj->hw_ops->handle_poison_consumption))) { 4077 r = amdgpu_ras_interrupt_add_handler(adev, ras_block); 4078 if (r) 4079 goto cleanup; 4080 } 4081 4082 if (ras_obj->hw_ops && 4083 (ras_obj->hw_ops->query_ras_error_count || 4084 ras_obj->hw_ops->query_ras_error_status)) { 4085 r = amdgpu_ras_sysfs_create(adev, ras_block); 4086 if (r) 4087 goto interrupt; 4088 4089 /* Those are the cached values at init. 4090 */ 4091 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL); 4092 if (!query_info) 4093 return -ENOMEM; 4094 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if)); 4095 4096 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) { 4097 atomic_set(&con->ras_ce_count, ce_count); 4098 atomic_set(&con->ras_ue_count, ue_count); 4099 } 4100 4101 kfree(query_info); 4102 } 4103 4104 return 0; 4105 4106 interrupt: 4107 if (ras_obj->ras_cb) 4108 amdgpu_ras_interrupt_remove_handler(adev, ras_block); 4109 cleanup: 4110 amdgpu_ras_feature_enable(adev, ras_block, 0); 4111 return r; 4112 } 4113 4114 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev, 4115 struct ras_common_if *ras_block) 4116 { 4117 return amdgpu_ras_block_late_init(adev, ras_block); 4118 } 4119 4120 /* helper function to remove ras fs node and interrupt handler */ 4121 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 4122 struct ras_common_if *ras_block) 4123 { 4124 struct amdgpu_ras_block_object *ras_obj; 4125 if (!ras_block) 4126 return; 4127 4128 amdgpu_ras_sysfs_remove(adev, ras_block); 4129 4130 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); 4131 if (ras_obj->ras_cb) 4132 amdgpu_ras_interrupt_remove_handler(adev, ras_block); 4133 } 4134 4135 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev, 4136 struct ras_common_if *ras_block) 4137 { 4138 return amdgpu_ras_block_late_fini(adev, ras_block); 4139 } 4140 4141 /* do some init work after IP late init as dependence. 4142 * and it runs in resume/gpu reset/booting up cases. 4143 */ 4144 void amdgpu_ras_resume(struct amdgpu_device *adev) 4145 { 4146 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4147 struct ras_manager *obj, *tmp; 4148 4149 if (!adev->ras_enabled || !con) { 4150 /* clean ras context for VEGA20 Gaming after send ras disable cmd */ 4151 amdgpu_release_ras_context(adev); 4152 4153 return; 4154 } 4155 4156 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { 4157 /* Set up all other IPs which are not implemented. There is a 4158 * tricky thing that IP's actual ras error type should be 4159 * MULTI_UNCORRECTABLE, but as driver does not handle it, so 4160 * ERROR_NONE make sense anyway. 4161 */ 4162 amdgpu_ras_enable_all_features(adev, 1); 4163 4164 /* We enable ras on all hw_supported block, but as boot 4165 * parameter might disable some of them and one or more IP has 4166 * not implemented yet. So we disable them on behalf. 4167 */ 4168 list_for_each_entry_safe(obj, tmp, &con->head, node) { 4169 if (!amdgpu_ras_is_supported(adev, obj->head.block)) { 4170 amdgpu_ras_feature_enable(adev, &obj->head, 0); 4171 /* there should be no any reference. */ 4172 WARN_ON(alive_obj(obj)); 4173 } 4174 } 4175 } 4176 } 4177 4178 void amdgpu_ras_suspend(struct amdgpu_device *adev) 4179 { 4180 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4181 4182 if (!adev->ras_enabled || !con) 4183 return; 4184 4185 amdgpu_ras_disable_all_features(adev, 0); 4186 /* Make sure all ras objects are disabled. */ 4187 if (AMDGPU_RAS_GET_FEATURES(con->features)) 4188 amdgpu_ras_disable_all_features(adev, 1); 4189 } 4190 4191 int amdgpu_ras_late_init(struct amdgpu_device *adev) 4192 { 4193 struct amdgpu_ras_block_list *node, *tmp; 4194 struct amdgpu_ras_block_object *obj; 4195 int r; 4196 4197 amdgpu_ras_event_mgr_init(adev); 4198 4199 if (amdgpu_ras_aca_is_supported(adev)) { 4200 if (amdgpu_reset_in_recovery(adev)) { 4201 if (amdgpu_aca_is_enabled(adev)) 4202 r = amdgpu_aca_reset(adev); 4203 else 4204 r = amdgpu_mca_reset(adev); 4205 if (r) 4206 return r; 4207 } 4208 4209 if (!amdgpu_sriov_vf(adev)) { 4210 if (amdgpu_aca_is_enabled(adev)) 4211 amdgpu_ras_set_aca_debug_mode(adev, false); 4212 else 4213 amdgpu_ras_set_mca_debug_mode(adev, false); 4214 } 4215 } 4216 4217 /* Guest side doesn't need init ras feature */ 4218 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_ras_telemetry_en(adev)) 4219 return 0; 4220 4221 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { 4222 obj = node->ras_obj; 4223 if (!obj) { 4224 dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); 4225 continue; 4226 } 4227 4228 if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block)) 4229 continue; 4230 4231 if (obj->ras_late_init) { 4232 r = obj->ras_late_init(adev, &obj->ras_comm); 4233 if (r) { 4234 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n", 4235 obj->ras_comm.name, r); 4236 return r; 4237 } 4238 } else 4239 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); 4240 } 4241 4242 return 0; 4243 } 4244 4245 /* do some fini work before IP fini as dependence */ 4246 int amdgpu_ras_pre_fini(struct amdgpu_device *adev) 4247 { 4248 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4249 4250 if (!adev->ras_enabled || !con) 4251 return 0; 4252 4253 4254 /* Need disable ras on all IPs here before ip [hw/sw]fini */ 4255 if (AMDGPU_RAS_GET_FEATURES(con->features)) 4256 amdgpu_ras_disable_all_features(adev, 0); 4257 amdgpu_ras_recovery_fini(adev); 4258 return 0; 4259 } 4260 4261 int amdgpu_ras_fini(struct amdgpu_device *adev) 4262 { 4263 struct amdgpu_ras_block_list *ras_node, *tmp; 4264 struct amdgpu_ras_block_object *obj = NULL; 4265 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4266 4267 if (!adev->ras_enabled || !con) 4268 return 0; 4269 4270 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { 4271 if (ras_node->ras_obj) { 4272 obj = ras_node->ras_obj; 4273 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) && 4274 obj->ras_fini) 4275 obj->ras_fini(adev, &obj->ras_comm); 4276 else 4277 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm); 4278 } 4279 4280 /* Clear ras blocks from ras_list and free ras block list node */ 4281 list_del(&ras_node->node); 4282 kfree(ras_node); 4283 } 4284 4285 amdgpu_ras_fs_fini(adev); 4286 amdgpu_ras_interrupt_remove_all(adev); 4287 4288 if (amdgpu_ras_aca_is_supported(adev)) { 4289 if (amdgpu_aca_is_enabled(adev)) 4290 amdgpu_aca_fini(adev); 4291 else 4292 amdgpu_mca_fini(adev); 4293 } 4294 4295 WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not cleared"); 4296 4297 if (AMDGPU_RAS_GET_FEATURES(con->features)) 4298 amdgpu_ras_disable_all_features(adev, 0); 4299 4300 cancel_delayed_work_sync(&con->ras_counte_delay_work); 4301 4302 amdgpu_ras_set_context(adev, NULL); 4303 kfree(con); 4304 4305 return 0; 4306 } 4307 4308 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev) 4309 { 4310 struct amdgpu_ras *ras; 4311 4312 ras = amdgpu_ras_get_context(adev); 4313 if (!ras) 4314 return false; 4315 4316 return test_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state); 4317 } 4318 4319 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status) 4320 { 4321 struct amdgpu_ras *ras; 4322 4323 ras = amdgpu_ras_get_context(adev); 4324 if (ras) { 4325 if (status) 4326 set_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state); 4327 else 4328 clear_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state); 4329 } 4330 } 4331 4332 void amdgpu_ras_clear_err_state(struct amdgpu_device *adev) 4333 { 4334 struct amdgpu_ras *ras; 4335 4336 ras = amdgpu_ras_get_context(adev); 4337 if (ras) 4338 ras->ras_err_state = 0; 4339 } 4340 4341 void amdgpu_ras_set_err_poison(struct amdgpu_device *adev, 4342 enum amdgpu_ras_block block) 4343 { 4344 struct amdgpu_ras *ras; 4345 4346 ras = amdgpu_ras_get_context(adev); 4347 if (ras) 4348 set_bit(block, &ras->ras_err_state); 4349 } 4350 4351 bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block) 4352 { 4353 struct amdgpu_ras *ras; 4354 4355 ras = amdgpu_ras_get_context(adev); 4356 if (ras) { 4357 if (block == AMDGPU_RAS_BLOCK__ANY) 4358 return (ras->ras_err_state != 0); 4359 else 4360 return test_bit(block, &ras->ras_err_state) || 4361 test_bit(AMDGPU_RAS_BLOCK__LAST, 4362 &ras->ras_err_state); 4363 } 4364 4365 return false; 4366 } 4367 4368 static struct ras_event_manager *__get_ras_event_mgr(struct amdgpu_device *adev) 4369 { 4370 struct amdgpu_ras *ras; 4371 4372 ras = amdgpu_ras_get_context(adev); 4373 if (!ras) 4374 return NULL; 4375 4376 return ras->event_mgr; 4377 } 4378 4379 int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, 4380 const void *caller) 4381 { 4382 struct ras_event_manager *event_mgr; 4383 struct ras_event_state *event_state; 4384 int ret = 0; 4385 4386 if (type >= RAS_EVENT_TYPE_COUNT) { 4387 ret = -EINVAL; 4388 goto out; 4389 } 4390 4391 event_mgr = __get_ras_event_mgr(adev); 4392 if (!event_mgr) { 4393 ret = -EINVAL; 4394 goto out; 4395 } 4396 4397 event_state = &event_mgr->event_state[type]; 4398 event_state->last_seqno = atomic64_inc_return(&event_mgr->seqno); 4399 atomic64_inc(&event_state->count); 4400 4401 out: 4402 if (ret && caller) 4403 dev_warn(adev->dev, "failed mark ras event (%d) in %ps, ret:%d\n", 4404 (int)type, caller, ret); 4405 4406 return ret; 4407 } 4408 4409 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type) 4410 { 4411 struct ras_event_manager *event_mgr; 4412 u64 id; 4413 4414 if (type >= RAS_EVENT_TYPE_COUNT) 4415 return RAS_EVENT_INVALID_ID; 4416 4417 switch (type) { 4418 case RAS_EVENT_TYPE_FATAL: 4419 case RAS_EVENT_TYPE_POISON_CREATION: 4420 case RAS_EVENT_TYPE_POISON_CONSUMPTION: 4421 event_mgr = __get_ras_event_mgr(adev); 4422 if (!event_mgr) 4423 return RAS_EVENT_INVALID_ID; 4424 4425 id = event_mgr->event_state[type].last_seqno; 4426 break; 4427 case RAS_EVENT_TYPE_INVALID: 4428 default: 4429 id = RAS_EVENT_INVALID_ID; 4430 break; 4431 } 4432 4433 return id; 4434 } 4435 4436 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) 4437 { 4438 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { 4439 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 4440 enum ras_event_type type = RAS_EVENT_TYPE_FATAL; 4441 u64 event_id; 4442 4443 if (amdgpu_ras_mark_ras_event(adev, type)) 4444 return; 4445 4446 event_id = amdgpu_ras_acquire_event_id(adev, type); 4447 4448 RAS_EVENT_LOG(adev, event_id, "uncorrectable hardware error" 4449 "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); 4450 4451 amdgpu_ras_set_fed(adev, true); 4452 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; 4453 amdgpu_ras_reset_gpu(adev); 4454 } 4455 } 4456 4457 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) 4458 { 4459 if (adev->asic_type == CHIP_VEGA20 && 4460 adev->pm.fw_version <= 0x283400) { 4461 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && 4462 amdgpu_ras_intr_triggered(); 4463 } 4464 4465 return false; 4466 } 4467 4468 void amdgpu_release_ras_context(struct amdgpu_device *adev) 4469 { 4470 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4471 4472 if (!con) 4473 return; 4474 4475 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { 4476 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); 4477 amdgpu_ras_set_context(adev, NULL); 4478 kfree(con); 4479 } 4480 } 4481 4482 #ifdef CONFIG_X86_MCE_AMD 4483 static struct amdgpu_device *find_adev(uint32_t node_id) 4484 { 4485 int i; 4486 struct amdgpu_device *adev = NULL; 4487 4488 for (i = 0; i < mce_adev_list.num_gpu; i++) { 4489 adev = mce_adev_list.devs[i]; 4490 4491 if (adev && adev->gmc.xgmi.connected_to_cpu && 4492 adev->gmc.xgmi.physical_node_id == node_id) 4493 break; 4494 adev = NULL; 4495 } 4496 4497 return adev; 4498 } 4499 4500 #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) 4501 #define GET_UMC_INST(m) (((m) >> 21) & 0x7) 4502 #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4)) 4503 #define GPU_ID_OFFSET 8 4504 4505 static int amdgpu_bad_page_notifier(struct notifier_block *nb, 4506 unsigned long val, void *data) 4507 { 4508 struct mce *m = (struct mce *)data; 4509 struct amdgpu_device *adev = NULL; 4510 uint32_t gpu_id = 0; 4511 uint32_t umc_inst = 0, ch_inst = 0; 4512 4513 /* 4514 * If the error was generated in UMC_V2, which belongs to GPU UMCs, 4515 * and error occurred in DramECC (Extended error code = 0) then only 4516 * process the error, else bail out. 4517 */ 4518 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && 4519 (XEC(m->status, 0x3f) == 0x0))) 4520 return NOTIFY_DONE; 4521 4522 /* 4523 * If it is correctable error, return. 4524 */ 4525 if (mce_is_correctable(m)) 4526 return NOTIFY_OK; 4527 4528 /* 4529 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register. 4530 */ 4531 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET; 4532 4533 adev = find_adev(gpu_id); 4534 if (!adev) { 4535 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__, 4536 gpu_id); 4537 return NOTIFY_DONE; 4538 } 4539 4540 /* 4541 * If it is uncorrectable error, then find out UMC instance and 4542 * channel index. 4543 */ 4544 umc_inst = GET_UMC_INST(m->ipid); 4545 ch_inst = GET_CHAN_INDEX(m->ipid); 4546 4547 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", 4548 umc_inst, ch_inst); 4549 4550 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) 4551 return NOTIFY_OK; 4552 else 4553 return NOTIFY_DONE; 4554 } 4555 4556 static struct notifier_block amdgpu_bad_page_nb = { 4557 .notifier_call = amdgpu_bad_page_notifier, 4558 .priority = MCE_PRIO_UC, 4559 }; 4560 4561 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) 4562 { 4563 /* 4564 * Add the adev to the mce_adev_list. 4565 * During mode2 reset, amdgpu device is temporarily 4566 * removed from the mgpu_info list which can cause 4567 * page retirement to fail. 4568 * Use this list instead of mgpu_info to find the amdgpu 4569 * device on which the UMC error was reported. 4570 */ 4571 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev; 4572 4573 /* 4574 * Register the x86 notifier only once 4575 * with MCE subsystem. 4576 */ 4577 if (notifier_registered == false) { 4578 mce_register_decode_chain(&amdgpu_bad_page_nb); 4579 notifier_registered = true; 4580 } 4581 } 4582 #endif 4583 4584 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) 4585 { 4586 if (!adev) 4587 return NULL; 4588 4589 return adev->psp.ras_context.ras; 4590 } 4591 4592 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con) 4593 { 4594 if (!adev) 4595 return -EINVAL; 4596 4597 adev->psp.ras_context.ras = ras_con; 4598 return 0; 4599 } 4600 4601 /* check if ras is supported on block, say, sdma, gfx */ 4602 int amdgpu_ras_is_supported(struct amdgpu_device *adev, 4603 unsigned int block) 4604 { 4605 int ret = 0; 4606 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 4607 4608 if (block >= AMDGPU_RAS_BLOCK_COUNT) 4609 return 0; 4610 4611 ret = ras && (adev->ras_enabled & (1 << block)); 4612 4613 /* For the special asic with mem ecc enabled but sram ecc 4614 * not enabled, even if the ras block is not supported on 4615 * .ras_enabled, if the asic supports poison mode and the 4616 * ras block has ras configuration, it can be considered 4617 * that the ras block supports ras function. 4618 */ 4619 if (!ret && 4620 (block == AMDGPU_RAS_BLOCK__GFX || 4621 block == AMDGPU_RAS_BLOCK__SDMA || 4622 block == AMDGPU_RAS_BLOCK__VCN || 4623 block == AMDGPU_RAS_BLOCK__JPEG) && 4624 (amdgpu_ras_mask & (1 << block)) && 4625 amdgpu_ras_is_poison_mode_supported(adev) && 4626 amdgpu_ras_get_ras_block(adev, block, 0)) 4627 ret = 1; 4628 4629 return ret; 4630 } 4631 4632 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) 4633 { 4634 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 4635 4636 /* mode1 is the only selection for RMA status */ 4637 if (amdgpu_ras_is_rma(adev)) { 4638 ras->gpu_reset_flags = 0; 4639 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; 4640 } 4641 4642 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) { 4643 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); 4644 int hive_ras_recovery = 0; 4645 4646 if (hive) { 4647 hive_ras_recovery = atomic_read(&hive->ras_recovery); 4648 amdgpu_put_xgmi_hive(hive); 4649 } 4650 /* In the case of multiple GPUs, after a GPU has started 4651 * resetting all GPUs on hive, other GPUs do not need to 4652 * trigger GPU reset again. 4653 */ 4654 if (!hive_ras_recovery) 4655 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); 4656 else 4657 atomic_set(&ras->in_recovery, 0); 4658 } else { 4659 flush_work(&ras->recovery_work); 4660 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); 4661 } 4662 4663 return 0; 4664 } 4665 4666 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable) 4667 { 4668 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4669 int ret = 0; 4670 4671 if (con) { 4672 ret = amdgpu_mca_smu_set_debug_mode(adev, enable); 4673 if (!ret) 4674 con->is_aca_debug_mode = enable; 4675 } 4676 4677 return ret; 4678 } 4679 4680 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable) 4681 { 4682 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4683 int ret = 0; 4684 4685 if (con) { 4686 if (amdgpu_aca_is_enabled(adev)) 4687 ret = amdgpu_aca_smu_set_debug_mode(adev, enable); 4688 else 4689 ret = amdgpu_mca_smu_set_debug_mode(adev, enable); 4690 if (!ret) 4691 con->is_aca_debug_mode = enable; 4692 } 4693 4694 return ret; 4695 } 4696 4697 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev) 4698 { 4699 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4700 const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; 4701 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 4702 4703 if (!con) 4704 return false; 4705 4706 if ((amdgpu_aca_is_enabled(adev) && smu_funcs && smu_funcs->set_debug_mode) || 4707 (!amdgpu_aca_is_enabled(adev) && mca_funcs && mca_funcs->mca_set_debug_mode)) 4708 return con->is_aca_debug_mode; 4709 else 4710 return true; 4711 } 4712 4713 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 4714 unsigned int *error_query_mode) 4715 { 4716 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 4717 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 4718 const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; 4719 4720 if (!con) { 4721 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY; 4722 return false; 4723 } 4724 4725 if (amdgpu_sriov_vf(adev)) { 4726 *error_query_mode = AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY; 4727 } else if ((smu_funcs && smu_funcs->set_debug_mode) || (mca_funcs && mca_funcs->mca_set_debug_mode)) { 4728 *error_query_mode = 4729 (con->is_aca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY; 4730 } else { 4731 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY; 4732 } 4733 4734 return true; 4735 } 4736 4737 /* Register each ip ras block into amdgpu ras */ 4738 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 4739 struct amdgpu_ras_block_object *ras_block_obj) 4740 { 4741 struct amdgpu_ras_block_list *ras_node; 4742 if (!adev || !ras_block_obj) 4743 return -EINVAL; 4744 4745 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL); 4746 if (!ras_node) 4747 return -ENOMEM; 4748 4749 INIT_LIST_HEAD(&ras_node->node); 4750 ras_node->ras_obj = ras_block_obj; 4751 list_add_tail(&ras_node->node, &adev->ras_list); 4752 4753 return 0; 4754 } 4755 4756 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name) 4757 { 4758 if (!err_type_name) 4759 return; 4760 4761 switch (err_type) { 4762 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 4763 sprintf(err_type_name, "correctable"); 4764 break; 4765 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 4766 sprintf(err_type_name, "uncorrectable"); 4767 break; 4768 default: 4769 sprintf(err_type_name, "unknown"); 4770 break; 4771 } 4772 } 4773 4774 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 4775 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 4776 uint32_t instance, 4777 uint32_t *memory_id) 4778 { 4779 uint32_t err_status_lo_data, err_status_lo_offset; 4780 4781 if (!reg_entry) 4782 return false; 4783 4784 err_status_lo_offset = 4785 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, 4786 reg_entry->seg_lo, reg_entry->reg_lo); 4787 err_status_lo_data = RREG32(err_status_lo_offset); 4788 4789 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && 4790 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG)) 4791 return false; 4792 4793 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID); 4794 4795 return true; 4796 } 4797 4798 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 4799 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 4800 uint32_t instance, 4801 unsigned long *err_cnt) 4802 { 4803 uint32_t err_status_hi_data, err_status_hi_offset; 4804 4805 if (!reg_entry) 4806 return false; 4807 4808 err_status_hi_offset = 4809 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, 4810 reg_entry->seg_hi, reg_entry->reg_hi); 4811 err_status_hi_data = RREG32(err_status_hi_offset); 4812 4813 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && 4814 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG)) 4815 /* keep the check here in case we need to refer to the result later */ 4816 dev_dbg(adev->dev, "Invalid err_info field\n"); 4817 4818 /* read err count */ 4819 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT); 4820 4821 return true; 4822 } 4823 4824 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 4825 const struct amdgpu_ras_err_status_reg_entry *reg_list, 4826 uint32_t reg_list_size, 4827 const struct amdgpu_ras_memory_id_entry *mem_list, 4828 uint32_t mem_list_size, 4829 uint32_t instance, 4830 uint32_t err_type, 4831 unsigned long *err_count) 4832 { 4833 uint32_t memory_id; 4834 unsigned long err_cnt; 4835 char err_type_name[16]; 4836 uint32_t i, j; 4837 4838 for (i = 0; i < reg_list_size; i++) { 4839 /* query memory_id from err_status_lo */ 4840 if (!amdgpu_ras_inst_get_memory_id_field(adev, ®_list[i], 4841 instance, &memory_id)) 4842 continue; 4843 4844 /* query err_cnt from err_status_hi */ 4845 if (!amdgpu_ras_inst_get_err_cnt_field(adev, ®_list[i], 4846 instance, &err_cnt) || 4847 !err_cnt) 4848 continue; 4849 4850 *err_count += err_cnt; 4851 4852 /* log the errors */ 4853 amdgpu_ras_get_error_type_name(err_type, err_type_name); 4854 if (!mem_list) { 4855 /* memory_list is not supported */ 4856 dev_info(adev->dev, 4857 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n", 4858 err_cnt, err_type_name, 4859 reg_list[i].block_name, 4860 instance, memory_id); 4861 } else { 4862 for (j = 0; j < mem_list_size; j++) { 4863 if (memory_id == mem_list[j].memory_id) { 4864 dev_info(adev->dev, 4865 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n", 4866 err_cnt, err_type_name, 4867 reg_list[i].block_name, 4868 instance, mem_list[j].name); 4869 break; 4870 } 4871 } 4872 } 4873 } 4874 } 4875 4876 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 4877 const struct amdgpu_ras_err_status_reg_entry *reg_list, 4878 uint32_t reg_list_size, 4879 uint32_t instance) 4880 { 4881 uint32_t err_status_lo_offset, err_status_hi_offset; 4882 uint32_t i; 4883 4884 for (i = 0; i < reg_list_size; i++) { 4885 err_status_lo_offset = 4886 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, 4887 reg_list[i].seg_lo, reg_list[i].reg_lo); 4888 err_status_hi_offset = 4889 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, 4890 reg_list[i].seg_hi, reg_list[i].reg_hi); 4891 WREG32(err_status_lo_offset, 0); 4892 WREG32(err_status_hi_offset, 0); 4893 } 4894 } 4895 4896 int amdgpu_ras_error_data_init(struct ras_err_data *err_data) 4897 { 4898 memset(err_data, 0, sizeof(*err_data)); 4899 4900 INIT_LIST_HEAD(&err_data->err_node_list); 4901 4902 return 0; 4903 } 4904 4905 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node) 4906 { 4907 if (!err_node) 4908 return; 4909 4910 list_del(&err_node->node); 4911 kvfree(err_node); 4912 } 4913 4914 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data) 4915 { 4916 struct ras_err_node *err_node, *tmp; 4917 4918 list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node) 4919 amdgpu_ras_error_node_release(err_node); 4920 } 4921 4922 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data, 4923 struct amdgpu_smuio_mcm_config_info *mcm_info) 4924 { 4925 struct ras_err_node *err_node; 4926 struct amdgpu_smuio_mcm_config_info *ref_id; 4927 4928 if (!err_data || !mcm_info) 4929 return NULL; 4930 4931 for_each_ras_error(err_node, err_data) { 4932 ref_id = &err_node->err_info.mcm_info; 4933 4934 if (mcm_info->socket_id == ref_id->socket_id && 4935 mcm_info->die_id == ref_id->die_id) 4936 return err_node; 4937 } 4938 4939 return NULL; 4940 } 4941 4942 static struct ras_err_node *amdgpu_ras_error_node_new(void) 4943 { 4944 struct ras_err_node *err_node; 4945 4946 err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL); 4947 if (!err_node) 4948 return NULL; 4949 4950 INIT_LIST_HEAD(&err_node->node); 4951 4952 return err_node; 4953 } 4954 4955 static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) 4956 { 4957 struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); 4958 struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); 4959 struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info; 4960 struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info; 4961 4962 if (unlikely(infoa->socket_id != infob->socket_id)) 4963 return infoa->socket_id - infob->socket_id; 4964 else 4965 return infoa->die_id - infob->die_id; 4966 4967 return 0; 4968 } 4969 4970 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data, 4971 struct amdgpu_smuio_mcm_config_info *mcm_info) 4972 { 4973 struct ras_err_node *err_node; 4974 4975 err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info); 4976 if (err_node) 4977 return &err_node->err_info; 4978 4979 err_node = amdgpu_ras_error_node_new(); 4980 if (!err_node) 4981 return NULL; 4982 4983 memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info)); 4984 4985 err_data->err_list_count++; 4986 list_add_tail(&err_node->node, &err_data->err_node_list); 4987 list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp); 4988 4989 return &err_node->err_info; 4990 } 4991 4992 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, 4993 struct amdgpu_smuio_mcm_config_info *mcm_info, 4994 u64 count) 4995 { 4996 struct ras_err_info *err_info; 4997 4998 if (!err_data || !mcm_info) 4999 return -EINVAL; 5000 5001 if (!count) 5002 return 0; 5003 5004 err_info = amdgpu_ras_error_get_info(err_data, mcm_info); 5005 if (!err_info) 5006 return -EINVAL; 5007 5008 err_info->ue_count += count; 5009 err_data->ue_count += count; 5010 5011 return 0; 5012 } 5013 5014 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, 5015 struct amdgpu_smuio_mcm_config_info *mcm_info, 5016 u64 count) 5017 { 5018 struct ras_err_info *err_info; 5019 5020 if (!err_data || !mcm_info) 5021 return -EINVAL; 5022 5023 if (!count) 5024 return 0; 5025 5026 err_info = amdgpu_ras_error_get_info(err_data, mcm_info); 5027 if (!err_info) 5028 return -EINVAL; 5029 5030 err_info->ce_count += count; 5031 err_data->ce_count += count; 5032 5033 return 0; 5034 } 5035 5036 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, 5037 struct amdgpu_smuio_mcm_config_info *mcm_info, 5038 u64 count) 5039 { 5040 struct ras_err_info *err_info; 5041 5042 if (!err_data || !mcm_info) 5043 return -EINVAL; 5044 5045 if (!count) 5046 return 0; 5047 5048 err_info = amdgpu_ras_error_get_info(err_data, mcm_info); 5049 if (!err_info) 5050 return -EINVAL; 5051 5052 err_info->de_count += count; 5053 err_data->de_count += count; 5054 5055 return 0; 5056 } 5057 5058 #define mmMP0_SMN_C2PMSG_92 0x1609C 5059 #define mmMP0_SMN_C2PMSG_126 0x160BE 5060 static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev, 5061 u32 instance) 5062 { 5063 u32 socket_id, aid_id, hbm_id; 5064 u32 fw_status; 5065 u32 boot_error; 5066 u64 reg_addr; 5067 5068 /* The pattern for smn addressing in other SOC could be different from 5069 * the one for aqua_vanjaram. We should revisit the code if the pattern 5070 * is changed. In such case, replace the aqua_vanjaram implementation 5071 * with more common helper */ 5072 reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + 5073 aqua_vanjaram_encode_ext_smn_addressing(instance); 5074 fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr); 5075 5076 reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) + 5077 aqua_vanjaram_encode_ext_smn_addressing(instance); 5078 boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr); 5079 5080 socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error); 5081 aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error); 5082 hbm_id = ((1 == AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error)) ? 0 : 1); 5083 5084 if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error)) 5085 dev_info(adev->dev, 5086 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, memory training failed\n", 5087 socket_id, aid_id, hbm_id, fw_status); 5088 5089 if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error)) 5090 dev_info(adev->dev, 5091 "socket: %d, aid: %d, fw_status: 0x%x, firmware load failed at boot time\n", 5092 socket_id, aid_id, fw_status); 5093 5094 if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error)) 5095 dev_info(adev->dev, 5096 "socket: %d, aid: %d, fw_status: 0x%x, wafl link training failed\n", 5097 socket_id, aid_id, fw_status); 5098 5099 if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error)) 5100 dev_info(adev->dev, 5101 "socket: %d, aid: %d, fw_status: 0x%x, xgmi link training failed\n", 5102 socket_id, aid_id, fw_status); 5103 5104 if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error)) 5105 dev_info(adev->dev, 5106 "socket: %d, aid: %d, fw_status: 0x%x, usr cp link training failed\n", 5107 socket_id, aid_id, fw_status); 5108 5109 if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error)) 5110 dev_info(adev->dev, 5111 "socket: %d, aid: %d, fw_status: 0x%x, usr dp link training failed\n", 5112 socket_id, aid_id, fw_status); 5113 5114 if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error)) 5115 dev_info(adev->dev, 5116 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, hbm memory test failed\n", 5117 socket_id, aid_id, hbm_id, fw_status); 5118 5119 if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_error)) 5120 dev_info(adev->dev, 5121 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, hbm bist test failed\n", 5122 socket_id, aid_id, hbm_id, fw_status); 5123 5124 if (AMDGPU_RAS_GPU_ERR_DATA_ABORT(boot_error)) 5125 dev_info(adev->dev, 5126 "socket: %d, aid: %d, fw_status: 0x%x, data abort exception\n", 5127 socket_id, aid_id, fw_status); 5128 5129 if (AMDGPU_RAS_GPU_ERR_UNKNOWN(boot_error)) 5130 dev_info(adev->dev, 5131 "socket: %d, aid: %d, fw_status: 0x%x, unknown boot time errors\n", 5132 socket_id, aid_id, fw_status); 5133 } 5134 5135 static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev, 5136 u32 instance) 5137 { 5138 u64 reg_addr; 5139 u32 reg_data; 5140 int retry_loop; 5141 5142 reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + 5143 aqua_vanjaram_encode_ext_smn_addressing(instance); 5144 5145 for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) { 5146 reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); 5147 if ((reg_data & AMDGPU_RAS_BOOT_STATUS_MASK) == AMDGPU_RAS_BOOT_STEADY_STATUS) 5148 return false; 5149 else 5150 msleep(1); 5151 } 5152 5153 return true; 5154 } 5155 5156 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances) 5157 { 5158 u32 i; 5159 5160 for (i = 0; i < num_instances; i++) { 5161 if (amdgpu_ras_boot_error_detected(adev, i)) 5162 amdgpu_ras_boot_time_error_reporting(adev, i); 5163 } 5164 } 5165 5166 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn) 5167 { 5168 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 5169 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; 5170 uint64_t start = pfn << AMDGPU_GPU_PAGE_SHIFT; 5171 int ret = 0; 5172 5173 mutex_lock(&con->page_rsv_lock); 5174 ret = amdgpu_vram_mgr_query_page_status(mgr, start); 5175 if (ret == -ENOENT) 5176 ret = amdgpu_vram_mgr_reserve_range(mgr, start, AMDGPU_GPU_PAGE_SIZE); 5177 mutex_unlock(&con->page_rsv_lock); 5178 5179 return ret; 5180 } 5181 5182 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, 5183 const char *fmt, ...) 5184 { 5185 struct va_format vaf; 5186 va_list args; 5187 5188 va_start(args, fmt); 5189 vaf.fmt = fmt; 5190 vaf.va = &args; 5191 5192 if (RAS_EVENT_ID_IS_VALID(event_id)) 5193 dev_printk(KERN_INFO, adev->dev, "{%llu}%pV", event_id, &vaf); 5194 else 5195 dev_printk(KERN_INFO, adev->dev, "%pV", &vaf); 5196 5197 va_end(args); 5198 } 5199 5200 bool amdgpu_ras_is_rma(struct amdgpu_device *adev) 5201 { 5202 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 5203 5204 if (!con) 5205 return false; 5206 5207 return con->is_rma; 5208 } 5209