1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 extern const struct attribute_group amdgpu_flash_attr_group; 43 44 enum psp_shared_mem_size { 45 PSP_ASD_SHARED_MEM_SIZE = 0x0, 46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 49 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 50 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 52 }; 53 54 enum ta_type_id { 55 TA_TYPE_XGMI = 1, 56 TA_TYPE_RAS, 57 TA_TYPE_HDCP, 58 TA_TYPE_DTM, 59 TA_TYPE_RAP, 60 TA_TYPE_SECUREDISPLAY, 61 62 TA_TYPE_MAX_INDEX, 63 }; 64 65 struct psp_context; 66 struct psp_xgmi_node_info; 67 struct psp_xgmi_topology_info; 68 struct psp_bin_desc; 69 70 enum psp_bootloader_cmd { 71 PSP_BL__LOAD_SYSDRV = 0x10000, 72 PSP_BL__LOAD_SOSDRV = 0x20000, 73 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 74 PSP_BL__LOAD_SOCDRV = 0xB0000, 75 PSP_BL__LOAD_DBGDRV = 0xC0000, 76 PSP_BL__LOAD_INTFDRV = 0xD0000, 77 PSP_BL__LOAD_RASDRV = 0xE0000, 78 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 79 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 80 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 81 }; 82 83 enum psp_ring_type { 84 PSP_RING_TYPE__INVALID = 0, 85 /* 86 * These values map to the way the PSP kernel identifies the 87 * rings. 88 */ 89 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 90 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 91 }; 92 93 struct psp_ring { 94 enum psp_ring_type ring_type; 95 struct psp_gfx_rb_frame *ring_mem; 96 uint64_t ring_mem_mc_addr; 97 void *ring_mem_handle; 98 uint32_t ring_size; 99 uint32_t ring_wptr; 100 }; 101 102 /* More registers may will be supported */ 103 enum psp_reg_prog_id { 104 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 105 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 106 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 107 PSP_REG_LAST 108 }; 109 110 struct psp_funcs { 111 int (*init_microcode)(struct psp_context *psp); 112 int (*wait_for_bootloader)(struct psp_context *psp); 113 int (*bootloader_load_kdb)(struct psp_context *psp); 114 int (*bootloader_load_spl)(struct psp_context *psp); 115 int (*bootloader_load_sysdrv)(struct psp_context *psp); 116 int (*bootloader_load_soc_drv)(struct psp_context *psp); 117 int (*bootloader_load_intf_drv)(struct psp_context *psp); 118 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 119 int (*bootloader_load_ras_drv)(struct psp_context *psp); 120 int (*bootloader_load_sos)(struct psp_context *psp); 121 int (*ring_create)(struct psp_context *psp, 122 enum psp_ring_type ring_type); 123 int (*ring_stop)(struct psp_context *psp, 124 enum psp_ring_type ring_type); 125 int (*ring_destroy)(struct psp_context *psp, 126 enum psp_ring_type ring_type); 127 bool (*smu_reload_quirk)(struct psp_context *psp); 128 int (*mode1_reset)(struct psp_context *psp); 129 int (*mem_training)(struct psp_context *psp, uint32_t ops); 130 uint32_t (*ring_get_wptr)(struct psp_context *psp); 131 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 132 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 133 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 134 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 135 int (*vbflash_stat)(struct psp_context *psp); 136 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 137 bool (*get_ras_capability)(struct psp_context *psp); 138 }; 139 140 struct ta_funcs { 141 int (*fn_ta_initialize)(struct psp_context *psp); 142 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 143 int (*fn_ta_terminate)(struct psp_context *psp); 144 }; 145 146 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 147 struct psp_xgmi_node_info { 148 uint64_t node_id; 149 uint8_t num_hops; 150 uint8_t is_sharing_enabled; 151 enum ta_xgmi_assigned_sdma_engine sdma_engine; 152 uint8_t num_links; 153 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 154 }; 155 156 struct psp_xgmi_topology_info { 157 uint32_t num_nodes; 158 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 159 }; 160 161 struct psp_bin_desc { 162 uint32_t fw_version; 163 uint32_t feature_version; 164 uint32_t size_bytes; 165 uint8_t *start_addr; 166 }; 167 168 struct ta_mem_context { 169 struct amdgpu_bo *shared_bo; 170 uint64_t shared_mc_addr; 171 void *shared_buf; 172 enum psp_shared_mem_size shared_mem_size; 173 }; 174 175 struct ta_context { 176 bool initialized; 177 uint32_t session_id; 178 uint32_t resp_status; 179 struct ta_mem_context mem_context; 180 struct psp_bin_desc bin_desc; 181 enum psp_gfx_cmd_id ta_load_type; 182 enum ta_type_id ta_type; 183 }; 184 185 struct ta_cp_context { 186 struct ta_context context; 187 struct mutex mutex; 188 }; 189 190 struct psp_xgmi_context { 191 struct ta_context context; 192 struct psp_xgmi_topology_info top_info; 193 bool supports_extended_data; 194 uint8_t xgmi_ta_caps; 195 }; 196 197 struct psp_ras_context { 198 struct ta_context context; 199 struct amdgpu_ras *ras; 200 }; 201 202 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 203 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 204 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 205 /*Define the VRAM size that will be encroached by BIST training.*/ 206 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 207 208 enum psp_memory_training_init_flag { 209 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 210 PSP_MEM_TRAIN_SUPPORT = 0x1, 211 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 212 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 213 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 214 }; 215 216 enum psp_memory_training_ops { 217 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 218 PSP_MEM_TRAIN_SAVE = 0x2, 219 PSP_MEM_TRAIN_RESTORE = 0x4, 220 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 221 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 222 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 223 }; 224 225 struct psp_memory_training_context { 226 /*training data size*/ 227 u64 train_data_size; 228 /* 229 * sys_cache 230 * cpu virtual address 231 * system memory buffer that used to store the training data. 232 */ 233 void *sys_cache; 234 235 /*vram offset of the p2c training data*/ 236 u64 p2c_train_data_offset; 237 238 /*vram offset of the c2p training data*/ 239 u64 c2p_train_data_offset; 240 struct amdgpu_bo *c2p_bo; 241 242 enum psp_memory_training_init_flag init; 243 u32 training_cnt; 244 bool enable_mem_training; 245 }; 246 247 /** PSP runtime DB **/ 248 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 249 #define PSP_RUNTIME_DB_OFFSET 0x100000 250 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 251 #define PSP_RUNTIME_DB_VER_1 0x0100 252 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 253 254 enum psp_runtime_entry_type { 255 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 256 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 257 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 258 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 259 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 260 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 261 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 262 }; 263 264 /* PSP runtime DB header */ 265 struct psp_runtime_data_header { 266 /* determine the existence of runtime db */ 267 uint16_t cookie; 268 /* version of runtime db */ 269 uint16_t version; 270 }; 271 272 /* PSP runtime DB entry */ 273 struct psp_runtime_entry { 274 /* type of runtime db entry */ 275 uint32_t entry_type; 276 /* offset of entry in bytes */ 277 uint16_t offset; 278 /* size of entry in bytes */ 279 uint16_t size; 280 }; 281 282 /* PSP runtime DB directory */ 283 struct psp_runtime_data_directory { 284 /* number of valid entries */ 285 uint16_t entry_count; 286 /* db entries*/ 287 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 288 }; 289 290 /* PSP runtime DB boot config feature bitmask */ 291 enum psp_runtime_boot_cfg_feature { 292 BOOT_CFG_FEATURE_GECC = 0x1, 293 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 294 }; 295 296 /* PSP run time DB SCPM authentication defines */ 297 enum psp_runtime_scpm_authentication { 298 SCPM_DISABLE = 0x0, 299 SCPM_ENABLE = 0x1, 300 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 301 }; 302 303 /* PSP runtime DB boot config entry */ 304 struct psp_runtime_boot_cfg_entry { 305 uint32_t boot_cfg_bitmask; 306 uint32_t reserved; 307 }; 308 309 /* PSP runtime DB SCPM entry */ 310 struct psp_runtime_scpm_entry { 311 enum psp_runtime_scpm_authentication scpm_status; 312 }; 313 314 struct psp_context { 315 struct amdgpu_device *adev; 316 struct psp_ring km_ring; 317 struct psp_gfx_cmd_resp *cmd; 318 319 const struct psp_funcs *funcs; 320 const struct ta_funcs *ta_funcs; 321 322 /* firmware buffer */ 323 struct amdgpu_bo *fw_pri_bo; 324 uint64_t fw_pri_mc_addr; 325 void *fw_pri_buf; 326 327 /* sos firmware */ 328 const struct firmware *sos_fw; 329 struct psp_bin_desc sys; 330 struct psp_bin_desc sos; 331 struct psp_bin_desc toc; 332 struct psp_bin_desc kdb; 333 struct psp_bin_desc spl; 334 struct psp_bin_desc rl; 335 struct psp_bin_desc soc_drv; 336 struct psp_bin_desc intf_drv; 337 struct psp_bin_desc dbg_drv; 338 struct psp_bin_desc ras_drv; 339 340 /* tmr buffer */ 341 struct amdgpu_bo *tmr_bo; 342 uint64_t tmr_mc_addr; 343 344 /* asd firmware */ 345 const struct firmware *asd_fw; 346 347 /* toc firmware */ 348 const struct firmware *toc_fw; 349 350 /* cap firmware */ 351 const struct firmware *cap_fw; 352 353 /* fence buffer */ 354 struct amdgpu_bo *fence_buf_bo; 355 uint64_t fence_buf_mc_addr; 356 void *fence_buf; 357 358 /* cmd buffer */ 359 struct amdgpu_bo *cmd_buf_bo; 360 uint64_t cmd_buf_mc_addr; 361 struct psp_gfx_cmd_resp *cmd_buf_mem; 362 363 /* fence value associated with cmd buffer */ 364 atomic_t fence_value; 365 /* flag to mark whether gfx fw autoload is supported or not */ 366 bool autoload_supported; 367 /* flag to mark whether psp use runtime TMR or boottime TMR */ 368 bool boot_time_tmr; 369 /* flag to mark whether df cstate management centralized to PMFW */ 370 bool pmfw_centralized_cstate_management; 371 372 /* xgmi ta firmware and buffer */ 373 const struct firmware *ta_fw; 374 uint32_t ta_fw_version; 375 376 uint32_t cap_fw_version; 377 uint32_t cap_feature_version; 378 uint32_t cap_ucode_size; 379 380 struct ta_context asd_context; 381 struct psp_xgmi_context xgmi_context; 382 struct psp_ras_context ras_context; 383 struct ta_cp_context hdcp_context; 384 struct ta_cp_context dtm_context; 385 struct ta_cp_context rap_context; 386 struct ta_cp_context securedisplay_context; 387 struct mutex mutex; 388 struct psp_memory_training_context mem_train_ctx; 389 390 uint32_t boot_cfg_bitmask; 391 392 /* firmware upgrades supported */ 393 bool sup_pd_fw_up; 394 bool sup_ifwi_up; 395 396 char *vbflash_tmp_buf; 397 size_t vbflash_image_size; 398 bool vbflash_done; 399 }; 400 401 struct amdgpu_psp_funcs { 402 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 403 enum AMDGPU_UCODE_ID); 404 }; 405 406 407 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 408 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 409 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 410 #define psp_init_microcode(psp) \ 411 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 412 #define psp_bootloader_load_kdb(psp) \ 413 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 414 #define psp_bootloader_load_spl(psp) \ 415 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 416 #define psp_bootloader_load_sysdrv(psp) \ 417 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 418 #define psp_bootloader_load_soc_drv(psp) \ 419 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 420 #define psp_bootloader_load_intf_drv(psp) \ 421 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 422 #define psp_bootloader_load_dbg_drv(psp) \ 423 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 424 #define psp_bootloader_load_ras_drv(psp) \ 425 ((psp)->funcs->bootloader_load_ras_drv ? \ 426 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 427 #define psp_bootloader_load_sos(psp) \ 428 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 429 #define psp_smu_reload_quirk(psp) \ 430 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 431 #define psp_mode1_reset(psp) \ 432 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 433 #define psp_mem_training(psp, ops) \ 434 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 435 436 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 437 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 438 439 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 440 ((psp)->funcs->load_usbc_pd_fw ? \ 441 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 442 443 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 444 ((psp)->funcs->read_usbc_pd_fw ? \ 445 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 446 447 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 448 ((psp)->funcs->update_spirom ? \ 449 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 450 451 #define psp_vbflash_status(psp) \ 452 ((psp)->funcs->vbflash_stat ? \ 453 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 454 455 #define psp_fatal_error_recovery_quirk(psp) \ 456 ((psp)->funcs->fatal_error_recovery_quirk ? \ 457 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 458 459 extern const struct amd_ip_funcs psp_ip_funcs; 460 461 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 462 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 463 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 464 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 465 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 466 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 467 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 468 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 469 470 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 471 uint32_t field_val, uint32_t mask, bool check_changed); 472 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 473 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 474 475 int psp_execute_ip_fw_load(struct psp_context *psp, 476 struct amdgpu_firmware_info *ucode); 477 478 int psp_gpu_reset(struct amdgpu_device *adev); 479 480 int psp_ta_init_shared_buf(struct psp_context *psp, 481 struct ta_mem_context *mem_ctx); 482 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 483 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 484 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 485 int psp_ta_invoke(struct psp_context *psp, 486 uint32_t ta_cmd_id, 487 struct ta_context *context); 488 489 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 490 int psp_xgmi_terminate(struct psp_context *psp); 491 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 492 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 493 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 494 int psp_xgmi_get_topology_info(struct psp_context *psp, 495 int number_devices, 496 struct psp_xgmi_topology_info *topology, 497 bool get_extended_data); 498 int psp_xgmi_set_topology_info(struct psp_context *psp, 499 int number_devices, 500 struct psp_xgmi_topology_info *topology); 501 int psp_ras_initialize(struct psp_context *psp); 502 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 503 int psp_ras_enable_features(struct psp_context *psp, 504 union ta_ras_cmd_input *info, bool enable); 505 int psp_ras_trigger_error(struct psp_context *psp, 506 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 507 int psp_ras_terminate(struct psp_context *psp); 508 int psp_ras_query_address(struct psp_context *psp, 509 struct ta_ras_query_address_input *addr_in, 510 struct ta_ras_query_address_output *addr_out); 511 512 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 513 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 514 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 515 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 516 517 int psp_rlc_autoload_start(struct psp_context *psp); 518 519 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 520 uint32_t value); 521 int psp_ring_cmd_submit(struct psp_context *psp, 522 uint64_t cmd_buf_mc_addr, 523 uint64_t fence_mc_addr, 524 int index); 525 int psp_init_asd_microcode(struct psp_context *psp, 526 const char *chip_name); 527 int psp_init_toc_microcode(struct psp_context *psp, 528 const char *chip_name); 529 int psp_init_sos_microcode(struct psp_context *psp, 530 const char *chip_name); 531 int psp_init_ta_microcode(struct psp_context *psp, 532 const char *chip_name); 533 int psp_init_cap_microcode(struct psp_context *psp, 534 const char *chip_name); 535 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 536 uint64_t *output_ptr); 537 538 int psp_load_fw_list(struct psp_context *psp, 539 struct amdgpu_firmware_info **ucode_list, int ucode_count); 540 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 541 542 int psp_spatial_partition(struct psp_context *psp, int mode); 543 544 int is_psp_fw_valid(struct psp_bin_desc bin); 545 546 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 547 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 548 #endif 549