1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 extern const struct attribute_group amdgpu_flash_attr_group; 43 44 enum psp_shared_mem_size { 45 PSP_ASD_SHARED_MEM_SIZE = 0x0, 46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 49 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 50 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 52 }; 53 54 enum ta_type_id { 55 TA_TYPE_XGMI = 1, 56 TA_TYPE_RAS, 57 TA_TYPE_HDCP, 58 TA_TYPE_DTM, 59 TA_TYPE_RAP, 60 TA_TYPE_SECUREDISPLAY, 61 62 TA_TYPE_MAX_INDEX, 63 }; 64 65 struct psp_context; 66 struct psp_xgmi_node_info; 67 struct psp_xgmi_topology_info; 68 struct psp_bin_desc; 69 70 enum psp_bootloader_cmd { 71 PSP_BL__LOAD_SYSDRV = 0x10000, 72 PSP_BL__LOAD_SOSDRV = 0x20000, 73 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 74 PSP_BL__LOAD_SOCDRV = 0xB0000, 75 PSP_BL__LOAD_DBGDRV = 0xC0000, 76 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 77 PSP_BL__LOAD_INTFDRV = 0xD0000, 78 PSP_BL__LOAD_RASDRV = 0xE0000, 79 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 80 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 81 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 82 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 83 PSP_BL__LOAD_SPDMDRV = 0x20000000, 84 }; 85 86 enum psp_ring_type { 87 PSP_RING_TYPE__INVALID = 0, 88 /* 89 * These values map to the way the PSP kernel identifies the 90 * rings. 91 */ 92 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 93 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 94 }; 95 96 struct psp_ring { 97 enum psp_ring_type ring_type; 98 struct psp_gfx_rb_frame *ring_mem; 99 uint64_t ring_mem_mc_addr; 100 void *ring_mem_handle; 101 uint32_t ring_size; 102 uint32_t ring_wptr; 103 }; 104 105 /* More registers may will be supported */ 106 enum psp_reg_prog_id { 107 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 108 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 109 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 110 PSP_REG_MMHUB_L1_TLB_CNTL = 25, 111 PSP_REG_LAST 112 }; 113 114 struct psp_funcs { 115 int (*init_microcode)(struct psp_context *psp); 116 int (*wait_for_bootloader)(struct psp_context *psp); 117 int (*bootloader_load_kdb)(struct psp_context *psp); 118 int (*bootloader_load_spl)(struct psp_context *psp); 119 int (*bootloader_load_sysdrv)(struct psp_context *psp); 120 int (*bootloader_load_soc_drv)(struct psp_context *psp); 121 int (*bootloader_load_intf_drv)(struct psp_context *psp); 122 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 123 int (*bootloader_load_ras_drv)(struct psp_context *psp); 124 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 125 int (*bootloader_load_spdm_drv)(struct psp_context *psp); 126 int (*bootloader_load_sos)(struct psp_context *psp); 127 int (*ring_create)(struct psp_context *psp, 128 enum psp_ring_type ring_type); 129 int (*ring_stop)(struct psp_context *psp, 130 enum psp_ring_type ring_type); 131 int (*ring_destroy)(struct psp_context *psp, 132 enum psp_ring_type ring_type); 133 bool (*smu_reload_quirk)(struct psp_context *psp); 134 int (*mode1_reset)(struct psp_context *psp); 135 int (*mem_training)(struct psp_context *psp, uint32_t ops); 136 uint32_t (*ring_get_wptr)(struct psp_context *psp); 137 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 138 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 139 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 140 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 141 int (*vbflash_stat)(struct psp_context *psp); 142 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 143 bool (*get_ras_capability)(struct psp_context *psp); 144 bool (*is_aux_sos_load_required)(struct psp_context *psp); 145 bool (*is_reload_needed)(struct psp_context *psp); 146 int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val, 147 enum psp_reg_prog_id id); 148 }; 149 150 struct ta_funcs { 151 int (*fn_ta_initialize)(struct psp_context *psp); 152 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 153 int (*fn_ta_terminate)(struct psp_context *psp); 154 }; 155 156 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 157 struct psp_xgmi_node_info { 158 uint64_t node_id; 159 uint8_t num_hops; 160 uint8_t is_sharing_enabled; 161 enum ta_xgmi_assigned_sdma_engine sdma_engine; 162 uint8_t num_links; 163 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 164 }; 165 166 struct psp_xgmi_topology_info { 167 uint32_t num_nodes; 168 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 169 }; 170 171 struct psp_bin_desc { 172 uint32_t fw_version; 173 uint32_t feature_version; 174 uint32_t size_bytes; 175 uint8_t *start_addr; 176 }; 177 178 struct ta_mem_context { 179 struct amdgpu_bo *shared_bo; 180 uint64_t shared_mc_addr; 181 void *shared_buf; 182 enum psp_shared_mem_size shared_mem_size; 183 }; 184 185 struct ta_context { 186 bool initialized; 187 uint32_t session_id; 188 uint32_t resp_status; 189 struct ta_mem_context mem_context; 190 struct psp_bin_desc bin_desc; 191 enum psp_gfx_cmd_id ta_load_type; 192 enum ta_type_id ta_type; 193 }; 194 195 struct ta_cp_context { 196 struct ta_context context; 197 struct mutex mutex; 198 }; 199 200 struct psp_xgmi_context { 201 struct ta_context context; 202 struct psp_xgmi_topology_info top_info; 203 bool supports_extended_data; 204 uint8_t xgmi_ta_caps; 205 }; 206 207 struct psp_ras_context { 208 struct ta_context context; 209 struct amdgpu_ras *ras; 210 struct mutex mutex; 211 }; 212 213 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 214 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 215 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 216 /*Define the VRAM size that will be encroached by BIST training.*/ 217 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 218 219 enum psp_memory_training_init_flag { 220 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 221 PSP_MEM_TRAIN_SUPPORT = 0x1, 222 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 223 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 224 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 225 }; 226 227 enum psp_memory_training_ops { 228 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 229 PSP_MEM_TRAIN_SAVE = 0x2, 230 PSP_MEM_TRAIN_RESTORE = 0x4, 231 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 232 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 233 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 234 }; 235 236 struct psp_memory_training_context { 237 /*training data size*/ 238 u64 train_data_size; 239 /* 240 * sys_cache 241 * cpu virtual address 242 * system memory buffer that used to store the training data. 243 */ 244 void *sys_cache; 245 246 /*vram offset of the p2c training data*/ 247 u64 p2c_train_data_offset; 248 249 /*vram offset of the c2p training data*/ 250 u64 c2p_train_data_offset; 251 struct amdgpu_bo *c2p_bo; 252 253 enum psp_memory_training_init_flag init; 254 u32 training_cnt; 255 bool enable_mem_training; 256 }; 257 258 /** PSP runtime DB **/ 259 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 260 #define PSP_RUNTIME_DB_OFFSET 0x100000 261 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 262 #define PSP_RUNTIME_DB_VER_1 0x0100 263 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 264 265 enum psp_runtime_entry_type { 266 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 267 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 268 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 269 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 270 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 271 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 272 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 273 }; 274 275 /* PSP runtime DB header */ 276 struct psp_runtime_data_header { 277 /* determine the existence of runtime db */ 278 uint16_t cookie; 279 /* version of runtime db */ 280 uint16_t version; 281 }; 282 283 /* PSP runtime DB entry */ 284 struct psp_runtime_entry { 285 /* type of runtime db entry */ 286 uint32_t entry_type; 287 /* offset of entry in bytes */ 288 uint16_t offset; 289 /* size of entry in bytes */ 290 uint16_t size; 291 }; 292 293 /* PSP runtime DB directory */ 294 struct psp_runtime_data_directory { 295 /* number of valid entries */ 296 uint16_t entry_count; 297 /* db entries*/ 298 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 299 }; 300 301 /* PSP runtime DB boot config feature bitmask */ 302 enum psp_runtime_boot_cfg_feature { 303 BOOT_CFG_FEATURE_GECC = 0x1, 304 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 305 }; 306 307 /* PSP run time DB SCPM authentication defines */ 308 enum psp_runtime_scpm_authentication { 309 SCPM_DISABLE = 0x0, 310 SCPM_ENABLE = 0x1, 311 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 312 }; 313 314 /* PSP runtime DB boot config entry */ 315 struct psp_runtime_boot_cfg_entry { 316 uint32_t boot_cfg_bitmask; 317 uint32_t reserved; 318 }; 319 320 /* PSP runtime DB SCPM entry */ 321 struct psp_runtime_scpm_entry { 322 enum psp_runtime_scpm_authentication scpm_status; 323 }; 324 325 struct psp_context { 326 struct amdgpu_device *adev; 327 struct psp_ring km_ring; 328 struct psp_gfx_cmd_resp *cmd; 329 330 const struct psp_funcs *funcs; 331 const struct ta_funcs *ta_funcs; 332 333 /* firmware buffer */ 334 struct amdgpu_bo *fw_pri_bo; 335 uint64_t fw_pri_mc_addr; 336 void *fw_pri_buf; 337 338 /* sos firmware */ 339 const struct firmware *sos_fw; 340 struct psp_bin_desc sys; 341 struct psp_bin_desc sos; 342 struct psp_bin_desc toc; 343 struct psp_bin_desc kdb; 344 struct psp_bin_desc spl; 345 struct psp_bin_desc rl; 346 struct psp_bin_desc soc_drv; 347 struct psp_bin_desc intf_drv; 348 struct psp_bin_desc dbg_drv; 349 struct psp_bin_desc ras_drv; 350 struct psp_bin_desc ipkeymgr_drv; 351 struct psp_bin_desc spdm_drv; 352 353 /* tmr buffer */ 354 struct amdgpu_bo *tmr_bo; 355 uint64_t tmr_mc_addr; 356 357 /* asd firmware */ 358 const struct firmware *asd_fw; 359 360 /* toc firmware */ 361 const struct firmware *toc_fw; 362 363 /* cap firmware */ 364 const struct firmware *cap_fw; 365 366 /* fence buffer */ 367 struct amdgpu_bo *fence_buf_bo; 368 uint64_t fence_buf_mc_addr; 369 void *fence_buf; 370 371 /* cmd buffer */ 372 struct amdgpu_bo *cmd_buf_bo; 373 uint64_t cmd_buf_mc_addr; 374 struct psp_gfx_cmd_resp *cmd_buf_mem; 375 376 /* fence value associated with cmd buffer */ 377 atomic_t fence_value; 378 /* flag to mark whether gfx fw autoload is supported or not */ 379 bool autoload_supported; 380 /* flag to mark whether psp use runtime TMR or boottime TMR */ 381 bool boot_time_tmr; 382 /* flag to mark whether df cstate management centralized to PMFW */ 383 bool pmfw_centralized_cstate_management; 384 385 /* xgmi ta firmware and buffer */ 386 const struct firmware *ta_fw; 387 uint32_t ta_fw_version; 388 389 uint32_t cap_fw_version; 390 uint32_t cap_feature_version; 391 uint32_t cap_ucode_size; 392 393 struct ta_context asd_context; 394 struct psp_xgmi_context xgmi_context; 395 struct psp_ras_context ras_context; 396 struct ta_cp_context hdcp_context; 397 struct ta_cp_context dtm_context; 398 struct ta_cp_context rap_context; 399 struct ta_cp_context securedisplay_context; 400 struct mutex mutex; 401 struct psp_memory_training_context mem_train_ctx; 402 403 uint32_t boot_cfg_bitmask; 404 405 /* firmware upgrades supported */ 406 bool sup_pd_fw_up; 407 bool sup_ifwi_up; 408 409 char *vbflash_tmp_buf; 410 size_t vbflash_image_size; 411 bool vbflash_done; 412 }; 413 414 struct amdgpu_psp_funcs { 415 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 416 enum AMDGPU_UCODE_ID); 417 }; 418 419 420 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 421 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 422 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 423 #define psp_init_microcode(psp) \ 424 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 425 #define psp_bootloader_load_kdb(psp) \ 426 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 427 #define psp_bootloader_load_spl(psp) \ 428 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 429 #define psp_bootloader_load_sysdrv(psp) \ 430 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 431 #define psp_bootloader_load_soc_drv(psp) \ 432 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 433 #define psp_bootloader_load_intf_drv(psp) \ 434 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 435 #define psp_bootloader_load_dbg_drv(psp) \ 436 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 437 #define psp_bootloader_load_ras_drv(psp) \ 438 ((psp)->funcs->bootloader_load_ras_drv ? \ 439 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 440 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 441 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 442 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 443 #define psp_bootloader_load_spdm_drv(psp) \ 444 ((psp)->funcs->bootloader_load_spdm_drv ? \ 445 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0) 446 #define psp_bootloader_load_sos(psp) \ 447 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 448 #define psp_smu_reload_quirk(psp) \ 449 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 450 #define psp_mode1_reset(psp) \ 451 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 452 #define psp_mem_training(psp, ops) \ 453 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 454 455 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 456 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 457 458 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 459 ((psp)->funcs->load_usbc_pd_fw ? \ 460 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 461 462 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 463 ((psp)->funcs->read_usbc_pd_fw ? \ 464 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 465 466 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 467 ((psp)->funcs->update_spirom ? \ 468 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 469 470 #define psp_vbflash_status(psp) \ 471 ((psp)->funcs->vbflash_stat ? \ 472 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 473 474 #define psp_fatal_error_recovery_quirk(psp) \ 475 ((psp)->funcs->fatal_error_recovery_quirk ? \ 476 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 477 478 #define psp_is_aux_sos_load_required(psp) \ 479 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) 480 481 #define psp_reg_program_no_ring(psp, val, id) \ 482 ((psp)->funcs->reg_program_no_ring ? \ 483 (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL) 484 485 extern const struct amd_ip_funcs psp_ip_funcs; 486 487 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 488 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 489 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 490 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 491 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 492 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 493 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 494 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 495 496 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 497 uint32_t field_val, uint32_t mask, bool check_changed); 498 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 499 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 500 501 int psp_execute_ip_fw_load(struct psp_context *psp, 502 struct amdgpu_firmware_info *ucode); 503 504 int psp_gpu_reset(struct amdgpu_device *adev); 505 506 int psp_ta_init_shared_buf(struct psp_context *psp, 507 struct ta_mem_context *mem_ctx); 508 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 509 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 510 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 511 int psp_ta_invoke(struct psp_context *psp, 512 uint32_t ta_cmd_id, 513 struct ta_context *context); 514 515 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 516 int psp_xgmi_terminate(struct psp_context *psp); 517 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 518 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 519 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 520 int psp_xgmi_get_topology_info(struct psp_context *psp, 521 int number_devices, 522 struct psp_xgmi_topology_info *topology, 523 bool get_extended_data); 524 int psp_xgmi_set_topology_info(struct psp_context *psp, 525 int number_devices, 526 struct psp_xgmi_topology_info *topology); 527 int psp_ras_initialize(struct psp_context *psp); 528 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 529 int psp_ras_enable_features(struct psp_context *psp, 530 union ta_ras_cmd_input *info, bool enable); 531 int psp_ras_trigger_error(struct psp_context *psp, 532 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 533 int psp_ras_terminate(struct psp_context *psp); 534 int psp_ras_query_address(struct psp_context *psp, 535 struct ta_ras_query_address_input *addr_in, 536 struct ta_ras_query_address_output *addr_out); 537 538 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 539 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 540 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 541 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 542 543 int psp_rlc_autoload_start(struct psp_context *psp); 544 545 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 546 uint32_t value); 547 int psp_ring_cmd_submit(struct psp_context *psp, 548 uint64_t cmd_buf_mc_addr, 549 uint64_t fence_mc_addr, 550 int index); 551 int psp_init_asd_microcode(struct psp_context *psp, 552 const char *chip_name); 553 int psp_init_toc_microcode(struct psp_context *psp, 554 const char *chip_name); 555 int psp_init_sos_microcode(struct psp_context *psp, 556 const char *chip_name); 557 int psp_init_ta_microcode(struct psp_context *psp, 558 const char *chip_name); 559 int psp_init_cap_microcode(struct psp_context *psp, 560 const char *chip_name); 561 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 562 uint64_t *output_ptr); 563 564 int psp_load_fw_list(struct psp_context *psp, 565 struct amdgpu_firmware_info **ucode_list, int ucode_count); 566 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 567 568 int psp_spatial_partition(struct psp_context *psp, int mode); 569 int psp_memory_partition(struct psp_context *psp, int mode); 570 571 int is_psp_fw_valid(struct psp_bin_desc bin); 572 573 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 574 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 575 576 int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, 577 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 578 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); 579 int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, 580 enum psp_reg_prog_id id); 581 582 583 #endif 584