1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 extern const struct attribute_group amdgpu_flash_attr_group; 43 44 enum psp_shared_mem_size { 45 PSP_ASD_SHARED_MEM_SIZE = 0x0, 46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 49 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 50 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 52 }; 53 54 enum ta_type_id { 55 TA_TYPE_XGMI = 1, 56 TA_TYPE_RAS, 57 TA_TYPE_HDCP, 58 TA_TYPE_DTM, 59 TA_TYPE_RAP, 60 TA_TYPE_SECUREDISPLAY, 61 62 TA_TYPE_MAX_INDEX, 63 }; 64 65 struct psp_context; 66 struct psp_xgmi_node_info; 67 struct psp_xgmi_topology_info; 68 struct psp_bin_desc; 69 70 enum psp_bootloader_cmd { 71 PSP_BL__LOAD_SYSDRV = 0x10000, 72 PSP_BL__LOAD_SOSDRV = 0x20000, 73 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 74 PSP_BL__LOAD_SOCDRV = 0xB0000, 75 PSP_BL__LOAD_DBGDRV = 0xC0000, 76 PSP_BL__LOAD_INTFDRV = 0xD0000, 77 PSP_BL__LOAD_RASDRV = 0xE0000, 78 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 79 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 80 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 81 }; 82 83 enum psp_ring_type { 84 PSP_RING_TYPE__INVALID = 0, 85 /* 86 * These values map to the way the PSP kernel identifies the 87 * rings. 88 */ 89 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 90 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 91 }; 92 93 struct psp_ring { 94 enum psp_ring_type ring_type; 95 struct psp_gfx_rb_frame *ring_mem; 96 uint64_t ring_mem_mc_addr; 97 void *ring_mem_handle; 98 uint32_t ring_size; 99 uint32_t ring_wptr; 100 }; 101 102 /* More registers may will be supported */ 103 enum psp_reg_prog_id { 104 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 105 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 106 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 107 PSP_REG_LAST 108 }; 109 110 struct psp_funcs { 111 int (*init_microcode)(struct psp_context *psp); 112 int (*wait_for_bootloader)(struct psp_context *psp); 113 int (*bootloader_load_kdb)(struct psp_context *psp); 114 int (*bootloader_load_spl)(struct psp_context *psp); 115 int (*bootloader_load_sysdrv)(struct psp_context *psp); 116 int (*bootloader_load_soc_drv)(struct psp_context *psp); 117 int (*bootloader_load_intf_drv)(struct psp_context *psp); 118 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 119 int (*bootloader_load_ras_drv)(struct psp_context *psp); 120 int (*bootloader_load_sos)(struct psp_context *psp); 121 int (*ring_create)(struct psp_context *psp, 122 enum psp_ring_type ring_type); 123 int (*ring_stop)(struct psp_context *psp, 124 enum psp_ring_type ring_type); 125 int (*ring_destroy)(struct psp_context *psp, 126 enum psp_ring_type ring_type); 127 bool (*smu_reload_quirk)(struct psp_context *psp); 128 int (*mode1_reset)(struct psp_context *psp); 129 int (*mem_training)(struct psp_context *psp, uint32_t ops); 130 uint32_t (*ring_get_wptr)(struct psp_context *psp); 131 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 132 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 133 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 134 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 135 int (*vbflash_stat)(struct psp_context *psp); 136 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 137 int (*query_boot_status)(struct psp_context *psp); 138 }; 139 140 struct ta_funcs { 141 int (*fn_ta_initialize)(struct psp_context *psp); 142 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 143 int (*fn_ta_terminate)(struct psp_context *psp); 144 }; 145 146 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 147 struct psp_xgmi_node_info { 148 uint64_t node_id; 149 uint8_t num_hops; 150 uint8_t is_sharing_enabled; 151 enum ta_xgmi_assigned_sdma_engine sdma_engine; 152 uint8_t num_links; 153 }; 154 155 struct psp_xgmi_topology_info { 156 uint32_t num_nodes; 157 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 158 }; 159 160 struct psp_bin_desc { 161 uint32_t fw_version; 162 uint32_t feature_version; 163 uint32_t size_bytes; 164 uint8_t *start_addr; 165 }; 166 167 struct ta_mem_context { 168 struct amdgpu_bo *shared_bo; 169 uint64_t shared_mc_addr; 170 void *shared_buf; 171 enum psp_shared_mem_size shared_mem_size; 172 }; 173 174 struct ta_context { 175 bool initialized; 176 uint32_t session_id; 177 uint32_t resp_status; 178 struct ta_mem_context mem_context; 179 struct psp_bin_desc bin_desc; 180 enum psp_gfx_cmd_id ta_load_type; 181 enum ta_type_id ta_type; 182 }; 183 184 struct ta_cp_context { 185 struct ta_context context; 186 struct mutex mutex; 187 }; 188 189 struct psp_xgmi_context { 190 struct ta_context context; 191 struct psp_xgmi_topology_info top_info; 192 bool supports_extended_data; 193 uint8_t xgmi_ta_caps; 194 }; 195 196 struct psp_ras_context { 197 struct ta_context context; 198 struct amdgpu_ras *ras; 199 }; 200 201 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 202 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 203 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 204 /*Define the VRAM size that will be encroached by BIST training.*/ 205 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 206 207 enum psp_memory_training_init_flag { 208 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 209 PSP_MEM_TRAIN_SUPPORT = 0x1, 210 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 211 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 212 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 213 }; 214 215 enum psp_memory_training_ops { 216 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 217 PSP_MEM_TRAIN_SAVE = 0x2, 218 PSP_MEM_TRAIN_RESTORE = 0x4, 219 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 220 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 221 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 222 }; 223 224 struct psp_memory_training_context { 225 /*training data size*/ 226 u64 train_data_size; 227 /* 228 * sys_cache 229 * cpu virtual address 230 * system memory buffer that used to store the training data. 231 */ 232 void *sys_cache; 233 234 /*vram offset of the p2c training data*/ 235 u64 p2c_train_data_offset; 236 237 /*vram offset of the c2p training data*/ 238 u64 c2p_train_data_offset; 239 struct amdgpu_bo *c2p_bo; 240 241 enum psp_memory_training_init_flag init; 242 u32 training_cnt; 243 bool enable_mem_training; 244 }; 245 246 /** PSP runtime DB **/ 247 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 248 #define PSP_RUNTIME_DB_OFFSET 0x100000 249 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 250 #define PSP_RUNTIME_DB_VER_1 0x0100 251 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 252 253 enum psp_runtime_entry_type { 254 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 255 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 256 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 257 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 258 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 259 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 260 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 261 }; 262 263 /* PSP runtime DB header */ 264 struct psp_runtime_data_header { 265 /* determine the existence of runtime db */ 266 uint16_t cookie; 267 /* version of runtime db */ 268 uint16_t version; 269 }; 270 271 /* PSP runtime DB entry */ 272 struct psp_runtime_entry { 273 /* type of runtime db entry */ 274 uint32_t entry_type; 275 /* offset of entry in bytes */ 276 uint16_t offset; 277 /* size of entry in bytes */ 278 uint16_t size; 279 }; 280 281 /* PSP runtime DB directory */ 282 struct psp_runtime_data_directory { 283 /* number of valid entries */ 284 uint16_t entry_count; 285 /* db entries*/ 286 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 287 }; 288 289 /* PSP runtime DB boot config feature bitmask */ 290 enum psp_runtime_boot_cfg_feature { 291 BOOT_CFG_FEATURE_GECC = 0x1, 292 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 293 }; 294 295 /* PSP run time DB SCPM authentication defines */ 296 enum psp_runtime_scpm_authentication { 297 SCPM_DISABLE = 0x0, 298 SCPM_ENABLE = 0x1, 299 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 300 }; 301 302 /* PSP runtime DB boot config entry */ 303 struct psp_runtime_boot_cfg_entry { 304 uint32_t boot_cfg_bitmask; 305 uint32_t reserved; 306 }; 307 308 /* PSP runtime DB SCPM entry */ 309 struct psp_runtime_scpm_entry { 310 enum psp_runtime_scpm_authentication scpm_status; 311 }; 312 313 struct psp_context { 314 struct amdgpu_device *adev; 315 struct psp_ring km_ring; 316 struct psp_gfx_cmd_resp *cmd; 317 318 const struct psp_funcs *funcs; 319 const struct ta_funcs *ta_funcs; 320 321 /* firmware buffer */ 322 struct amdgpu_bo *fw_pri_bo; 323 uint64_t fw_pri_mc_addr; 324 void *fw_pri_buf; 325 326 /* sos firmware */ 327 const struct firmware *sos_fw; 328 struct psp_bin_desc sys; 329 struct psp_bin_desc sos; 330 struct psp_bin_desc toc; 331 struct psp_bin_desc kdb; 332 struct psp_bin_desc spl; 333 struct psp_bin_desc rl; 334 struct psp_bin_desc soc_drv; 335 struct psp_bin_desc intf_drv; 336 struct psp_bin_desc dbg_drv; 337 struct psp_bin_desc ras_drv; 338 339 /* tmr buffer */ 340 struct amdgpu_bo *tmr_bo; 341 uint64_t tmr_mc_addr; 342 343 /* asd firmware */ 344 const struct firmware *asd_fw; 345 346 /* toc firmware */ 347 const struct firmware *toc_fw; 348 349 /* cap firmware */ 350 const struct firmware *cap_fw; 351 352 /* fence buffer */ 353 struct amdgpu_bo *fence_buf_bo; 354 uint64_t fence_buf_mc_addr; 355 void *fence_buf; 356 357 /* cmd buffer */ 358 struct amdgpu_bo *cmd_buf_bo; 359 uint64_t cmd_buf_mc_addr; 360 struct psp_gfx_cmd_resp *cmd_buf_mem; 361 362 /* fence value associated with cmd buffer */ 363 atomic_t fence_value; 364 /* flag to mark whether gfx fw autoload is supported or not */ 365 bool autoload_supported; 366 /* flag to mark whether df cstate management centralized to PMFW */ 367 bool pmfw_centralized_cstate_management; 368 369 /* xgmi ta firmware and buffer */ 370 const struct firmware *ta_fw; 371 uint32_t ta_fw_version; 372 373 uint32_t cap_fw_version; 374 uint32_t cap_feature_version; 375 uint32_t cap_ucode_size; 376 377 struct ta_context asd_context; 378 struct psp_xgmi_context xgmi_context; 379 struct psp_ras_context ras_context; 380 struct ta_cp_context hdcp_context; 381 struct ta_cp_context dtm_context; 382 struct ta_cp_context rap_context; 383 struct ta_cp_context securedisplay_context; 384 struct mutex mutex; 385 struct psp_memory_training_context mem_train_ctx; 386 387 uint32_t boot_cfg_bitmask; 388 389 /* firmware upgrades supported */ 390 bool sup_pd_fw_up; 391 bool sup_ifwi_up; 392 393 char *vbflash_tmp_buf; 394 size_t vbflash_image_size; 395 bool vbflash_done; 396 }; 397 398 struct amdgpu_psp_funcs { 399 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 400 enum AMDGPU_UCODE_ID); 401 }; 402 403 404 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 405 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 406 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 407 #define psp_init_microcode(psp) \ 408 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 409 #define psp_bootloader_load_kdb(psp) \ 410 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 411 #define psp_bootloader_load_spl(psp) \ 412 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 413 #define psp_bootloader_load_sysdrv(psp) \ 414 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 415 #define psp_bootloader_load_soc_drv(psp) \ 416 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 417 #define psp_bootloader_load_intf_drv(psp) \ 418 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 419 #define psp_bootloader_load_dbg_drv(psp) \ 420 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 421 #define psp_bootloader_load_ras_drv(psp) \ 422 ((psp)->funcs->bootloader_load_ras_drv ? \ 423 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 424 #define psp_bootloader_load_sos(psp) \ 425 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 426 #define psp_smu_reload_quirk(psp) \ 427 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 428 #define psp_mode1_reset(psp) \ 429 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 430 #define psp_mem_training(psp, ops) \ 431 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 432 433 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 434 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 435 436 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 437 ((psp)->funcs->load_usbc_pd_fw ? \ 438 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 439 440 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 441 ((psp)->funcs->read_usbc_pd_fw ? \ 442 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 443 444 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 445 ((psp)->funcs->update_spirom ? \ 446 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 447 448 #define psp_vbflash_status(psp) \ 449 ((psp)->funcs->vbflash_stat ? \ 450 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 451 452 #define psp_fatal_error_recovery_quirk(psp) \ 453 ((psp)->funcs->fatal_error_recovery_quirk ? \ 454 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 455 456 extern const struct amd_ip_funcs psp_ip_funcs; 457 458 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 459 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 460 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 461 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 462 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 463 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 464 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 465 466 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 467 uint32_t field_val, uint32_t mask, bool check_changed); 468 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 469 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 470 471 int psp_execute_ip_fw_load(struct psp_context *psp, 472 struct amdgpu_firmware_info *ucode); 473 474 int psp_gpu_reset(struct amdgpu_device *adev); 475 476 int psp_ta_init_shared_buf(struct psp_context *psp, 477 struct ta_mem_context *mem_ctx); 478 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 479 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 480 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 481 int psp_ta_invoke(struct psp_context *psp, 482 uint32_t ta_cmd_id, 483 struct ta_context *context); 484 485 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 486 int psp_xgmi_terminate(struct psp_context *psp); 487 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 488 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 489 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 490 int psp_xgmi_get_topology_info(struct psp_context *psp, 491 int number_devices, 492 struct psp_xgmi_topology_info *topology, 493 bool get_extended_data); 494 int psp_xgmi_set_topology_info(struct psp_context *psp, 495 int number_devices, 496 struct psp_xgmi_topology_info *topology); 497 int psp_ras_initialize(struct psp_context *psp); 498 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 499 int psp_ras_enable_features(struct psp_context *psp, 500 union ta_ras_cmd_input *info, bool enable); 501 int psp_ras_trigger_error(struct psp_context *psp, 502 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 503 int psp_ras_terminate(struct psp_context *psp); 504 505 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 506 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 507 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 508 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 509 510 int psp_rlc_autoload_start(struct psp_context *psp); 511 512 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 513 uint32_t value); 514 int psp_ring_cmd_submit(struct psp_context *psp, 515 uint64_t cmd_buf_mc_addr, 516 uint64_t fence_mc_addr, 517 int index); 518 int psp_init_asd_microcode(struct psp_context *psp, 519 const char *chip_name); 520 int psp_init_toc_microcode(struct psp_context *psp, 521 const char *chip_name); 522 int psp_init_sos_microcode(struct psp_context *psp, 523 const char *chip_name); 524 int psp_init_ta_microcode(struct psp_context *psp, 525 const char *chip_name); 526 int psp_init_cap_microcode(struct psp_context *psp, 527 const char *chip_name); 528 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 529 uint64_t *output_ptr); 530 531 int psp_load_fw_list(struct psp_context *psp, 532 struct amdgpu_firmware_info **ucode_list, int ucode_count); 533 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 534 535 int psp_spatial_partition(struct psp_context *psp, int mode); 536 537 int is_psp_fw_valid(struct psp_bin_desc bin); 538 539 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 540 541 int amdgpu_psp_query_boot_status(struct amdgpu_device *adev); 542 543 #endif 544