1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 extern const struct attribute_group amdgpu_flash_attr_group; 43 44 enum psp_shared_mem_size { 45 PSP_ASD_SHARED_MEM_SIZE = 0x0, 46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 49 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 50 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 52 }; 53 54 enum ta_type_id { 55 TA_TYPE_XGMI = 1, 56 TA_TYPE_RAS, 57 TA_TYPE_HDCP, 58 TA_TYPE_DTM, 59 TA_TYPE_RAP, 60 TA_TYPE_SECUREDISPLAY, 61 62 TA_TYPE_MAX_INDEX, 63 }; 64 65 struct psp_context; 66 struct psp_xgmi_node_info; 67 struct psp_xgmi_topology_info; 68 struct psp_bin_desc; 69 70 enum psp_bootloader_cmd { 71 PSP_BL__LOAD_SYSDRV = 0x10000, 72 PSP_BL__LOAD_SOSDRV = 0x20000, 73 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 74 PSP_BL__LOAD_SOCDRV = 0xB0000, 75 PSP_BL__LOAD_DBGDRV = 0xC0000, 76 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 77 PSP_BL__LOAD_INTFDRV = 0xD0000, 78 PSP_BL__LOAD_RASDRV = 0xE0000, 79 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 80 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 81 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 82 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 83 }; 84 85 enum psp_ring_type { 86 PSP_RING_TYPE__INVALID = 0, 87 /* 88 * These values map to the way the PSP kernel identifies the 89 * rings. 90 */ 91 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 92 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 93 }; 94 95 struct psp_ring { 96 enum psp_ring_type ring_type; 97 struct psp_gfx_rb_frame *ring_mem; 98 uint64_t ring_mem_mc_addr; 99 void *ring_mem_handle; 100 uint32_t ring_size; 101 uint32_t ring_wptr; 102 }; 103 104 /* More registers may will be supported */ 105 enum psp_reg_prog_id { 106 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 107 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 108 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 109 PSP_REG_LAST 110 }; 111 112 struct psp_funcs { 113 int (*init_microcode)(struct psp_context *psp); 114 int (*wait_for_bootloader)(struct psp_context *psp); 115 int (*bootloader_load_kdb)(struct psp_context *psp); 116 int (*bootloader_load_spl)(struct psp_context *psp); 117 int (*bootloader_load_sysdrv)(struct psp_context *psp); 118 int (*bootloader_load_soc_drv)(struct psp_context *psp); 119 int (*bootloader_load_intf_drv)(struct psp_context *psp); 120 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 121 int (*bootloader_load_ras_drv)(struct psp_context *psp); 122 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 123 int (*bootloader_load_sos)(struct psp_context *psp); 124 int (*ring_create)(struct psp_context *psp, 125 enum psp_ring_type ring_type); 126 int (*ring_stop)(struct psp_context *psp, 127 enum psp_ring_type ring_type); 128 int (*ring_destroy)(struct psp_context *psp, 129 enum psp_ring_type ring_type); 130 bool (*smu_reload_quirk)(struct psp_context *psp); 131 int (*mode1_reset)(struct psp_context *psp); 132 int (*mem_training)(struct psp_context *psp, uint32_t ops); 133 uint32_t (*ring_get_wptr)(struct psp_context *psp); 134 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 135 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 136 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 137 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 138 int (*vbflash_stat)(struct psp_context *psp); 139 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 140 bool (*get_ras_capability)(struct psp_context *psp); 141 bool (*is_aux_sos_load_required)(struct psp_context *psp); 142 bool (*is_reload_needed)(struct psp_context *psp); 143 }; 144 145 struct ta_funcs { 146 int (*fn_ta_initialize)(struct psp_context *psp); 147 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 148 int (*fn_ta_terminate)(struct psp_context *psp); 149 }; 150 151 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 152 struct psp_xgmi_node_info { 153 uint64_t node_id; 154 uint8_t num_hops; 155 uint8_t is_sharing_enabled; 156 enum ta_xgmi_assigned_sdma_engine sdma_engine; 157 uint8_t num_links; 158 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 159 }; 160 161 struct psp_xgmi_topology_info { 162 uint32_t num_nodes; 163 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 164 }; 165 166 struct psp_bin_desc { 167 uint32_t fw_version; 168 uint32_t feature_version; 169 uint32_t size_bytes; 170 uint8_t *start_addr; 171 }; 172 173 struct ta_mem_context { 174 struct amdgpu_bo *shared_bo; 175 uint64_t shared_mc_addr; 176 void *shared_buf; 177 enum psp_shared_mem_size shared_mem_size; 178 }; 179 180 struct ta_context { 181 bool initialized; 182 uint32_t session_id; 183 uint32_t resp_status; 184 struct ta_mem_context mem_context; 185 struct psp_bin_desc bin_desc; 186 enum psp_gfx_cmd_id ta_load_type; 187 enum ta_type_id ta_type; 188 }; 189 190 struct ta_cp_context { 191 struct ta_context context; 192 struct mutex mutex; 193 }; 194 195 struct psp_xgmi_context { 196 struct ta_context context; 197 struct psp_xgmi_topology_info top_info; 198 bool supports_extended_data; 199 uint8_t xgmi_ta_caps; 200 }; 201 202 struct psp_ras_context { 203 struct ta_context context; 204 struct amdgpu_ras *ras; 205 struct mutex mutex; 206 }; 207 208 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 209 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 210 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 211 /*Define the VRAM size that will be encroached by BIST training.*/ 212 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 213 214 enum psp_memory_training_init_flag { 215 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 216 PSP_MEM_TRAIN_SUPPORT = 0x1, 217 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 218 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 219 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 220 }; 221 222 enum psp_memory_training_ops { 223 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 224 PSP_MEM_TRAIN_SAVE = 0x2, 225 PSP_MEM_TRAIN_RESTORE = 0x4, 226 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 227 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 228 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 229 }; 230 231 struct psp_memory_training_context { 232 /*training data size*/ 233 u64 train_data_size; 234 /* 235 * sys_cache 236 * cpu virtual address 237 * system memory buffer that used to store the training data. 238 */ 239 void *sys_cache; 240 241 /*vram offset of the p2c training data*/ 242 u64 p2c_train_data_offset; 243 244 /*vram offset of the c2p training data*/ 245 u64 c2p_train_data_offset; 246 struct amdgpu_bo *c2p_bo; 247 248 enum psp_memory_training_init_flag init; 249 u32 training_cnt; 250 bool enable_mem_training; 251 }; 252 253 /** PSP runtime DB **/ 254 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 255 #define PSP_RUNTIME_DB_OFFSET 0x100000 256 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 257 #define PSP_RUNTIME_DB_VER_1 0x0100 258 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 259 260 enum psp_runtime_entry_type { 261 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 262 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 263 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 264 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 265 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 266 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 267 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 268 }; 269 270 /* PSP runtime DB header */ 271 struct psp_runtime_data_header { 272 /* determine the existence of runtime db */ 273 uint16_t cookie; 274 /* version of runtime db */ 275 uint16_t version; 276 }; 277 278 /* PSP runtime DB entry */ 279 struct psp_runtime_entry { 280 /* type of runtime db entry */ 281 uint32_t entry_type; 282 /* offset of entry in bytes */ 283 uint16_t offset; 284 /* size of entry in bytes */ 285 uint16_t size; 286 }; 287 288 /* PSP runtime DB directory */ 289 struct psp_runtime_data_directory { 290 /* number of valid entries */ 291 uint16_t entry_count; 292 /* db entries*/ 293 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 294 }; 295 296 /* PSP runtime DB boot config feature bitmask */ 297 enum psp_runtime_boot_cfg_feature { 298 BOOT_CFG_FEATURE_GECC = 0x1, 299 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 300 }; 301 302 /* PSP run time DB SCPM authentication defines */ 303 enum psp_runtime_scpm_authentication { 304 SCPM_DISABLE = 0x0, 305 SCPM_ENABLE = 0x1, 306 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 307 }; 308 309 /* PSP runtime DB boot config entry */ 310 struct psp_runtime_boot_cfg_entry { 311 uint32_t boot_cfg_bitmask; 312 uint32_t reserved; 313 }; 314 315 /* PSP runtime DB SCPM entry */ 316 struct psp_runtime_scpm_entry { 317 enum psp_runtime_scpm_authentication scpm_status; 318 }; 319 320 struct psp_context { 321 struct amdgpu_device *adev; 322 struct psp_ring km_ring; 323 struct psp_gfx_cmd_resp *cmd; 324 325 const struct psp_funcs *funcs; 326 const struct ta_funcs *ta_funcs; 327 328 /* firmware buffer */ 329 struct amdgpu_bo *fw_pri_bo; 330 uint64_t fw_pri_mc_addr; 331 void *fw_pri_buf; 332 333 /* sos firmware */ 334 const struct firmware *sos_fw; 335 struct psp_bin_desc sys; 336 struct psp_bin_desc sos; 337 struct psp_bin_desc toc; 338 struct psp_bin_desc kdb; 339 struct psp_bin_desc spl; 340 struct psp_bin_desc rl; 341 struct psp_bin_desc soc_drv; 342 struct psp_bin_desc intf_drv; 343 struct psp_bin_desc dbg_drv; 344 struct psp_bin_desc ras_drv; 345 struct psp_bin_desc ipkeymgr_drv; 346 347 /* tmr buffer */ 348 struct amdgpu_bo *tmr_bo; 349 uint64_t tmr_mc_addr; 350 351 /* asd firmware */ 352 const struct firmware *asd_fw; 353 354 /* toc firmware */ 355 const struct firmware *toc_fw; 356 357 /* cap firmware */ 358 const struct firmware *cap_fw; 359 360 /* fence buffer */ 361 struct amdgpu_bo *fence_buf_bo; 362 uint64_t fence_buf_mc_addr; 363 void *fence_buf; 364 365 /* cmd buffer */ 366 struct amdgpu_bo *cmd_buf_bo; 367 uint64_t cmd_buf_mc_addr; 368 struct psp_gfx_cmd_resp *cmd_buf_mem; 369 370 /* fence value associated with cmd buffer */ 371 atomic_t fence_value; 372 /* flag to mark whether gfx fw autoload is supported or not */ 373 bool autoload_supported; 374 /* flag to mark whether psp use runtime TMR or boottime TMR */ 375 bool boot_time_tmr; 376 /* flag to mark whether df cstate management centralized to PMFW */ 377 bool pmfw_centralized_cstate_management; 378 379 /* xgmi ta firmware and buffer */ 380 const struct firmware *ta_fw; 381 uint32_t ta_fw_version; 382 383 uint32_t cap_fw_version; 384 uint32_t cap_feature_version; 385 uint32_t cap_ucode_size; 386 387 struct ta_context asd_context; 388 struct psp_xgmi_context xgmi_context; 389 struct psp_ras_context ras_context; 390 struct ta_cp_context hdcp_context; 391 struct ta_cp_context dtm_context; 392 struct ta_cp_context rap_context; 393 struct ta_cp_context securedisplay_context; 394 struct mutex mutex; 395 struct psp_memory_training_context mem_train_ctx; 396 397 uint32_t boot_cfg_bitmask; 398 399 /* firmware upgrades supported */ 400 bool sup_pd_fw_up; 401 bool sup_ifwi_up; 402 403 char *vbflash_tmp_buf; 404 size_t vbflash_image_size; 405 bool vbflash_done; 406 }; 407 408 struct amdgpu_psp_funcs { 409 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 410 enum AMDGPU_UCODE_ID); 411 }; 412 413 414 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 415 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 416 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 417 #define psp_init_microcode(psp) \ 418 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 419 #define psp_bootloader_load_kdb(psp) \ 420 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 421 #define psp_bootloader_load_spl(psp) \ 422 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 423 #define psp_bootloader_load_sysdrv(psp) \ 424 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 425 #define psp_bootloader_load_soc_drv(psp) \ 426 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 427 #define psp_bootloader_load_intf_drv(psp) \ 428 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 429 #define psp_bootloader_load_dbg_drv(psp) \ 430 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 431 #define psp_bootloader_load_ras_drv(psp) \ 432 ((psp)->funcs->bootloader_load_ras_drv ? \ 433 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 434 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 435 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 436 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 437 #define psp_bootloader_load_sos(psp) \ 438 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 439 #define psp_smu_reload_quirk(psp) \ 440 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 441 #define psp_mode1_reset(psp) \ 442 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 443 #define psp_mem_training(psp, ops) \ 444 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 445 446 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 447 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 448 449 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 450 ((psp)->funcs->load_usbc_pd_fw ? \ 451 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 452 453 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 454 ((psp)->funcs->read_usbc_pd_fw ? \ 455 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 456 457 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 458 ((psp)->funcs->update_spirom ? \ 459 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 460 461 #define psp_vbflash_status(psp) \ 462 ((psp)->funcs->vbflash_stat ? \ 463 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 464 465 #define psp_fatal_error_recovery_quirk(psp) \ 466 ((psp)->funcs->fatal_error_recovery_quirk ? \ 467 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 468 469 #define psp_is_aux_sos_load_required(psp) \ 470 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) 471 472 extern const struct amd_ip_funcs psp_ip_funcs; 473 474 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 475 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 476 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 477 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 478 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 479 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 480 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 481 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 482 483 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 484 uint32_t field_val, uint32_t mask, bool check_changed); 485 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 486 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 487 488 int psp_execute_ip_fw_load(struct psp_context *psp, 489 struct amdgpu_firmware_info *ucode); 490 491 int psp_gpu_reset(struct amdgpu_device *adev); 492 493 int psp_ta_init_shared_buf(struct psp_context *psp, 494 struct ta_mem_context *mem_ctx); 495 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 496 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 497 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 498 int psp_ta_invoke(struct psp_context *psp, 499 uint32_t ta_cmd_id, 500 struct ta_context *context); 501 502 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 503 int psp_xgmi_terminate(struct psp_context *psp); 504 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 505 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 506 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 507 int psp_xgmi_get_topology_info(struct psp_context *psp, 508 int number_devices, 509 struct psp_xgmi_topology_info *topology, 510 bool get_extended_data); 511 int psp_xgmi_set_topology_info(struct psp_context *psp, 512 int number_devices, 513 struct psp_xgmi_topology_info *topology); 514 int psp_ras_initialize(struct psp_context *psp); 515 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 516 int psp_ras_enable_features(struct psp_context *psp, 517 union ta_ras_cmd_input *info, bool enable); 518 int psp_ras_trigger_error(struct psp_context *psp, 519 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 520 int psp_ras_terminate(struct psp_context *psp); 521 int psp_ras_query_address(struct psp_context *psp, 522 struct ta_ras_query_address_input *addr_in, 523 struct ta_ras_query_address_output *addr_out); 524 525 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 526 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 527 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 528 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 529 530 int psp_rlc_autoload_start(struct psp_context *psp); 531 532 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 533 uint32_t value); 534 int psp_ring_cmd_submit(struct psp_context *psp, 535 uint64_t cmd_buf_mc_addr, 536 uint64_t fence_mc_addr, 537 int index); 538 int psp_init_asd_microcode(struct psp_context *psp, 539 const char *chip_name); 540 int psp_init_toc_microcode(struct psp_context *psp, 541 const char *chip_name); 542 int psp_init_sos_microcode(struct psp_context *psp, 543 const char *chip_name); 544 int psp_init_ta_microcode(struct psp_context *psp, 545 const char *chip_name); 546 int psp_init_cap_microcode(struct psp_context *psp, 547 const char *chip_name); 548 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 549 uint64_t *output_ptr); 550 551 int psp_load_fw_list(struct psp_context *psp, 552 struct amdgpu_firmware_info **ucode_list, int ucode_count); 553 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 554 555 int psp_spatial_partition(struct psp_context *psp, int mode); 556 int psp_memory_partition(struct psp_context *psp, int mode); 557 558 int is_psp_fw_valid(struct psp_bin_desc bin); 559 560 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 561 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 562 563 int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, 564 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 565 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); 566 567 #endif 568