1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 #include <linux/bitops.h> 35 #include "amdgpu_ptl.h" 36 37 #define PSP_FENCE_BUFFER_SIZE 0x1000 38 #define PSP_CMD_BUFFER_SIZE 0x1000 39 #define PSP_1_MEG 0x100000 40 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 41 #define PSP_TMR_ALIGNMENT 0x100000 42 #define PSP_FW_NAME_LEN 0x24 43 44 /* VBIOS gfl defines */ 45 #define MBOX_READY_MASK 0x80000000 46 #define MBOX_STATUS_MASK 0x0000FFFF 47 #define MBOX_COMMAND_MASK 0x00FF0000 48 #define MBOX_READY_FLAG 0x80000000 49 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 50 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 51 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 52 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO 0xf 53 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10 54 #define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11 55 56 /* Command register bit 31 set to indicate readiness */ 57 #define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE) 58 #define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) 59 60 /* Values to check for a successful GFX_CMD response wait. Check against 61 * both status bits and response state - helps to detect a command failure 62 * or other unexpected cases like a device drop reading all 0xFFs 63 */ 64 #define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE) 65 #define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) 66 67 extern const struct attribute_group amdgpu_flash_attr_group; 68 69 enum psp_shared_mem_size { 70 PSP_ASD_SHARED_MEM_SIZE = 0x0, 71 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 72 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 73 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 74 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 75 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 76 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 77 }; 78 79 enum ta_type_id { 80 TA_TYPE_XGMI = 1, 81 TA_TYPE_RAS, 82 TA_TYPE_HDCP, 83 TA_TYPE_DTM, 84 TA_TYPE_RAP, 85 TA_TYPE_SECUREDISPLAY, 86 87 TA_TYPE_MAX_INDEX, 88 }; 89 90 struct psp_context; 91 struct psp_xgmi_node_info; 92 struct psp_xgmi_topology_info; 93 struct psp_bin_desc; 94 95 enum psp_bootloader_cmd { 96 PSP_BL__LOAD_SYSDRV = 0x10000, 97 PSP_BL__LOAD_SOSDRV = 0x20000, 98 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 99 PSP_BL__LOAD_SOCDRV = 0xB0000, 100 PSP_BL__LOAD_DBGDRV = 0xC0000, 101 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 102 PSP_BL__LOAD_INTFDRV = 0xD0000, 103 PSP_BL__LOAD_RASDRV = 0xE0000, 104 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 105 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 106 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 107 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 108 PSP_BL__LOAD_SPDMDRV = 0x20000000, 109 }; 110 111 enum psp_ring_type { 112 PSP_RING_TYPE__INVALID = 0, 113 /* 114 * These values map to the way the PSP kernel identifies the 115 * rings. 116 */ 117 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 118 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 119 }; 120 121 struct psp_ring { 122 enum psp_ring_type ring_type; 123 struct psp_gfx_rb_frame *ring_mem; 124 uint64_t ring_mem_mc_addr; 125 void *ring_mem_handle; 126 uint32_t ring_size; 127 uint32_t ring_wptr; 128 }; 129 130 /* More registers may will be supported */ 131 enum psp_reg_prog_id { 132 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 133 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 134 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 135 PSP_REG_MMHUB_L1_TLB_CNTL = 25, 136 PSP_REG_LAST 137 }; 138 139 #define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */ 140 #define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */ 141 142 struct amdgpu_psp_irq_mgr; 143 144 struct psp_funcs { 145 int (*init_microcode)(struct psp_context *psp); 146 int (*wait_for_bootloader)(struct psp_context *psp); 147 int (*bootloader_load_kdb)(struct psp_context *psp); 148 int (*bootloader_load_spl)(struct psp_context *psp); 149 int (*bootloader_load_sysdrv)(struct psp_context *psp); 150 int (*bootloader_load_soc_drv)(struct psp_context *psp); 151 int (*bootloader_load_intf_drv)(struct psp_context *psp); 152 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 153 int (*bootloader_load_ras_drv)(struct psp_context *psp); 154 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 155 int (*bootloader_load_spdm_drv)(struct psp_context *psp); 156 int (*bootloader_load_sos)(struct psp_context *psp); 157 int (*ring_create)(struct psp_context *psp, 158 enum psp_ring_type ring_type); 159 int (*ring_stop)(struct psp_context *psp, 160 enum psp_ring_type ring_type); 161 int (*ring_destroy)(struct psp_context *psp, 162 enum psp_ring_type ring_type); 163 bool (*smu_reload_quirk)(struct psp_context *psp); 164 int (*mode1_reset)(struct psp_context *psp); 165 int (*mem_training)(struct psp_context *psp, uint32_t ops); 166 uint32_t (*ring_get_wptr)(struct psp_context *psp); 167 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 168 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 169 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 170 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 171 int (*dump_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 172 int (*vbflash_stat)(struct psp_context *psp); 173 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 174 bool (*get_ras_capability)(struct psp_context *psp); 175 bool (*is_aux_sos_load_required)(struct psp_context *psp); 176 bool (*is_reload_needed)(struct psp_context *psp); 177 int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val, 178 enum psp_reg_prog_id id); 179 int (*get_fw_type)(struct amdgpu_firmware_info *ucode, 180 enum psp_gfx_fw_type *type); 181 int (*register_irq_handler)(struct amdgpu_psp_irq_mgr *mgr, 182 struct amdgpu_irq_src *irq_src); 183 }; 184 185 struct ta_funcs { 186 int (*fn_ta_initialize)(struct psp_context *psp); 187 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 188 int (*fn_ta_terminate)(struct psp_context *psp); 189 }; 190 191 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 192 struct psp_xgmi_node_info { 193 uint64_t node_id; 194 uint8_t num_hops; 195 uint8_t is_sharing_enabled; 196 enum ta_xgmi_assigned_sdma_engine sdma_engine; 197 uint8_t num_links; 198 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 199 }; 200 201 struct psp_xgmi_topology_info { 202 uint32_t num_nodes; 203 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 204 }; 205 206 struct psp_bin_desc { 207 uint32_t fw_version; 208 uint32_t feature_version; 209 uint32_t size_bytes; 210 uint8_t *start_addr; 211 }; 212 213 struct ta_mem_context { 214 struct amdgpu_bo *shared_bo; 215 uint64_t shared_mc_addr; 216 void *shared_buf; 217 enum psp_shared_mem_size shared_mem_size; 218 }; 219 220 struct ta_context { 221 bool initialized; 222 uint32_t session_id; 223 uint32_t resp_status; 224 struct ta_mem_context mem_context; 225 struct psp_bin_desc bin_desc; 226 enum psp_gfx_cmd_id ta_load_type; 227 enum ta_type_id ta_type; 228 }; 229 230 struct ta_cp_context { 231 struct ta_context context; 232 struct mutex mutex; 233 }; 234 235 struct psp_xgmi_context { 236 struct ta_context context; 237 struct psp_xgmi_topology_info top_info; 238 bool supports_extended_data; 239 bool supports_ext_link_info; 240 uint8_t xgmi_ta_caps; 241 }; 242 243 struct psp_ras_context { 244 struct ta_context context; 245 struct amdgpu_ras *ras; 246 struct mutex mutex; 247 }; 248 249 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 250 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 251 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 252 /*Define the VRAM size that will be encroached by BIST training.*/ 253 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 254 255 enum psp_memory_training_init_flag { 256 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 257 PSP_MEM_TRAIN_SUPPORT = 0x1, 258 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 259 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 260 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 261 }; 262 263 enum psp_memory_training_ops { 264 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 265 PSP_MEM_TRAIN_SAVE = 0x2, 266 PSP_MEM_TRAIN_RESTORE = 0x4, 267 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 268 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 269 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 270 }; 271 272 struct psp_memory_training_context { 273 /*training data size*/ 274 u64 train_data_size; 275 /* 276 * sys_cache 277 * cpu virtual address 278 * system memory buffer that used to store the training data. 279 */ 280 void *sys_cache; 281 282 /*vram offset of the p2c training data*/ 283 u64 p2c_train_data_offset; 284 285 /*vram offset of the c2p training data*/ 286 u64 c2p_train_data_offset; 287 288 enum psp_memory_training_init_flag init; 289 u32 training_cnt; 290 bool enable_mem_training; 291 }; 292 293 /** PSP runtime DB **/ 294 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 295 #define PSP_RUNTIME_DB_OFFSET 0x100000 296 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 297 #define PSP_RUNTIME_DB_VER_1 0x0100 298 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 299 #define PSP_RUNTIME_DB_OFFSET_FROM_IP_DISCOVERY_TABLE 0x10000 300 301 enum psp_runtime_entry_type { 302 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 303 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 304 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 305 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 306 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 307 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 308 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 309 }; 310 311 /* PSP runtime DB header */ 312 struct psp_runtime_data_header { 313 /* determine the existence of runtime db */ 314 uint16_t cookie; 315 /* version of runtime db */ 316 uint16_t version; 317 }; 318 319 /* PSP runtime DB entry */ 320 struct psp_runtime_entry { 321 /* type of runtime db entry */ 322 uint32_t entry_type; 323 /* offset of entry in bytes */ 324 uint16_t offset; 325 /* size of entry in bytes */ 326 uint16_t size; 327 }; 328 329 /* PSP runtime DB directory */ 330 struct psp_runtime_data_directory { 331 /* number of valid entries */ 332 uint16_t entry_count; 333 /* db entries*/ 334 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 335 }; 336 337 /* PSP runtime DB boot config feature bitmask */ 338 enum psp_runtime_boot_cfg_feature { 339 BOOT_CFG_FEATURE_GECC = 0x1, 340 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 341 }; 342 343 /* PSP run time DB SCPM authentication defines */ 344 enum psp_runtime_scpm_authentication { 345 SCPM_DISABLE = 0x0, 346 SCPM_ENABLE = 0x1, 347 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 348 }; 349 350 /* PSP runtime DB boot config entry */ 351 struct psp_runtime_boot_cfg_entry { 352 uint32_t boot_cfg_bitmask; 353 uint32_t reserved; 354 }; 355 356 /* PSP runtime DB SCPM entry */ 357 struct psp_runtime_scpm_entry { 358 enum psp_runtime_scpm_authentication scpm_status; 359 }; 360 361 #if defined(CONFIG_DEBUG_FS) 362 struct spirom_bo { 363 struct amdgpu_bo *bo; 364 uint64_t mc_addr; 365 void *cpu_addr; 366 }; 367 #endif 368 369 enum psp_ptl_cmd { 370 PSP_PTL_PERF_MON_QUERY = 0xA0000000, 371 PSP_PTL_PERF_MON_SET = 0xA0000001, 372 }; 373 374 enum psp_ptl_format_type { 375 GFX_FTYPE_I8 = 0x00000000, 376 GFX_FTYPE_F16 = 0x00000001, 377 GFX_FTYPE_BF16 = 0x00000002, 378 GFX_FTYPE_F32 = 0x00000003, 379 GFX_FTYPE_F64 = 0x00000004, 380 GFX_FTYPE_F8 = 0x00000005, 381 GFX_FTYPE_VECTOR = 0x00000006, 382 GFX_FTYPE_INVALID = 0xFFFFFFFF, 383 }; 384 385 struct psp_ptl_perf_req { 386 enum psp_ptl_cmd req; 387 uint32_t ptl_state; 388 uint32_t pref_format1; 389 uint32_t pref_format2; 390 }; 391 392 /** 393 * typedef amdgpu_psp_irq_handler_fn - callback for a registered PSP event id 394 * @mgr: IRQ manager 395 * @entry: copy of the IH entry that triggered this event 396 */ 397 typedef void (*amdgpu_psp_irq_handler_fn)(struct amdgpu_psp_irq_mgr *mgr, 398 u32 event_id, 399 struct amdgpu_iv_entry *entry); 400 401 /** 402 * struct amdgpu_psp_irq_handler - statically allocated handler node 403 * 404 * Callers define these statically; a single instance can be shared across 405 * multiple devices. Indexed in &amdgpu_psp_irq_mgr.irq_bh_handlers by @event_id. 406 */ 407 struct amdgpu_psp_irq_handler { 408 u32 event_id; 409 amdgpu_psp_irq_handler_fn callback; 410 }; 411 412 /** 413 * struct amdgpu_psp_irq_mgr - deferred dispatch for PSP-driven IH events 414 * 415 * The xarray's own lock serializes handler lookup against registration. 416 */ 417 struct amdgpu_psp_irq_mgr { 418 struct psp_context *psp; 419 struct amdgpu_irq_src irq_src; 420 struct xarray irq_bh_handlers; 421 }; 422 423 struct psp_context { 424 struct amdgpu_device *adev; 425 struct psp_ring km_ring; 426 struct psp_gfx_cmd_resp *cmd; 427 428 const struct psp_funcs *funcs; 429 const struct ta_funcs *ta_funcs; 430 431 /* firmware buffer */ 432 struct amdgpu_bo *fw_pri_bo; 433 uint64_t fw_pri_mc_addr; 434 void *fw_pri_buf; 435 436 /* sos firmware */ 437 const struct firmware *sos_fw; 438 struct psp_bin_desc sys; 439 struct psp_bin_desc sos; 440 struct psp_bin_desc toc; 441 struct psp_bin_desc kdb; 442 struct psp_bin_desc spl; 443 struct psp_bin_desc rl; 444 struct psp_bin_desc soc_drv; 445 struct psp_bin_desc intf_drv; 446 struct psp_bin_desc dbg_drv; 447 struct psp_bin_desc ras_drv; 448 struct psp_bin_desc ipkeymgr_drv; 449 struct psp_bin_desc spdm_drv; 450 451 /* tmr buffer */ 452 struct amdgpu_bo *tmr_bo; 453 uint64_t tmr_mc_addr; 454 455 /* asd firmware */ 456 const struct firmware *asd_fw; 457 458 /* toc firmware */ 459 const struct firmware *toc_fw; 460 461 /* cap firmware */ 462 const struct firmware *cap_fw; 463 464 /* rl firmware */ 465 const struct firmware *rl_fw; 466 467 /* fence buffer */ 468 struct amdgpu_bo *fence_buf_bo; 469 uint64_t fence_buf_mc_addr; 470 void *fence_buf; 471 472 /* cmd buffer */ 473 struct amdgpu_bo *cmd_resp_buf_bo; 474 uint64_t cmd_resp_buf_mc_addr; 475 struct psp_gfx_cmd_resp *cmd_resp_buf_mem; 476 uint64_t cmd_ext_resp_mc_addr; 477 void *cmd_ext_resp_mem; 478 479 /* fence value associated with cmd buffer */ 480 atomic_t fence_value; 481 /* flag to mark whether gfx fw autoload is supported or not */ 482 bool autoload_supported; 483 /* flag to mark whether psp use runtime TMR or boottime TMR */ 484 bool boot_time_tmr; 485 /* flag to mark whether df cstate management centralized to PMFW */ 486 bool pmfw_centralized_cstate_management; 487 488 /* xgmi ta firmware and buffer */ 489 const struct firmware *ta_fw; 490 uint32_t ta_fw_version; 491 492 struct psp_bin_desc cap; 493 494 struct ta_context asd_context; 495 struct psp_xgmi_context xgmi_context; 496 struct psp_ras_context ras_context; 497 struct ta_cp_context hdcp_context; 498 struct ta_cp_context dtm_context; 499 struct ta_cp_context rap_context; 500 struct ta_cp_context securedisplay_context; 501 struct mutex mutex; 502 struct psp_memory_training_context mem_train_ctx; 503 504 uint32_t boot_cfg_bitmask; 505 506 /* firmware upgrades supported */ 507 bool sup_pd_fw_up; 508 bool sup_ifwi_up; 509 510 char *vbflash_tmp_buf; 511 size_t vbflash_image_size; 512 bool vbflash_done; 513 struct amdgpu_psp_irq_mgr irq_mgr; 514 #if defined(CONFIG_DEBUG_FS) 515 struct spirom_bo *spirom_dump_trip; 516 #endif 517 struct amdgpu_ptl ptl; 518 }; 519 520 struct amdgpu_psp_funcs { 521 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 522 enum AMDGPU_UCODE_ID); 523 }; 524 525 526 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 527 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 528 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 529 #define psp_init_microcode(psp) \ 530 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 531 #define psp_bootloader_load_kdb(psp) \ 532 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 533 #define psp_bootloader_load_spl(psp) \ 534 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 535 #define psp_bootloader_load_sysdrv(psp) \ 536 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 537 #define psp_bootloader_load_soc_drv(psp) \ 538 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 539 #define psp_bootloader_load_intf_drv(psp) \ 540 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 541 #define psp_bootloader_load_dbg_drv(psp) \ 542 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 543 #define psp_bootloader_load_ras_drv(psp) \ 544 ((psp)->funcs->bootloader_load_ras_drv ? \ 545 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 546 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 547 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 548 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 549 #define psp_bootloader_load_spdm_drv(psp) \ 550 ((psp)->funcs->bootloader_load_spdm_drv ? \ 551 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0) 552 #define psp_bootloader_load_sos(psp) \ 553 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 554 #define psp_smu_reload_quirk(psp) \ 555 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 556 #define psp_mode1_reset(psp) \ 557 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 558 #define psp_mem_training(psp, ops) \ 559 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 560 561 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 562 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 563 564 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 565 ((psp)->funcs->load_usbc_pd_fw ? \ 566 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 567 568 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 569 ((psp)->funcs->read_usbc_pd_fw ? \ 570 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 571 572 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 573 ((psp)->funcs->update_spirom ? \ 574 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 575 576 #define psp_dump_spirom(psp, fw_pri_mc_addr) \ 577 ((psp)->funcs->dump_spirom ? \ 578 (psp)->funcs->dump_spirom((psp), fw_pri_mc_addr) : -EINVAL) 579 580 #define psp_vbflash_status(psp) \ 581 ((psp)->funcs->vbflash_stat ? \ 582 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 583 584 #define psp_fatal_error_recovery_quirk(psp) \ 585 ((psp)->funcs->fatal_error_recovery_quirk ? \ 586 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 587 588 #define psp_is_aux_sos_load_required(psp) \ 589 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) 590 591 #define psp_reg_program_no_ring(psp, val, id) \ 592 ((psp)->funcs->reg_program_no_ring ? \ 593 (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL) 594 595 #define psp_get_fw_type(psp, ucode, type) \ 596 ((psp)->funcs->get_fw_type ? \ 597 (psp)->funcs->get_fw_type(ucode, type):amdgpu_psp_get_fw_type(ucode, type)) 598 599 extern const struct amd_ip_funcs psp_ip_funcs; 600 601 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 602 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 603 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 604 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 605 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 606 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 607 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 608 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 609 extern const struct amdgpu_ip_block_version psp_v15_0_ip_block; 610 extern const struct amdgpu_ip_block_version psp_v15_0_3_ip_block; 611 extern const struct amdgpu_ip_block_version psp_v15_0_8_ip_block; 612 613 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 614 uint32_t field_val, uint32_t mask, uint32_t flags); 615 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 616 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 617 618 int psp_execute_ip_fw_load(struct psp_context *psp, 619 struct amdgpu_firmware_info *ucode); 620 621 int psp_gpu_reset(struct amdgpu_device *adev); 622 623 int psp_ta_init_shared_buf(struct psp_context *psp, 624 struct ta_mem_context *mem_ctx); 625 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 626 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 627 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 628 int psp_ta_invoke(struct psp_context *psp, 629 uint32_t ta_cmd_id, 630 struct ta_context *context); 631 632 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 633 bool psp_is_xgmi_ta_supported(struct psp_context *psp); 634 int psp_xgmi_terminate(struct psp_context *psp); 635 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 636 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 637 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 638 int psp_xgmi_get_topology_info(struct psp_context *psp, 639 int number_devices, 640 struct psp_xgmi_topology_info *topology, 641 bool get_extended_data); 642 int psp_xgmi_set_topology_info(struct psp_context *psp, 643 int number_devices, 644 struct psp_xgmi_topology_info *topology); 645 int psp_ras_initialize(struct psp_context *psp); 646 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 647 int psp_ras_enable_features(struct psp_context *psp, 648 union ta_ras_cmd_input *info, bool enable); 649 int psp_ras_trigger_error(struct psp_context *psp, 650 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 651 int psp_ras_terminate(struct psp_context *psp); 652 int psp_ras_query_address(struct psp_context *psp, 653 struct ta_ras_query_address_input *addr_in, 654 struct ta_ras_query_address_output *addr_out); 655 656 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 657 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 658 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 659 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 660 661 int psp_rlc_autoload_start(struct psp_context *psp); 662 663 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 664 uint32_t value); 665 int psp_ring_cmd_submit(struct psp_context *psp, 666 uint64_t cmd_buf_mc_addr, 667 uint64_t fence_mc_addr, 668 int index); 669 int psp_init_asd_microcode(struct psp_context *psp, 670 const char *chip_name); 671 int psp_init_toc_microcode(struct psp_context *psp, 672 const char *chip_name); 673 int psp_init_sos_microcode(struct psp_context *psp, 674 const char *chip_name); 675 int psp_init_ta_microcode(struct psp_context *psp, 676 const char *chip_name); 677 int psp_init_cap_microcode(struct psp_context *psp, 678 const char *chip_name); 679 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 680 uint64_t *output_ptr); 681 int psp_update_fw_reservation(struct psp_context *psp); 682 int psp_load_fw_list(struct psp_context *psp, 683 struct amdgpu_firmware_info **ucode_list, int ucode_count); 684 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 685 686 int psp_spatial_partition(struct psp_context *psp, int mode); 687 int psp_memory_partition(struct psp_context *psp, int mode); 688 689 int is_psp_fw_valid(struct psp_bin_desc bin); 690 691 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 692 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 693 694 int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, 695 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 696 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); 697 int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, 698 enum psp_reg_prog_id id); 699 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); 700 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 701 enum psp_gfx_fw_type *type); 702 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev); 703 int psp_init_rl_microcode(struct psp_context *psp, const char *chip_name); 704 705 void amdgpu_psp_irq_mgr_dispatch(struct amdgpu_psp_irq_mgr *mgr, 706 struct amdgpu_iv_entry *entry); 707 int amdgpu_psp_irq_mgr_register( 708 struct amdgpu_psp_irq_mgr *mgr, 709 const struct amdgpu_psp_irq_handler *handlers, int count, 710 const struct amdgpu_psp_irq_handler *default_handler); 711 712 struct amdgpu_ualink_info; 713 struct amdgpu_ualink_ppod_setup; 714 struct amdgpu_ualink_vpod_config; 715 struct amdgpu_ualink_station_config; 716 717 int psp_ual_get_interface_version(struct psp_context *psp, uint32_t *intf_ver); 718 719 int psp_ual_query_info(struct psp_context *psp, uint32_t intf_ver, 720 struct amdgpu_ualink_info *info, 721 enum psp_gfx_ual_config_state *cfg_state); 722 723 int psp_ual_set_ppod_config(struct psp_context *psp, uint32_t intf_ver, 724 const struct amdgpu_ualink_ppod_setup *setup); 725 726 int psp_ual_set_vpod_config(struct psp_context *psp, uint32_t intf_ver, 727 const struct amdgpu_ualink_vpod_config *config); 728 729 int psp_ual_set_station_config(struct psp_context *psp, uint32_t intf_ver, 730 const struct amdgpu_ualink_station_config *stations); 731 732 int psp_ual_set_npa_config(struct psp_context *psp, uint32_t intf_ver, 733 unsigned int vmid, bool enable); 734 735 int psp_ual_send_completion(struct psp_context *psp, uint32_t intf_ver, 736 uint32_t cmd_id, uint32_t status); 737 738 #endif 739