1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 #include <linux/bitops.h> 35 #include "amdgpu_ptl.h" 36 37 #define PSP_FENCE_BUFFER_SIZE 0x1000 38 #define PSP_CMD_BUFFER_SIZE 0x1000 39 #define PSP_1_MEG 0x100000 40 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 41 #define PSP_TMR_ALIGNMENT 0x100000 42 #define PSP_FW_NAME_LEN 0x24 43 44 /* VBIOS gfl defines */ 45 #define MBOX_READY_MASK 0x80000000 46 #define MBOX_STATUS_MASK 0x0000FFFF 47 #define MBOX_COMMAND_MASK 0x00FF0000 48 #define MBOX_READY_FLAG 0x80000000 49 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 50 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 51 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 52 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO 0xf 53 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10 54 #define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11 55 56 /* Command register bit 31 set to indicate readiness */ 57 #define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE) 58 #define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) 59 60 /* Values to check for a successful GFX_CMD response wait. Check against 61 * both status bits and response state - helps to detect a command failure 62 * or other unexpected cases like a device drop reading all 0xFFs 63 */ 64 #define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE) 65 #define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) 66 67 extern const struct attribute_group amdgpu_flash_attr_group; 68 69 enum psp_shared_mem_size { 70 PSP_ASD_SHARED_MEM_SIZE = 0x0, 71 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 72 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 73 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 74 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 75 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 76 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 77 }; 78 79 enum ta_type_id { 80 TA_TYPE_XGMI = 1, 81 TA_TYPE_RAS, 82 TA_TYPE_HDCP, 83 TA_TYPE_DTM, 84 TA_TYPE_RAP, 85 TA_TYPE_SECUREDISPLAY, 86 87 TA_TYPE_MAX_INDEX, 88 }; 89 90 struct psp_context; 91 struct psp_xgmi_node_info; 92 struct psp_xgmi_topology_info; 93 struct psp_bin_desc; 94 95 enum psp_bootloader_cmd { 96 PSP_BL__LOAD_SYSDRV = 0x10000, 97 PSP_BL__LOAD_SOSDRV = 0x20000, 98 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 99 PSP_BL__LOAD_SOCDRV = 0xB0000, 100 PSP_BL__LOAD_DBGDRV = 0xC0000, 101 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 102 PSP_BL__LOAD_INTFDRV = 0xD0000, 103 PSP_BL__LOAD_RASDRV = 0xE0000, 104 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 105 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 106 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 107 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 108 PSP_BL__LOAD_SPDMDRV = 0x20000000, 109 }; 110 111 enum psp_ring_type { 112 PSP_RING_TYPE__INVALID = 0, 113 /* 114 * These values map to the way the PSP kernel identifies the 115 * rings. 116 */ 117 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 118 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 119 }; 120 121 struct psp_ring { 122 enum psp_ring_type ring_type; 123 struct psp_gfx_rb_frame *ring_mem; 124 uint64_t ring_mem_mc_addr; 125 void *ring_mem_handle; 126 uint32_t ring_size; 127 uint32_t ring_wptr; 128 }; 129 130 /* More registers may will be supported */ 131 enum psp_reg_prog_id { 132 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 133 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 134 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 135 PSP_REG_MMHUB_L1_TLB_CNTL = 25, 136 PSP_REG_LAST 137 }; 138 139 #define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */ 140 #define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */ 141 142 struct psp_funcs { 143 int (*init_microcode)(struct psp_context *psp); 144 int (*wait_for_bootloader)(struct psp_context *psp); 145 int (*bootloader_load_kdb)(struct psp_context *psp); 146 int (*bootloader_load_spl)(struct psp_context *psp); 147 int (*bootloader_load_sysdrv)(struct psp_context *psp); 148 int (*bootloader_load_soc_drv)(struct psp_context *psp); 149 int (*bootloader_load_intf_drv)(struct psp_context *psp); 150 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 151 int (*bootloader_load_ras_drv)(struct psp_context *psp); 152 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 153 int (*bootloader_load_spdm_drv)(struct psp_context *psp); 154 int (*bootloader_load_sos)(struct psp_context *psp); 155 int (*ring_create)(struct psp_context *psp, 156 enum psp_ring_type ring_type); 157 int (*ring_stop)(struct psp_context *psp, 158 enum psp_ring_type ring_type); 159 int (*ring_destroy)(struct psp_context *psp, 160 enum psp_ring_type ring_type); 161 bool (*smu_reload_quirk)(struct psp_context *psp); 162 int (*mode1_reset)(struct psp_context *psp); 163 int (*mem_training)(struct psp_context *psp, uint32_t ops); 164 uint32_t (*ring_get_wptr)(struct psp_context *psp); 165 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 166 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 167 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 168 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 169 int (*dump_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 170 int (*vbflash_stat)(struct psp_context *psp); 171 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 172 bool (*get_ras_capability)(struct psp_context *psp); 173 bool (*is_aux_sos_load_required)(struct psp_context *psp); 174 bool (*is_reload_needed)(struct psp_context *psp); 175 int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val, 176 enum psp_reg_prog_id id); 177 int (*get_fw_type)(struct amdgpu_firmware_info *ucode, 178 enum psp_gfx_fw_type *type); 179 }; 180 181 struct ta_funcs { 182 int (*fn_ta_initialize)(struct psp_context *psp); 183 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 184 int (*fn_ta_terminate)(struct psp_context *psp); 185 }; 186 187 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 188 struct psp_xgmi_node_info { 189 uint64_t node_id; 190 uint8_t num_hops; 191 uint8_t is_sharing_enabled; 192 enum ta_xgmi_assigned_sdma_engine sdma_engine; 193 uint8_t num_links; 194 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 195 }; 196 197 struct psp_xgmi_topology_info { 198 uint32_t num_nodes; 199 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 200 }; 201 202 struct psp_bin_desc { 203 uint32_t fw_version; 204 uint32_t feature_version; 205 uint32_t size_bytes; 206 uint8_t *start_addr; 207 }; 208 209 struct ta_mem_context { 210 struct amdgpu_bo *shared_bo; 211 uint64_t shared_mc_addr; 212 void *shared_buf; 213 enum psp_shared_mem_size shared_mem_size; 214 }; 215 216 struct ta_context { 217 bool initialized; 218 uint32_t session_id; 219 uint32_t resp_status; 220 struct ta_mem_context mem_context; 221 struct psp_bin_desc bin_desc; 222 enum psp_gfx_cmd_id ta_load_type; 223 enum ta_type_id ta_type; 224 }; 225 226 struct ta_cp_context { 227 struct ta_context context; 228 struct mutex mutex; 229 }; 230 231 struct psp_xgmi_context { 232 struct ta_context context; 233 struct psp_xgmi_topology_info top_info; 234 bool supports_extended_data; 235 bool supports_ext_link_info; 236 uint8_t xgmi_ta_caps; 237 }; 238 239 struct psp_ras_context { 240 struct ta_context context; 241 struct amdgpu_ras *ras; 242 struct mutex mutex; 243 }; 244 245 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 246 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 247 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 248 /*Define the VRAM size that will be encroached by BIST training.*/ 249 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 250 251 enum psp_memory_training_init_flag { 252 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 253 PSP_MEM_TRAIN_SUPPORT = 0x1, 254 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 255 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 256 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 257 }; 258 259 enum psp_memory_training_ops { 260 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 261 PSP_MEM_TRAIN_SAVE = 0x2, 262 PSP_MEM_TRAIN_RESTORE = 0x4, 263 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 264 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 265 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 266 }; 267 268 struct psp_memory_training_context { 269 /*training data size*/ 270 u64 train_data_size; 271 /* 272 * sys_cache 273 * cpu virtual address 274 * system memory buffer that used to store the training data. 275 */ 276 void *sys_cache; 277 278 /*vram offset of the p2c training data*/ 279 u64 p2c_train_data_offset; 280 281 /*vram offset of the c2p training data*/ 282 u64 c2p_train_data_offset; 283 284 enum psp_memory_training_init_flag init; 285 u32 training_cnt; 286 bool enable_mem_training; 287 }; 288 289 /** PSP runtime DB **/ 290 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 291 #define PSP_RUNTIME_DB_OFFSET 0x100000 292 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 293 #define PSP_RUNTIME_DB_VER_1 0x0100 294 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 295 296 enum psp_runtime_entry_type { 297 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 298 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 299 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 300 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 301 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 302 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 303 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 304 }; 305 306 /* PSP runtime DB header */ 307 struct psp_runtime_data_header { 308 /* determine the existence of runtime db */ 309 uint16_t cookie; 310 /* version of runtime db */ 311 uint16_t version; 312 }; 313 314 /* PSP runtime DB entry */ 315 struct psp_runtime_entry { 316 /* type of runtime db entry */ 317 uint32_t entry_type; 318 /* offset of entry in bytes */ 319 uint16_t offset; 320 /* size of entry in bytes */ 321 uint16_t size; 322 }; 323 324 /* PSP runtime DB directory */ 325 struct psp_runtime_data_directory { 326 /* number of valid entries */ 327 uint16_t entry_count; 328 /* db entries*/ 329 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 330 }; 331 332 /* PSP runtime DB boot config feature bitmask */ 333 enum psp_runtime_boot_cfg_feature { 334 BOOT_CFG_FEATURE_GECC = 0x1, 335 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 336 }; 337 338 /* PSP run time DB SCPM authentication defines */ 339 enum psp_runtime_scpm_authentication { 340 SCPM_DISABLE = 0x0, 341 SCPM_ENABLE = 0x1, 342 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 343 }; 344 345 /* PSP runtime DB boot config entry */ 346 struct psp_runtime_boot_cfg_entry { 347 uint32_t boot_cfg_bitmask; 348 uint32_t reserved; 349 }; 350 351 /* PSP runtime DB SCPM entry */ 352 struct psp_runtime_scpm_entry { 353 enum psp_runtime_scpm_authentication scpm_status; 354 }; 355 356 #if defined(CONFIG_DEBUG_FS) 357 struct spirom_bo { 358 struct amdgpu_bo *bo; 359 uint64_t mc_addr; 360 void *cpu_addr; 361 }; 362 #endif 363 364 enum psp_ptl_cmd { 365 PSP_PTL_PERF_MON_QUERY = 0xA0000000, 366 PSP_PTL_PERF_MON_SET = 0xA0000001, 367 }; 368 369 enum psp_ptl_format_type { 370 GFX_FTYPE_I8 = 0x00000000, 371 GFX_FTYPE_F16 = 0x00000001, 372 GFX_FTYPE_BF16 = 0x00000002, 373 GFX_FTYPE_F32 = 0x00000003, 374 GFX_FTYPE_F64 = 0x00000004, 375 GFX_FTYPE_F8 = 0x00000005, 376 GFX_FTYPE_VECTOR = 0x00000006, 377 GFX_FTYPE_INVALID = 0xFFFFFFFF, 378 }; 379 380 struct psp_ptl_perf_req { 381 enum psp_ptl_cmd req; 382 uint32_t ptl_state; 383 uint32_t pref_format1; 384 uint32_t pref_format2; 385 }; 386 387 struct psp_context { 388 struct amdgpu_device *adev; 389 struct psp_ring km_ring; 390 struct psp_gfx_cmd_resp *cmd; 391 392 const struct psp_funcs *funcs; 393 const struct ta_funcs *ta_funcs; 394 395 /* firmware buffer */ 396 struct amdgpu_bo *fw_pri_bo; 397 uint64_t fw_pri_mc_addr; 398 void *fw_pri_buf; 399 400 /* sos firmware */ 401 const struct firmware *sos_fw; 402 struct psp_bin_desc sys; 403 struct psp_bin_desc sos; 404 struct psp_bin_desc toc; 405 struct psp_bin_desc kdb; 406 struct psp_bin_desc spl; 407 struct psp_bin_desc rl; 408 struct psp_bin_desc soc_drv; 409 struct psp_bin_desc intf_drv; 410 struct psp_bin_desc dbg_drv; 411 struct psp_bin_desc ras_drv; 412 struct psp_bin_desc ipkeymgr_drv; 413 struct psp_bin_desc spdm_drv; 414 415 /* tmr buffer */ 416 struct amdgpu_bo *tmr_bo; 417 uint64_t tmr_mc_addr; 418 419 /* asd firmware */ 420 const struct firmware *asd_fw; 421 422 /* toc firmware */ 423 const struct firmware *toc_fw; 424 425 /* cap firmware */ 426 const struct firmware *cap_fw; 427 428 /* fence buffer */ 429 struct amdgpu_bo *fence_buf_bo; 430 uint64_t fence_buf_mc_addr; 431 void *fence_buf; 432 433 /* cmd buffer */ 434 struct amdgpu_bo *cmd_buf_bo; 435 uint64_t cmd_buf_mc_addr; 436 struct psp_gfx_cmd_resp *cmd_buf_mem; 437 438 /* fence value associated with cmd buffer */ 439 atomic_t fence_value; 440 /* flag to mark whether gfx fw autoload is supported or not */ 441 bool autoload_supported; 442 /* flag to mark whether psp use runtime TMR or boottime TMR */ 443 bool boot_time_tmr; 444 /* flag to mark whether df cstate management centralized to PMFW */ 445 bool pmfw_centralized_cstate_management; 446 447 /* xgmi ta firmware and buffer */ 448 const struct firmware *ta_fw; 449 uint32_t ta_fw_version; 450 451 uint32_t cap_fw_version; 452 uint32_t cap_feature_version; 453 uint32_t cap_ucode_size; 454 455 struct ta_context asd_context; 456 struct psp_xgmi_context xgmi_context; 457 struct psp_ras_context ras_context; 458 struct ta_cp_context hdcp_context; 459 struct ta_cp_context dtm_context; 460 struct ta_cp_context rap_context; 461 struct ta_cp_context securedisplay_context; 462 struct mutex mutex; 463 struct psp_memory_training_context mem_train_ctx; 464 465 uint32_t boot_cfg_bitmask; 466 467 /* firmware upgrades supported */ 468 bool sup_pd_fw_up; 469 bool sup_ifwi_up; 470 471 char *vbflash_tmp_buf; 472 size_t vbflash_image_size; 473 bool vbflash_done; 474 #if defined(CONFIG_DEBUG_FS) 475 struct spirom_bo *spirom_dump_trip; 476 #endif 477 struct amdgpu_ptl ptl; 478 }; 479 480 struct amdgpu_psp_funcs { 481 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 482 enum AMDGPU_UCODE_ID); 483 }; 484 485 486 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 487 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 488 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 489 #define psp_init_microcode(psp) \ 490 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 491 #define psp_bootloader_load_kdb(psp) \ 492 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 493 #define psp_bootloader_load_spl(psp) \ 494 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 495 #define psp_bootloader_load_sysdrv(psp) \ 496 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 497 #define psp_bootloader_load_soc_drv(psp) \ 498 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 499 #define psp_bootloader_load_intf_drv(psp) \ 500 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 501 #define psp_bootloader_load_dbg_drv(psp) \ 502 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 503 #define psp_bootloader_load_ras_drv(psp) \ 504 ((psp)->funcs->bootloader_load_ras_drv ? \ 505 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 506 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 507 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 508 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 509 #define psp_bootloader_load_spdm_drv(psp) \ 510 ((psp)->funcs->bootloader_load_spdm_drv ? \ 511 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0) 512 #define psp_bootloader_load_sos(psp) \ 513 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 514 #define psp_smu_reload_quirk(psp) \ 515 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 516 #define psp_mode1_reset(psp) \ 517 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 518 #define psp_mem_training(psp, ops) \ 519 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 520 521 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 522 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 523 524 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 525 ((psp)->funcs->load_usbc_pd_fw ? \ 526 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 527 528 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 529 ((psp)->funcs->read_usbc_pd_fw ? \ 530 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 531 532 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 533 ((psp)->funcs->update_spirom ? \ 534 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 535 536 #define psp_dump_spirom(psp, fw_pri_mc_addr) \ 537 ((psp)->funcs->dump_spirom ? \ 538 (psp)->funcs->dump_spirom((psp), fw_pri_mc_addr) : -EINVAL) 539 540 #define psp_vbflash_status(psp) \ 541 ((psp)->funcs->vbflash_stat ? \ 542 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 543 544 #define psp_fatal_error_recovery_quirk(psp) \ 545 ((psp)->funcs->fatal_error_recovery_quirk ? \ 546 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 547 548 #define psp_is_aux_sos_load_required(psp) \ 549 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) 550 551 #define psp_reg_program_no_ring(psp, val, id) \ 552 ((psp)->funcs->reg_program_no_ring ? \ 553 (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL) 554 555 #define psp_get_fw_type(psp, ucode, type) \ 556 ((psp)->funcs->get_fw_type ? \ 557 (psp)->funcs->get_fw_type(ucode, type):amdgpu_psp_get_fw_type(ucode, type)) 558 559 extern const struct amd_ip_funcs psp_ip_funcs; 560 561 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 562 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 563 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 564 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 565 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 566 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 567 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 568 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 569 extern const struct amdgpu_ip_block_version psp_v15_0_ip_block; 570 extern const struct amdgpu_ip_block_version psp_v15_0_8_ip_block; 571 572 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 573 uint32_t field_val, uint32_t mask, uint32_t flags); 574 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 575 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 576 577 int psp_execute_ip_fw_load(struct psp_context *psp, 578 struct amdgpu_firmware_info *ucode); 579 580 int psp_gpu_reset(struct amdgpu_device *adev); 581 582 int psp_ta_init_shared_buf(struct psp_context *psp, 583 struct ta_mem_context *mem_ctx); 584 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 585 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 586 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 587 int psp_ta_invoke(struct psp_context *psp, 588 uint32_t ta_cmd_id, 589 struct ta_context *context); 590 591 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 592 int psp_xgmi_terminate(struct psp_context *psp); 593 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 594 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 595 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 596 int psp_xgmi_get_topology_info(struct psp_context *psp, 597 int number_devices, 598 struct psp_xgmi_topology_info *topology, 599 bool get_extended_data); 600 int psp_xgmi_set_topology_info(struct psp_context *psp, 601 int number_devices, 602 struct psp_xgmi_topology_info *topology); 603 int psp_ras_initialize(struct psp_context *psp); 604 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 605 int psp_ras_enable_features(struct psp_context *psp, 606 union ta_ras_cmd_input *info, bool enable); 607 int psp_ras_trigger_error(struct psp_context *psp, 608 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 609 int psp_ras_terminate(struct psp_context *psp); 610 int psp_ras_query_address(struct psp_context *psp, 611 struct ta_ras_query_address_input *addr_in, 612 struct ta_ras_query_address_output *addr_out); 613 614 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 615 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 616 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 617 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 618 619 int psp_rlc_autoload_start(struct psp_context *psp); 620 621 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 622 uint32_t value); 623 int psp_ring_cmd_submit(struct psp_context *psp, 624 uint64_t cmd_buf_mc_addr, 625 uint64_t fence_mc_addr, 626 int index); 627 int psp_init_asd_microcode(struct psp_context *psp, 628 const char *chip_name); 629 int psp_init_toc_microcode(struct psp_context *psp, 630 const char *chip_name); 631 int psp_init_sos_microcode(struct psp_context *psp, 632 const char *chip_name); 633 int psp_init_ta_microcode(struct psp_context *psp, 634 const char *chip_name); 635 int psp_init_cap_microcode(struct psp_context *psp, 636 const char *chip_name); 637 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 638 uint64_t *output_ptr); 639 int psp_update_fw_reservation(struct psp_context *psp); 640 int psp_load_fw_list(struct psp_context *psp, 641 struct amdgpu_firmware_info **ucode_list, int ucode_count); 642 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 643 644 int psp_spatial_partition(struct psp_context *psp, int mode); 645 int psp_memory_partition(struct psp_context *psp, int mode); 646 647 int is_psp_fw_valid(struct psp_bin_desc bin); 648 649 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 650 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 651 652 int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, 653 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 654 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); 655 int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, 656 enum psp_reg_prog_id id); 657 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); 658 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 659 enum psp_gfx_fw_type *type); 660 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev); 661 662 #endif 663