1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 33 #define PSP_FENCE_BUFFER_SIZE 0x1000 34 #define PSP_CMD_BUFFER_SIZE 0x1000 35 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 36 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE 0x400000 39 #define PSP_HDCP_SHARED_MEM_SIZE 0x4000 40 #define PSP_DTM_SHARED_MEM_SIZE 0x4000 41 #define PSP_SHARED_MEM_SIZE 0x4000 42 43 struct psp_context; 44 struct psp_xgmi_node_info; 45 struct psp_xgmi_topology_info; 46 47 enum psp_bootloader_cmd { 48 PSP_BL__LOAD_SYSDRV = 0x10000, 49 PSP_BL__LOAD_SOSDRV = 0x20000, 50 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 51 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 52 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 53 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 54 }; 55 56 enum psp_ring_type 57 { 58 PSP_RING_TYPE__INVALID = 0, 59 /* 60 * These values map to the way the PSP kernel identifies the 61 * rings. 62 */ 63 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 64 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 65 }; 66 67 struct psp_ring 68 { 69 enum psp_ring_type ring_type; 70 struct psp_gfx_rb_frame *ring_mem; 71 uint64_t ring_mem_mc_addr; 72 void *ring_mem_handle; 73 uint32_t ring_size; 74 }; 75 76 /* More registers may will be supported */ 77 enum psp_reg_prog_id { 78 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 79 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 80 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 81 PSP_REG_LAST 82 }; 83 84 struct psp_funcs 85 { 86 int (*init_microcode)(struct psp_context *psp); 87 int (*bootloader_load_kdb)(struct psp_context *psp); 88 int (*bootloader_load_spl)(struct psp_context *psp); 89 int (*bootloader_load_sysdrv)(struct psp_context *psp); 90 int (*bootloader_load_sos)(struct psp_context *psp); 91 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 92 int (*ring_create)(struct psp_context *psp, 93 enum psp_ring_type ring_type); 94 int (*ring_stop)(struct psp_context *psp, 95 enum psp_ring_type ring_type); 96 int (*ring_destroy)(struct psp_context *psp, 97 enum psp_ring_type ring_type); 98 bool (*smu_reload_quirk)(struct psp_context *psp); 99 int (*mode1_reset)(struct psp_context *psp); 100 int (*mem_training)(struct psp_context *psp, uint32_t ops); 101 uint32_t (*ring_get_wptr)(struct psp_context *psp); 102 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 103 int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr); 104 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 105 }; 106 107 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 108 struct psp_xgmi_node_info { 109 uint64_t node_id; 110 uint8_t num_hops; 111 uint8_t is_sharing_enabled; 112 enum ta_xgmi_assigned_sdma_engine sdma_engine; 113 }; 114 115 struct psp_xgmi_topology_info { 116 uint32_t num_nodes; 117 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 118 }; 119 120 struct psp_asd_context { 121 bool asd_initialized; 122 uint32_t session_id; 123 }; 124 125 struct psp_xgmi_context { 126 uint8_t initialized; 127 uint32_t session_id; 128 struct amdgpu_bo *xgmi_shared_bo; 129 uint64_t xgmi_shared_mc_addr; 130 void *xgmi_shared_buf; 131 struct psp_xgmi_topology_info top_info; 132 }; 133 134 struct psp_ras_context { 135 /*ras fw*/ 136 bool ras_initialized; 137 uint32_t session_id; 138 struct amdgpu_bo *ras_shared_bo; 139 uint64_t ras_shared_mc_addr; 140 void *ras_shared_buf; 141 struct amdgpu_ras *ras; 142 }; 143 144 struct psp_hdcp_context { 145 bool hdcp_initialized; 146 uint32_t session_id; 147 struct amdgpu_bo *hdcp_shared_bo; 148 uint64_t hdcp_shared_mc_addr; 149 void *hdcp_shared_buf; 150 struct mutex mutex; 151 }; 152 153 struct psp_dtm_context { 154 bool dtm_initialized; 155 uint32_t session_id; 156 struct amdgpu_bo *dtm_shared_bo; 157 uint64_t dtm_shared_mc_addr; 158 void *dtm_shared_buf; 159 struct mutex mutex; 160 }; 161 162 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 163 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 164 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 165 /*Define the VRAM size that will be encroached by BIST training.*/ 166 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 167 168 enum psp_memory_training_init_flag { 169 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 170 PSP_MEM_TRAIN_SUPPORT = 0x1, 171 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 172 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 173 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 174 }; 175 176 enum psp_memory_training_ops { 177 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 178 PSP_MEM_TRAIN_SAVE = 0x2, 179 PSP_MEM_TRAIN_RESTORE = 0x4, 180 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 181 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 182 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 183 }; 184 185 struct psp_memory_training_context { 186 /*training data size*/ 187 u64 train_data_size; 188 /* 189 * sys_cache 190 * cpu virtual address 191 * system memory buffer that used to store the training data. 192 */ 193 void *sys_cache; 194 195 /*vram offset of the p2c training data*/ 196 u64 p2c_train_data_offset; 197 198 /*vram offset of the c2p training data*/ 199 u64 c2p_train_data_offset; 200 struct amdgpu_bo *c2p_bo; 201 202 enum psp_memory_training_init_flag init; 203 u32 training_cnt; 204 }; 205 206 struct psp_context 207 { 208 struct amdgpu_device *adev; 209 struct psp_ring km_ring; 210 struct psp_gfx_cmd_resp *cmd; 211 212 const struct psp_funcs *funcs; 213 214 /* firmware buffer */ 215 struct amdgpu_bo *fw_pri_bo; 216 uint64_t fw_pri_mc_addr; 217 void *fw_pri_buf; 218 219 /* sos firmware */ 220 const struct firmware *sos_fw; 221 uint32_t sos_fw_version; 222 uint32_t sos_feature_version; 223 uint32_t sys_bin_size; 224 uint32_t sos_bin_size; 225 uint32_t toc_bin_size; 226 uint32_t kdb_bin_size; 227 uint32_t spl_bin_size; 228 uint8_t *sys_start_addr; 229 uint8_t *sos_start_addr; 230 uint8_t *toc_start_addr; 231 uint8_t *kdb_start_addr; 232 uint8_t *spl_start_addr; 233 234 /* tmr buffer */ 235 struct amdgpu_bo *tmr_bo; 236 uint64_t tmr_mc_addr; 237 238 /* asd firmware */ 239 const struct firmware *asd_fw; 240 uint32_t asd_fw_version; 241 uint32_t asd_feature_version; 242 uint32_t asd_ucode_size; 243 uint8_t *asd_start_addr; 244 245 /* fence buffer */ 246 struct amdgpu_bo *fence_buf_bo; 247 uint64_t fence_buf_mc_addr; 248 void *fence_buf; 249 250 /* cmd buffer */ 251 struct amdgpu_bo *cmd_buf_bo; 252 uint64_t cmd_buf_mc_addr; 253 struct psp_gfx_cmd_resp *cmd_buf_mem; 254 255 /* fence value associated with cmd buffer */ 256 atomic_t fence_value; 257 /* flag to mark whether gfx fw autoload is supported or not */ 258 bool autoload_supported; 259 /* flag to mark whether df cstate management centralized to PMFW */ 260 bool pmfw_centralized_cstate_management; 261 262 /* xgmi ta firmware and buffer */ 263 const struct firmware *ta_fw; 264 uint32_t ta_fw_version; 265 uint32_t ta_xgmi_ucode_version; 266 uint32_t ta_xgmi_ucode_size; 267 uint8_t *ta_xgmi_start_addr; 268 uint32_t ta_ras_ucode_version; 269 uint32_t ta_ras_ucode_size; 270 uint8_t *ta_ras_start_addr; 271 272 uint32_t ta_hdcp_ucode_version; 273 uint32_t ta_hdcp_ucode_size; 274 uint8_t *ta_hdcp_start_addr; 275 276 uint32_t ta_dtm_ucode_version; 277 uint32_t ta_dtm_ucode_size; 278 uint8_t *ta_dtm_start_addr; 279 280 struct psp_asd_context asd_context; 281 struct psp_xgmi_context xgmi_context; 282 struct psp_ras_context ras; 283 struct psp_hdcp_context hdcp_context; 284 struct psp_dtm_context dtm_context; 285 struct mutex mutex; 286 struct psp_memory_training_context mem_train_ctx; 287 }; 288 289 struct amdgpu_psp_funcs { 290 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 291 enum AMDGPU_UCODE_ID); 292 }; 293 294 295 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 296 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 297 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 298 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 299 #define psp_init_microcode(psp) \ 300 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 301 #define psp_bootloader_load_kdb(psp) \ 302 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 303 #define psp_bootloader_load_spl(psp) \ 304 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 305 #define psp_bootloader_load_sysdrv(psp) \ 306 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 307 #define psp_bootloader_load_sos(psp) \ 308 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 309 #define psp_smu_reload_quirk(psp) \ 310 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 311 #define psp_mode1_reset(psp) \ 312 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 313 #define psp_mem_training(psp, ops) \ 314 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 315 316 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 317 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 318 319 #define psp_load_usbc_pd_fw(psp, dma_addr) \ 320 ((psp)->funcs->load_usbc_pd_fw ? \ 321 (psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL) 322 323 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 324 ((psp)->funcs->read_usbc_pd_fw ? \ 325 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 326 327 extern const struct amd_ip_funcs psp_ip_funcs; 328 329 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 330 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 331 uint32_t field_val, uint32_t mask, bool check_changed); 332 333 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 334 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 335 336 int psp_gpu_reset(struct amdgpu_device *adev); 337 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 338 uint64_t cmd_gpu_addr, int cmd_size); 339 340 int psp_xgmi_initialize(struct psp_context *psp); 341 int psp_xgmi_terminate(struct psp_context *psp); 342 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 343 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 344 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 345 int psp_xgmi_get_topology_info(struct psp_context *psp, 346 int number_devices, 347 struct psp_xgmi_topology_info *topology); 348 int psp_xgmi_set_topology_info(struct psp_context *psp, 349 int number_devices, 350 struct psp_xgmi_topology_info *topology); 351 352 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 353 int psp_ras_enable_features(struct psp_context *psp, 354 union ta_ras_cmd_input *info, bool enable); 355 int psp_ras_trigger_error(struct psp_context *psp, 356 struct ta_ras_trigger_error_input *info); 357 358 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 359 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 360 361 int psp_rlc_autoload_start(struct psp_context *psp); 362 363 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 364 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 365 uint32_t value); 366 int psp_ring_cmd_submit(struct psp_context *psp, 367 uint64_t cmd_buf_mc_addr, 368 uint64_t fence_mc_addr, 369 int index); 370 int psp_init_asd_microcode(struct psp_context *psp, 371 const char *chip_name); 372 int psp_init_sos_microcode(struct psp_context *psp, 373 const char *chip_name); 374 int psp_init_ta_microcode(struct psp_context *psp, 375 const char *chip_name); 376 #endif 377