1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000 38 #define PSP_RAS_SHARED_MEM_SIZE 0x4000 39 #define PSP_1_MEG 0x100000 40 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 41 #define PSP_HDCP_SHARED_MEM_SIZE 0x4000 42 #define PSP_DTM_SHARED_MEM_SIZE 0x4000 43 #define PSP_RAP_SHARED_MEM_SIZE 0x4000 44 #define PSP_SECUREDISPLAY_SHARED_MEM_SIZE 0x4000 45 #define PSP_SHARED_MEM_SIZE 0x4000 46 #define PSP_FW_NAME_LEN 0x24 47 48 struct psp_context; 49 struct psp_xgmi_node_info; 50 struct psp_xgmi_topology_info; 51 struct psp_bin_desc; 52 53 enum psp_bootloader_cmd { 54 PSP_BL__LOAD_SYSDRV = 0x10000, 55 PSP_BL__LOAD_SOSDRV = 0x20000, 56 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 57 PSP_BL__LOAD_SOCDRV = 0xB0000, 58 PSP_BL__LOAD_INTFDRV = 0xC0000, 59 PSP_BL__LOAD_DBGDRV = 0xD0000, 60 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 61 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 62 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 63 }; 64 65 enum psp_ring_type 66 { 67 PSP_RING_TYPE__INVALID = 0, 68 /* 69 * These values map to the way the PSP kernel identifies the 70 * rings. 71 */ 72 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 73 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 74 }; 75 76 struct psp_ring 77 { 78 enum psp_ring_type ring_type; 79 struct psp_gfx_rb_frame *ring_mem; 80 uint64_t ring_mem_mc_addr; 81 void *ring_mem_handle; 82 uint32_t ring_size; 83 uint32_t ring_wptr; 84 }; 85 86 /* More registers may will be supported */ 87 enum psp_reg_prog_id { 88 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 89 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 90 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 91 PSP_REG_LAST 92 }; 93 94 struct psp_funcs 95 { 96 int (*init_microcode)(struct psp_context *psp); 97 int (*bootloader_load_kdb)(struct psp_context *psp); 98 int (*bootloader_load_spl)(struct psp_context *psp); 99 int (*bootloader_load_sysdrv)(struct psp_context *psp); 100 int (*bootloader_load_soc_drv)(struct psp_context *psp); 101 int (*bootloader_load_intf_drv)(struct psp_context *psp); 102 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 103 int (*bootloader_load_sos)(struct psp_context *psp); 104 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 105 int (*ring_create)(struct psp_context *psp, 106 enum psp_ring_type ring_type); 107 int (*ring_stop)(struct psp_context *psp, 108 enum psp_ring_type ring_type); 109 int (*ring_destroy)(struct psp_context *psp, 110 enum psp_ring_type ring_type); 111 bool (*smu_reload_quirk)(struct psp_context *psp); 112 int (*mode1_reset)(struct psp_context *psp); 113 int (*mem_training)(struct psp_context *psp, uint32_t ops); 114 uint32_t (*ring_get_wptr)(struct psp_context *psp); 115 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 116 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 117 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 118 }; 119 120 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 121 struct psp_xgmi_node_info { 122 uint64_t node_id; 123 uint8_t num_hops; 124 uint8_t is_sharing_enabled; 125 enum ta_xgmi_assigned_sdma_engine sdma_engine; 126 uint8_t num_links; 127 }; 128 129 struct psp_xgmi_topology_info { 130 uint32_t num_nodes; 131 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 132 }; 133 134 struct psp_asd_context { 135 bool asd_initialized; 136 uint32_t session_id; 137 }; 138 139 struct psp_xgmi_context { 140 uint8_t initialized; 141 uint32_t session_id; 142 struct amdgpu_bo *xgmi_shared_bo; 143 uint64_t xgmi_shared_mc_addr; 144 void *xgmi_shared_buf; 145 struct psp_xgmi_topology_info top_info; 146 }; 147 148 struct psp_ras_context { 149 /*ras fw*/ 150 bool ras_initialized; 151 uint32_t session_id; 152 struct amdgpu_bo *ras_shared_bo; 153 uint64_t ras_shared_mc_addr; 154 void *ras_shared_buf; 155 struct amdgpu_ras *ras; 156 }; 157 158 struct psp_hdcp_context { 159 bool hdcp_initialized; 160 uint32_t session_id; 161 struct amdgpu_bo *hdcp_shared_bo; 162 uint64_t hdcp_shared_mc_addr; 163 void *hdcp_shared_buf; 164 struct mutex mutex; 165 }; 166 167 struct psp_dtm_context { 168 bool dtm_initialized; 169 uint32_t session_id; 170 struct amdgpu_bo *dtm_shared_bo; 171 uint64_t dtm_shared_mc_addr; 172 void *dtm_shared_buf; 173 struct mutex mutex; 174 }; 175 176 struct psp_rap_context { 177 bool rap_initialized; 178 uint32_t session_id; 179 struct amdgpu_bo *rap_shared_bo; 180 uint64_t rap_shared_mc_addr; 181 void *rap_shared_buf; 182 struct mutex mutex; 183 }; 184 185 struct psp_securedisplay_context { 186 bool securedisplay_initialized; 187 uint32_t session_id; 188 struct amdgpu_bo *securedisplay_shared_bo; 189 uint64_t securedisplay_shared_mc_addr; 190 void *securedisplay_shared_buf; 191 struct mutex mutex; 192 }; 193 194 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 195 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 196 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 197 /*Define the VRAM size that will be encroached by BIST training.*/ 198 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 199 200 enum psp_memory_training_init_flag { 201 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 202 PSP_MEM_TRAIN_SUPPORT = 0x1, 203 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 204 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 205 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 206 }; 207 208 enum psp_memory_training_ops { 209 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 210 PSP_MEM_TRAIN_SAVE = 0x2, 211 PSP_MEM_TRAIN_RESTORE = 0x4, 212 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 213 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 214 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 215 }; 216 217 struct psp_memory_training_context { 218 /*training data size*/ 219 u64 train_data_size; 220 /* 221 * sys_cache 222 * cpu virtual address 223 * system memory buffer that used to store the training data. 224 */ 225 void *sys_cache; 226 227 /*vram offset of the p2c training data*/ 228 u64 p2c_train_data_offset; 229 230 /*vram offset of the c2p training data*/ 231 u64 c2p_train_data_offset; 232 struct amdgpu_bo *c2p_bo; 233 234 enum psp_memory_training_init_flag init; 235 u32 training_cnt; 236 bool enable_mem_training; 237 }; 238 239 /** PSP runtime DB **/ 240 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 241 #define PSP_RUNTIME_DB_OFFSET 0x100000 242 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 243 #define PSP_RUNTIME_DB_VER_1 0x0100 244 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 245 246 enum psp_runtime_entry_type { 247 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 248 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 249 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 250 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 251 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 252 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 253 }; 254 255 /* PSP runtime DB header */ 256 struct psp_runtime_data_header { 257 /* determine the existence of runtime db */ 258 uint16_t cookie; 259 /* version of runtime db */ 260 uint16_t version; 261 }; 262 263 /* PSP runtime DB entry */ 264 struct psp_runtime_entry { 265 /* type of runtime db entry */ 266 uint32_t entry_type; 267 /* offset of entry in bytes */ 268 uint16_t offset; 269 /* size of entry in bytes */ 270 uint16_t size; 271 }; 272 273 /* PSP runtime DB directory */ 274 struct psp_runtime_data_directory { 275 /* number of valid entries */ 276 uint16_t entry_count; 277 /* db entries*/ 278 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 279 }; 280 281 /* PSP runtime DB boot config feature bitmask */ 282 enum psp_runtime_boot_cfg_feature { 283 BOOT_CFG_FEATURE_GECC = 0x1, 284 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 285 }; 286 287 /* PSP runtime DB boot config entry */ 288 struct psp_runtime_boot_cfg_entry { 289 uint32_t boot_cfg_bitmask; 290 uint32_t reserved; 291 }; 292 293 struct psp_bin_desc { 294 uint32_t fw_version; 295 uint32_t feature_version; 296 uint32_t size_bytes; 297 uint8_t *start_addr; 298 }; 299 300 struct psp_context 301 { 302 struct amdgpu_device *adev; 303 struct psp_ring km_ring; 304 struct psp_gfx_cmd_resp *cmd; 305 306 const struct psp_funcs *funcs; 307 308 /* firmware buffer */ 309 struct amdgpu_bo *fw_pri_bo; 310 uint64_t fw_pri_mc_addr; 311 void *fw_pri_buf; 312 313 /* sos firmware */ 314 const struct firmware *sos_fw; 315 struct psp_bin_desc sys; 316 struct psp_bin_desc sos; 317 struct psp_bin_desc toc; 318 struct psp_bin_desc kdb; 319 struct psp_bin_desc spl; 320 struct psp_bin_desc rl; 321 struct psp_bin_desc soc_drv; 322 struct psp_bin_desc intf_drv; 323 struct psp_bin_desc dbg_drv; 324 325 /* tmr buffer */ 326 struct amdgpu_bo *tmr_bo; 327 uint64_t tmr_mc_addr; 328 329 /* asd firmware */ 330 const struct firmware *asd_fw; 331 uint32_t asd_fw_version; 332 uint32_t asd_feature_version; 333 uint32_t asd_ucode_size; 334 uint8_t *asd_start_addr; 335 336 /* toc firmware */ 337 const struct firmware *toc_fw; 338 339 /* fence buffer */ 340 struct amdgpu_bo *fence_buf_bo; 341 uint64_t fence_buf_mc_addr; 342 void *fence_buf; 343 344 /* cmd buffer */ 345 struct amdgpu_bo *cmd_buf_bo; 346 uint64_t cmd_buf_mc_addr; 347 struct psp_gfx_cmd_resp *cmd_buf_mem; 348 349 /* fence value associated with cmd buffer */ 350 atomic_t fence_value; 351 /* flag to mark whether gfx fw autoload is supported or not */ 352 bool autoload_supported; 353 /* flag to mark whether df cstate management centralized to PMFW */ 354 bool pmfw_centralized_cstate_management; 355 356 /* xgmi ta firmware and buffer */ 357 const struct firmware *ta_fw; 358 uint32_t ta_fw_version; 359 uint32_t ta_xgmi_ucode_version; 360 uint32_t ta_xgmi_ucode_size; 361 uint8_t *ta_xgmi_start_addr; 362 uint32_t ta_ras_ucode_version; 363 uint32_t ta_ras_ucode_size; 364 uint8_t *ta_ras_start_addr; 365 366 uint32_t ta_hdcp_ucode_version; 367 uint32_t ta_hdcp_ucode_size; 368 uint8_t *ta_hdcp_start_addr; 369 370 uint32_t ta_dtm_ucode_version; 371 uint32_t ta_dtm_ucode_size; 372 uint8_t *ta_dtm_start_addr; 373 374 uint32_t ta_rap_ucode_version; 375 uint32_t ta_rap_ucode_size; 376 uint8_t *ta_rap_start_addr; 377 378 uint32_t ta_securedisplay_ucode_version; 379 uint32_t ta_securedisplay_ucode_size; 380 uint8_t *ta_securedisplay_start_addr; 381 382 struct psp_asd_context asd_context; 383 struct psp_xgmi_context xgmi_context; 384 struct psp_ras_context ras; 385 struct psp_hdcp_context hdcp_context; 386 struct psp_dtm_context dtm_context; 387 struct psp_rap_context rap_context; 388 struct psp_securedisplay_context securedisplay_context; 389 struct mutex mutex; 390 struct psp_memory_training_context mem_train_ctx; 391 392 uint32_t boot_cfg_bitmask; 393 }; 394 395 struct amdgpu_psp_funcs { 396 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 397 enum AMDGPU_UCODE_ID); 398 }; 399 400 401 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 402 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 403 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 404 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 405 #define psp_init_microcode(psp) \ 406 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 407 #define psp_bootloader_load_kdb(psp) \ 408 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 409 #define psp_bootloader_load_spl(psp) \ 410 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 411 #define psp_bootloader_load_sysdrv(psp) \ 412 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 413 #define psp_bootloader_load_soc_drv(psp) \ 414 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 415 #define psp_bootloader_load_intf_drv(psp) \ 416 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 417 #define psp_bootloader_load_dbg_drv(psp) \ 418 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 419 #define psp_bootloader_load_sos(psp) \ 420 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 421 #define psp_smu_reload_quirk(psp) \ 422 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 423 #define psp_mode1_reset(psp) \ 424 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 425 #define psp_mem_training(psp, ops) \ 426 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 427 428 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 429 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 430 431 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 432 ((psp)->funcs->load_usbc_pd_fw ? \ 433 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 434 435 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 436 ((psp)->funcs->read_usbc_pd_fw ? \ 437 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 438 439 extern const struct amd_ip_funcs psp_ip_funcs; 440 441 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 442 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 443 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 444 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 445 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 446 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 447 448 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 449 uint32_t field_val, uint32_t mask, bool check_changed); 450 451 int psp_gpu_reset(struct amdgpu_device *adev); 452 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 453 uint64_t cmd_gpu_addr, int cmd_size); 454 455 int psp_xgmi_initialize(struct psp_context *psp); 456 int psp_xgmi_terminate(struct psp_context *psp); 457 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 458 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 459 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 460 int psp_xgmi_get_topology_info(struct psp_context *psp, 461 int number_devices, 462 struct psp_xgmi_topology_info *topology); 463 int psp_xgmi_set_topology_info(struct psp_context *psp, 464 int number_devices, 465 struct psp_xgmi_topology_info *topology); 466 467 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 468 int psp_ras_enable_features(struct psp_context *psp, 469 union ta_ras_cmd_input *info, bool enable); 470 int psp_ras_trigger_error(struct psp_context *psp, 471 struct ta_ras_trigger_error_input *info); 472 473 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 474 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 475 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 476 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 477 478 int psp_rlc_autoload_start(struct psp_context *psp); 479 480 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 481 uint32_t value); 482 int psp_ring_cmd_submit(struct psp_context *psp, 483 uint64_t cmd_buf_mc_addr, 484 uint64_t fence_mc_addr, 485 int index); 486 int psp_init_asd_microcode(struct psp_context *psp, 487 const char *chip_name); 488 int psp_init_toc_microcode(struct psp_context *psp, 489 const char *chip_name); 490 int psp_init_sos_microcode(struct psp_context *psp, 491 const char *chip_name); 492 int psp_init_ta_microcode(struct psp_context *psp, 493 const char *chip_name); 494 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 495 uint64_t *output_ptr); 496 497 int psp_load_fw_list(struct psp_context *psp, 498 struct amdgpu_firmware_info **ucode_list, int ucode_count); 499 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 500 501 int is_psp_fw_valid(struct psp_bin_desc bin); 502 #endif 503