1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 /* VBIOS gfl defines */ 43 #define MBOX_READY_MASK 0x80000000 44 #define MBOX_STATUS_MASK 0x0000FFFF 45 #define MBOX_COMMAND_MASK 0x00FF0000 46 #define MBOX_READY_FLAG 0x80000000 47 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 48 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 49 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 50 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO 0xf 51 #define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10 52 #define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11 53 54 /* Command register bit 31 set to indicate readiness */ 55 #define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE) 56 #define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) 57 58 /* Values to check for a successful GFX_CMD response wait. Check against 59 * both status bits and response state - helps to detect a command failure 60 * or other unexpected cases like a device drop reading all 0xFFs 61 */ 62 #define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE) 63 #define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) 64 65 extern const struct attribute_group amdgpu_flash_attr_group; 66 67 enum psp_shared_mem_size { 68 PSP_ASD_SHARED_MEM_SIZE = 0x0, 69 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 70 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 71 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 72 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 73 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 74 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 75 }; 76 77 enum ta_type_id { 78 TA_TYPE_XGMI = 1, 79 TA_TYPE_RAS, 80 TA_TYPE_HDCP, 81 TA_TYPE_DTM, 82 TA_TYPE_RAP, 83 TA_TYPE_SECUREDISPLAY, 84 85 TA_TYPE_MAX_INDEX, 86 }; 87 88 struct psp_context; 89 struct psp_xgmi_node_info; 90 struct psp_xgmi_topology_info; 91 struct psp_bin_desc; 92 93 enum psp_bootloader_cmd { 94 PSP_BL__LOAD_SYSDRV = 0x10000, 95 PSP_BL__LOAD_SOSDRV = 0x20000, 96 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 97 PSP_BL__LOAD_SOCDRV = 0xB0000, 98 PSP_BL__LOAD_DBGDRV = 0xC0000, 99 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 100 PSP_BL__LOAD_INTFDRV = 0xD0000, 101 PSP_BL__LOAD_RASDRV = 0xE0000, 102 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 103 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 104 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 105 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 106 PSP_BL__LOAD_SPDMDRV = 0x20000000, 107 }; 108 109 enum psp_ring_type { 110 PSP_RING_TYPE__INVALID = 0, 111 /* 112 * These values map to the way the PSP kernel identifies the 113 * rings. 114 */ 115 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 116 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 117 }; 118 119 struct psp_ring { 120 enum psp_ring_type ring_type; 121 struct psp_gfx_rb_frame *ring_mem; 122 uint64_t ring_mem_mc_addr; 123 void *ring_mem_handle; 124 uint32_t ring_size; 125 uint32_t ring_wptr; 126 }; 127 128 /* More registers may will be supported */ 129 enum psp_reg_prog_id { 130 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 131 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 132 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 133 PSP_REG_MMHUB_L1_TLB_CNTL = 25, 134 PSP_REG_LAST 135 }; 136 137 struct psp_funcs { 138 int (*init_microcode)(struct psp_context *psp); 139 int (*wait_for_bootloader)(struct psp_context *psp); 140 int (*bootloader_load_kdb)(struct psp_context *psp); 141 int (*bootloader_load_spl)(struct psp_context *psp); 142 int (*bootloader_load_sysdrv)(struct psp_context *psp); 143 int (*bootloader_load_soc_drv)(struct psp_context *psp); 144 int (*bootloader_load_intf_drv)(struct psp_context *psp); 145 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 146 int (*bootloader_load_ras_drv)(struct psp_context *psp); 147 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 148 int (*bootloader_load_spdm_drv)(struct psp_context *psp); 149 int (*bootloader_load_sos)(struct psp_context *psp); 150 int (*ring_create)(struct psp_context *psp, 151 enum psp_ring_type ring_type); 152 int (*ring_stop)(struct psp_context *psp, 153 enum psp_ring_type ring_type); 154 int (*ring_destroy)(struct psp_context *psp, 155 enum psp_ring_type ring_type); 156 bool (*smu_reload_quirk)(struct psp_context *psp); 157 int (*mode1_reset)(struct psp_context *psp); 158 int (*mem_training)(struct psp_context *psp, uint32_t ops); 159 uint32_t (*ring_get_wptr)(struct psp_context *psp); 160 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 161 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 162 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 163 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 164 int (*dump_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 165 int (*vbflash_stat)(struct psp_context *psp); 166 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 167 bool (*get_ras_capability)(struct psp_context *psp); 168 bool (*is_aux_sos_load_required)(struct psp_context *psp); 169 bool (*is_reload_needed)(struct psp_context *psp); 170 int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val, 171 enum psp_reg_prog_id id); 172 }; 173 174 struct ta_funcs { 175 int (*fn_ta_initialize)(struct psp_context *psp); 176 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 177 int (*fn_ta_terminate)(struct psp_context *psp); 178 }; 179 180 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 181 struct psp_xgmi_node_info { 182 uint64_t node_id; 183 uint8_t num_hops; 184 uint8_t is_sharing_enabled; 185 enum ta_xgmi_assigned_sdma_engine sdma_engine; 186 uint8_t num_links; 187 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 188 }; 189 190 struct psp_xgmi_topology_info { 191 uint32_t num_nodes; 192 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 193 }; 194 195 struct psp_bin_desc { 196 uint32_t fw_version; 197 uint32_t feature_version; 198 uint32_t size_bytes; 199 uint8_t *start_addr; 200 }; 201 202 struct ta_mem_context { 203 struct amdgpu_bo *shared_bo; 204 uint64_t shared_mc_addr; 205 void *shared_buf; 206 enum psp_shared_mem_size shared_mem_size; 207 }; 208 209 struct ta_context { 210 bool initialized; 211 uint32_t session_id; 212 uint32_t resp_status; 213 struct ta_mem_context mem_context; 214 struct psp_bin_desc bin_desc; 215 enum psp_gfx_cmd_id ta_load_type; 216 enum ta_type_id ta_type; 217 }; 218 219 struct ta_cp_context { 220 struct ta_context context; 221 struct mutex mutex; 222 }; 223 224 struct psp_xgmi_context { 225 struct ta_context context; 226 struct psp_xgmi_topology_info top_info; 227 bool supports_extended_data; 228 uint8_t xgmi_ta_caps; 229 }; 230 231 struct psp_ras_context { 232 struct ta_context context; 233 struct amdgpu_ras *ras; 234 struct mutex mutex; 235 }; 236 237 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 238 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 239 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 240 /*Define the VRAM size that will be encroached by BIST training.*/ 241 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 242 243 enum psp_memory_training_init_flag { 244 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 245 PSP_MEM_TRAIN_SUPPORT = 0x1, 246 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 247 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 248 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 249 }; 250 251 enum psp_memory_training_ops { 252 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 253 PSP_MEM_TRAIN_SAVE = 0x2, 254 PSP_MEM_TRAIN_RESTORE = 0x4, 255 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 256 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 257 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 258 }; 259 260 struct psp_memory_training_context { 261 /*training data size*/ 262 u64 train_data_size; 263 /* 264 * sys_cache 265 * cpu virtual address 266 * system memory buffer that used to store the training data. 267 */ 268 void *sys_cache; 269 270 /*vram offset of the p2c training data*/ 271 u64 p2c_train_data_offset; 272 273 /*vram offset of the c2p training data*/ 274 u64 c2p_train_data_offset; 275 struct amdgpu_bo *c2p_bo; 276 277 enum psp_memory_training_init_flag init; 278 u32 training_cnt; 279 bool enable_mem_training; 280 }; 281 282 /** PSP runtime DB **/ 283 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 284 #define PSP_RUNTIME_DB_OFFSET 0x100000 285 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 286 #define PSP_RUNTIME_DB_VER_1 0x0100 287 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 288 289 enum psp_runtime_entry_type { 290 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 291 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 292 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 293 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 294 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 295 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 296 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 297 }; 298 299 /* PSP runtime DB header */ 300 struct psp_runtime_data_header { 301 /* determine the existence of runtime db */ 302 uint16_t cookie; 303 /* version of runtime db */ 304 uint16_t version; 305 }; 306 307 /* PSP runtime DB entry */ 308 struct psp_runtime_entry { 309 /* type of runtime db entry */ 310 uint32_t entry_type; 311 /* offset of entry in bytes */ 312 uint16_t offset; 313 /* size of entry in bytes */ 314 uint16_t size; 315 }; 316 317 /* PSP runtime DB directory */ 318 struct psp_runtime_data_directory { 319 /* number of valid entries */ 320 uint16_t entry_count; 321 /* db entries*/ 322 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 323 }; 324 325 /* PSP runtime DB boot config feature bitmask */ 326 enum psp_runtime_boot_cfg_feature { 327 BOOT_CFG_FEATURE_GECC = 0x1, 328 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 329 }; 330 331 /* PSP run time DB SCPM authentication defines */ 332 enum psp_runtime_scpm_authentication { 333 SCPM_DISABLE = 0x0, 334 SCPM_ENABLE = 0x1, 335 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 336 }; 337 338 /* PSP runtime DB boot config entry */ 339 struct psp_runtime_boot_cfg_entry { 340 uint32_t boot_cfg_bitmask; 341 uint32_t reserved; 342 }; 343 344 /* PSP runtime DB SCPM entry */ 345 struct psp_runtime_scpm_entry { 346 enum psp_runtime_scpm_authentication scpm_status; 347 }; 348 349 #if defined(CONFIG_DEBUG_FS) 350 struct spirom_bo { 351 struct amdgpu_bo *bo; 352 uint64_t mc_addr; 353 void *cpu_addr; 354 }; 355 #endif 356 357 struct psp_context { 358 struct amdgpu_device *adev; 359 struct psp_ring km_ring; 360 struct psp_gfx_cmd_resp *cmd; 361 362 const struct psp_funcs *funcs; 363 const struct ta_funcs *ta_funcs; 364 365 /* firmware buffer */ 366 struct amdgpu_bo *fw_pri_bo; 367 uint64_t fw_pri_mc_addr; 368 void *fw_pri_buf; 369 370 /* sos firmware */ 371 const struct firmware *sos_fw; 372 struct psp_bin_desc sys; 373 struct psp_bin_desc sos; 374 struct psp_bin_desc toc; 375 struct psp_bin_desc kdb; 376 struct psp_bin_desc spl; 377 struct psp_bin_desc rl; 378 struct psp_bin_desc soc_drv; 379 struct psp_bin_desc intf_drv; 380 struct psp_bin_desc dbg_drv; 381 struct psp_bin_desc ras_drv; 382 struct psp_bin_desc ipkeymgr_drv; 383 struct psp_bin_desc spdm_drv; 384 385 /* tmr buffer */ 386 struct amdgpu_bo *tmr_bo; 387 uint64_t tmr_mc_addr; 388 389 /* asd firmware */ 390 const struct firmware *asd_fw; 391 392 /* toc firmware */ 393 const struct firmware *toc_fw; 394 395 /* cap firmware */ 396 const struct firmware *cap_fw; 397 398 /* fence buffer */ 399 struct amdgpu_bo *fence_buf_bo; 400 uint64_t fence_buf_mc_addr; 401 void *fence_buf; 402 403 /* cmd buffer */ 404 struct amdgpu_bo *cmd_buf_bo; 405 uint64_t cmd_buf_mc_addr; 406 struct psp_gfx_cmd_resp *cmd_buf_mem; 407 408 /* fence value associated with cmd buffer */ 409 atomic_t fence_value; 410 /* flag to mark whether gfx fw autoload is supported or not */ 411 bool autoload_supported; 412 /* flag to mark whether psp use runtime TMR or boottime TMR */ 413 bool boot_time_tmr; 414 /* flag to mark whether df cstate management centralized to PMFW */ 415 bool pmfw_centralized_cstate_management; 416 417 /* xgmi ta firmware and buffer */ 418 const struct firmware *ta_fw; 419 uint32_t ta_fw_version; 420 421 uint32_t cap_fw_version; 422 uint32_t cap_feature_version; 423 uint32_t cap_ucode_size; 424 425 struct ta_context asd_context; 426 struct psp_xgmi_context xgmi_context; 427 struct psp_ras_context ras_context; 428 struct ta_cp_context hdcp_context; 429 struct ta_cp_context dtm_context; 430 struct ta_cp_context rap_context; 431 struct ta_cp_context securedisplay_context; 432 struct mutex mutex; 433 struct psp_memory_training_context mem_train_ctx; 434 435 uint32_t boot_cfg_bitmask; 436 437 /* firmware upgrades supported */ 438 bool sup_pd_fw_up; 439 bool sup_ifwi_up; 440 441 char *vbflash_tmp_buf; 442 size_t vbflash_image_size; 443 bool vbflash_done; 444 #if defined(CONFIG_DEBUG_FS) 445 struct spirom_bo *spirom_dump_trip; 446 #endif 447 }; 448 449 struct amdgpu_psp_funcs { 450 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 451 enum AMDGPU_UCODE_ID); 452 }; 453 454 455 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 456 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 457 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 458 #define psp_init_microcode(psp) \ 459 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 460 #define psp_bootloader_load_kdb(psp) \ 461 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 462 #define psp_bootloader_load_spl(psp) \ 463 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 464 #define psp_bootloader_load_sysdrv(psp) \ 465 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 466 #define psp_bootloader_load_soc_drv(psp) \ 467 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 468 #define psp_bootloader_load_intf_drv(psp) \ 469 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 470 #define psp_bootloader_load_dbg_drv(psp) \ 471 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 472 #define psp_bootloader_load_ras_drv(psp) \ 473 ((psp)->funcs->bootloader_load_ras_drv ? \ 474 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 475 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 476 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 477 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 478 #define psp_bootloader_load_spdm_drv(psp) \ 479 ((psp)->funcs->bootloader_load_spdm_drv ? \ 480 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0) 481 #define psp_bootloader_load_sos(psp) \ 482 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 483 #define psp_smu_reload_quirk(psp) \ 484 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 485 #define psp_mode1_reset(psp) \ 486 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 487 #define psp_mem_training(psp, ops) \ 488 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 489 490 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 491 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 492 493 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 494 ((psp)->funcs->load_usbc_pd_fw ? \ 495 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 496 497 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 498 ((psp)->funcs->read_usbc_pd_fw ? \ 499 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 500 501 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 502 ((psp)->funcs->update_spirom ? \ 503 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 504 505 #define psp_dump_spirom(psp, fw_pri_mc_addr) \ 506 ((psp)->funcs->dump_spirom ? \ 507 (psp)->funcs->dump_spirom((psp), fw_pri_mc_addr) : -EINVAL) 508 509 #define psp_vbflash_status(psp) \ 510 ((psp)->funcs->vbflash_stat ? \ 511 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 512 513 #define psp_fatal_error_recovery_quirk(psp) \ 514 ((psp)->funcs->fatal_error_recovery_quirk ? \ 515 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 516 517 #define psp_is_aux_sos_load_required(psp) \ 518 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) 519 520 #define psp_reg_program_no_ring(psp, val, id) \ 521 ((psp)->funcs->reg_program_no_ring ? \ 522 (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL) 523 524 extern const struct amd_ip_funcs psp_ip_funcs; 525 526 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 527 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 528 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 529 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 530 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 531 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 532 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 533 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 534 535 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 536 uint32_t field_val, uint32_t mask, bool check_changed); 537 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 538 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 539 540 int psp_execute_ip_fw_load(struct psp_context *psp, 541 struct amdgpu_firmware_info *ucode); 542 543 int psp_gpu_reset(struct amdgpu_device *adev); 544 545 int psp_ta_init_shared_buf(struct psp_context *psp, 546 struct ta_mem_context *mem_ctx); 547 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 548 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 549 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 550 int psp_ta_invoke(struct psp_context *psp, 551 uint32_t ta_cmd_id, 552 struct ta_context *context); 553 554 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 555 int psp_xgmi_terminate(struct psp_context *psp); 556 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 557 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 558 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 559 int psp_xgmi_get_topology_info(struct psp_context *psp, 560 int number_devices, 561 struct psp_xgmi_topology_info *topology, 562 bool get_extended_data); 563 int psp_xgmi_set_topology_info(struct psp_context *psp, 564 int number_devices, 565 struct psp_xgmi_topology_info *topology); 566 int psp_ras_initialize(struct psp_context *psp); 567 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 568 int psp_ras_enable_features(struct psp_context *psp, 569 union ta_ras_cmd_input *info, bool enable); 570 int psp_ras_trigger_error(struct psp_context *psp, 571 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 572 int psp_ras_terminate(struct psp_context *psp); 573 int psp_ras_query_address(struct psp_context *psp, 574 struct ta_ras_query_address_input *addr_in, 575 struct ta_ras_query_address_output *addr_out); 576 577 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 578 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 579 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 580 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 581 582 int psp_rlc_autoload_start(struct psp_context *psp); 583 584 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 585 uint32_t value); 586 int psp_ring_cmd_submit(struct psp_context *psp, 587 uint64_t cmd_buf_mc_addr, 588 uint64_t fence_mc_addr, 589 int index); 590 int psp_init_asd_microcode(struct psp_context *psp, 591 const char *chip_name); 592 int psp_init_toc_microcode(struct psp_context *psp, 593 const char *chip_name); 594 int psp_init_sos_microcode(struct psp_context *psp, 595 const char *chip_name); 596 int psp_init_ta_microcode(struct psp_context *psp, 597 const char *chip_name); 598 int psp_init_cap_microcode(struct psp_context *psp, 599 const char *chip_name); 600 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 601 uint64_t *output_ptr); 602 int psp_update_fw_reservation(struct psp_context *psp); 603 int psp_load_fw_list(struct psp_context *psp, 604 struct amdgpu_firmware_info **ucode_list, int ucode_count); 605 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 606 607 int psp_spatial_partition(struct psp_context *psp, int mode); 608 int psp_memory_partition(struct psp_context *psp, int mode); 609 610 int is_psp_fw_valid(struct psp_bin_desc bin); 611 612 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 613 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 614 615 int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, 616 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 617 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); 618 int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, 619 enum psp_reg_prog_id id); 620 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); 621 622 623 #endif 624