1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 case IP_VERSION(13, 0, 14): 149 ret = psp_init_cap_microcode(psp, ucode_prefix); 150 ret &= psp_init_ta_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 case IP_VERSION(13, 0, 12): 157 ret = psp_init_ta_microcode(psp, ucode_prefix); 158 break; 159 default: 160 return -EINVAL; 161 } 162 return ret; 163 } 164 165 static int psp_early_init(struct amdgpu_ip_block *ip_block) 166 { 167 struct amdgpu_device *adev = ip_block->adev; 168 struct psp_context *psp = &adev->psp; 169 170 psp->autoload_supported = true; 171 psp->boot_time_tmr = true; 172 173 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 174 case IP_VERSION(9, 0, 0): 175 psp_v3_1_set_psp_funcs(psp); 176 psp->autoload_supported = false; 177 psp->boot_time_tmr = false; 178 break; 179 case IP_VERSION(10, 0, 0): 180 case IP_VERSION(10, 0, 1): 181 psp_v10_0_set_psp_funcs(psp); 182 psp->autoload_supported = false; 183 psp->boot_time_tmr = false; 184 break; 185 case IP_VERSION(11, 0, 2): 186 case IP_VERSION(11, 0, 4): 187 psp_v11_0_set_psp_funcs(psp); 188 psp->autoload_supported = false; 189 psp->boot_time_tmr = false; 190 break; 191 case IP_VERSION(11, 0, 0): 192 case IP_VERSION(11, 0, 7): 193 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 194 fallthrough; 195 case IP_VERSION(11, 0, 5): 196 case IP_VERSION(11, 0, 9): 197 case IP_VERSION(11, 0, 11): 198 case IP_VERSION(11, 5, 0): 199 case IP_VERSION(11, 5, 2): 200 case IP_VERSION(11, 0, 12): 201 case IP_VERSION(11, 0, 13): 202 psp_v11_0_set_psp_funcs(psp); 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 3): 206 case IP_VERSION(12, 0, 1): 207 psp_v12_0_set_psp_funcs(psp); 208 psp->autoload_supported = false; 209 psp->boot_time_tmr = false; 210 break; 211 case IP_VERSION(13, 0, 2): 212 psp->boot_time_tmr = false; 213 fallthrough; 214 case IP_VERSION(13, 0, 6): 215 case IP_VERSION(13, 0, 14): 216 psp_v13_0_set_psp_funcs(psp); 217 psp->autoload_supported = false; 218 break; 219 case IP_VERSION(13, 0, 12): 220 psp_v13_0_set_psp_funcs(psp); 221 psp->autoload_supported = false; 222 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 223 break; 224 case IP_VERSION(13, 0, 1): 225 case IP_VERSION(13, 0, 3): 226 case IP_VERSION(13, 0, 5): 227 case IP_VERSION(13, 0, 8): 228 case IP_VERSION(13, 0, 11): 229 case IP_VERSION(14, 0, 0): 230 case IP_VERSION(14, 0, 1): 231 case IP_VERSION(14, 0, 4): 232 psp_v13_0_set_psp_funcs(psp); 233 psp->boot_time_tmr = false; 234 break; 235 case IP_VERSION(11, 0, 8): 236 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 237 psp_v11_0_8_set_psp_funcs(psp); 238 } 239 psp->autoload_supported = false; 240 psp->boot_time_tmr = false; 241 break; 242 case IP_VERSION(13, 0, 0): 243 case IP_VERSION(13, 0, 7): 244 case IP_VERSION(13, 0, 10): 245 psp_v13_0_set_psp_funcs(psp); 246 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 247 psp->boot_time_tmr = false; 248 break; 249 case IP_VERSION(13, 0, 4): 250 psp_v13_0_4_set_psp_funcs(psp); 251 psp->boot_time_tmr = false; 252 break; 253 case IP_VERSION(14, 0, 2): 254 case IP_VERSION(14, 0, 3): 255 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 256 psp_v14_0_set_psp_funcs(psp); 257 break; 258 case IP_VERSION(14, 0, 5): 259 psp_v14_0_set_psp_funcs(psp); 260 psp->boot_time_tmr = false; 261 break; 262 default: 263 return -EINVAL; 264 } 265 266 psp->adev = adev; 267 268 adev->psp_timeout = 20000; 269 270 psp_check_pmfw_centralized_cstate_management(psp); 271 272 if (amdgpu_sriov_vf(adev)) 273 return psp_init_sriov_microcode(psp); 274 else 275 return psp_init_microcode(psp); 276 } 277 278 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 279 { 280 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 281 &mem_ctx->shared_buf); 282 mem_ctx->shared_bo = NULL; 283 } 284 285 static void psp_free_shared_bufs(struct psp_context *psp) 286 { 287 void *tmr_buf; 288 void **pptr; 289 290 /* free TMR memory buffer */ 291 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 292 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 293 psp->tmr_bo = NULL; 294 295 /* free xgmi shared memory */ 296 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 297 298 /* free ras shared memory */ 299 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 300 301 /* free hdcp shared memory */ 302 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 303 304 /* free dtm shared memory */ 305 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 306 307 /* free rap shared memory */ 308 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 309 310 /* free securedisplay shared memory */ 311 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 312 313 314 } 315 316 static void psp_memory_training_fini(struct psp_context *psp) 317 { 318 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 319 320 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 321 kfree(ctx->sys_cache); 322 ctx->sys_cache = NULL; 323 } 324 325 static int psp_memory_training_init(struct psp_context *psp) 326 { 327 int ret; 328 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 329 330 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 331 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 332 return 0; 333 } 334 335 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 336 if (ctx->sys_cache == NULL) { 337 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 338 ret = -ENOMEM; 339 goto Err_out; 340 } 341 342 dev_dbg(psp->adev->dev, 343 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 344 ctx->train_data_size, 345 ctx->p2c_train_data_offset, 346 ctx->c2p_train_data_offset); 347 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 348 return 0; 349 350 Err_out: 351 psp_memory_training_fini(psp); 352 return ret; 353 } 354 355 /* 356 * Helper funciton to query psp runtime database entry 357 * 358 * @adev: amdgpu_device pointer 359 * @entry_type: the type of psp runtime database entry 360 * @db_entry: runtime database entry pointer 361 * 362 * Return false if runtime database doesn't exit or entry is invalid 363 * or true if the specific database entry is found, and copy to @db_entry 364 */ 365 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 366 enum psp_runtime_entry_type entry_type, 367 void *db_entry) 368 { 369 uint64_t db_header_pos, db_dir_pos; 370 struct psp_runtime_data_header db_header = {0}; 371 struct psp_runtime_data_directory db_dir = {0}; 372 bool ret = false; 373 int i; 374 375 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 376 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 377 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) 378 return false; 379 380 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 381 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 382 383 /* read runtime db header from vram */ 384 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 385 sizeof(struct psp_runtime_data_header), false); 386 387 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 388 /* runtime db doesn't exist, exit */ 389 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 390 return false; 391 } 392 393 /* read runtime database entry from vram */ 394 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 395 sizeof(struct psp_runtime_data_directory), false); 396 397 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 398 /* invalid db entry count, exit */ 399 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 400 return false; 401 } 402 403 /* look up for requested entry type */ 404 for (i = 0; i < db_dir.entry_count && !ret; i++) { 405 if (db_dir.entry_list[i].entry_type == entry_type) { 406 switch (entry_type) { 407 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 408 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 409 /* invalid db entry size */ 410 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 411 return false; 412 } 413 /* read runtime database entry */ 414 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 415 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 416 ret = true; 417 break; 418 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 419 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 420 /* invalid db entry size */ 421 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 422 return false; 423 } 424 /* read runtime database entry */ 425 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 426 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 427 ret = true; 428 break; 429 default: 430 ret = false; 431 break; 432 } 433 } 434 } 435 436 return ret; 437 } 438 439 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 440 { 441 struct amdgpu_device *adev = ip_block->adev; 442 struct psp_context *psp = &adev->psp; 443 int ret; 444 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 445 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 446 struct psp_runtime_scpm_entry scpm_entry; 447 448 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 449 if (!psp->cmd) { 450 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 451 return -ENOMEM; 452 } 453 454 adev->psp.xgmi_context.supports_extended_data = 455 !adev->gmc.xgmi.connected_to_cpu && 456 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 457 458 memset(&scpm_entry, 0, sizeof(scpm_entry)); 459 if ((psp_get_runtime_db_entry(adev, 460 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 461 &scpm_entry)) && 462 (scpm_entry.scpm_status != SCPM_DISABLE)) { 463 adev->scpm_enabled = true; 464 adev->scpm_status = scpm_entry.scpm_status; 465 } else { 466 adev->scpm_enabled = false; 467 adev->scpm_status = SCPM_DISABLE; 468 } 469 470 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 471 472 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 473 if (psp_get_runtime_db_entry(adev, 474 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 475 &boot_cfg_entry)) { 476 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 477 if ((psp->boot_cfg_bitmask) & 478 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 479 /* If psp runtime database exists, then 480 * only enable two stage memory training 481 * when TWO_STAGE_DRAM_TRAINING bit is set 482 * in runtime database 483 */ 484 mem_training_ctx->enable_mem_training = true; 485 } 486 487 } else { 488 /* If psp runtime database doesn't exist or is 489 * invalid, force enable two stage memory training 490 */ 491 mem_training_ctx->enable_mem_training = true; 492 } 493 494 if (mem_training_ctx->enable_mem_training) { 495 ret = psp_memory_training_init(psp); 496 if (ret) { 497 dev_err(adev->dev, "Failed to initialize memory training!\n"); 498 return ret; 499 } 500 501 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 502 if (ret) { 503 dev_err(adev->dev, "Failed to process memory training!\n"); 504 return ret; 505 } 506 } 507 508 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 509 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 510 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 511 &psp->fw_pri_bo, 512 &psp->fw_pri_mc_addr, 513 &psp->fw_pri_buf); 514 if (ret) 515 return ret; 516 517 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 518 AMDGPU_GEM_DOMAIN_VRAM | 519 AMDGPU_GEM_DOMAIN_GTT, 520 &psp->fence_buf_bo, 521 &psp->fence_buf_mc_addr, 522 &psp->fence_buf); 523 if (ret) 524 goto failed1; 525 526 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 527 AMDGPU_GEM_DOMAIN_VRAM | 528 AMDGPU_GEM_DOMAIN_GTT, 529 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 530 (void **)&psp->cmd_buf_mem); 531 if (ret) 532 goto failed2; 533 534 return 0; 535 536 failed2: 537 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 538 &psp->fence_buf_mc_addr, &psp->fence_buf); 539 failed1: 540 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 541 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 542 return ret; 543 } 544 545 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 546 { 547 struct amdgpu_device *adev = ip_block->adev; 548 struct psp_context *psp = &adev->psp; 549 550 psp_memory_training_fini(psp); 551 552 amdgpu_ucode_release(&psp->sos_fw); 553 amdgpu_ucode_release(&psp->asd_fw); 554 amdgpu_ucode_release(&psp->ta_fw); 555 amdgpu_ucode_release(&psp->cap_fw); 556 amdgpu_ucode_release(&psp->toc_fw); 557 558 kfree(psp->cmd); 559 psp->cmd = NULL; 560 561 psp_free_shared_bufs(psp); 562 563 if (psp->km_ring.ring_mem) 564 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 565 &psp->km_ring.ring_mem_mc_addr, 566 (void **)&psp->km_ring.ring_mem); 567 568 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 569 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 570 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 571 &psp->fence_buf_mc_addr, &psp->fence_buf); 572 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 573 (void **)&psp->cmd_buf_mem); 574 575 return 0; 576 } 577 578 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 579 uint32_t mask, uint32_t flags) 580 { 581 bool check_changed = flags & PSP_WAITREG_CHANGED; 582 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 583 uint32_t val; 584 int i; 585 struct amdgpu_device *adev = psp->adev; 586 587 if (psp->adev->no_hw_access) 588 return 0; 589 590 for (i = 0; i < adev->usec_timeout; i++) { 591 val = RREG32(reg_index); 592 if (check_changed) { 593 if (val != reg_val) 594 return 0; 595 } else { 596 if ((val & mask) == reg_val) 597 return 0; 598 } 599 udelay(1); 600 } 601 602 if (verbose) 603 dev_err(adev->dev, 604 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 605 reg_index, mask, val, reg_val); 606 607 return -ETIME; 608 } 609 610 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 611 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 612 { 613 uint32_t val; 614 int i; 615 struct amdgpu_device *adev = psp->adev; 616 617 if (psp->adev->no_hw_access) 618 return 0; 619 620 for (i = 0; i < msec_timeout; i++) { 621 val = RREG32(reg_index); 622 if ((val & mask) == reg_val) 623 return 0; 624 msleep(1); 625 } 626 627 return -ETIME; 628 } 629 630 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 631 { 632 switch (cmd_id) { 633 case GFX_CMD_ID_LOAD_TA: 634 return "LOAD_TA"; 635 case GFX_CMD_ID_UNLOAD_TA: 636 return "UNLOAD_TA"; 637 case GFX_CMD_ID_INVOKE_CMD: 638 return "INVOKE_CMD"; 639 case GFX_CMD_ID_LOAD_ASD: 640 return "LOAD_ASD"; 641 case GFX_CMD_ID_SETUP_TMR: 642 return "SETUP_TMR"; 643 case GFX_CMD_ID_LOAD_IP_FW: 644 return "LOAD_IP_FW"; 645 case GFX_CMD_ID_DESTROY_TMR: 646 return "DESTROY_TMR"; 647 case GFX_CMD_ID_SAVE_RESTORE: 648 return "SAVE_RESTORE_IP_FW"; 649 case GFX_CMD_ID_SETUP_VMR: 650 return "SETUP_VMR"; 651 case GFX_CMD_ID_DESTROY_VMR: 652 return "DESTROY_VMR"; 653 case GFX_CMD_ID_PROG_REG: 654 return "PROG_REG"; 655 case GFX_CMD_ID_GET_FW_ATTESTATION: 656 return "GET_FW_ATTESTATION"; 657 case GFX_CMD_ID_LOAD_TOC: 658 return "ID_LOAD_TOC"; 659 case GFX_CMD_ID_AUTOLOAD_RLC: 660 return "AUTOLOAD_RLC"; 661 case GFX_CMD_ID_BOOT_CFG: 662 return "BOOT_CFG"; 663 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 664 return "CONFIG_SQ_PERFMON"; 665 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 666 return "FB_FW_RESERV_ADDR"; 667 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 668 return "FB_FW_RESERV_EXT_ADDR"; 669 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 670 return "SPATIAL_PARTITION"; 671 case GFX_CMD_ID_FB_NPS_MODE: 672 return "NPS_MODE_CHANGE"; 673 default: 674 return "UNKNOWN CMD"; 675 } 676 } 677 678 static bool psp_err_warn(struct psp_context *psp) 679 { 680 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 681 682 /* This response indicates reg list is already loaded */ 683 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 684 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 685 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 686 cmd->resp.status == TEE_ERROR_CANCEL) 687 return false; 688 689 return true; 690 } 691 692 static int 693 psp_cmd_submit_buf(struct psp_context *psp, 694 struct amdgpu_firmware_info *ucode, 695 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 696 { 697 int ret; 698 int index; 699 int timeout = psp->adev->psp_timeout; 700 bool ras_intr = false; 701 bool skip_unsupport = false; 702 703 if (psp->adev->no_hw_access) 704 return 0; 705 706 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 707 708 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 709 710 index = atomic_inc_return(&psp->fence_value); 711 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 712 if (ret) { 713 atomic_dec(&psp->fence_value); 714 goto exit; 715 } 716 717 amdgpu_device_invalidate_hdp(psp->adev, NULL); 718 while (*((unsigned int *)psp->fence_buf) != index) { 719 if (--timeout == 0) 720 break; 721 /* 722 * Shouldn't wait for timeout when err_event_athub occurs, 723 * because gpu reset thread triggered and lock resource should 724 * be released for psp resume sequence. 725 */ 726 ras_intr = amdgpu_ras_intr_triggered(); 727 if (ras_intr) 728 break; 729 usleep_range(10, 100); 730 amdgpu_device_invalidate_hdp(psp->adev, NULL); 731 } 732 733 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 734 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 735 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 736 737 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 738 739 /* In some cases, psp response status is not 0 even there is no 740 * problem while the command is submitted. Some version of PSP FW 741 * doesn't write 0 to that field. 742 * So here we would like to only print a warning instead of an error 743 * during psp initialization to avoid breaking hw_init and it doesn't 744 * return -EINVAL. 745 */ 746 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 747 if (ucode) 748 dev_warn(psp->adev->dev, 749 "failed to load ucode %s(0x%X) ", 750 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 751 if (psp_err_warn(psp)) 752 dev_warn( 753 psp->adev->dev, 754 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 755 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 756 psp->cmd_buf_mem->cmd_id, 757 psp->cmd_buf_mem->resp.status); 758 /* If any firmware (including CAP) load fails under SRIOV, it should 759 * return failure to stop the VF from initializing. 760 * Also return failure in case of timeout 761 */ 762 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 763 ret = -EINVAL; 764 goto exit; 765 } 766 } 767 768 if (ucode) { 769 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 770 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 771 } 772 773 exit: 774 return ret; 775 } 776 777 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 778 { 779 struct psp_gfx_cmd_resp *cmd = psp->cmd; 780 781 mutex_lock(&psp->mutex); 782 783 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 784 785 return cmd; 786 } 787 788 static void release_psp_cmd_buf(struct psp_context *psp) 789 { 790 mutex_unlock(&psp->mutex); 791 } 792 793 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 794 struct psp_gfx_cmd_resp *cmd, 795 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 796 { 797 struct amdgpu_device *adev = psp->adev; 798 uint32_t size = 0; 799 uint64_t tmr_pa = 0; 800 801 if (tmr_bo) { 802 size = amdgpu_bo_size(tmr_bo); 803 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 804 } 805 806 if (amdgpu_sriov_vf(psp->adev)) 807 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 808 else 809 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 810 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 811 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 812 cmd->cmd.cmd_setup_tmr.buf_size = size; 813 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 814 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 815 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 816 } 817 818 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 819 uint64_t pri_buf_mc, uint32_t size) 820 { 821 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 822 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 823 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 824 cmd->cmd.cmd_load_toc.toc_size = size; 825 } 826 827 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 828 static int psp_load_toc(struct psp_context *psp, 829 uint32_t *tmr_size) 830 { 831 int ret; 832 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 833 834 /* Copy toc to psp firmware private buffer */ 835 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 836 837 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 838 839 ret = psp_cmd_submit_buf(psp, NULL, cmd, 840 psp->fence_buf_mc_addr); 841 if (!ret) 842 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 843 844 release_psp_cmd_buf(psp); 845 846 return ret; 847 } 848 849 /* Set up Trusted Memory Region */ 850 static int psp_tmr_init(struct psp_context *psp) 851 { 852 int ret = 0; 853 int tmr_size; 854 void *tmr_buf; 855 void **pptr; 856 857 /* 858 * According to HW engineer, they prefer the TMR address be "naturally 859 * aligned" , e.g. the start address be an integer divide of TMR size. 860 * 861 * Note: this memory need be reserved till the driver 862 * uninitializes. 863 */ 864 tmr_size = PSP_TMR_SIZE(psp->adev); 865 866 /* For ASICs support RLC autoload, psp will parse the toc 867 * and calculate the total size of TMR needed 868 */ 869 if (!amdgpu_sriov_vf(psp->adev) && 870 psp->toc.start_addr && 871 psp->toc.size_bytes && 872 psp->fw_pri_buf) { 873 ret = psp_load_toc(psp, &tmr_size); 874 if (ret) { 875 dev_err(psp->adev->dev, "Failed to load toc\n"); 876 return ret; 877 } 878 } 879 880 if (!psp->tmr_bo && !psp->boot_time_tmr) { 881 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 882 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 883 PSP_TMR_ALIGNMENT, 884 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 885 &psp->tmr_bo, &psp->tmr_mc_addr, 886 pptr); 887 } 888 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 889 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 890 891 return ret; 892 } 893 894 static bool psp_skip_tmr(struct psp_context *psp) 895 { 896 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 897 case IP_VERSION(11, 0, 9): 898 case IP_VERSION(11, 0, 7): 899 case IP_VERSION(13, 0, 2): 900 case IP_VERSION(13, 0, 6): 901 case IP_VERSION(13, 0, 10): 902 case IP_VERSION(13, 0, 12): 903 case IP_VERSION(13, 0, 14): 904 return true; 905 default: 906 return false; 907 } 908 } 909 910 static int psp_tmr_load(struct psp_context *psp) 911 { 912 int ret; 913 struct psp_gfx_cmd_resp *cmd; 914 915 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 916 * Already set up by host driver. 917 */ 918 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 919 return 0; 920 921 cmd = acquire_psp_cmd_buf(psp); 922 923 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 924 if (psp->tmr_bo) 925 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 926 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 927 928 ret = psp_cmd_submit_buf(psp, NULL, cmd, 929 psp->fence_buf_mc_addr); 930 931 release_psp_cmd_buf(psp); 932 933 return ret; 934 } 935 936 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 937 struct psp_gfx_cmd_resp *cmd) 938 { 939 if (amdgpu_sriov_vf(psp->adev)) 940 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 941 else 942 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 943 } 944 945 static int psp_tmr_unload(struct psp_context *psp) 946 { 947 int ret; 948 struct psp_gfx_cmd_resp *cmd; 949 950 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 951 * as TMR is not loaded at all 952 */ 953 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 954 return 0; 955 956 cmd = acquire_psp_cmd_buf(psp); 957 958 psp_prep_tmr_unload_cmd_buf(psp, cmd); 959 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 960 961 ret = psp_cmd_submit_buf(psp, NULL, cmd, 962 psp->fence_buf_mc_addr); 963 964 release_psp_cmd_buf(psp); 965 966 return ret; 967 } 968 969 static int psp_tmr_terminate(struct psp_context *psp) 970 { 971 return psp_tmr_unload(psp); 972 } 973 974 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 975 uint64_t *output_ptr) 976 { 977 int ret; 978 struct psp_gfx_cmd_resp *cmd; 979 980 if (!output_ptr) 981 return -EINVAL; 982 983 if (amdgpu_sriov_vf(psp->adev)) 984 return 0; 985 986 cmd = acquire_psp_cmd_buf(psp); 987 988 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 989 990 ret = psp_cmd_submit_buf(psp, NULL, cmd, 991 psp->fence_buf_mc_addr); 992 993 if (!ret) { 994 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 995 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 996 } 997 998 release_psp_cmd_buf(psp); 999 1000 return ret; 1001 } 1002 1003 static int psp_get_fw_reservation_info(struct psp_context *psp, 1004 uint32_t cmd_id, 1005 uint64_t *addr, 1006 uint32_t *size) 1007 { 1008 int ret; 1009 uint32_t status; 1010 struct psp_gfx_cmd_resp *cmd; 1011 1012 cmd = acquire_psp_cmd_buf(psp); 1013 1014 cmd->cmd_id = cmd_id; 1015 1016 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1017 psp->fence_buf_mc_addr); 1018 if (ret) { 1019 release_psp_cmd_buf(psp); 1020 return ret; 1021 } 1022 1023 status = cmd->resp.status; 1024 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1025 release_psp_cmd_buf(psp); 1026 *addr = 0; 1027 *size = 0; 1028 return 0; 1029 } 1030 1031 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1032 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1033 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1034 1035 release_psp_cmd_buf(psp); 1036 1037 return 0; 1038 } 1039 1040 int psp_update_fw_reservation(struct psp_context *psp) 1041 { 1042 int ret; 1043 uint64_t reserv_addr, reserv_addr_ext; 1044 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1045 struct amdgpu_device *adev = psp->adev; 1046 1047 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1048 1049 if (amdgpu_sriov_vf(psp->adev)) 1050 return 0; 1051 1052 switch (mp0_ip_ver) { 1053 case IP_VERSION(14, 0, 2): 1054 if (adev->psp.sos.fw_version < 0x3b0e0d) 1055 return 0; 1056 break; 1057 1058 case IP_VERSION(14, 0, 3): 1059 if (adev->psp.sos.fw_version < 0x3a0e14) 1060 return 0; 1061 break; 1062 1063 default: 1064 return 0; 1065 } 1066 1067 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1068 if (ret) 1069 return ret; 1070 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1071 if (ret) 1072 return ret; 1073 1074 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1075 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1076 return 0; 1077 } 1078 1079 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, NULL); 1080 1081 reserv_size = roundup(reserv_size, SZ_1M); 1082 1083 ret = amdgpu_bo_create_kernel_at(adev, reserv_addr, reserv_size, &adev->mman.fw_reserved_memory, NULL); 1084 if (ret) { 1085 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1086 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, NULL); 1087 return ret; 1088 } 1089 1090 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1091 1092 ret = amdgpu_bo_create_kernel_at(adev, reserv_addr_ext, reserv_size_ext, 1093 &adev->mman.fw_reserved_memory_extend, NULL); 1094 if (ret) { 1095 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1096 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory_extend, NULL, NULL); 1097 return ret; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1104 { 1105 struct psp_context *psp = &adev->psp; 1106 struct psp_gfx_cmd_resp *cmd; 1107 int ret; 1108 1109 if (amdgpu_sriov_vf(adev)) 1110 return 0; 1111 1112 cmd = acquire_psp_cmd_buf(psp); 1113 1114 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1115 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1116 1117 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1118 if (!ret) { 1119 *boot_cfg = 1120 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1121 } 1122 1123 release_psp_cmd_buf(psp); 1124 1125 return ret; 1126 } 1127 1128 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1129 { 1130 int ret; 1131 struct psp_context *psp = &adev->psp; 1132 struct psp_gfx_cmd_resp *cmd; 1133 1134 if (amdgpu_sriov_vf(adev)) 1135 return 0; 1136 1137 cmd = acquire_psp_cmd_buf(psp); 1138 1139 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1140 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1141 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1142 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1143 1144 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1145 1146 release_psp_cmd_buf(psp); 1147 1148 return ret; 1149 } 1150 1151 static int psp_rl_load(struct amdgpu_device *adev) 1152 { 1153 int ret; 1154 struct psp_context *psp = &adev->psp; 1155 struct psp_gfx_cmd_resp *cmd; 1156 1157 if (!is_psp_fw_valid(psp->rl)) 1158 return 0; 1159 1160 cmd = acquire_psp_cmd_buf(psp); 1161 1162 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1163 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1164 1165 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1166 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1167 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1168 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1169 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1170 1171 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1172 1173 release_psp_cmd_buf(psp); 1174 1175 return ret; 1176 } 1177 1178 int psp_memory_partition(struct psp_context *psp, int mode) 1179 { 1180 struct psp_gfx_cmd_resp *cmd; 1181 int ret; 1182 1183 if (amdgpu_sriov_vf(psp->adev)) 1184 return 0; 1185 1186 cmd = acquire_psp_cmd_buf(psp); 1187 1188 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1189 cmd->cmd.cmd_memory_part.mode = mode; 1190 1191 dev_info(psp->adev->dev, 1192 "Requesting %d memory partition change through PSP", mode); 1193 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1194 if (ret) 1195 dev_err(psp->adev->dev, 1196 "PSP request failed to change to NPS%d mode\n", mode); 1197 1198 release_psp_cmd_buf(psp); 1199 1200 return ret; 1201 } 1202 1203 int psp_spatial_partition(struct psp_context *psp, int mode) 1204 { 1205 struct psp_gfx_cmd_resp *cmd; 1206 int ret; 1207 1208 if (amdgpu_sriov_vf(psp->adev)) 1209 return 0; 1210 1211 cmd = acquire_psp_cmd_buf(psp); 1212 1213 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1214 cmd->cmd.cmd_spatial_part.mode = mode; 1215 1216 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1217 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1218 1219 release_psp_cmd_buf(psp); 1220 1221 return ret; 1222 } 1223 1224 static int psp_asd_initialize(struct psp_context *psp) 1225 { 1226 int ret; 1227 1228 /* If PSP version doesn't match ASD version, asd loading will be failed. 1229 * add workaround to bypass it for sriov now. 1230 * TODO: add version check to make it common 1231 */ 1232 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1233 return 0; 1234 1235 /* bypass asd if display hardware is not available */ 1236 if (!amdgpu_device_has_display_hardware(psp->adev) && 1237 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1238 return 0; 1239 1240 psp->asd_context.mem_context.shared_mc_addr = 0; 1241 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1242 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1243 1244 ret = psp_ta_load(psp, &psp->asd_context); 1245 if (!ret) 1246 psp->asd_context.initialized = true; 1247 1248 return ret; 1249 } 1250 1251 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1252 uint32_t session_id) 1253 { 1254 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1255 cmd->cmd.cmd_unload_ta.session_id = session_id; 1256 } 1257 1258 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1259 { 1260 int ret; 1261 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1262 1263 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1264 1265 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1266 1267 context->resp_status = cmd->resp.status; 1268 1269 release_psp_cmd_buf(psp); 1270 1271 return ret; 1272 } 1273 1274 static int psp_asd_terminate(struct psp_context *psp) 1275 { 1276 int ret; 1277 1278 if (amdgpu_sriov_vf(psp->adev)) 1279 return 0; 1280 1281 if (!psp->asd_context.initialized) 1282 return 0; 1283 1284 ret = psp_ta_unload(psp, &psp->asd_context); 1285 if (!ret) 1286 psp->asd_context.initialized = false; 1287 1288 return ret; 1289 } 1290 1291 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1292 uint32_t id, uint32_t value) 1293 { 1294 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1295 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1296 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1297 } 1298 1299 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1300 uint32_t value) 1301 { 1302 struct psp_gfx_cmd_resp *cmd; 1303 int ret = 0; 1304 1305 if (reg >= PSP_REG_LAST) 1306 return -EINVAL; 1307 1308 cmd = acquire_psp_cmd_buf(psp); 1309 1310 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1311 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1312 if (ret) 1313 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1314 1315 release_psp_cmd_buf(psp); 1316 1317 return ret; 1318 } 1319 1320 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1321 uint64_t ta_bin_mc, 1322 struct ta_context *context) 1323 { 1324 cmd->cmd_id = context->ta_load_type; 1325 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1326 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1327 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1328 1329 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1330 lower_32_bits(context->mem_context.shared_mc_addr); 1331 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1332 upper_32_bits(context->mem_context.shared_mc_addr); 1333 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1334 } 1335 1336 int psp_ta_init_shared_buf(struct psp_context *psp, 1337 struct ta_mem_context *mem_ctx) 1338 { 1339 /* 1340 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1341 * physical) for ta to host memory 1342 */ 1343 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1344 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1345 AMDGPU_GEM_DOMAIN_GTT, 1346 &mem_ctx->shared_bo, 1347 &mem_ctx->shared_mc_addr, 1348 &mem_ctx->shared_buf); 1349 } 1350 1351 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1352 uint32_t ta_cmd_id, 1353 uint32_t session_id) 1354 { 1355 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1356 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1357 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1358 } 1359 1360 int psp_ta_invoke(struct psp_context *psp, 1361 uint32_t ta_cmd_id, 1362 struct ta_context *context) 1363 { 1364 int ret; 1365 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1366 1367 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1368 1369 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1370 psp->fence_buf_mc_addr); 1371 1372 context->resp_status = cmd->resp.status; 1373 1374 release_psp_cmd_buf(psp); 1375 1376 return ret; 1377 } 1378 1379 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1380 { 1381 int ret; 1382 struct psp_gfx_cmd_resp *cmd; 1383 1384 cmd = acquire_psp_cmd_buf(psp); 1385 1386 psp_copy_fw(psp, context->bin_desc.start_addr, 1387 context->bin_desc.size_bytes); 1388 1389 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1390 context->mem_context.shared_bo) 1391 context->mem_context.shared_mc_addr = 1392 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1393 1394 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1395 1396 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1397 psp->fence_buf_mc_addr); 1398 1399 context->resp_status = cmd->resp.status; 1400 1401 if (!ret) 1402 context->session_id = cmd->resp.session_id; 1403 1404 release_psp_cmd_buf(psp); 1405 1406 return ret; 1407 } 1408 1409 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1410 { 1411 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1412 } 1413 1414 int psp_xgmi_terminate(struct psp_context *psp) 1415 { 1416 int ret; 1417 struct amdgpu_device *adev = psp->adev; 1418 1419 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1420 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1421 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1422 adev->gmc.xgmi.connected_to_cpu)) 1423 return 0; 1424 1425 if (!psp->xgmi_context.context.initialized) 1426 return 0; 1427 1428 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1429 1430 psp->xgmi_context.context.initialized = false; 1431 1432 return ret; 1433 } 1434 1435 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1436 { 1437 struct ta_xgmi_shared_memory *xgmi_cmd; 1438 int ret; 1439 1440 if (!psp->ta_fw || 1441 !psp->xgmi_context.context.bin_desc.size_bytes || 1442 !psp->xgmi_context.context.bin_desc.start_addr) 1443 return -ENOENT; 1444 1445 if (!load_ta) 1446 goto invoke; 1447 1448 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1449 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1450 1451 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1452 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1453 if (ret) 1454 return ret; 1455 } 1456 1457 /* Load XGMI TA */ 1458 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1459 if (!ret) 1460 psp->xgmi_context.context.initialized = true; 1461 else 1462 return ret; 1463 1464 invoke: 1465 /* Initialize XGMI session */ 1466 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1467 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1468 xgmi_cmd->flag_extend_link_record = set_extended_data; 1469 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1470 1471 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1472 /* note down the capbility flag for XGMI TA */ 1473 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1474 1475 return ret; 1476 } 1477 1478 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1479 { 1480 struct ta_xgmi_shared_memory *xgmi_cmd; 1481 int ret; 1482 1483 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1484 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1485 1486 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1487 1488 /* Invoke xgmi ta to get hive id */ 1489 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1490 if (ret) 1491 return ret; 1492 1493 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1494 1495 return 0; 1496 } 1497 1498 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1499 { 1500 struct ta_xgmi_shared_memory *xgmi_cmd; 1501 int ret; 1502 1503 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1504 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1505 1506 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1507 1508 /* Invoke xgmi ta to get the node id */ 1509 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1510 if (ret) 1511 return ret; 1512 1513 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1514 1515 return 0; 1516 } 1517 1518 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1519 { 1520 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1521 IP_VERSION(13, 0, 2) && 1522 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1523 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1524 IP_VERSION(13, 0, 6); 1525 } 1526 1527 /* 1528 * Chips that support extended topology information require the driver to 1529 * reflect topology information in the opposite direction. This is 1530 * because the TA has already exceeded its link record limit and if the 1531 * TA holds bi-directional information, the driver would have to do 1532 * multiple fetches instead of just two. 1533 */ 1534 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1535 struct psp_xgmi_node_info node_info) 1536 { 1537 struct amdgpu_device *mirror_adev; 1538 struct amdgpu_hive_info *hive; 1539 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1540 uint64_t dst_node_id = node_info.node_id; 1541 uint8_t dst_num_hops = node_info.num_hops; 1542 uint8_t dst_num_links = node_info.num_links; 1543 1544 hive = amdgpu_get_xgmi_hive(psp->adev); 1545 if (WARN_ON(!hive)) 1546 return; 1547 1548 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1549 struct psp_xgmi_topology_info *mirror_top_info; 1550 int j; 1551 1552 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1553 continue; 1554 1555 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1556 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1557 if (mirror_top_info->nodes[j].node_id != src_node_id) 1558 continue; 1559 1560 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1561 /* 1562 * prevent 0 num_links value re-reflection since reflection 1563 * criteria is based on num_hops (direct or indirect). 1564 * 1565 */ 1566 if (dst_num_links) 1567 mirror_top_info->nodes[j].num_links = dst_num_links; 1568 1569 break; 1570 } 1571 1572 break; 1573 } 1574 1575 amdgpu_put_xgmi_hive(hive); 1576 } 1577 1578 int psp_xgmi_get_topology_info(struct psp_context *psp, 1579 int number_devices, 1580 struct psp_xgmi_topology_info *topology, 1581 bool get_extended_data) 1582 { 1583 struct ta_xgmi_shared_memory *xgmi_cmd; 1584 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1585 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1586 int i; 1587 int ret; 1588 1589 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1590 return -EINVAL; 1591 1592 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1593 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1594 xgmi_cmd->flag_extend_link_record = get_extended_data; 1595 1596 /* Fill in the shared memory with topology information as input */ 1597 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1598 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1599 topology_info_input->num_nodes = number_devices; 1600 1601 for (i = 0; i < topology_info_input->num_nodes; i++) { 1602 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1603 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1604 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1605 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1606 } 1607 1608 /* Invoke xgmi ta to get the topology information */ 1609 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1610 if (ret) 1611 return ret; 1612 1613 /* Read the output topology information from the shared memory */ 1614 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1615 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1616 for (i = 0; i < topology->num_nodes; i++) { 1617 /* extended data will either be 0 or equal to non-extended data */ 1618 if (topology_info_output->nodes[i].num_hops) 1619 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1620 1621 /* non-extended data gets everything here so no need to update */ 1622 if (!get_extended_data) { 1623 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1624 topology->nodes[i].is_sharing_enabled = 1625 topology_info_output->nodes[i].is_sharing_enabled; 1626 topology->nodes[i].sdma_engine = 1627 topology_info_output->nodes[i].sdma_engine; 1628 } 1629 1630 } 1631 1632 /* Invoke xgmi ta again to get the link information */ 1633 if (psp_xgmi_peer_link_info_supported(psp)) { 1634 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1635 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1636 bool requires_reflection = 1637 (psp->xgmi_context.supports_extended_data && 1638 get_extended_data) || 1639 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1640 IP_VERSION(13, 0, 6) || 1641 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1642 IP_VERSION(13, 0, 14); 1643 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1644 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1645 1646 /* popluate the shared output buffer rather than the cmd input buffer 1647 * with node_ids as the input for GET_PEER_LINKS command execution. 1648 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1649 * The same requirement for GET_EXTEND_PEER_LINKS command. 1650 */ 1651 if (ta_port_num_support) { 1652 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1653 1654 for (i = 0; i < topology->num_nodes; i++) 1655 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1656 1657 link_extend_info_output->num_nodes = topology->num_nodes; 1658 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1659 } else { 1660 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1661 1662 for (i = 0; i < topology->num_nodes; i++) 1663 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1664 1665 link_info_output->num_nodes = topology->num_nodes; 1666 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1667 } 1668 1669 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1670 if (ret) 1671 return ret; 1672 1673 for (i = 0; i < topology->num_nodes; i++) { 1674 uint8_t node_num_links = ta_port_num_support ? 1675 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1676 /* accumulate num_links on extended data */ 1677 if (get_extended_data) { 1678 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1679 } else { 1680 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1681 topology->nodes[i].num_links : node_num_links; 1682 } 1683 /* popluate the connected port num info if supported and available */ 1684 if (ta_port_num_support && topology->nodes[i].num_links) { 1685 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1686 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1687 } 1688 1689 /* reflect the topology information for bi-directionality */ 1690 if (requires_reflection && topology->nodes[i].num_hops) 1691 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1692 } 1693 } 1694 1695 return 0; 1696 } 1697 1698 int psp_xgmi_set_topology_info(struct psp_context *psp, 1699 int number_devices, 1700 struct psp_xgmi_topology_info *topology) 1701 { 1702 struct ta_xgmi_shared_memory *xgmi_cmd; 1703 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1704 int i; 1705 1706 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1707 return -EINVAL; 1708 1709 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1710 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1711 1712 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1713 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1714 topology_info_input->num_nodes = number_devices; 1715 1716 for (i = 0; i < topology_info_input->num_nodes; i++) { 1717 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1718 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1719 topology_info_input->nodes[i].is_sharing_enabled = 1; 1720 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1721 } 1722 1723 /* Invoke xgmi ta to set topology information */ 1724 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1725 } 1726 1727 // ras begin 1728 static void psp_ras_ta_check_status(struct psp_context *psp) 1729 { 1730 struct ta_ras_shared_memory *ras_cmd = 1731 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1732 1733 switch (ras_cmd->ras_status) { 1734 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1735 dev_warn(psp->adev->dev, 1736 "RAS WARNING: cmd failed due to unsupported ip\n"); 1737 break; 1738 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1739 dev_warn(psp->adev->dev, 1740 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1741 break; 1742 case TA_RAS_STATUS__SUCCESS: 1743 break; 1744 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1745 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1746 dev_warn(psp->adev->dev, 1747 "RAS WARNING: Inject error to critical region is not allowed\n"); 1748 break; 1749 default: 1750 dev_warn(psp->adev->dev, 1751 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1752 break; 1753 } 1754 } 1755 1756 static int psp_ras_send_cmd(struct psp_context *psp, 1757 enum ras_command cmd_id, void *in, void *out) 1758 { 1759 struct ta_ras_shared_memory *ras_cmd; 1760 uint32_t cmd = cmd_id; 1761 int ret = 0; 1762 1763 if (!in) 1764 return -EINVAL; 1765 1766 mutex_lock(&psp->ras_context.mutex); 1767 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1768 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1769 1770 switch (cmd) { 1771 case TA_RAS_COMMAND__ENABLE_FEATURES: 1772 case TA_RAS_COMMAND__DISABLE_FEATURES: 1773 memcpy(&ras_cmd->ras_in_message, 1774 in, sizeof(ras_cmd->ras_in_message)); 1775 break; 1776 case TA_RAS_COMMAND__TRIGGER_ERROR: 1777 memcpy(&ras_cmd->ras_in_message.trigger_error, 1778 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 1779 break; 1780 case TA_RAS_COMMAND__QUERY_ADDRESS: 1781 memcpy(&ras_cmd->ras_in_message.address, 1782 in, sizeof(ras_cmd->ras_in_message.address)); 1783 break; 1784 default: 1785 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 1786 ret = -EINVAL; 1787 goto err_out; 1788 } 1789 1790 ras_cmd->cmd_id = cmd; 1791 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1792 1793 switch (cmd) { 1794 case TA_RAS_COMMAND__TRIGGER_ERROR: 1795 if (!ret && out) 1796 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 1797 break; 1798 case TA_RAS_COMMAND__QUERY_ADDRESS: 1799 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1800 ret = -EINVAL; 1801 else if (out) 1802 memcpy(out, 1803 &ras_cmd->ras_out_message.address, 1804 sizeof(ras_cmd->ras_out_message.address)); 1805 break; 1806 default: 1807 break; 1808 } 1809 1810 err_out: 1811 mutex_unlock(&psp->ras_context.mutex); 1812 1813 return ret; 1814 } 1815 1816 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1817 { 1818 struct ta_ras_shared_memory *ras_cmd; 1819 int ret; 1820 1821 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1822 1823 /* 1824 * TODO: bypass the loading in sriov for now 1825 */ 1826 if (amdgpu_sriov_vf(psp->adev)) 1827 return 0; 1828 1829 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1830 1831 if (amdgpu_ras_intr_triggered()) 1832 return ret; 1833 1834 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1835 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1836 return -EINVAL; 1837 } 1838 1839 if (!ret) { 1840 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1841 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1842 1843 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1844 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1845 dev_warn(psp->adev->dev, 1846 "RAS internal register access blocked\n"); 1847 1848 psp_ras_ta_check_status(psp); 1849 } 1850 1851 return ret; 1852 } 1853 1854 int psp_ras_enable_features(struct psp_context *psp, 1855 union ta_ras_cmd_input *info, bool enable) 1856 { 1857 enum ras_command cmd_id; 1858 int ret; 1859 1860 if (!psp->ras_context.context.initialized || !info) 1861 return -EINVAL; 1862 1863 cmd_id = enable ? 1864 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 1865 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 1866 if (ret) 1867 return -EINVAL; 1868 1869 return 0; 1870 } 1871 1872 int psp_ras_terminate(struct psp_context *psp) 1873 { 1874 int ret; 1875 1876 /* 1877 * TODO: bypass the terminate in sriov for now 1878 */ 1879 if (amdgpu_sriov_vf(psp->adev)) 1880 return 0; 1881 1882 if (!psp->ras_context.context.initialized) 1883 return 0; 1884 1885 ret = psp_ta_unload(psp, &psp->ras_context.context); 1886 1887 psp->ras_context.context.initialized = false; 1888 1889 mutex_destroy(&psp->ras_context.mutex); 1890 1891 return ret; 1892 } 1893 1894 int psp_ras_initialize(struct psp_context *psp) 1895 { 1896 int ret; 1897 uint32_t boot_cfg = 0xFF; 1898 struct amdgpu_device *adev = psp->adev; 1899 struct ta_ras_shared_memory *ras_cmd; 1900 1901 /* 1902 * TODO: bypass the initialize in sriov for now 1903 */ 1904 if (amdgpu_sriov_vf(adev)) 1905 return 0; 1906 1907 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1908 !adev->psp.ras_context.context.bin_desc.start_addr) { 1909 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1910 return 0; 1911 } 1912 1913 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1914 /* query GECC enablement status from boot config 1915 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1916 */ 1917 ret = psp_boot_config_get(adev, &boot_cfg); 1918 if (ret) 1919 dev_warn(adev->dev, "PSP get boot config failed\n"); 1920 1921 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 1922 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1923 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 1924 dev_warn(adev->dev, 1925 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 1926 } else { 1927 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 1928 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1929 if (boot_cfg == 1) { 1930 dev_info(adev->dev, "GECC is enabled\n"); 1931 } else { 1932 /* enable GECC in next boot cycle if it is disabled 1933 * in boot config, or force enable GECC if failed to 1934 * get boot configuration 1935 */ 1936 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1937 if (ret) 1938 dev_warn(adev->dev, "PSP set boot config failed\n"); 1939 else 1940 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1941 } 1942 } else { 1943 if (!boot_cfg) { 1944 if (!adev->ras_default_ecc_enabled && 1945 amdgpu_ras_enable != 1 && 1946 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1947 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 1948 else 1949 dev_info(adev->dev, "GECC is disabled\n"); 1950 } else { 1951 /* disable GECC in next boot cycle if ras is 1952 * disabled by module parameter amdgpu_ras_enable 1953 * and/or amdgpu_ras_mask, or boot_config_get call 1954 * is failed 1955 */ 1956 ret = psp_boot_config_set(adev, 0); 1957 if (ret) 1958 dev_warn(adev->dev, "PSP set boot config failed\n"); 1959 else 1960 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1961 } 1962 } 1963 } 1964 } 1965 1966 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1967 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1968 1969 if (!psp->ras_context.context.mem_context.shared_buf) { 1970 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1971 if (ret) 1972 return ret; 1973 } 1974 1975 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1976 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1977 1978 if (amdgpu_ras_is_poison_mode_supported(adev)) 1979 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1980 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1981 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1982 ras_cmd->ras_in_message.init_flags.xcc_mask = 1983 adev->gfx.xcc_mask; 1984 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1985 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 1986 ras_cmd->ras_in_message.init_flags.nps_mode = 1987 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1988 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 1989 1990 ret = psp_ta_load(psp, &psp->ras_context.context); 1991 1992 if (!ret && !ras_cmd->ras_status) { 1993 psp->ras_context.context.initialized = true; 1994 mutex_init(&psp->ras_context.mutex); 1995 } else { 1996 if (ras_cmd->ras_status) 1997 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1998 1999 /* fail to load RAS TA */ 2000 psp->ras_context.context.initialized = false; 2001 } 2002 2003 return ret; 2004 } 2005 2006 int psp_ras_trigger_error(struct psp_context *psp, 2007 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2008 { 2009 struct amdgpu_device *adev = psp->adev; 2010 int ret; 2011 uint32_t dev_mask; 2012 uint32_t ras_status = 0; 2013 2014 if (!psp->ras_context.context.initialized || !info) 2015 return -EINVAL; 2016 2017 switch (info->block_id) { 2018 case TA_RAS_BLOCK__GFX: 2019 dev_mask = GET_MASK(GC, instance_mask); 2020 break; 2021 case TA_RAS_BLOCK__SDMA: 2022 dev_mask = GET_MASK(SDMA0, instance_mask); 2023 break; 2024 case TA_RAS_BLOCK__VCN: 2025 case TA_RAS_BLOCK__JPEG: 2026 dev_mask = GET_MASK(VCN, instance_mask); 2027 break; 2028 default: 2029 dev_mask = instance_mask; 2030 break; 2031 } 2032 2033 /* reuse sub_block_index for backward compatibility */ 2034 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2035 dev_mask &= AMDGPU_RAS_INST_MASK; 2036 info->sub_block_index |= dev_mask; 2037 2038 ret = psp_ras_send_cmd(psp, 2039 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2040 if (ret) 2041 return -EINVAL; 2042 2043 /* If err_event_athub occurs error inject was successful, however 2044 * return status from TA is no long reliable 2045 */ 2046 if (amdgpu_ras_intr_triggered()) 2047 return 0; 2048 2049 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2050 return -EACCES; 2051 else if (ras_status) 2052 return -EINVAL; 2053 2054 return 0; 2055 } 2056 2057 int psp_ras_query_address(struct psp_context *psp, 2058 struct ta_ras_query_address_input *addr_in, 2059 struct ta_ras_query_address_output *addr_out) 2060 { 2061 int ret; 2062 2063 if (!psp->ras_context.context.initialized || 2064 !addr_in || !addr_out) 2065 return -EINVAL; 2066 2067 ret = psp_ras_send_cmd(psp, 2068 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2069 2070 return ret; 2071 } 2072 // ras end 2073 2074 // HDCP start 2075 static int psp_hdcp_initialize(struct psp_context *psp) 2076 { 2077 int ret; 2078 2079 /* 2080 * TODO: bypass the initialize in sriov for now 2081 */ 2082 if (amdgpu_sriov_vf(psp->adev)) 2083 return 0; 2084 2085 /* bypass hdcp initialization if dmu is harvested */ 2086 if (!amdgpu_device_has_display_hardware(psp->adev)) 2087 return 0; 2088 2089 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2090 !psp->hdcp_context.context.bin_desc.start_addr) { 2091 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2092 return 0; 2093 } 2094 2095 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2096 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2097 2098 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2099 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2100 if (ret) 2101 return ret; 2102 } 2103 2104 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2105 if (!ret) { 2106 psp->hdcp_context.context.initialized = true; 2107 mutex_init(&psp->hdcp_context.mutex); 2108 } 2109 2110 return ret; 2111 } 2112 2113 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2114 { 2115 /* 2116 * TODO: bypass the loading in sriov for now 2117 */ 2118 if (amdgpu_sriov_vf(psp->adev)) 2119 return 0; 2120 2121 if (!psp->hdcp_context.context.initialized) 2122 return 0; 2123 2124 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2125 } 2126 2127 static int psp_hdcp_terminate(struct psp_context *psp) 2128 { 2129 int ret; 2130 2131 /* 2132 * TODO: bypass the terminate in sriov for now 2133 */ 2134 if (amdgpu_sriov_vf(psp->adev)) 2135 return 0; 2136 2137 if (!psp->hdcp_context.context.initialized) 2138 return 0; 2139 2140 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2141 2142 psp->hdcp_context.context.initialized = false; 2143 2144 return ret; 2145 } 2146 // HDCP end 2147 2148 // DTM start 2149 static int psp_dtm_initialize(struct psp_context *psp) 2150 { 2151 int ret; 2152 2153 /* 2154 * TODO: bypass the initialize in sriov for now 2155 */ 2156 if (amdgpu_sriov_vf(psp->adev)) 2157 return 0; 2158 2159 /* bypass dtm initialization if dmu is harvested */ 2160 if (!amdgpu_device_has_display_hardware(psp->adev)) 2161 return 0; 2162 2163 if (!psp->dtm_context.context.bin_desc.size_bytes || 2164 !psp->dtm_context.context.bin_desc.start_addr) { 2165 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2166 return 0; 2167 } 2168 2169 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2170 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2171 2172 if (!psp->dtm_context.context.mem_context.shared_buf) { 2173 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2174 if (ret) 2175 return ret; 2176 } 2177 2178 ret = psp_ta_load(psp, &psp->dtm_context.context); 2179 if (!ret) { 2180 psp->dtm_context.context.initialized = true; 2181 mutex_init(&psp->dtm_context.mutex); 2182 } 2183 2184 return ret; 2185 } 2186 2187 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2188 { 2189 /* 2190 * TODO: bypass the loading in sriov for now 2191 */ 2192 if (amdgpu_sriov_vf(psp->adev)) 2193 return 0; 2194 2195 if (!psp->dtm_context.context.initialized) 2196 return 0; 2197 2198 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2199 } 2200 2201 static int psp_dtm_terminate(struct psp_context *psp) 2202 { 2203 int ret; 2204 2205 /* 2206 * TODO: bypass the terminate in sriov for now 2207 */ 2208 if (amdgpu_sriov_vf(psp->adev)) 2209 return 0; 2210 2211 if (!psp->dtm_context.context.initialized) 2212 return 0; 2213 2214 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2215 2216 psp->dtm_context.context.initialized = false; 2217 2218 return ret; 2219 } 2220 // DTM end 2221 2222 // RAP start 2223 static int psp_rap_initialize(struct psp_context *psp) 2224 { 2225 int ret; 2226 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2227 2228 /* 2229 * TODO: bypass the initialize in sriov for now 2230 */ 2231 if (amdgpu_sriov_vf(psp->adev)) 2232 return 0; 2233 2234 if (!psp->rap_context.context.bin_desc.size_bytes || 2235 !psp->rap_context.context.bin_desc.start_addr) { 2236 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2237 return 0; 2238 } 2239 2240 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2241 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2242 2243 if (!psp->rap_context.context.mem_context.shared_buf) { 2244 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2245 if (ret) 2246 return ret; 2247 } 2248 2249 ret = psp_ta_load(psp, &psp->rap_context.context); 2250 if (!ret) { 2251 psp->rap_context.context.initialized = true; 2252 mutex_init(&psp->rap_context.mutex); 2253 } else 2254 return ret; 2255 2256 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2257 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2258 psp_rap_terminate(psp); 2259 /* free rap shared memory */ 2260 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2261 2262 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2263 ret, status); 2264 2265 return ret; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static int psp_rap_terminate(struct psp_context *psp) 2272 { 2273 int ret; 2274 2275 if (!psp->rap_context.context.initialized) 2276 return 0; 2277 2278 ret = psp_ta_unload(psp, &psp->rap_context.context); 2279 2280 psp->rap_context.context.initialized = false; 2281 2282 return ret; 2283 } 2284 2285 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2286 { 2287 struct ta_rap_shared_memory *rap_cmd; 2288 int ret = 0; 2289 2290 if (!psp->rap_context.context.initialized) 2291 return 0; 2292 2293 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2294 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2295 return -EINVAL; 2296 2297 mutex_lock(&psp->rap_context.mutex); 2298 2299 rap_cmd = (struct ta_rap_shared_memory *) 2300 psp->rap_context.context.mem_context.shared_buf; 2301 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2302 2303 rap_cmd->cmd_id = ta_cmd_id; 2304 rap_cmd->validation_method_id = METHOD_A; 2305 2306 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2307 if (ret) 2308 goto out_unlock; 2309 2310 if (status) 2311 *status = rap_cmd->rap_status; 2312 2313 out_unlock: 2314 mutex_unlock(&psp->rap_context.mutex); 2315 2316 return ret; 2317 } 2318 // RAP end 2319 2320 /* securedisplay start */ 2321 static int psp_securedisplay_initialize(struct psp_context *psp) 2322 { 2323 int ret; 2324 struct ta_securedisplay_cmd *securedisplay_cmd; 2325 2326 /* 2327 * TODO: bypass the initialize in sriov for now 2328 */ 2329 if (amdgpu_sriov_vf(psp->adev)) 2330 return 0; 2331 2332 /* bypass securedisplay initialization if dmu is harvested */ 2333 if (!amdgpu_device_has_display_hardware(psp->adev)) 2334 return 0; 2335 2336 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2337 !psp->securedisplay_context.context.bin_desc.start_addr) { 2338 dev_info(psp->adev->dev, 2339 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2340 return 0; 2341 } 2342 2343 psp->securedisplay_context.context.mem_context.shared_mem_size = 2344 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2345 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2346 2347 if (!psp->securedisplay_context.context.initialized) { 2348 ret = psp_ta_init_shared_buf(psp, 2349 &psp->securedisplay_context.context.mem_context); 2350 if (ret) 2351 return ret; 2352 } 2353 2354 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2355 if (!ret && !psp->securedisplay_context.context.resp_status) { 2356 psp->securedisplay_context.context.initialized = true; 2357 mutex_init(&psp->securedisplay_context.mutex); 2358 } else { 2359 /* don't try again */ 2360 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2361 return ret; 2362 } 2363 2364 mutex_lock(&psp->securedisplay_context.mutex); 2365 2366 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2367 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2368 2369 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2370 2371 mutex_unlock(&psp->securedisplay_context.mutex); 2372 2373 if (ret) { 2374 psp_securedisplay_terminate(psp); 2375 /* free securedisplay shared memory */ 2376 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2377 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2378 return -EINVAL; 2379 } 2380 2381 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2382 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2383 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2384 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2385 /* don't try again */ 2386 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2387 } 2388 2389 return 0; 2390 } 2391 2392 static int psp_securedisplay_terminate(struct psp_context *psp) 2393 { 2394 int ret; 2395 2396 /* 2397 * TODO:bypass the terminate in sriov for now 2398 */ 2399 if (amdgpu_sriov_vf(psp->adev)) 2400 return 0; 2401 2402 if (!psp->securedisplay_context.context.initialized) 2403 return 0; 2404 2405 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2406 2407 psp->securedisplay_context.context.initialized = false; 2408 2409 return ret; 2410 } 2411 2412 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2413 { 2414 int ret; 2415 2416 if (!psp->securedisplay_context.context.initialized) 2417 return -EINVAL; 2418 2419 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2420 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2421 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2422 return -EINVAL; 2423 2424 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2425 2426 return ret; 2427 } 2428 /* SECUREDISPLAY end */ 2429 2430 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2431 { 2432 struct psp_context *psp = &adev->psp; 2433 int ret = 0; 2434 2435 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2436 ret = psp->funcs->wait_for_bootloader(psp); 2437 2438 return ret; 2439 } 2440 2441 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2442 { 2443 if (psp->funcs && 2444 psp->funcs->get_ras_capability) { 2445 return psp->funcs->get_ras_capability(psp); 2446 } else { 2447 return false; 2448 } 2449 } 2450 2451 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2452 { 2453 struct psp_context *psp = &adev->psp; 2454 2455 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2456 return false; 2457 2458 if (psp->funcs && psp->funcs->is_reload_needed) 2459 return psp->funcs->is_reload_needed(psp); 2460 2461 return false; 2462 } 2463 2464 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2465 { 2466 struct psp_context *psp = &adev->psp; 2467 2468 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2469 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2470 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2471 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2472 } 2473 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2474 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2475 } 2476 2477 static int psp_hw_start(struct psp_context *psp) 2478 { 2479 struct amdgpu_device *adev = psp->adev; 2480 int ret; 2481 2482 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2483 psp_update_gpu_addresses(adev); 2484 2485 if (!amdgpu_sriov_vf(adev)) { 2486 if ((is_psp_fw_valid(psp->kdb)) && 2487 (psp->funcs->bootloader_load_kdb != NULL)) { 2488 ret = psp_bootloader_load_kdb(psp); 2489 if (ret) { 2490 dev_err(adev->dev, "PSP load kdb failed!\n"); 2491 return ret; 2492 } 2493 } 2494 2495 if ((is_psp_fw_valid(psp->spl)) && 2496 (psp->funcs->bootloader_load_spl != NULL)) { 2497 ret = psp_bootloader_load_spl(psp); 2498 if (ret) { 2499 dev_err(adev->dev, "PSP load spl failed!\n"); 2500 return ret; 2501 } 2502 } 2503 2504 if ((is_psp_fw_valid(psp->sys)) && 2505 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2506 ret = psp_bootloader_load_sysdrv(psp); 2507 if (ret) { 2508 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2509 return ret; 2510 } 2511 } 2512 2513 if ((is_psp_fw_valid(psp->soc_drv)) && 2514 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2515 ret = psp_bootloader_load_soc_drv(psp); 2516 if (ret) { 2517 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2518 return ret; 2519 } 2520 } 2521 2522 if ((is_psp_fw_valid(psp->intf_drv)) && 2523 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2524 ret = psp_bootloader_load_intf_drv(psp); 2525 if (ret) { 2526 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2527 return ret; 2528 } 2529 } 2530 2531 if ((is_psp_fw_valid(psp->dbg_drv)) && 2532 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2533 ret = psp_bootloader_load_dbg_drv(psp); 2534 if (ret) { 2535 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2536 return ret; 2537 } 2538 } 2539 2540 if ((is_psp_fw_valid(psp->ras_drv)) && 2541 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2542 ret = psp_bootloader_load_ras_drv(psp); 2543 if (ret) { 2544 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2545 return ret; 2546 } 2547 } 2548 2549 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2550 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2551 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2552 if (ret) { 2553 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2554 return ret; 2555 } 2556 } 2557 2558 if ((is_psp_fw_valid(psp->spdm_drv)) && 2559 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2560 ret = psp_bootloader_load_spdm_drv(psp); 2561 if (ret) { 2562 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2563 return ret; 2564 } 2565 } 2566 2567 if ((is_psp_fw_valid(psp->sos)) && 2568 (psp->funcs->bootloader_load_sos != NULL)) { 2569 ret = psp_bootloader_load_sos(psp); 2570 if (ret) { 2571 dev_err(adev->dev, "PSP load sos failed!\n"); 2572 return ret; 2573 } 2574 } 2575 } 2576 2577 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2578 if (ret) { 2579 dev_err(adev->dev, "PSP create ring failed!\n"); 2580 return ret; 2581 } 2582 2583 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2584 ret = psp_update_fw_reservation(psp); 2585 if (ret) { 2586 dev_err(adev->dev, "update fw reservation failed!\n"); 2587 return ret; 2588 } 2589 } 2590 2591 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2592 goto skip_pin_bo; 2593 2594 if (!psp->boot_time_tmr || psp->autoload_supported) { 2595 ret = psp_tmr_init(psp); 2596 if (ret) { 2597 dev_err(adev->dev, "PSP tmr init failed!\n"); 2598 return ret; 2599 } 2600 } 2601 2602 skip_pin_bo: 2603 /* 2604 * For ASICs with DF Cstate management centralized 2605 * to PMFW, TMR setup should be performed after PMFW 2606 * loaded and before other non-psp firmware loaded. 2607 */ 2608 if (psp->pmfw_centralized_cstate_management) { 2609 ret = psp_load_smu_fw(psp); 2610 if (ret) 2611 return ret; 2612 } 2613 2614 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2615 ret = psp_tmr_load(psp); 2616 if (ret) { 2617 dev_err(adev->dev, "PSP load tmr failed!\n"); 2618 return ret; 2619 } 2620 } 2621 2622 return 0; 2623 } 2624 2625 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2626 enum psp_gfx_fw_type *type) 2627 { 2628 switch (ucode->ucode_id) { 2629 case AMDGPU_UCODE_ID_CAP: 2630 *type = GFX_FW_TYPE_CAP; 2631 break; 2632 case AMDGPU_UCODE_ID_SDMA0: 2633 *type = GFX_FW_TYPE_SDMA0; 2634 break; 2635 case AMDGPU_UCODE_ID_SDMA1: 2636 *type = GFX_FW_TYPE_SDMA1; 2637 break; 2638 case AMDGPU_UCODE_ID_SDMA2: 2639 *type = GFX_FW_TYPE_SDMA2; 2640 break; 2641 case AMDGPU_UCODE_ID_SDMA3: 2642 *type = GFX_FW_TYPE_SDMA3; 2643 break; 2644 case AMDGPU_UCODE_ID_SDMA4: 2645 *type = GFX_FW_TYPE_SDMA4; 2646 break; 2647 case AMDGPU_UCODE_ID_SDMA5: 2648 *type = GFX_FW_TYPE_SDMA5; 2649 break; 2650 case AMDGPU_UCODE_ID_SDMA6: 2651 *type = GFX_FW_TYPE_SDMA6; 2652 break; 2653 case AMDGPU_UCODE_ID_SDMA7: 2654 *type = GFX_FW_TYPE_SDMA7; 2655 break; 2656 case AMDGPU_UCODE_ID_CP_MES: 2657 *type = GFX_FW_TYPE_CP_MES; 2658 break; 2659 case AMDGPU_UCODE_ID_CP_MES_DATA: 2660 *type = GFX_FW_TYPE_MES_STACK; 2661 break; 2662 case AMDGPU_UCODE_ID_CP_MES1: 2663 *type = GFX_FW_TYPE_CP_MES_KIQ; 2664 break; 2665 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2666 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2667 break; 2668 case AMDGPU_UCODE_ID_CP_CE: 2669 *type = GFX_FW_TYPE_CP_CE; 2670 break; 2671 case AMDGPU_UCODE_ID_CP_PFP: 2672 *type = GFX_FW_TYPE_CP_PFP; 2673 break; 2674 case AMDGPU_UCODE_ID_CP_ME: 2675 *type = GFX_FW_TYPE_CP_ME; 2676 break; 2677 case AMDGPU_UCODE_ID_CP_MEC1: 2678 *type = GFX_FW_TYPE_CP_MEC; 2679 break; 2680 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2681 *type = GFX_FW_TYPE_CP_MEC_ME1; 2682 break; 2683 case AMDGPU_UCODE_ID_CP_MEC2: 2684 *type = GFX_FW_TYPE_CP_MEC; 2685 break; 2686 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2687 *type = GFX_FW_TYPE_CP_MEC_ME2; 2688 break; 2689 case AMDGPU_UCODE_ID_RLC_P: 2690 *type = GFX_FW_TYPE_RLC_P; 2691 break; 2692 case AMDGPU_UCODE_ID_RLC_V: 2693 *type = GFX_FW_TYPE_RLC_V; 2694 break; 2695 case AMDGPU_UCODE_ID_RLC_G: 2696 *type = GFX_FW_TYPE_RLC_G; 2697 break; 2698 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2699 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2700 break; 2701 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2702 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2703 break; 2704 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2705 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2706 break; 2707 case AMDGPU_UCODE_ID_RLC_IRAM: 2708 *type = GFX_FW_TYPE_RLC_IRAM; 2709 break; 2710 case AMDGPU_UCODE_ID_RLC_DRAM: 2711 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2712 break; 2713 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2714 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2715 break; 2716 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2717 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2718 break; 2719 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2720 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2721 break; 2722 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2723 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2724 break; 2725 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2726 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2727 break; 2728 case AMDGPU_UCODE_ID_SMC: 2729 *type = GFX_FW_TYPE_SMU; 2730 break; 2731 case AMDGPU_UCODE_ID_PPTABLE: 2732 *type = GFX_FW_TYPE_PPTABLE; 2733 break; 2734 case AMDGPU_UCODE_ID_UVD: 2735 *type = GFX_FW_TYPE_UVD; 2736 break; 2737 case AMDGPU_UCODE_ID_UVD1: 2738 *type = GFX_FW_TYPE_UVD1; 2739 break; 2740 case AMDGPU_UCODE_ID_VCE: 2741 *type = GFX_FW_TYPE_VCE; 2742 break; 2743 case AMDGPU_UCODE_ID_VCN: 2744 *type = GFX_FW_TYPE_VCN; 2745 break; 2746 case AMDGPU_UCODE_ID_VCN1: 2747 *type = GFX_FW_TYPE_VCN1; 2748 break; 2749 case AMDGPU_UCODE_ID_DMCU_ERAM: 2750 *type = GFX_FW_TYPE_DMCU_ERAM; 2751 break; 2752 case AMDGPU_UCODE_ID_DMCU_INTV: 2753 *type = GFX_FW_TYPE_DMCU_ISR; 2754 break; 2755 case AMDGPU_UCODE_ID_VCN0_RAM: 2756 *type = GFX_FW_TYPE_VCN0_RAM; 2757 break; 2758 case AMDGPU_UCODE_ID_VCN1_RAM: 2759 *type = GFX_FW_TYPE_VCN1_RAM; 2760 break; 2761 case AMDGPU_UCODE_ID_DMCUB: 2762 *type = GFX_FW_TYPE_DMUB; 2763 break; 2764 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2765 case AMDGPU_UCODE_ID_SDMA_RS64: 2766 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2767 break; 2768 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2769 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2770 break; 2771 case AMDGPU_UCODE_ID_IMU_I: 2772 *type = GFX_FW_TYPE_IMU_I; 2773 break; 2774 case AMDGPU_UCODE_ID_IMU_D: 2775 *type = GFX_FW_TYPE_IMU_D; 2776 break; 2777 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2778 *type = GFX_FW_TYPE_RS64_PFP; 2779 break; 2780 case AMDGPU_UCODE_ID_CP_RS64_ME: 2781 *type = GFX_FW_TYPE_RS64_ME; 2782 break; 2783 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2784 *type = GFX_FW_TYPE_RS64_MEC; 2785 break; 2786 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2787 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2788 break; 2789 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2790 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2791 break; 2792 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2793 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2794 break; 2795 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2796 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2797 break; 2798 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2799 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2800 break; 2801 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2802 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2803 break; 2804 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2805 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2806 break; 2807 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2808 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2809 break; 2810 case AMDGPU_UCODE_ID_VPE_CTX: 2811 *type = GFX_FW_TYPE_VPEC_FW1; 2812 break; 2813 case AMDGPU_UCODE_ID_VPE_CTL: 2814 *type = GFX_FW_TYPE_VPEC_FW2; 2815 break; 2816 case AMDGPU_UCODE_ID_VPE: 2817 *type = GFX_FW_TYPE_VPE; 2818 break; 2819 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2820 *type = GFX_FW_TYPE_UMSCH_UCODE; 2821 break; 2822 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2823 *type = GFX_FW_TYPE_UMSCH_DATA; 2824 break; 2825 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2826 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2827 break; 2828 case AMDGPU_UCODE_ID_P2S_TABLE: 2829 *type = GFX_FW_TYPE_P2S_TABLE; 2830 break; 2831 case AMDGPU_UCODE_ID_JPEG_RAM: 2832 *type = GFX_FW_TYPE_JPEG_RAM; 2833 break; 2834 case AMDGPU_UCODE_ID_ISP: 2835 *type = GFX_FW_TYPE_ISP; 2836 break; 2837 case AMDGPU_UCODE_ID_MAXIMUM: 2838 default: 2839 return -EINVAL; 2840 } 2841 2842 return 0; 2843 } 2844 2845 static void psp_print_fw_hdr(struct psp_context *psp, 2846 struct amdgpu_firmware_info *ucode) 2847 { 2848 struct amdgpu_device *adev = psp->adev; 2849 struct common_firmware_header *hdr; 2850 2851 switch (ucode->ucode_id) { 2852 case AMDGPU_UCODE_ID_SDMA0: 2853 case AMDGPU_UCODE_ID_SDMA1: 2854 case AMDGPU_UCODE_ID_SDMA2: 2855 case AMDGPU_UCODE_ID_SDMA3: 2856 case AMDGPU_UCODE_ID_SDMA4: 2857 case AMDGPU_UCODE_ID_SDMA5: 2858 case AMDGPU_UCODE_ID_SDMA6: 2859 case AMDGPU_UCODE_ID_SDMA7: 2860 hdr = (struct common_firmware_header *) 2861 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2862 amdgpu_ucode_print_sdma_hdr(hdr); 2863 break; 2864 case AMDGPU_UCODE_ID_CP_CE: 2865 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2866 amdgpu_ucode_print_gfx_hdr(hdr); 2867 break; 2868 case AMDGPU_UCODE_ID_CP_PFP: 2869 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2870 amdgpu_ucode_print_gfx_hdr(hdr); 2871 break; 2872 case AMDGPU_UCODE_ID_CP_ME: 2873 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2874 amdgpu_ucode_print_gfx_hdr(hdr); 2875 break; 2876 case AMDGPU_UCODE_ID_CP_MEC1: 2877 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2878 amdgpu_ucode_print_gfx_hdr(hdr); 2879 break; 2880 case AMDGPU_UCODE_ID_RLC_G: 2881 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2882 amdgpu_ucode_print_rlc_hdr(hdr); 2883 break; 2884 case AMDGPU_UCODE_ID_SMC: 2885 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2886 amdgpu_ucode_print_smc_hdr(hdr); 2887 break; 2888 default: 2889 break; 2890 } 2891 } 2892 2893 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2894 struct amdgpu_firmware_info *ucode, 2895 struct psp_gfx_cmd_resp *cmd) 2896 { 2897 int ret; 2898 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2899 2900 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2901 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2902 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2903 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2904 2905 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2906 if (ret) 2907 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2908 2909 return ret; 2910 } 2911 2912 int psp_execute_ip_fw_load(struct psp_context *psp, 2913 struct amdgpu_firmware_info *ucode) 2914 { 2915 int ret = 0; 2916 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2917 2918 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2919 if (!ret) { 2920 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2921 psp->fence_buf_mc_addr); 2922 } 2923 2924 release_psp_cmd_buf(psp); 2925 2926 return ret; 2927 } 2928 2929 static int psp_load_p2s_table(struct psp_context *psp) 2930 { 2931 int ret; 2932 struct amdgpu_device *adev = psp->adev; 2933 struct amdgpu_firmware_info *ucode = 2934 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2935 2936 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2937 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2938 return 0; 2939 2940 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2941 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2942 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2943 0x0036003C; 2944 if (psp->sos.fw_version < supp_vers) 2945 return 0; 2946 } 2947 2948 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2949 return 0; 2950 2951 ret = psp_execute_ip_fw_load(psp, ucode); 2952 2953 return ret; 2954 } 2955 2956 static int psp_load_smu_fw(struct psp_context *psp) 2957 { 2958 int ret; 2959 struct amdgpu_device *adev = psp->adev; 2960 struct amdgpu_firmware_info *ucode = 2961 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2962 struct amdgpu_ras *ras = psp->ras_context.ras; 2963 2964 /* 2965 * Skip SMU FW reloading in case of using BACO for runpm only, 2966 * as SMU is always alive. 2967 */ 2968 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2969 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2970 return 0; 2971 2972 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2973 return 0; 2974 2975 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2976 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2977 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2978 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2979 if (ret) 2980 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2981 } 2982 2983 ret = psp_execute_ip_fw_load(psp, ucode); 2984 2985 if (ret) 2986 dev_err(adev->dev, "PSP load smu failed!\n"); 2987 2988 return ret; 2989 } 2990 2991 static bool fw_load_skip_check(struct psp_context *psp, 2992 struct amdgpu_firmware_info *ucode) 2993 { 2994 if (!ucode->fw || !ucode->ucode_size) 2995 return true; 2996 2997 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2998 return true; 2999 3000 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3001 (psp_smu_reload_quirk(psp) || 3002 psp->autoload_supported || 3003 psp->pmfw_centralized_cstate_management)) 3004 return true; 3005 3006 if (amdgpu_sriov_vf(psp->adev) && 3007 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3008 return true; 3009 3010 if (psp->autoload_supported && 3011 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3012 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3013 /* skip mec JT when autoload is enabled */ 3014 return true; 3015 3016 return false; 3017 } 3018 3019 int psp_load_fw_list(struct psp_context *psp, 3020 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3021 { 3022 int ret = 0, i; 3023 struct amdgpu_firmware_info *ucode; 3024 3025 for (i = 0; i < ucode_count; ++i) { 3026 ucode = ucode_list[i]; 3027 psp_print_fw_hdr(psp, ucode); 3028 ret = psp_execute_ip_fw_load(psp, ucode); 3029 if (ret) 3030 return ret; 3031 } 3032 return ret; 3033 } 3034 3035 static int psp_load_non_psp_fw(struct psp_context *psp) 3036 { 3037 int i, ret; 3038 struct amdgpu_firmware_info *ucode; 3039 struct amdgpu_device *adev = psp->adev; 3040 3041 if (psp->autoload_supported && 3042 !psp->pmfw_centralized_cstate_management) { 3043 ret = psp_load_smu_fw(psp); 3044 if (ret) 3045 return ret; 3046 } 3047 3048 /* Load P2S table first if it's available */ 3049 psp_load_p2s_table(psp); 3050 3051 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3052 ucode = &adev->firmware.ucode[i]; 3053 3054 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3055 !fw_load_skip_check(psp, ucode)) { 3056 ret = psp_load_smu_fw(psp); 3057 if (ret) 3058 return ret; 3059 continue; 3060 } 3061 3062 if (fw_load_skip_check(psp, ucode)) 3063 continue; 3064 3065 if (psp->autoload_supported && 3066 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3067 IP_VERSION(11, 0, 7) || 3068 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3069 IP_VERSION(11, 0, 11) || 3070 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3071 IP_VERSION(11, 0, 12)) && 3072 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3073 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3074 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3075 /* PSP only receive one SDMA fw for sienna_cichlid, 3076 * as all four sdma fw are same 3077 */ 3078 continue; 3079 3080 psp_print_fw_hdr(psp, ucode); 3081 3082 ret = psp_execute_ip_fw_load(psp, ucode); 3083 if (ret) 3084 return ret; 3085 3086 /* Start rlc autoload after psp received all the gfx firmware */ 3087 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3088 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3089 ret = psp_rlc_autoload_start(psp); 3090 if (ret) { 3091 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3092 return ret; 3093 } 3094 } 3095 } 3096 3097 return 0; 3098 } 3099 3100 static int psp_load_fw(struct amdgpu_device *adev) 3101 { 3102 int ret; 3103 struct psp_context *psp = &adev->psp; 3104 3105 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3106 /* should not destroy ring, only stop */ 3107 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3108 } else { 3109 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3110 3111 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3112 if (ret) { 3113 dev_err(adev->dev, "PSP ring init failed!\n"); 3114 goto failed; 3115 } 3116 } 3117 3118 ret = psp_hw_start(psp); 3119 if (ret) 3120 goto failed; 3121 3122 ret = psp_load_non_psp_fw(psp); 3123 if (ret) 3124 goto failed1; 3125 3126 ret = psp_asd_initialize(psp); 3127 if (ret) { 3128 dev_err(adev->dev, "PSP load asd failed!\n"); 3129 goto failed1; 3130 } 3131 3132 ret = psp_rl_load(adev); 3133 if (ret) { 3134 dev_err(adev->dev, "PSP load RL failed!\n"); 3135 goto failed1; 3136 } 3137 3138 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3139 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3140 ret = psp_xgmi_initialize(psp, false, true); 3141 /* Warning the XGMI seesion initialize failure 3142 * Instead of stop driver initialization 3143 */ 3144 if (ret) 3145 dev_err(psp->adev->dev, 3146 "XGMI: Failed to initialize XGMI session\n"); 3147 } 3148 } 3149 3150 if (psp->ta_fw) { 3151 ret = psp_ras_initialize(psp); 3152 if (ret) 3153 dev_err(psp->adev->dev, 3154 "RAS: Failed to initialize RAS\n"); 3155 3156 ret = psp_hdcp_initialize(psp); 3157 if (ret) 3158 dev_err(psp->adev->dev, 3159 "HDCP: Failed to initialize HDCP\n"); 3160 3161 ret = psp_dtm_initialize(psp); 3162 if (ret) 3163 dev_err(psp->adev->dev, 3164 "DTM: Failed to initialize DTM\n"); 3165 3166 ret = psp_rap_initialize(psp); 3167 if (ret) 3168 dev_err(psp->adev->dev, 3169 "RAP: Failed to initialize RAP\n"); 3170 3171 ret = psp_securedisplay_initialize(psp); 3172 if (ret) 3173 dev_err(psp->adev->dev, 3174 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3175 } 3176 3177 return 0; 3178 3179 failed1: 3180 psp_free_shared_bufs(psp); 3181 failed: 3182 /* 3183 * all cleanup jobs (xgmi terminate, ras terminate, 3184 * ring destroy, cmd/fence/fw buffers destory, 3185 * psp->cmd destory) are delayed to psp_hw_fini 3186 */ 3187 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3188 return ret; 3189 } 3190 3191 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3192 { 3193 int ret; 3194 struct amdgpu_device *adev = ip_block->adev; 3195 3196 mutex_lock(&adev->firmware.mutex); 3197 3198 ret = amdgpu_ucode_init_bo(adev); 3199 if (ret) 3200 goto failed; 3201 3202 ret = psp_load_fw(adev); 3203 if (ret) { 3204 dev_err(adev->dev, "PSP firmware loading failed\n"); 3205 goto failed; 3206 } 3207 3208 mutex_unlock(&adev->firmware.mutex); 3209 return 0; 3210 3211 failed: 3212 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3213 mutex_unlock(&adev->firmware.mutex); 3214 return -EINVAL; 3215 } 3216 3217 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3218 { 3219 struct amdgpu_device *adev = ip_block->adev; 3220 struct psp_context *psp = &adev->psp; 3221 3222 if (psp->ta_fw) { 3223 psp_ras_terminate(psp); 3224 psp_securedisplay_terminate(psp); 3225 psp_rap_terminate(psp); 3226 psp_dtm_terminate(psp); 3227 psp_hdcp_terminate(psp); 3228 3229 if (adev->gmc.xgmi.num_physical_nodes > 1) 3230 psp_xgmi_terminate(psp); 3231 } 3232 3233 psp_asd_terminate(psp); 3234 psp_tmr_terminate(psp); 3235 3236 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3237 3238 return 0; 3239 } 3240 3241 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3242 { 3243 int ret = 0; 3244 struct amdgpu_device *adev = ip_block->adev; 3245 struct psp_context *psp = &adev->psp; 3246 3247 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3248 psp->xgmi_context.context.initialized) { 3249 ret = psp_xgmi_terminate(psp); 3250 if (ret) { 3251 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3252 goto out; 3253 } 3254 } 3255 3256 if (psp->ta_fw) { 3257 ret = psp_ras_terminate(psp); 3258 if (ret) { 3259 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3260 goto out; 3261 } 3262 ret = psp_hdcp_terminate(psp); 3263 if (ret) { 3264 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3265 goto out; 3266 } 3267 ret = psp_dtm_terminate(psp); 3268 if (ret) { 3269 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3270 goto out; 3271 } 3272 ret = psp_rap_terminate(psp); 3273 if (ret) { 3274 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3275 goto out; 3276 } 3277 ret = psp_securedisplay_terminate(psp); 3278 if (ret) { 3279 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3280 goto out; 3281 } 3282 } 3283 3284 ret = psp_asd_terminate(psp); 3285 if (ret) { 3286 dev_err(adev->dev, "Failed to terminate asd\n"); 3287 goto out; 3288 } 3289 3290 ret = psp_tmr_terminate(psp); 3291 if (ret) { 3292 dev_err(adev->dev, "Failed to terminate tmr\n"); 3293 goto out; 3294 } 3295 3296 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3297 if (ret) 3298 dev_err(adev->dev, "PSP ring stop failed\n"); 3299 3300 out: 3301 return ret; 3302 } 3303 3304 static int psp_resume(struct amdgpu_ip_block *ip_block) 3305 { 3306 int ret; 3307 struct amdgpu_device *adev = ip_block->adev; 3308 struct psp_context *psp = &adev->psp; 3309 3310 dev_info(adev->dev, "PSP is resuming...\n"); 3311 3312 if (psp->mem_train_ctx.enable_mem_training) { 3313 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3314 if (ret) { 3315 dev_err(adev->dev, "Failed to process memory training!\n"); 3316 return ret; 3317 } 3318 } 3319 3320 mutex_lock(&adev->firmware.mutex); 3321 3322 ret = amdgpu_ucode_init_bo(adev); 3323 if (ret) 3324 goto failed; 3325 3326 ret = psp_hw_start(psp); 3327 if (ret) 3328 goto failed; 3329 3330 ret = psp_load_non_psp_fw(psp); 3331 if (ret) 3332 goto failed; 3333 3334 ret = psp_asd_initialize(psp); 3335 if (ret) { 3336 dev_err(adev->dev, "PSP load asd failed!\n"); 3337 goto failed; 3338 } 3339 3340 ret = psp_rl_load(adev); 3341 if (ret) { 3342 dev_err(adev->dev, "PSP load RL failed!\n"); 3343 goto failed; 3344 } 3345 3346 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3347 ret = psp_xgmi_initialize(psp, false, true); 3348 /* Warning the XGMI seesion initialize failure 3349 * Instead of stop driver initialization 3350 */ 3351 if (ret) 3352 dev_err(psp->adev->dev, 3353 "XGMI: Failed to initialize XGMI session\n"); 3354 } 3355 3356 if (psp->ta_fw) { 3357 ret = psp_ras_initialize(psp); 3358 if (ret) 3359 dev_err(psp->adev->dev, 3360 "RAS: Failed to initialize RAS\n"); 3361 3362 ret = psp_hdcp_initialize(psp); 3363 if (ret) 3364 dev_err(psp->adev->dev, 3365 "HDCP: Failed to initialize HDCP\n"); 3366 3367 ret = psp_dtm_initialize(psp); 3368 if (ret) 3369 dev_err(psp->adev->dev, 3370 "DTM: Failed to initialize DTM\n"); 3371 3372 ret = psp_rap_initialize(psp); 3373 if (ret) 3374 dev_err(psp->adev->dev, 3375 "RAP: Failed to initialize RAP\n"); 3376 3377 ret = psp_securedisplay_initialize(psp); 3378 if (ret) 3379 dev_err(psp->adev->dev, 3380 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3381 } 3382 3383 mutex_unlock(&adev->firmware.mutex); 3384 3385 return 0; 3386 3387 failed: 3388 dev_err(adev->dev, "PSP resume failed\n"); 3389 mutex_unlock(&adev->firmware.mutex); 3390 return ret; 3391 } 3392 3393 int psp_gpu_reset(struct amdgpu_device *adev) 3394 { 3395 int ret; 3396 3397 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3398 return 0; 3399 3400 mutex_lock(&adev->psp.mutex); 3401 ret = psp_mode1_reset(&adev->psp); 3402 mutex_unlock(&adev->psp.mutex); 3403 3404 return ret; 3405 } 3406 3407 int psp_rlc_autoload_start(struct psp_context *psp) 3408 { 3409 int ret; 3410 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3411 3412 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3413 3414 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3415 psp->fence_buf_mc_addr); 3416 3417 release_psp_cmd_buf(psp); 3418 3419 return ret; 3420 } 3421 3422 int psp_ring_cmd_submit(struct psp_context *psp, 3423 uint64_t cmd_buf_mc_addr, 3424 uint64_t fence_mc_addr, 3425 int index) 3426 { 3427 unsigned int psp_write_ptr_reg = 0; 3428 struct psp_gfx_rb_frame *write_frame; 3429 struct psp_ring *ring = &psp->km_ring; 3430 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3431 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3432 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3433 struct amdgpu_device *adev = psp->adev; 3434 uint32_t ring_size_dw = ring->ring_size / 4; 3435 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3436 3437 /* KM (GPCOM) prepare write pointer */ 3438 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3439 3440 /* Update KM RB frame pointer to new frame */ 3441 /* write_frame ptr increments by size of rb_frame in bytes */ 3442 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3443 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3444 write_frame = ring_buffer_start; 3445 else 3446 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3447 /* Check invalid write_frame ptr address */ 3448 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3449 dev_err(adev->dev, 3450 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3451 ring_buffer_start, ring_buffer_end, write_frame); 3452 dev_err(adev->dev, 3453 "write_frame is pointing to address out of bounds\n"); 3454 return -EINVAL; 3455 } 3456 3457 /* Initialize KM RB frame */ 3458 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3459 3460 /* Update KM RB frame */ 3461 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3462 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3463 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3464 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3465 write_frame->fence_value = index; 3466 amdgpu_device_flush_hdp(adev, NULL); 3467 3468 /* Update the write Pointer in DWORDs */ 3469 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3470 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3471 return 0; 3472 } 3473 3474 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3475 { 3476 struct amdgpu_device *adev = psp->adev; 3477 const struct psp_firmware_header_v1_0 *asd_hdr; 3478 int err = 0; 3479 3480 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3481 "amdgpu/%s_asd.bin", chip_name); 3482 if (err) 3483 goto out; 3484 3485 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3486 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3487 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3488 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3489 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3490 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3491 return 0; 3492 out: 3493 amdgpu_ucode_release(&adev->psp.asd_fw); 3494 return err; 3495 } 3496 3497 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3498 { 3499 struct amdgpu_device *adev = psp->adev; 3500 const struct psp_firmware_header_v1_0 *toc_hdr; 3501 int err = 0; 3502 3503 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3504 "amdgpu/%s_toc.bin", chip_name); 3505 if (err) 3506 goto out; 3507 3508 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3509 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3510 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3511 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3512 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3513 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3514 return 0; 3515 out: 3516 amdgpu_ucode_release(&adev->psp.toc_fw); 3517 return err; 3518 } 3519 3520 static int parse_sos_bin_descriptor(struct psp_context *psp, 3521 const struct psp_fw_bin_desc *desc, 3522 const struct psp_firmware_header_v2_0 *sos_hdr) 3523 { 3524 uint8_t *ucode_start_addr = NULL; 3525 3526 if (!psp || !desc || !sos_hdr) 3527 return -EINVAL; 3528 3529 ucode_start_addr = (uint8_t *)sos_hdr + 3530 le32_to_cpu(desc->offset_bytes) + 3531 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3532 3533 switch (desc->fw_type) { 3534 case PSP_FW_TYPE_PSP_SOS: 3535 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3536 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3537 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3538 psp->sos.start_addr = ucode_start_addr; 3539 break; 3540 case PSP_FW_TYPE_PSP_SYS_DRV: 3541 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3542 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3543 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3544 psp->sys.start_addr = ucode_start_addr; 3545 break; 3546 case PSP_FW_TYPE_PSP_KDB: 3547 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3548 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3549 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3550 psp->kdb.start_addr = ucode_start_addr; 3551 break; 3552 case PSP_FW_TYPE_PSP_TOC: 3553 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3554 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3555 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3556 psp->toc.start_addr = ucode_start_addr; 3557 break; 3558 case PSP_FW_TYPE_PSP_SPL: 3559 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3560 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3561 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3562 psp->spl.start_addr = ucode_start_addr; 3563 break; 3564 case PSP_FW_TYPE_PSP_RL: 3565 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3566 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3567 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3568 psp->rl.start_addr = ucode_start_addr; 3569 break; 3570 case PSP_FW_TYPE_PSP_SOC_DRV: 3571 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3572 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3573 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3574 psp->soc_drv.start_addr = ucode_start_addr; 3575 break; 3576 case PSP_FW_TYPE_PSP_INTF_DRV: 3577 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3578 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3579 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3580 psp->intf_drv.start_addr = ucode_start_addr; 3581 break; 3582 case PSP_FW_TYPE_PSP_DBG_DRV: 3583 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3584 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3585 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3586 psp->dbg_drv.start_addr = ucode_start_addr; 3587 break; 3588 case PSP_FW_TYPE_PSP_RAS_DRV: 3589 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3590 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3591 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3592 psp->ras_drv.start_addr = ucode_start_addr; 3593 break; 3594 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3595 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3596 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3597 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3598 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3599 break; 3600 case PSP_FW_TYPE_PSP_SPDM_DRV: 3601 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 3602 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 3603 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3604 psp->spdm_drv.start_addr = ucode_start_addr; 3605 break; 3606 default: 3607 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3608 break; 3609 } 3610 3611 return 0; 3612 } 3613 3614 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3615 { 3616 const struct psp_firmware_header_v1_0 *sos_hdr; 3617 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3618 uint8_t *ucode_array_start_addr; 3619 3620 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3621 ucode_array_start_addr = (uint8_t *)sos_hdr + 3622 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3623 3624 if (adev->gmc.xgmi.connected_to_cpu || 3625 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3626 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3627 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3628 3629 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3630 adev->psp.sys.start_addr = ucode_array_start_addr; 3631 3632 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3633 adev->psp.sos.start_addr = ucode_array_start_addr + 3634 le32_to_cpu(sos_hdr->sos.offset_bytes); 3635 } else { 3636 /* Load alternate PSP SOS FW */ 3637 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3638 3639 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3640 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3641 3642 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3643 adev->psp.sys.start_addr = ucode_array_start_addr + 3644 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3645 3646 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3647 adev->psp.sos.start_addr = ucode_array_start_addr + 3648 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3649 } 3650 3651 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3652 dev_warn(adev->dev, "PSP SOS FW not available"); 3653 return -EINVAL; 3654 } 3655 3656 return 0; 3657 } 3658 3659 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3660 { 3661 struct amdgpu_device *adev = psp->adev; 3662 const struct psp_firmware_header_v1_0 *sos_hdr; 3663 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3664 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3665 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3666 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3667 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 3668 int fw_index, fw_bin_count, start_index = 0; 3669 const struct psp_fw_bin_desc *fw_bin; 3670 uint8_t *ucode_array_start_addr; 3671 int err = 0; 3672 3673 if (amdgpu_is_kicker_fw(adev)) 3674 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3675 "amdgpu/%s_sos_kicker.bin", chip_name); 3676 else 3677 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3678 "amdgpu/%s_sos.bin", chip_name); 3679 if (err) 3680 goto out; 3681 3682 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3683 ucode_array_start_addr = (uint8_t *)sos_hdr + 3684 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3685 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3686 3687 switch (sos_hdr->header.header_version_major) { 3688 case 1: 3689 err = psp_init_sos_base_fw(adev); 3690 if (err) 3691 goto out; 3692 3693 if (sos_hdr->header.header_version_minor == 1) { 3694 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3695 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3696 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3697 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3698 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3699 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3700 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3701 } 3702 if (sos_hdr->header.header_version_minor == 2) { 3703 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3704 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3705 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3706 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3707 } 3708 if (sos_hdr->header.header_version_minor == 3) { 3709 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3710 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3711 adev->psp.toc.start_addr = ucode_array_start_addr + 3712 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3713 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3714 adev->psp.kdb.start_addr = ucode_array_start_addr + 3715 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3716 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3717 adev->psp.spl.start_addr = ucode_array_start_addr + 3718 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3719 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3720 adev->psp.rl.start_addr = ucode_array_start_addr + 3721 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3722 } 3723 break; 3724 case 2: 3725 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3726 3727 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 3728 3729 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 3730 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3731 err = -EINVAL; 3732 goto out; 3733 } 3734 3735 if (sos_hdr_v2_0->header.header_version_minor == 1) { 3736 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 3737 3738 fw_bin = sos_hdr_v2_1->psp_fw_bin; 3739 3740 if (psp_is_aux_sos_load_required(psp)) 3741 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3742 else 3743 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3744 3745 } else { 3746 fw_bin = sos_hdr_v2_0->psp_fw_bin; 3747 } 3748 3749 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 3750 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 3751 sos_hdr_v2_0); 3752 if (err) 3753 goto out; 3754 } 3755 break; 3756 default: 3757 dev_err(adev->dev, 3758 "unsupported psp sos firmware\n"); 3759 err = -EINVAL; 3760 goto out; 3761 } 3762 3763 return 0; 3764 out: 3765 amdgpu_ucode_release(&adev->psp.sos_fw); 3766 3767 return err; 3768 } 3769 3770 static bool is_ta_fw_applicable(struct psp_context *psp, 3771 const struct psp_fw_bin_desc *desc) 3772 { 3773 struct amdgpu_device *adev = psp->adev; 3774 uint32_t fw_version; 3775 3776 switch (desc->fw_type) { 3777 case TA_FW_TYPE_PSP_XGMI: 3778 case TA_FW_TYPE_PSP_XGMI_AUX: 3779 /* for now, AUX TA only exists on 13.0.6 ta bin, 3780 * from v20.00.0x.14 3781 */ 3782 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3783 IP_VERSION(13, 0, 6)) { 3784 fw_version = le32_to_cpu(desc->fw_version); 3785 3786 if (adev->flags & AMD_IS_APU && 3787 (fw_version & 0xff) >= 0x14) 3788 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 3789 else 3790 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 3791 } 3792 break; 3793 default: 3794 break; 3795 } 3796 3797 return true; 3798 } 3799 3800 static int parse_ta_bin_descriptor(struct psp_context *psp, 3801 const struct psp_fw_bin_desc *desc, 3802 const struct ta_firmware_header_v2_0 *ta_hdr) 3803 { 3804 uint8_t *ucode_start_addr = NULL; 3805 3806 if (!psp || !desc || !ta_hdr) 3807 return -EINVAL; 3808 3809 if (!is_ta_fw_applicable(psp, desc)) 3810 return 0; 3811 3812 ucode_start_addr = (uint8_t *)ta_hdr + 3813 le32_to_cpu(desc->offset_bytes) + 3814 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3815 3816 switch (desc->fw_type) { 3817 case TA_FW_TYPE_PSP_ASD: 3818 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3819 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3820 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3821 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3822 break; 3823 case TA_FW_TYPE_PSP_XGMI: 3824 case TA_FW_TYPE_PSP_XGMI_AUX: 3825 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3826 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3827 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3828 break; 3829 case TA_FW_TYPE_PSP_RAS: 3830 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3831 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3832 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3833 break; 3834 case TA_FW_TYPE_PSP_HDCP: 3835 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3836 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3837 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3838 break; 3839 case TA_FW_TYPE_PSP_DTM: 3840 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3841 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3842 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3843 break; 3844 case TA_FW_TYPE_PSP_RAP: 3845 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3846 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3847 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3848 break; 3849 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3850 psp->securedisplay_context.context.bin_desc.fw_version = 3851 le32_to_cpu(desc->fw_version); 3852 psp->securedisplay_context.context.bin_desc.size_bytes = 3853 le32_to_cpu(desc->size_bytes); 3854 psp->securedisplay_context.context.bin_desc.start_addr = 3855 ucode_start_addr; 3856 break; 3857 default: 3858 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3859 break; 3860 } 3861 3862 return 0; 3863 } 3864 3865 static int parse_ta_v1_microcode(struct psp_context *psp) 3866 { 3867 const struct ta_firmware_header_v1_0 *ta_hdr; 3868 struct amdgpu_device *adev = psp->adev; 3869 3870 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3871 3872 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3873 return -EINVAL; 3874 3875 adev->psp.xgmi_context.context.bin_desc.fw_version = 3876 le32_to_cpu(ta_hdr->xgmi.fw_version); 3877 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3878 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3879 adev->psp.xgmi_context.context.bin_desc.start_addr = 3880 (uint8_t *)ta_hdr + 3881 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3882 3883 adev->psp.ras_context.context.bin_desc.fw_version = 3884 le32_to_cpu(ta_hdr->ras.fw_version); 3885 adev->psp.ras_context.context.bin_desc.size_bytes = 3886 le32_to_cpu(ta_hdr->ras.size_bytes); 3887 adev->psp.ras_context.context.bin_desc.start_addr = 3888 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3889 le32_to_cpu(ta_hdr->ras.offset_bytes); 3890 3891 adev->psp.hdcp_context.context.bin_desc.fw_version = 3892 le32_to_cpu(ta_hdr->hdcp.fw_version); 3893 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3894 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3895 adev->psp.hdcp_context.context.bin_desc.start_addr = 3896 (uint8_t *)ta_hdr + 3897 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3898 3899 adev->psp.dtm_context.context.bin_desc.fw_version = 3900 le32_to_cpu(ta_hdr->dtm.fw_version); 3901 adev->psp.dtm_context.context.bin_desc.size_bytes = 3902 le32_to_cpu(ta_hdr->dtm.size_bytes); 3903 adev->psp.dtm_context.context.bin_desc.start_addr = 3904 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3905 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3906 3907 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3908 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3909 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3910 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3911 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3912 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3913 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3914 3915 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3916 3917 return 0; 3918 } 3919 3920 static int parse_ta_v2_microcode(struct psp_context *psp) 3921 { 3922 const struct ta_firmware_header_v2_0 *ta_hdr; 3923 struct amdgpu_device *adev = psp->adev; 3924 int err = 0; 3925 int ta_index = 0; 3926 3927 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3928 3929 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3930 return -EINVAL; 3931 3932 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3933 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3934 return -EINVAL; 3935 } 3936 3937 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3938 err = parse_ta_bin_descriptor(psp, 3939 &ta_hdr->ta_fw_bin[ta_index], 3940 ta_hdr); 3941 if (err) 3942 return err; 3943 } 3944 3945 return 0; 3946 } 3947 3948 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3949 { 3950 const struct common_firmware_header *hdr; 3951 struct amdgpu_device *adev = psp->adev; 3952 int err; 3953 3954 if (amdgpu_is_kicker_fw(adev)) 3955 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3956 "amdgpu/%s_ta_kicker.bin", chip_name); 3957 else 3958 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3959 "amdgpu/%s_ta.bin", chip_name); 3960 if (err) 3961 return err; 3962 3963 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3964 switch (le16_to_cpu(hdr->header_version_major)) { 3965 case 1: 3966 err = parse_ta_v1_microcode(psp); 3967 break; 3968 case 2: 3969 err = parse_ta_v2_microcode(psp); 3970 break; 3971 default: 3972 dev_err(adev->dev, "unsupported TA header version\n"); 3973 err = -EINVAL; 3974 } 3975 3976 if (err) 3977 amdgpu_ucode_release(&adev->psp.ta_fw); 3978 3979 return err; 3980 } 3981 3982 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3983 { 3984 struct amdgpu_device *adev = psp->adev; 3985 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3986 struct amdgpu_firmware_info *info = NULL; 3987 int err = 0; 3988 3989 if (!amdgpu_sriov_vf(adev)) { 3990 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3991 return -EINVAL; 3992 } 3993 3994 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 3995 "amdgpu/%s_cap.bin", chip_name); 3996 if (err) { 3997 if (err == -ENODEV) { 3998 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3999 err = 0; 4000 } else { 4001 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4002 } 4003 goto out; 4004 } 4005 4006 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4007 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4008 info->fw = adev->psp.cap_fw; 4009 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4010 adev->psp.cap_fw->data; 4011 adev->firmware.fw_size += ALIGN( 4012 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4013 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4014 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4015 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4016 4017 return 0; 4018 4019 out: 4020 amdgpu_ucode_release(&adev->psp.cap_fw); 4021 return err; 4022 } 4023 4024 int psp_config_sq_perfmon(struct psp_context *psp, 4025 uint32_t xcp_id, bool core_override_enable, 4026 bool reg_override_enable, bool perfmon_override_enable) 4027 { 4028 int ret; 4029 4030 if (amdgpu_sriov_vf(psp->adev)) 4031 return 0; 4032 4033 if (xcp_id > MAX_XCP) { 4034 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4035 return -EINVAL; 4036 } 4037 4038 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4039 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4040 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4041 return -EINVAL; 4042 } 4043 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4044 4045 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4046 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4047 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4048 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4049 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4050 4051 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4052 if (ret) 4053 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4054 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4055 4056 release_psp_cmd_buf(psp); 4057 return ret; 4058 } 4059 4060 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4061 enum amd_clockgating_state state) 4062 { 4063 return 0; 4064 } 4065 4066 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4067 enum amd_powergating_state state) 4068 { 4069 return 0; 4070 } 4071 4072 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4073 struct device_attribute *attr, 4074 char *buf) 4075 { 4076 struct drm_device *ddev = dev_get_drvdata(dev); 4077 struct amdgpu_device *adev = drm_to_adev(ddev); 4078 struct amdgpu_ip_block *ip_block; 4079 uint32_t fw_ver; 4080 int ret; 4081 4082 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4083 if (!ip_block || !ip_block->status.late_initialized) { 4084 dev_info(adev->dev, "PSP block is not ready yet\n."); 4085 return -EBUSY; 4086 } 4087 4088 mutex_lock(&adev->psp.mutex); 4089 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4090 mutex_unlock(&adev->psp.mutex); 4091 4092 if (ret) { 4093 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4094 return ret; 4095 } 4096 4097 return sysfs_emit(buf, "%x\n", fw_ver); 4098 } 4099 4100 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4101 struct device_attribute *attr, 4102 const char *buf, 4103 size_t count) 4104 { 4105 struct drm_device *ddev = dev_get_drvdata(dev); 4106 struct amdgpu_device *adev = drm_to_adev(ddev); 4107 int ret, idx; 4108 const struct firmware *usbc_pd_fw; 4109 struct amdgpu_bo *fw_buf_bo = NULL; 4110 uint64_t fw_pri_mc_addr; 4111 void *fw_pri_cpu_addr; 4112 struct amdgpu_ip_block *ip_block; 4113 4114 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4115 if (!ip_block || !ip_block->status.late_initialized) { 4116 dev_err(adev->dev, "PSP block is not ready yet."); 4117 return -EBUSY; 4118 } 4119 4120 if (!drm_dev_enter(ddev, &idx)) 4121 return -ENODEV; 4122 4123 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4124 "amdgpu/%s", buf); 4125 if (ret) 4126 goto fail; 4127 4128 /* LFB address which is aligned to 1MB boundary per PSP request */ 4129 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4130 AMDGPU_GEM_DOMAIN_VRAM | 4131 AMDGPU_GEM_DOMAIN_GTT, 4132 &fw_buf_bo, &fw_pri_mc_addr, 4133 &fw_pri_cpu_addr); 4134 if (ret) 4135 goto rel_buf; 4136 4137 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4138 4139 mutex_lock(&adev->psp.mutex); 4140 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4141 mutex_unlock(&adev->psp.mutex); 4142 4143 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4144 4145 rel_buf: 4146 amdgpu_ucode_release(&usbc_pd_fw); 4147 fail: 4148 if (ret) { 4149 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4150 count = ret; 4151 } 4152 4153 drm_dev_exit(idx); 4154 return count; 4155 } 4156 4157 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4158 { 4159 int idx; 4160 4161 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4162 return; 4163 4164 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4165 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4166 4167 drm_dev_exit(idx); 4168 } 4169 4170 /** 4171 * DOC: usbc_pd_fw 4172 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4173 * this file will trigger the update process. 4174 */ 4175 static DEVICE_ATTR(usbc_pd_fw, 0644, 4176 psp_usbc_pd_fw_sysfs_read, 4177 psp_usbc_pd_fw_sysfs_write); 4178 4179 int is_psp_fw_valid(struct psp_bin_desc bin) 4180 { 4181 return bin.size_bytes; 4182 } 4183 4184 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4185 const struct bin_attribute *bin_attr, 4186 char *buffer, loff_t pos, size_t count) 4187 { 4188 struct device *dev = kobj_to_dev(kobj); 4189 struct drm_device *ddev = dev_get_drvdata(dev); 4190 struct amdgpu_device *adev = drm_to_adev(ddev); 4191 4192 adev->psp.vbflash_done = false; 4193 4194 /* Safeguard against memory drain */ 4195 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4196 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4197 kvfree(adev->psp.vbflash_tmp_buf); 4198 adev->psp.vbflash_tmp_buf = NULL; 4199 adev->psp.vbflash_image_size = 0; 4200 return -ENOMEM; 4201 } 4202 4203 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4204 if (!adev->psp.vbflash_tmp_buf) { 4205 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4206 if (!adev->psp.vbflash_tmp_buf) 4207 return -ENOMEM; 4208 } 4209 4210 mutex_lock(&adev->psp.mutex); 4211 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4212 adev->psp.vbflash_image_size += count; 4213 mutex_unlock(&adev->psp.mutex); 4214 4215 dev_dbg(adev->dev, "IFWI staged for update\n"); 4216 4217 return count; 4218 } 4219 4220 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4221 const struct bin_attribute *bin_attr, char *buffer, 4222 loff_t pos, size_t count) 4223 { 4224 struct device *dev = kobj_to_dev(kobj); 4225 struct drm_device *ddev = dev_get_drvdata(dev); 4226 struct amdgpu_device *adev = drm_to_adev(ddev); 4227 struct amdgpu_bo *fw_buf_bo = NULL; 4228 uint64_t fw_pri_mc_addr; 4229 void *fw_pri_cpu_addr; 4230 int ret; 4231 4232 if (adev->psp.vbflash_image_size == 0) 4233 return -EINVAL; 4234 4235 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4236 4237 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4238 AMDGPU_GPU_PAGE_SIZE, 4239 AMDGPU_GEM_DOMAIN_VRAM, 4240 &fw_buf_bo, 4241 &fw_pri_mc_addr, 4242 &fw_pri_cpu_addr); 4243 if (ret) 4244 goto rel_buf; 4245 4246 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4247 4248 mutex_lock(&adev->psp.mutex); 4249 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4250 mutex_unlock(&adev->psp.mutex); 4251 4252 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4253 4254 rel_buf: 4255 kvfree(adev->psp.vbflash_tmp_buf); 4256 adev->psp.vbflash_tmp_buf = NULL; 4257 adev->psp.vbflash_image_size = 0; 4258 4259 if (ret) { 4260 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4261 return ret; 4262 } 4263 4264 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4265 return 0; 4266 } 4267 4268 /** 4269 * DOC: psp_vbflash 4270 * Writing to this file will stage an IFWI for update. Reading from this file 4271 * will trigger the update process. 4272 */ 4273 static const struct bin_attribute psp_vbflash_bin_attr = { 4274 .attr = {.name = "psp_vbflash", .mode = 0660}, 4275 .size = 0, 4276 .write = amdgpu_psp_vbflash_write, 4277 .read = amdgpu_psp_vbflash_read, 4278 }; 4279 4280 /** 4281 * DOC: psp_vbflash_status 4282 * The status of the flash process. 4283 * 0: IFWI flash not complete. 4284 * 1: IFWI flash complete. 4285 */ 4286 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4287 struct device_attribute *attr, 4288 char *buf) 4289 { 4290 struct drm_device *ddev = dev_get_drvdata(dev); 4291 struct amdgpu_device *adev = drm_to_adev(ddev); 4292 uint32_t vbflash_status; 4293 4294 vbflash_status = psp_vbflash_status(&adev->psp); 4295 if (!adev->psp.vbflash_done) 4296 vbflash_status = 0; 4297 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4298 vbflash_status = 1; 4299 4300 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4301 } 4302 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4303 4304 static const struct bin_attribute *const bin_flash_attrs[] = { 4305 &psp_vbflash_bin_attr, 4306 NULL 4307 }; 4308 4309 static struct attribute *flash_attrs[] = { 4310 &dev_attr_psp_vbflash_status.attr, 4311 &dev_attr_usbc_pd_fw.attr, 4312 NULL 4313 }; 4314 4315 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4316 { 4317 struct device *dev = kobj_to_dev(kobj); 4318 struct drm_device *ddev = dev_get_drvdata(dev); 4319 struct amdgpu_device *adev = drm_to_adev(ddev); 4320 4321 if (attr == &dev_attr_usbc_pd_fw.attr) 4322 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4323 4324 return adev->psp.sup_ifwi_up ? 0440 : 0; 4325 } 4326 4327 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4328 const struct bin_attribute *attr, 4329 int idx) 4330 { 4331 struct device *dev = kobj_to_dev(kobj); 4332 struct drm_device *ddev = dev_get_drvdata(dev); 4333 struct amdgpu_device *adev = drm_to_adev(ddev); 4334 4335 return adev->psp.sup_ifwi_up ? 0660 : 0; 4336 } 4337 4338 const struct attribute_group amdgpu_flash_attr_group = { 4339 .attrs = flash_attrs, 4340 .bin_attrs = bin_flash_attrs, 4341 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4342 .is_visible = amdgpu_flash_attr_is_visible, 4343 }; 4344 4345 #if defined(CONFIG_DEBUG_FS) 4346 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4347 { 4348 struct amdgpu_device *adev = filp->f_inode->i_private; 4349 struct spirom_bo *bo_triplet; 4350 int ret; 4351 4352 /* serialize the open() file calling */ 4353 if (!mutex_trylock(&adev->psp.mutex)) 4354 return -EBUSY; 4355 4356 /* 4357 * make sure only one userpace process is alive for dumping so that 4358 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4359 * let's say the case where one process try opening the file while 4360 * another one has proceeded to read or release. In this way, eliminate 4361 * the use of mutex for read() or release() callback as well. 4362 */ 4363 if (adev->psp.spirom_dump_trip) { 4364 mutex_unlock(&adev->psp.mutex); 4365 return -EBUSY; 4366 } 4367 4368 bo_triplet = kzalloc(sizeof(struct spirom_bo), GFP_KERNEL); 4369 if (!bo_triplet) { 4370 mutex_unlock(&adev->psp.mutex); 4371 return -ENOMEM; 4372 } 4373 4374 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4375 AMDGPU_GPU_PAGE_SIZE, 4376 AMDGPU_GEM_DOMAIN_GTT, 4377 &bo_triplet->bo, 4378 &bo_triplet->mc_addr, 4379 &bo_triplet->cpu_addr); 4380 if (ret) 4381 goto rel_trip; 4382 4383 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4384 if (ret) 4385 goto rel_bo; 4386 4387 adev->psp.spirom_dump_trip = bo_triplet; 4388 mutex_unlock(&adev->psp.mutex); 4389 return 0; 4390 rel_bo: 4391 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4392 &bo_triplet->cpu_addr); 4393 rel_trip: 4394 kfree(bo_triplet); 4395 mutex_unlock(&adev->psp.mutex); 4396 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4397 return ret; 4398 } 4399 4400 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4401 loff_t *pos) 4402 { 4403 struct amdgpu_device *adev = filp->f_inode->i_private; 4404 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4405 4406 if (!bo_triplet) 4407 return -EINVAL; 4408 4409 return simple_read_from_buffer(buf, 4410 size, 4411 pos, bo_triplet->cpu_addr, 4412 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4413 } 4414 4415 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4416 { 4417 struct amdgpu_device *adev = filp->f_inode->i_private; 4418 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4419 4420 if (bo_triplet) { 4421 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4422 &bo_triplet->cpu_addr); 4423 kfree(bo_triplet); 4424 } 4425 4426 adev->psp.spirom_dump_trip = NULL; 4427 return 0; 4428 } 4429 4430 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4431 .owner = THIS_MODULE, 4432 .open = psp_read_spirom_debugfs_open, 4433 .read = psp_read_spirom_debugfs_read, 4434 .release = psp_read_spirom_debugfs_release, 4435 .llseek = default_llseek, 4436 }; 4437 #endif 4438 4439 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4440 { 4441 #if defined(CONFIG_DEBUG_FS) 4442 struct drm_minor *minor = adev_to_drm(adev)->primary; 4443 4444 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4445 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4446 #endif 4447 } 4448 4449 const struct amd_ip_funcs psp_ip_funcs = { 4450 .name = "psp", 4451 .early_init = psp_early_init, 4452 .sw_init = psp_sw_init, 4453 .sw_fini = psp_sw_fini, 4454 .hw_init = psp_hw_init, 4455 .hw_fini = psp_hw_fini, 4456 .suspend = psp_suspend, 4457 .resume = psp_resume, 4458 .set_clockgating_state = psp_set_clockgating_state, 4459 .set_powergating_state = psp_set_powergating_state, 4460 }; 4461 4462 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4463 .type = AMD_IP_BLOCK_TYPE_PSP, 4464 .major = 3, 4465 .minor = 1, 4466 .rev = 0, 4467 .funcs = &psp_ip_funcs, 4468 }; 4469 4470 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4471 .type = AMD_IP_BLOCK_TYPE_PSP, 4472 .major = 10, 4473 .minor = 0, 4474 .rev = 0, 4475 .funcs = &psp_ip_funcs, 4476 }; 4477 4478 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4479 .type = AMD_IP_BLOCK_TYPE_PSP, 4480 .major = 11, 4481 .minor = 0, 4482 .rev = 0, 4483 .funcs = &psp_ip_funcs, 4484 }; 4485 4486 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4487 .type = AMD_IP_BLOCK_TYPE_PSP, 4488 .major = 11, 4489 .minor = 0, 4490 .rev = 8, 4491 .funcs = &psp_ip_funcs, 4492 }; 4493 4494 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4495 .type = AMD_IP_BLOCK_TYPE_PSP, 4496 .major = 12, 4497 .minor = 0, 4498 .rev = 0, 4499 .funcs = &psp_ip_funcs, 4500 }; 4501 4502 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4503 .type = AMD_IP_BLOCK_TYPE_PSP, 4504 .major = 13, 4505 .minor = 0, 4506 .rev = 0, 4507 .funcs = &psp_ip_funcs, 4508 }; 4509 4510 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4511 .type = AMD_IP_BLOCK_TYPE_PSP, 4512 .major = 13, 4513 .minor = 0, 4514 .rev = 4, 4515 .funcs = &psp_ip_funcs, 4516 }; 4517 4518 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4519 .type = AMD_IP_BLOCK_TYPE_PSP, 4520 .major = 14, 4521 .minor = 0, 4522 .rev = 0, 4523 .funcs = &psp_ip_funcs, 4524 }; 4525