1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 case IP_VERSION(13, 0, 14): 149 ret = psp_init_cap_microcode(psp, ucode_prefix); 150 ret &= psp_init_ta_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 case IP_VERSION(13, 0, 12): 157 ret = psp_init_ta_microcode(psp, ucode_prefix); 158 break; 159 default: 160 return -EINVAL; 161 } 162 return ret; 163 } 164 165 static int psp_early_init(struct amdgpu_ip_block *ip_block) 166 { 167 struct amdgpu_device *adev = ip_block->adev; 168 struct psp_context *psp = &adev->psp; 169 170 psp->autoload_supported = true; 171 psp->boot_time_tmr = true; 172 173 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 174 case IP_VERSION(9, 0, 0): 175 psp_v3_1_set_psp_funcs(psp); 176 psp->autoload_supported = false; 177 psp->boot_time_tmr = false; 178 break; 179 case IP_VERSION(10, 0, 0): 180 case IP_VERSION(10, 0, 1): 181 psp_v10_0_set_psp_funcs(psp); 182 psp->autoload_supported = false; 183 psp->boot_time_tmr = false; 184 break; 185 case IP_VERSION(11, 0, 2): 186 case IP_VERSION(11, 0, 4): 187 psp_v11_0_set_psp_funcs(psp); 188 psp->autoload_supported = false; 189 psp->boot_time_tmr = false; 190 break; 191 case IP_VERSION(11, 0, 0): 192 case IP_VERSION(11, 0, 7): 193 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 194 fallthrough; 195 case IP_VERSION(11, 0, 5): 196 case IP_VERSION(11, 0, 9): 197 case IP_VERSION(11, 0, 11): 198 case IP_VERSION(11, 5, 0): 199 case IP_VERSION(11, 5, 2): 200 case IP_VERSION(11, 0, 12): 201 case IP_VERSION(11, 0, 13): 202 psp_v11_0_set_psp_funcs(psp); 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 3): 206 case IP_VERSION(12, 0, 1): 207 psp_v12_0_set_psp_funcs(psp); 208 psp->autoload_supported = false; 209 psp->boot_time_tmr = false; 210 break; 211 case IP_VERSION(13, 0, 2): 212 psp->boot_time_tmr = false; 213 fallthrough; 214 case IP_VERSION(13, 0, 6): 215 case IP_VERSION(13, 0, 14): 216 psp_v13_0_set_psp_funcs(psp); 217 psp->autoload_supported = false; 218 break; 219 case IP_VERSION(13, 0, 12): 220 psp_v13_0_set_psp_funcs(psp); 221 psp->autoload_supported = false; 222 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 223 break; 224 case IP_VERSION(13, 0, 1): 225 case IP_VERSION(13, 0, 3): 226 case IP_VERSION(13, 0, 5): 227 case IP_VERSION(13, 0, 8): 228 case IP_VERSION(13, 0, 11): 229 case IP_VERSION(14, 0, 0): 230 case IP_VERSION(14, 0, 1): 231 case IP_VERSION(14, 0, 4): 232 psp_v13_0_set_psp_funcs(psp); 233 psp->boot_time_tmr = false; 234 break; 235 case IP_VERSION(11, 0, 8): 236 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 237 psp_v11_0_8_set_psp_funcs(psp); 238 } 239 psp->autoload_supported = false; 240 psp->boot_time_tmr = false; 241 break; 242 case IP_VERSION(13, 0, 0): 243 case IP_VERSION(13, 0, 7): 244 case IP_VERSION(13, 0, 10): 245 psp_v13_0_set_psp_funcs(psp); 246 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 247 psp->boot_time_tmr = false; 248 break; 249 case IP_VERSION(13, 0, 4): 250 psp_v13_0_4_set_psp_funcs(psp); 251 psp->boot_time_tmr = false; 252 break; 253 case IP_VERSION(14, 0, 2): 254 case IP_VERSION(14, 0, 3): 255 psp_v14_0_set_psp_funcs(psp); 256 break; 257 case IP_VERSION(14, 0, 5): 258 psp_v14_0_set_psp_funcs(psp); 259 psp->boot_time_tmr = false; 260 break; 261 default: 262 return -EINVAL; 263 } 264 265 psp->adev = adev; 266 267 adev->psp_timeout = 20000; 268 269 psp_check_pmfw_centralized_cstate_management(psp); 270 271 if (amdgpu_sriov_vf(adev)) 272 return psp_init_sriov_microcode(psp); 273 else 274 return psp_init_microcode(psp); 275 } 276 277 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 278 { 279 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 280 &mem_ctx->shared_buf); 281 mem_ctx->shared_bo = NULL; 282 } 283 284 static void psp_free_shared_bufs(struct psp_context *psp) 285 { 286 void *tmr_buf; 287 void **pptr; 288 289 /* free TMR memory buffer */ 290 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 291 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 292 psp->tmr_bo = NULL; 293 294 /* free xgmi shared memory */ 295 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 296 297 /* free ras shared memory */ 298 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 299 300 /* free hdcp shared memory */ 301 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 302 303 /* free dtm shared memory */ 304 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 305 306 /* free rap shared memory */ 307 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 308 309 /* free securedisplay shared memory */ 310 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 311 312 313 } 314 315 static void psp_memory_training_fini(struct psp_context *psp) 316 { 317 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 318 319 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 320 kfree(ctx->sys_cache); 321 ctx->sys_cache = NULL; 322 } 323 324 static int psp_memory_training_init(struct psp_context *psp) 325 { 326 int ret; 327 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 328 329 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 330 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 331 return 0; 332 } 333 334 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 335 if (ctx->sys_cache == NULL) { 336 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 337 ret = -ENOMEM; 338 goto Err_out; 339 } 340 341 dev_dbg(psp->adev->dev, 342 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 343 ctx->train_data_size, 344 ctx->p2c_train_data_offset, 345 ctx->c2p_train_data_offset); 346 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 347 return 0; 348 349 Err_out: 350 psp_memory_training_fini(psp); 351 return ret; 352 } 353 354 /* 355 * Helper funciton to query psp runtime database entry 356 * 357 * @adev: amdgpu_device pointer 358 * @entry_type: the type of psp runtime database entry 359 * @db_entry: runtime database entry pointer 360 * 361 * Return false if runtime database doesn't exit or entry is invalid 362 * or true if the specific database entry is found, and copy to @db_entry 363 */ 364 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 365 enum psp_runtime_entry_type entry_type, 366 void *db_entry) 367 { 368 uint64_t db_header_pos, db_dir_pos; 369 struct psp_runtime_data_header db_header = {0}; 370 struct psp_runtime_data_directory db_dir = {0}; 371 bool ret = false; 372 int i; 373 374 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 375 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 376 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) 377 return false; 378 379 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 380 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 381 382 /* read runtime db header from vram */ 383 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 384 sizeof(struct psp_runtime_data_header), false); 385 386 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 387 /* runtime db doesn't exist, exit */ 388 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 389 return false; 390 } 391 392 /* read runtime database entry from vram */ 393 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 394 sizeof(struct psp_runtime_data_directory), false); 395 396 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 397 /* invalid db entry count, exit */ 398 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 399 return false; 400 } 401 402 /* look up for requested entry type */ 403 for (i = 0; i < db_dir.entry_count && !ret; i++) { 404 if (db_dir.entry_list[i].entry_type == entry_type) { 405 switch (entry_type) { 406 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 407 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 408 /* invalid db entry size */ 409 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 410 return false; 411 } 412 /* read runtime database entry */ 413 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 414 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 415 ret = true; 416 break; 417 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 418 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 419 /* invalid db entry size */ 420 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 421 return false; 422 } 423 /* read runtime database entry */ 424 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 425 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 426 ret = true; 427 break; 428 default: 429 ret = false; 430 break; 431 } 432 } 433 } 434 435 return ret; 436 } 437 438 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 439 { 440 struct amdgpu_device *adev = ip_block->adev; 441 struct psp_context *psp = &adev->psp; 442 int ret; 443 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 444 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 445 struct psp_runtime_scpm_entry scpm_entry; 446 447 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 448 if (!psp->cmd) { 449 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 450 ret = -ENOMEM; 451 } 452 453 adev->psp.xgmi_context.supports_extended_data = 454 !adev->gmc.xgmi.connected_to_cpu && 455 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 456 457 memset(&scpm_entry, 0, sizeof(scpm_entry)); 458 if ((psp_get_runtime_db_entry(adev, 459 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 460 &scpm_entry)) && 461 (scpm_entry.scpm_status != SCPM_DISABLE)) { 462 adev->scpm_enabled = true; 463 adev->scpm_status = scpm_entry.scpm_status; 464 } else { 465 adev->scpm_enabled = false; 466 adev->scpm_status = SCPM_DISABLE; 467 } 468 469 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 470 471 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 472 if (psp_get_runtime_db_entry(adev, 473 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 474 &boot_cfg_entry)) { 475 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 476 if ((psp->boot_cfg_bitmask) & 477 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 478 /* If psp runtime database exists, then 479 * only enable two stage memory training 480 * when TWO_STAGE_DRAM_TRAINING bit is set 481 * in runtime database 482 */ 483 mem_training_ctx->enable_mem_training = true; 484 } 485 486 } else { 487 /* If psp runtime database doesn't exist or is 488 * invalid, force enable two stage memory training 489 */ 490 mem_training_ctx->enable_mem_training = true; 491 } 492 493 if (mem_training_ctx->enable_mem_training) { 494 ret = psp_memory_training_init(psp); 495 if (ret) { 496 dev_err(adev->dev, "Failed to initialize memory training!\n"); 497 return ret; 498 } 499 500 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 501 if (ret) { 502 dev_err(adev->dev, "Failed to process memory training!\n"); 503 return ret; 504 } 505 } 506 507 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 508 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 509 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 510 &psp->fw_pri_bo, 511 &psp->fw_pri_mc_addr, 512 &psp->fw_pri_buf); 513 if (ret) 514 return ret; 515 516 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 517 AMDGPU_GEM_DOMAIN_VRAM | 518 AMDGPU_GEM_DOMAIN_GTT, 519 &psp->fence_buf_bo, 520 &psp->fence_buf_mc_addr, 521 &psp->fence_buf); 522 if (ret) 523 goto failed1; 524 525 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 526 AMDGPU_GEM_DOMAIN_VRAM | 527 AMDGPU_GEM_DOMAIN_GTT, 528 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 529 (void **)&psp->cmd_buf_mem); 530 if (ret) 531 goto failed2; 532 533 return 0; 534 535 failed2: 536 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 537 &psp->fence_buf_mc_addr, &psp->fence_buf); 538 failed1: 539 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 540 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 541 return ret; 542 } 543 544 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 545 { 546 struct amdgpu_device *adev = ip_block->adev; 547 struct psp_context *psp = &adev->psp; 548 549 psp_memory_training_fini(psp); 550 551 amdgpu_ucode_release(&psp->sos_fw); 552 amdgpu_ucode_release(&psp->asd_fw); 553 amdgpu_ucode_release(&psp->ta_fw); 554 amdgpu_ucode_release(&psp->cap_fw); 555 amdgpu_ucode_release(&psp->toc_fw); 556 557 kfree(psp->cmd); 558 psp->cmd = NULL; 559 560 psp_free_shared_bufs(psp); 561 562 if (psp->km_ring.ring_mem) 563 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 564 &psp->km_ring.ring_mem_mc_addr, 565 (void **)&psp->km_ring.ring_mem); 566 567 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 568 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 569 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 570 &psp->fence_buf_mc_addr, &psp->fence_buf); 571 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 572 (void **)&psp->cmd_buf_mem); 573 574 return 0; 575 } 576 577 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 578 uint32_t reg_val, uint32_t mask, bool check_changed) 579 { 580 uint32_t val; 581 int i; 582 struct amdgpu_device *adev = psp->adev; 583 584 if (psp->adev->no_hw_access) 585 return 0; 586 587 for (i = 0; i < adev->usec_timeout; i++) { 588 val = RREG32(reg_index); 589 if (check_changed) { 590 if (val != reg_val) 591 return 0; 592 } else { 593 if ((val & mask) == reg_val) 594 return 0; 595 } 596 udelay(1); 597 } 598 599 return -ETIME; 600 } 601 602 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 603 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 604 { 605 uint32_t val; 606 int i; 607 struct amdgpu_device *adev = psp->adev; 608 609 if (psp->adev->no_hw_access) 610 return 0; 611 612 for (i = 0; i < msec_timeout; i++) { 613 val = RREG32(reg_index); 614 if ((val & mask) == reg_val) 615 return 0; 616 msleep(1); 617 } 618 619 return -ETIME; 620 } 621 622 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 623 { 624 switch (cmd_id) { 625 case GFX_CMD_ID_LOAD_TA: 626 return "LOAD_TA"; 627 case GFX_CMD_ID_UNLOAD_TA: 628 return "UNLOAD_TA"; 629 case GFX_CMD_ID_INVOKE_CMD: 630 return "INVOKE_CMD"; 631 case GFX_CMD_ID_LOAD_ASD: 632 return "LOAD_ASD"; 633 case GFX_CMD_ID_SETUP_TMR: 634 return "SETUP_TMR"; 635 case GFX_CMD_ID_LOAD_IP_FW: 636 return "LOAD_IP_FW"; 637 case GFX_CMD_ID_DESTROY_TMR: 638 return "DESTROY_TMR"; 639 case GFX_CMD_ID_SAVE_RESTORE: 640 return "SAVE_RESTORE_IP_FW"; 641 case GFX_CMD_ID_SETUP_VMR: 642 return "SETUP_VMR"; 643 case GFX_CMD_ID_DESTROY_VMR: 644 return "DESTROY_VMR"; 645 case GFX_CMD_ID_PROG_REG: 646 return "PROG_REG"; 647 case GFX_CMD_ID_GET_FW_ATTESTATION: 648 return "GET_FW_ATTESTATION"; 649 case GFX_CMD_ID_LOAD_TOC: 650 return "ID_LOAD_TOC"; 651 case GFX_CMD_ID_AUTOLOAD_RLC: 652 return "AUTOLOAD_RLC"; 653 case GFX_CMD_ID_BOOT_CFG: 654 return "BOOT_CFG"; 655 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 656 return "CONFIG_SQ_PERFMON"; 657 default: 658 return "UNKNOWN CMD"; 659 } 660 } 661 662 static bool psp_err_warn(struct psp_context *psp) 663 { 664 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 665 666 /* This response indicates reg list is already loaded */ 667 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 668 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 669 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 670 cmd->resp.status == TEE_ERROR_CANCEL) 671 return false; 672 673 return true; 674 } 675 676 static int 677 psp_cmd_submit_buf(struct psp_context *psp, 678 struct amdgpu_firmware_info *ucode, 679 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 680 { 681 int ret; 682 int index; 683 int timeout = psp->adev->psp_timeout; 684 bool ras_intr = false; 685 bool skip_unsupport = false; 686 687 if (psp->adev->no_hw_access) 688 return 0; 689 690 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 691 692 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 693 694 index = atomic_inc_return(&psp->fence_value); 695 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 696 if (ret) { 697 atomic_dec(&psp->fence_value); 698 goto exit; 699 } 700 701 amdgpu_device_invalidate_hdp(psp->adev, NULL); 702 while (*((unsigned int *)psp->fence_buf) != index) { 703 if (--timeout == 0) 704 break; 705 /* 706 * Shouldn't wait for timeout when err_event_athub occurs, 707 * because gpu reset thread triggered and lock resource should 708 * be released for psp resume sequence. 709 */ 710 ras_intr = amdgpu_ras_intr_triggered(); 711 if (ras_intr) 712 break; 713 usleep_range(10, 100); 714 amdgpu_device_invalidate_hdp(psp->adev, NULL); 715 } 716 717 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 718 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 719 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 720 721 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 722 723 /* In some cases, psp response status is not 0 even there is no 724 * problem while the command is submitted. Some version of PSP FW 725 * doesn't write 0 to that field. 726 * So here we would like to only print a warning instead of an error 727 * during psp initialization to avoid breaking hw_init and it doesn't 728 * return -EINVAL. 729 */ 730 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 731 if (ucode) 732 dev_warn(psp->adev->dev, 733 "failed to load ucode %s(0x%X) ", 734 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 735 if (psp_err_warn(psp)) 736 dev_warn( 737 psp->adev->dev, 738 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 739 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 740 psp->cmd_buf_mem->cmd_id, 741 psp->cmd_buf_mem->resp.status); 742 /* If any firmware (including CAP) load fails under SRIOV, it should 743 * return failure to stop the VF from initializing. 744 * Also return failure in case of timeout 745 */ 746 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 747 ret = -EINVAL; 748 goto exit; 749 } 750 } 751 752 if (ucode) { 753 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 754 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 755 } 756 757 exit: 758 return ret; 759 } 760 761 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 762 { 763 struct psp_gfx_cmd_resp *cmd = psp->cmd; 764 765 mutex_lock(&psp->mutex); 766 767 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 768 769 return cmd; 770 } 771 772 static void release_psp_cmd_buf(struct psp_context *psp) 773 { 774 mutex_unlock(&psp->mutex); 775 } 776 777 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 778 struct psp_gfx_cmd_resp *cmd, 779 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 780 { 781 struct amdgpu_device *adev = psp->adev; 782 uint32_t size = 0; 783 uint64_t tmr_pa = 0; 784 785 if (tmr_bo) { 786 size = amdgpu_bo_size(tmr_bo); 787 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 788 } 789 790 if (amdgpu_sriov_vf(psp->adev)) 791 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 792 else 793 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 794 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 795 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 796 cmd->cmd.cmd_setup_tmr.buf_size = size; 797 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 798 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 799 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 800 } 801 802 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 803 uint64_t pri_buf_mc, uint32_t size) 804 { 805 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 806 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 807 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 808 cmd->cmd.cmd_load_toc.toc_size = size; 809 } 810 811 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 812 static int psp_load_toc(struct psp_context *psp, 813 uint32_t *tmr_size) 814 { 815 int ret; 816 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 817 818 /* Copy toc to psp firmware private buffer */ 819 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 820 821 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 822 823 ret = psp_cmd_submit_buf(psp, NULL, cmd, 824 psp->fence_buf_mc_addr); 825 if (!ret) 826 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 827 828 release_psp_cmd_buf(psp); 829 830 return ret; 831 } 832 833 /* Set up Trusted Memory Region */ 834 static int psp_tmr_init(struct psp_context *psp) 835 { 836 int ret = 0; 837 int tmr_size; 838 void *tmr_buf; 839 void **pptr; 840 841 /* 842 * According to HW engineer, they prefer the TMR address be "naturally 843 * aligned" , e.g. the start address be an integer divide of TMR size. 844 * 845 * Note: this memory need be reserved till the driver 846 * uninitializes. 847 */ 848 tmr_size = PSP_TMR_SIZE(psp->adev); 849 850 /* For ASICs support RLC autoload, psp will parse the toc 851 * and calculate the total size of TMR needed 852 */ 853 if (!amdgpu_sriov_vf(psp->adev) && 854 psp->toc.start_addr && 855 psp->toc.size_bytes && 856 psp->fw_pri_buf) { 857 ret = psp_load_toc(psp, &tmr_size); 858 if (ret) { 859 dev_err(psp->adev->dev, "Failed to load toc\n"); 860 return ret; 861 } 862 } 863 864 if (!psp->tmr_bo && !psp->boot_time_tmr) { 865 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 866 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 867 PSP_TMR_ALIGNMENT, 868 AMDGPU_HAS_VRAM(psp->adev) ? 869 AMDGPU_GEM_DOMAIN_VRAM : 870 AMDGPU_GEM_DOMAIN_GTT, 871 &psp->tmr_bo, &psp->tmr_mc_addr, 872 pptr); 873 } 874 875 return ret; 876 } 877 878 static bool psp_skip_tmr(struct psp_context *psp) 879 { 880 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 881 case IP_VERSION(11, 0, 9): 882 case IP_VERSION(11, 0, 7): 883 case IP_VERSION(13, 0, 2): 884 case IP_VERSION(13, 0, 6): 885 case IP_VERSION(13, 0, 10): 886 case IP_VERSION(13, 0, 12): 887 case IP_VERSION(13, 0, 14): 888 return true; 889 default: 890 return false; 891 } 892 } 893 894 static int psp_tmr_load(struct psp_context *psp) 895 { 896 int ret; 897 struct psp_gfx_cmd_resp *cmd; 898 899 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 900 * Already set up by host driver. 901 */ 902 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 903 return 0; 904 905 cmd = acquire_psp_cmd_buf(psp); 906 907 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 908 if (psp->tmr_bo) 909 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 910 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 911 912 ret = psp_cmd_submit_buf(psp, NULL, cmd, 913 psp->fence_buf_mc_addr); 914 915 release_psp_cmd_buf(psp); 916 917 return ret; 918 } 919 920 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 921 struct psp_gfx_cmd_resp *cmd) 922 { 923 if (amdgpu_sriov_vf(psp->adev)) 924 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 925 else 926 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 927 } 928 929 static int psp_tmr_unload(struct psp_context *psp) 930 { 931 int ret; 932 struct psp_gfx_cmd_resp *cmd; 933 934 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 935 * as TMR is not loaded at all 936 */ 937 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 938 return 0; 939 940 cmd = acquire_psp_cmd_buf(psp); 941 942 psp_prep_tmr_unload_cmd_buf(psp, cmd); 943 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 944 945 ret = psp_cmd_submit_buf(psp, NULL, cmd, 946 psp->fence_buf_mc_addr); 947 948 release_psp_cmd_buf(psp); 949 950 return ret; 951 } 952 953 static int psp_tmr_terminate(struct psp_context *psp) 954 { 955 return psp_tmr_unload(psp); 956 } 957 958 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 959 uint64_t *output_ptr) 960 { 961 int ret; 962 struct psp_gfx_cmd_resp *cmd; 963 964 if (!output_ptr) 965 return -EINVAL; 966 967 if (amdgpu_sriov_vf(psp->adev)) 968 return 0; 969 970 cmd = acquire_psp_cmd_buf(psp); 971 972 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 973 974 ret = psp_cmd_submit_buf(psp, NULL, cmd, 975 psp->fence_buf_mc_addr); 976 977 if (!ret) { 978 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 979 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 980 } 981 982 release_psp_cmd_buf(psp); 983 984 return ret; 985 } 986 987 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 988 { 989 struct psp_context *psp = &adev->psp; 990 struct psp_gfx_cmd_resp *cmd; 991 int ret; 992 993 if (amdgpu_sriov_vf(adev)) 994 return 0; 995 996 cmd = acquire_psp_cmd_buf(psp); 997 998 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 999 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1000 1001 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1002 if (!ret) { 1003 *boot_cfg = 1004 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1005 } 1006 1007 release_psp_cmd_buf(psp); 1008 1009 return ret; 1010 } 1011 1012 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1013 { 1014 int ret; 1015 struct psp_context *psp = &adev->psp; 1016 struct psp_gfx_cmd_resp *cmd; 1017 1018 if (amdgpu_sriov_vf(adev)) 1019 return 0; 1020 1021 cmd = acquire_psp_cmd_buf(psp); 1022 1023 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1024 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1025 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1026 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1027 1028 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1029 1030 release_psp_cmd_buf(psp); 1031 1032 return ret; 1033 } 1034 1035 static int psp_rl_load(struct amdgpu_device *adev) 1036 { 1037 int ret; 1038 struct psp_context *psp = &adev->psp; 1039 struct psp_gfx_cmd_resp *cmd; 1040 1041 if (!is_psp_fw_valid(psp->rl)) 1042 return 0; 1043 1044 cmd = acquire_psp_cmd_buf(psp); 1045 1046 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1047 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1048 1049 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1050 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1051 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1052 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1053 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1054 1055 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1056 1057 release_psp_cmd_buf(psp); 1058 1059 return ret; 1060 } 1061 1062 int psp_memory_partition(struct psp_context *psp, int mode) 1063 { 1064 struct psp_gfx_cmd_resp *cmd; 1065 int ret; 1066 1067 if (amdgpu_sriov_vf(psp->adev)) 1068 return 0; 1069 1070 cmd = acquire_psp_cmd_buf(psp); 1071 1072 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1073 cmd->cmd.cmd_memory_part.mode = mode; 1074 1075 dev_info(psp->adev->dev, 1076 "Requesting %d memory partition change through PSP", mode); 1077 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1078 if (ret) 1079 dev_err(psp->adev->dev, 1080 "PSP request failed to change to NPS%d mode\n", mode); 1081 1082 release_psp_cmd_buf(psp); 1083 1084 return ret; 1085 } 1086 1087 int psp_spatial_partition(struct psp_context *psp, int mode) 1088 { 1089 struct psp_gfx_cmd_resp *cmd; 1090 int ret; 1091 1092 if (amdgpu_sriov_vf(psp->adev)) 1093 return 0; 1094 1095 cmd = acquire_psp_cmd_buf(psp); 1096 1097 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1098 cmd->cmd.cmd_spatial_part.mode = mode; 1099 1100 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1101 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1102 1103 release_psp_cmd_buf(psp); 1104 1105 return ret; 1106 } 1107 1108 static int psp_asd_initialize(struct psp_context *psp) 1109 { 1110 int ret; 1111 1112 /* If PSP version doesn't match ASD version, asd loading will be failed. 1113 * add workaround to bypass it for sriov now. 1114 * TODO: add version check to make it common 1115 */ 1116 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1117 return 0; 1118 1119 /* bypass asd if display hardware is not available */ 1120 if (!amdgpu_device_has_display_hardware(psp->adev) && 1121 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1122 return 0; 1123 1124 psp->asd_context.mem_context.shared_mc_addr = 0; 1125 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1126 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1127 1128 ret = psp_ta_load(psp, &psp->asd_context); 1129 if (!ret) 1130 psp->asd_context.initialized = true; 1131 1132 return ret; 1133 } 1134 1135 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1136 uint32_t session_id) 1137 { 1138 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1139 cmd->cmd.cmd_unload_ta.session_id = session_id; 1140 } 1141 1142 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1143 { 1144 int ret; 1145 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1146 1147 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1148 1149 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1150 1151 context->resp_status = cmd->resp.status; 1152 1153 release_psp_cmd_buf(psp); 1154 1155 return ret; 1156 } 1157 1158 static int psp_asd_terminate(struct psp_context *psp) 1159 { 1160 int ret; 1161 1162 if (amdgpu_sriov_vf(psp->adev)) 1163 return 0; 1164 1165 if (!psp->asd_context.initialized) 1166 return 0; 1167 1168 ret = psp_ta_unload(psp, &psp->asd_context); 1169 if (!ret) 1170 psp->asd_context.initialized = false; 1171 1172 return ret; 1173 } 1174 1175 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1176 uint32_t id, uint32_t value) 1177 { 1178 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1179 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1180 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1181 } 1182 1183 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1184 uint32_t value) 1185 { 1186 struct psp_gfx_cmd_resp *cmd; 1187 int ret = 0; 1188 1189 if (reg >= PSP_REG_LAST) 1190 return -EINVAL; 1191 1192 cmd = acquire_psp_cmd_buf(psp); 1193 1194 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1195 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1196 if (ret) 1197 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1198 1199 release_psp_cmd_buf(psp); 1200 1201 return ret; 1202 } 1203 1204 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1205 uint64_t ta_bin_mc, 1206 struct ta_context *context) 1207 { 1208 cmd->cmd_id = context->ta_load_type; 1209 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1210 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1211 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1212 1213 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1214 lower_32_bits(context->mem_context.shared_mc_addr); 1215 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1216 upper_32_bits(context->mem_context.shared_mc_addr); 1217 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1218 } 1219 1220 int psp_ta_init_shared_buf(struct psp_context *psp, 1221 struct ta_mem_context *mem_ctx) 1222 { 1223 /* 1224 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1225 * physical) for ta to host memory 1226 */ 1227 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1229 AMDGPU_GEM_DOMAIN_GTT, 1230 &mem_ctx->shared_bo, 1231 &mem_ctx->shared_mc_addr, 1232 &mem_ctx->shared_buf); 1233 } 1234 1235 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1236 uint32_t ta_cmd_id, 1237 uint32_t session_id) 1238 { 1239 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1240 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1241 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1242 } 1243 1244 int psp_ta_invoke(struct psp_context *psp, 1245 uint32_t ta_cmd_id, 1246 struct ta_context *context) 1247 { 1248 int ret; 1249 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1250 1251 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1252 1253 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1254 psp->fence_buf_mc_addr); 1255 1256 context->resp_status = cmd->resp.status; 1257 1258 release_psp_cmd_buf(psp); 1259 1260 return ret; 1261 } 1262 1263 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1264 { 1265 int ret; 1266 struct psp_gfx_cmd_resp *cmd; 1267 1268 cmd = acquire_psp_cmd_buf(psp); 1269 1270 psp_copy_fw(psp, context->bin_desc.start_addr, 1271 context->bin_desc.size_bytes); 1272 1273 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1274 1275 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1276 psp->fence_buf_mc_addr); 1277 1278 context->resp_status = cmd->resp.status; 1279 1280 if (!ret) 1281 context->session_id = cmd->resp.session_id; 1282 1283 release_psp_cmd_buf(psp); 1284 1285 return ret; 1286 } 1287 1288 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1289 { 1290 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1291 } 1292 1293 int psp_xgmi_terminate(struct psp_context *psp) 1294 { 1295 int ret; 1296 struct amdgpu_device *adev = psp->adev; 1297 1298 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1299 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1300 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1301 adev->gmc.xgmi.connected_to_cpu)) 1302 return 0; 1303 1304 if (!psp->xgmi_context.context.initialized) 1305 return 0; 1306 1307 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1308 1309 psp->xgmi_context.context.initialized = false; 1310 1311 return ret; 1312 } 1313 1314 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1315 { 1316 struct ta_xgmi_shared_memory *xgmi_cmd; 1317 int ret; 1318 1319 if (!psp->ta_fw || 1320 !psp->xgmi_context.context.bin_desc.size_bytes || 1321 !psp->xgmi_context.context.bin_desc.start_addr) 1322 return -ENOENT; 1323 1324 if (!load_ta) 1325 goto invoke; 1326 1327 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1328 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1329 1330 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1331 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1332 if (ret) 1333 return ret; 1334 } 1335 1336 /* Load XGMI TA */ 1337 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1338 if (!ret) 1339 psp->xgmi_context.context.initialized = true; 1340 else 1341 return ret; 1342 1343 invoke: 1344 /* Initialize XGMI session */ 1345 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1346 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1347 xgmi_cmd->flag_extend_link_record = set_extended_data; 1348 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1349 1350 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1351 /* note down the capbility flag for XGMI TA */ 1352 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1353 1354 return ret; 1355 } 1356 1357 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1358 { 1359 struct ta_xgmi_shared_memory *xgmi_cmd; 1360 int ret; 1361 1362 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1363 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1364 1365 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1366 1367 /* Invoke xgmi ta to get hive id */ 1368 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1369 if (ret) 1370 return ret; 1371 1372 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1373 1374 return 0; 1375 } 1376 1377 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1378 { 1379 struct ta_xgmi_shared_memory *xgmi_cmd; 1380 int ret; 1381 1382 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1383 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1384 1385 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1386 1387 /* Invoke xgmi ta to get the node id */ 1388 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1389 if (ret) 1390 return ret; 1391 1392 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1393 1394 return 0; 1395 } 1396 1397 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1398 { 1399 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1400 IP_VERSION(13, 0, 2) && 1401 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1402 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1403 IP_VERSION(13, 0, 6); 1404 } 1405 1406 /* 1407 * Chips that support extended topology information require the driver to 1408 * reflect topology information in the opposite direction. This is 1409 * because the TA has already exceeded its link record limit and if the 1410 * TA holds bi-directional information, the driver would have to do 1411 * multiple fetches instead of just two. 1412 */ 1413 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1414 struct psp_xgmi_node_info node_info) 1415 { 1416 struct amdgpu_device *mirror_adev; 1417 struct amdgpu_hive_info *hive; 1418 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1419 uint64_t dst_node_id = node_info.node_id; 1420 uint8_t dst_num_hops = node_info.num_hops; 1421 uint8_t dst_num_links = node_info.num_links; 1422 1423 hive = amdgpu_get_xgmi_hive(psp->adev); 1424 if (WARN_ON(!hive)) 1425 return; 1426 1427 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1428 struct psp_xgmi_topology_info *mirror_top_info; 1429 int j; 1430 1431 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1432 continue; 1433 1434 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1435 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1436 if (mirror_top_info->nodes[j].node_id != src_node_id) 1437 continue; 1438 1439 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1440 /* 1441 * prevent 0 num_links value re-reflection since reflection 1442 * criteria is based on num_hops (direct or indirect). 1443 * 1444 */ 1445 if (dst_num_links) 1446 mirror_top_info->nodes[j].num_links = dst_num_links; 1447 1448 break; 1449 } 1450 1451 break; 1452 } 1453 1454 amdgpu_put_xgmi_hive(hive); 1455 } 1456 1457 int psp_xgmi_get_topology_info(struct psp_context *psp, 1458 int number_devices, 1459 struct psp_xgmi_topology_info *topology, 1460 bool get_extended_data) 1461 { 1462 struct ta_xgmi_shared_memory *xgmi_cmd; 1463 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1464 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1465 int i; 1466 int ret; 1467 1468 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1469 return -EINVAL; 1470 1471 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1472 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1473 xgmi_cmd->flag_extend_link_record = get_extended_data; 1474 1475 /* Fill in the shared memory with topology information as input */ 1476 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1477 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1478 topology_info_input->num_nodes = number_devices; 1479 1480 for (i = 0; i < topology_info_input->num_nodes; i++) { 1481 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1482 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1483 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1484 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1485 } 1486 1487 /* Invoke xgmi ta to get the topology information */ 1488 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1489 if (ret) 1490 return ret; 1491 1492 /* Read the output topology information from the shared memory */ 1493 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1494 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1495 for (i = 0; i < topology->num_nodes; i++) { 1496 /* extended data will either be 0 or equal to non-extended data */ 1497 if (topology_info_output->nodes[i].num_hops) 1498 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1499 1500 /* non-extended data gets everything here so no need to update */ 1501 if (!get_extended_data) { 1502 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1503 topology->nodes[i].is_sharing_enabled = 1504 topology_info_output->nodes[i].is_sharing_enabled; 1505 topology->nodes[i].sdma_engine = 1506 topology_info_output->nodes[i].sdma_engine; 1507 } 1508 1509 } 1510 1511 /* Invoke xgmi ta again to get the link information */ 1512 if (psp_xgmi_peer_link_info_supported(psp)) { 1513 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1514 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1515 bool requires_reflection = 1516 (psp->xgmi_context.supports_extended_data && 1517 get_extended_data) || 1518 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1519 IP_VERSION(13, 0, 6) || 1520 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1521 IP_VERSION(13, 0, 14); 1522 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1523 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1524 1525 /* popluate the shared output buffer rather than the cmd input buffer 1526 * with node_ids as the input for GET_PEER_LINKS command execution. 1527 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1528 * The same requirement for GET_EXTEND_PEER_LINKS command. 1529 */ 1530 if (ta_port_num_support) { 1531 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1532 1533 for (i = 0; i < topology->num_nodes; i++) 1534 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1535 1536 link_extend_info_output->num_nodes = topology->num_nodes; 1537 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1538 } else { 1539 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1540 1541 for (i = 0; i < topology->num_nodes; i++) 1542 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1543 1544 link_info_output->num_nodes = topology->num_nodes; 1545 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1546 } 1547 1548 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1549 if (ret) 1550 return ret; 1551 1552 for (i = 0; i < topology->num_nodes; i++) { 1553 uint8_t node_num_links = ta_port_num_support ? 1554 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1555 /* accumulate num_links on extended data */ 1556 if (get_extended_data) { 1557 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1558 } else { 1559 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1560 topology->nodes[i].num_links : node_num_links; 1561 } 1562 /* popluate the connected port num info if supported and available */ 1563 if (ta_port_num_support && topology->nodes[i].num_links) { 1564 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1565 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1566 } 1567 1568 /* reflect the topology information for bi-directionality */ 1569 if (requires_reflection && topology->nodes[i].num_hops) 1570 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1571 } 1572 } 1573 1574 return 0; 1575 } 1576 1577 int psp_xgmi_set_topology_info(struct psp_context *psp, 1578 int number_devices, 1579 struct psp_xgmi_topology_info *topology) 1580 { 1581 struct ta_xgmi_shared_memory *xgmi_cmd; 1582 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1583 int i; 1584 1585 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1586 return -EINVAL; 1587 1588 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1589 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1590 1591 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1592 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1593 topology_info_input->num_nodes = number_devices; 1594 1595 for (i = 0; i < topology_info_input->num_nodes; i++) { 1596 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1597 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1598 topology_info_input->nodes[i].is_sharing_enabled = 1; 1599 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1600 } 1601 1602 /* Invoke xgmi ta to set topology information */ 1603 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1604 } 1605 1606 // ras begin 1607 static void psp_ras_ta_check_status(struct psp_context *psp) 1608 { 1609 struct ta_ras_shared_memory *ras_cmd = 1610 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1611 1612 switch (ras_cmd->ras_status) { 1613 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1614 dev_warn(psp->adev->dev, 1615 "RAS WARNING: cmd failed due to unsupported ip\n"); 1616 break; 1617 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1618 dev_warn(psp->adev->dev, 1619 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1620 break; 1621 case TA_RAS_STATUS__SUCCESS: 1622 break; 1623 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1624 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1625 dev_warn(psp->adev->dev, 1626 "RAS WARNING: Inject error to critical region is not allowed\n"); 1627 break; 1628 default: 1629 dev_warn(psp->adev->dev, 1630 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1631 break; 1632 } 1633 } 1634 1635 static int psp_ras_send_cmd(struct psp_context *psp, 1636 enum ras_command cmd_id, void *in, void *out) 1637 { 1638 struct ta_ras_shared_memory *ras_cmd; 1639 uint32_t cmd = cmd_id; 1640 int ret = 0; 1641 1642 if (!in) 1643 return -EINVAL; 1644 1645 mutex_lock(&psp->ras_context.mutex); 1646 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1647 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1648 1649 switch (cmd) { 1650 case TA_RAS_COMMAND__ENABLE_FEATURES: 1651 case TA_RAS_COMMAND__DISABLE_FEATURES: 1652 memcpy(&ras_cmd->ras_in_message, 1653 in, sizeof(ras_cmd->ras_in_message)); 1654 break; 1655 case TA_RAS_COMMAND__TRIGGER_ERROR: 1656 memcpy(&ras_cmd->ras_in_message.trigger_error, 1657 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 1658 break; 1659 case TA_RAS_COMMAND__QUERY_ADDRESS: 1660 memcpy(&ras_cmd->ras_in_message.address, 1661 in, sizeof(ras_cmd->ras_in_message.address)); 1662 break; 1663 default: 1664 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 1665 ret = -EINVAL; 1666 goto err_out; 1667 } 1668 1669 ras_cmd->cmd_id = cmd; 1670 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1671 1672 switch (cmd) { 1673 case TA_RAS_COMMAND__TRIGGER_ERROR: 1674 if (!ret && out) 1675 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 1676 break; 1677 case TA_RAS_COMMAND__QUERY_ADDRESS: 1678 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1679 ret = -EINVAL; 1680 else if (out) 1681 memcpy(out, 1682 &ras_cmd->ras_out_message.address, 1683 sizeof(ras_cmd->ras_out_message.address)); 1684 break; 1685 default: 1686 break; 1687 } 1688 1689 err_out: 1690 mutex_unlock(&psp->ras_context.mutex); 1691 1692 return ret; 1693 } 1694 1695 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1696 { 1697 struct ta_ras_shared_memory *ras_cmd; 1698 int ret; 1699 1700 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1701 1702 /* 1703 * TODO: bypass the loading in sriov for now 1704 */ 1705 if (amdgpu_sriov_vf(psp->adev)) 1706 return 0; 1707 1708 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1709 1710 if (amdgpu_ras_intr_triggered()) 1711 return ret; 1712 1713 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1714 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1715 return -EINVAL; 1716 } 1717 1718 if (!ret) { 1719 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1720 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1721 1722 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1723 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1724 dev_warn(psp->adev->dev, 1725 "RAS internal register access blocked\n"); 1726 1727 psp_ras_ta_check_status(psp); 1728 } 1729 1730 return ret; 1731 } 1732 1733 int psp_ras_enable_features(struct psp_context *psp, 1734 union ta_ras_cmd_input *info, bool enable) 1735 { 1736 enum ras_command cmd_id; 1737 int ret; 1738 1739 if (!psp->ras_context.context.initialized || !info) 1740 return -EINVAL; 1741 1742 cmd_id = enable ? 1743 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 1744 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 1745 if (ret) 1746 return -EINVAL; 1747 1748 return 0; 1749 } 1750 1751 int psp_ras_terminate(struct psp_context *psp) 1752 { 1753 int ret; 1754 1755 /* 1756 * TODO: bypass the terminate in sriov for now 1757 */ 1758 if (amdgpu_sriov_vf(psp->adev)) 1759 return 0; 1760 1761 if (!psp->ras_context.context.initialized) 1762 return 0; 1763 1764 ret = psp_ta_unload(psp, &psp->ras_context.context); 1765 1766 psp->ras_context.context.initialized = false; 1767 1768 mutex_destroy(&psp->ras_context.mutex); 1769 1770 return ret; 1771 } 1772 1773 int psp_ras_initialize(struct psp_context *psp) 1774 { 1775 int ret; 1776 uint32_t boot_cfg = 0xFF; 1777 struct amdgpu_device *adev = psp->adev; 1778 struct ta_ras_shared_memory *ras_cmd; 1779 1780 /* 1781 * TODO: bypass the initialize in sriov for now 1782 */ 1783 if (amdgpu_sriov_vf(adev)) 1784 return 0; 1785 1786 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1787 !adev->psp.ras_context.context.bin_desc.start_addr) { 1788 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1789 return 0; 1790 } 1791 1792 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1793 /* query GECC enablement status from boot config 1794 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1795 */ 1796 ret = psp_boot_config_get(adev, &boot_cfg); 1797 if (ret) 1798 dev_warn(adev->dev, "PSP get boot config failed\n"); 1799 1800 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 1801 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1802 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 1803 dev_warn(adev->dev, 1804 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 1805 } else { 1806 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 1807 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1808 if (boot_cfg == 1) { 1809 dev_info(adev->dev, "GECC is enabled\n"); 1810 } else { 1811 /* enable GECC in next boot cycle if it is disabled 1812 * in boot config, or force enable GECC if failed to 1813 * get boot configuration 1814 */ 1815 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1816 if (ret) 1817 dev_warn(adev->dev, "PSP set boot config failed\n"); 1818 else 1819 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1820 } 1821 } else { 1822 if (!boot_cfg) { 1823 if (!adev->ras_default_ecc_enabled && 1824 amdgpu_ras_enable != 1 && 1825 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1826 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 1827 else 1828 dev_info(adev->dev, "GECC is disabled\n"); 1829 } else { 1830 /* disable GECC in next boot cycle if ras is 1831 * disabled by module parameter amdgpu_ras_enable 1832 * and/or amdgpu_ras_mask, or boot_config_get call 1833 * is failed 1834 */ 1835 ret = psp_boot_config_set(adev, 0); 1836 if (ret) 1837 dev_warn(adev->dev, "PSP set boot config failed\n"); 1838 else 1839 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1840 } 1841 } 1842 } 1843 } 1844 1845 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1846 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1847 1848 if (!psp->ras_context.context.mem_context.shared_buf) { 1849 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1850 if (ret) 1851 return ret; 1852 } 1853 1854 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1855 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1856 1857 if (amdgpu_ras_is_poison_mode_supported(adev)) 1858 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1859 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1860 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1861 ras_cmd->ras_in_message.init_flags.xcc_mask = 1862 adev->gfx.xcc_mask; 1863 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1864 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 1865 ras_cmd->ras_in_message.init_flags.nps_mode = 1866 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1867 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 1868 1869 ret = psp_ta_load(psp, &psp->ras_context.context); 1870 1871 if (!ret && !ras_cmd->ras_status) { 1872 psp->ras_context.context.initialized = true; 1873 mutex_init(&psp->ras_context.mutex); 1874 } else { 1875 if (ras_cmd->ras_status) 1876 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1877 1878 /* fail to load RAS TA */ 1879 psp->ras_context.context.initialized = false; 1880 } 1881 1882 return ret; 1883 } 1884 1885 int psp_ras_trigger_error(struct psp_context *psp, 1886 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1887 { 1888 struct amdgpu_device *adev = psp->adev; 1889 int ret; 1890 uint32_t dev_mask; 1891 uint32_t ras_status = 0; 1892 1893 if (!psp->ras_context.context.initialized || !info) 1894 return -EINVAL; 1895 1896 switch (info->block_id) { 1897 case TA_RAS_BLOCK__GFX: 1898 dev_mask = GET_MASK(GC, instance_mask); 1899 break; 1900 case TA_RAS_BLOCK__SDMA: 1901 dev_mask = GET_MASK(SDMA0, instance_mask); 1902 break; 1903 case TA_RAS_BLOCK__VCN: 1904 case TA_RAS_BLOCK__JPEG: 1905 dev_mask = GET_MASK(VCN, instance_mask); 1906 break; 1907 default: 1908 dev_mask = instance_mask; 1909 break; 1910 } 1911 1912 /* reuse sub_block_index for backward compatibility */ 1913 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1914 dev_mask &= AMDGPU_RAS_INST_MASK; 1915 info->sub_block_index |= dev_mask; 1916 1917 ret = psp_ras_send_cmd(psp, 1918 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 1919 if (ret) 1920 return -EINVAL; 1921 1922 /* If err_event_athub occurs error inject was successful, however 1923 * return status from TA is no long reliable 1924 */ 1925 if (amdgpu_ras_intr_triggered()) 1926 return 0; 1927 1928 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1929 return -EACCES; 1930 else if (ras_status) 1931 return -EINVAL; 1932 1933 return 0; 1934 } 1935 1936 int psp_ras_query_address(struct psp_context *psp, 1937 struct ta_ras_query_address_input *addr_in, 1938 struct ta_ras_query_address_output *addr_out) 1939 { 1940 int ret; 1941 1942 if (!psp->ras_context.context.initialized || 1943 !addr_in || !addr_out) 1944 return -EINVAL; 1945 1946 ret = psp_ras_send_cmd(psp, 1947 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 1948 1949 return ret; 1950 } 1951 // ras end 1952 1953 // HDCP start 1954 static int psp_hdcp_initialize(struct psp_context *psp) 1955 { 1956 int ret; 1957 1958 /* 1959 * TODO: bypass the initialize in sriov for now 1960 */ 1961 if (amdgpu_sriov_vf(psp->adev)) 1962 return 0; 1963 1964 /* bypass hdcp initialization if dmu is harvested */ 1965 if (!amdgpu_device_has_display_hardware(psp->adev)) 1966 return 0; 1967 1968 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1969 !psp->hdcp_context.context.bin_desc.start_addr) { 1970 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1971 return 0; 1972 } 1973 1974 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1975 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1976 1977 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1978 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1979 if (ret) 1980 return ret; 1981 } 1982 1983 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1984 if (!ret) { 1985 psp->hdcp_context.context.initialized = true; 1986 mutex_init(&psp->hdcp_context.mutex); 1987 } 1988 1989 return ret; 1990 } 1991 1992 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1993 { 1994 /* 1995 * TODO: bypass the loading in sriov for now 1996 */ 1997 if (amdgpu_sriov_vf(psp->adev)) 1998 return 0; 1999 2000 if (!psp->hdcp_context.context.initialized) 2001 return 0; 2002 2003 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2004 } 2005 2006 static int psp_hdcp_terminate(struct psp_context *psp) 2007 { 2008 int ret; 2009 2010 /* 2011 * TODO: bypass the terminate in sriov for now 2012 */ 2013 if (amdgpu_sriov_vf(psp->adev)) 2014 return 0; 2015 2016 if (!psp->hdcp_context.context.initialized) 2017 return 0; 2018 2019 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2020 2021 psp->hdcp_context.context.initialized = false; 2022 2023 return ret; 2024 } 2025 // HDCP end 2026 2027 // DTM start 2028 static int psp_dtm_initialize(struct psp_context *psp) 2029 { 2030 int ret; 2031 2032 /* 2033 * TODO: bypass the initialize in sriov for now 2034 */ 2035 if (amdgpu_sriov_vf(psp->adev)) 2036 return 0; 2037 2038 /* bypass dtm initialization if dmu is harvested */ 2039 if (!amdgpu_device_has_display_hardware(psp->adev)) 2040 return 0; 2041 2042 if (!psp->dtm_context.context.bin_desc.size_bytes || 2043 !psp->dtm_context.context.bin_desc.start_addr) { 2044 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2045 return 0; 2046 } 2047 2048 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2049 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2050 2051 if (!psp->dtm_context.context.mem_context.shared_buf) { 2052 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2053 if (ret) 2054 return ret; 2055 } 2056 2057 ret = psp_ta_load(psp, &psp->dtm_context.context); 2058 if (!ret) { 2059 psp->dtm_context.context.initialized = true; 2060 mutex_init(&psp->dtm_context.mutex); 2061 } 2062 2063 return ret; 2064 } 2065 2066 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2067 { 2068 /* 2069 * TODO: bypass the loading in sriov for now 2070 */ 2071 if (amdgpu_sriov_vf(psp->adev)) 2072 return 0; 2073 2074 if (!psp->dtm_context.context.initialized) 2075 return 0; 2076 2077 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2078 } 2079 2080 static int psp_dtm_terminate(struct psp_context *psp) 2081 { 2082 int ret; 2083 2084 /* 2085 * TODO: bypass the terminate in sriov for now 2086 */ 2087 if (amdgpu_sriov_vf(psp->adev)) 2088 return 0; 2089 2090 if (!psp->dtm_context.context.initialized) 2091 return 0; 2092 2093 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2094 2095 psp->dtm_context.context.initialized = false; 2096 2097 return ret; 2098 } 2099 // DTM end 2100 2101 // RAP start 2102 static int psp_rap_initialize(struct psp_context *psp) 2103 { 2104 int ret; 2105 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2106 2107 /* 2108 * TODO: bypass the initialize in sriov for now 2109 */ 2110 if (amdgpu_sriov_vf(psp->adev)) 2111 return 0; 2112 2113 if (!psp->rap_context.context.bin_desc.size_bytes || 2114 !psp->rap_context.context.bin_desc.start_addr) { 2115 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2116 return 0; 2117 } 2118 2119 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2120 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2121 2122 if (!psp->rap_context.context.mem_context.shared_buf) { 2123 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2124 if (ret) 2125 return ret; 2126 } 2127 2128 ret = psp_ta_load(psp, &psp->rap_context.context); 2129 if (!ret) { 2130 psp->rap_context.context.initialized = true; 2131 mutex_init(&psp->rap_context.mutex); 2132 } else 2133 return ret; 2134 2135 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2136 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2137 psp_rap_terminate(psp); 2138 /* free rap shared memory */ 2139 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2140 2141 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2142 ret, status); 2143 2144 return ret; 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int psp_rap_terminate(struct psp_context *psp) 2151 { 2152 int ret; 2153 2154 if (!psp->rap_context.context.initialized) 2155 return 0; 2156 2157 ret = psp_ta_unload(psp, &psp->rap_context.context); 2158 2159 psp->rap_context.context.initialized = false; 2160 2161 return ret; 2162 } 2163 2164 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2165 { 2166 struct ta_rap_shared_memory *rap_cmd; 2167 int ret = 0; 2168 2169 if (!psp->rap_context.context.initialized) 2170 return 0; 2171 2172 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2173 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2174 return -EINVAL; 2175 2176 mutex_lock(&psp->rap_context.mutex); 2177 2178 rap_cmd = (struct ta_rap_shared_memory *) 2179 psp->rap_context.context.mem_context.shared_buf; 2180 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2181 2182 rap_cmd->cmd_id = ta_cmd_id; 2183 rap_cmd->validation_method_id = METHOD_A; 2184 2185 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2186 if (ret) 2187 goto out_unlock; 2188 2189 if (status) 2190 *status = rap_cmd->rap_status; 2191 2192 out_unlock: 2193 mutex_unlock(&psp->rap_context.mutex); 2194 2195 return ret; 2196 } 2197 // RAP end 2198 2199 /* securedisplay start */ 2200 static int psp_securedisplay_initialize(struct psp_context *psp) 2201 { 2202 int ret; 2203 struct ta_securedisplay_cmd *securedisplay_cmd; 2204 2205 /* 2206 * TODO: bypass the initialize in sriov for now 2207 */ 2208 if (amdgpu_sriov_vf(psp->adev)) 2209 return 0; 2210 2211 /* bypass securedisplay initialization if dmu is harvested */ 2212 if (!amdgpu_device_has_display_hardware(psp->adev)) 2213 return 0; 2214 2215 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2216 !psp->securedisplay_context.context.bin_desc.start_addr) { 2217 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2218 return 0; 2219 } 2220 2221 psp->securedisplay_context.context.mem_context.shared_mem_size = 2222 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2223 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2224 2225 if (!psp->securedisplay_context.context.initialized) { 2226 ret = psp_ta_init_shared_buf(psp, 2227 &psp->securedisplay_context.context.mem_context); 2228 if (ret) 2229 return ret; 2230 } 2231 2232 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2233 if (!ret) { 2234 psp->securedisplay_context.context.initialized = true; 2235 mutex_init(&psp->securedisplay_context.mutex); 2236 } else 2237 return ret; 2238 2239 mutex_lock(&psp->securedisplay_context.mutex); 2240 2241 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2242 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2243 2244 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2245 2246 mutex_unlock(&psp->securedisplay_context.mutex); 2247 2248 if (ret) { 2249 psp_securedisplay_terminate(psp); 2250 /* free securedisplay shared memory */ 2251 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2252 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2253 return -EINVAL; 2254 } 2255 2256 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2257 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2258 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2259 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2260 /* don't try again */ 2261 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2262 } 2263 2264 return 0; 2265 } 2266 2267 static int psp_securedisplay_terminate(struct psp_context *psp) 2268 { 2269 int ret; 2270 2271 /* 2272 * TODO:bypass the terminate in sriov for now 2273 */ 2274 if (amdgpu_sriov_vf(psp->adev)) 2275 return 0; 2276 2277 if (!psp->securedisplay_context.context.initialized) 2278 return 0; 2279 2280 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2281 2282 psp->securedisplay_context.context.initialized = false; 2283 2284 return ret; 2285 } 2286 2287 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2288 { 2289 int ret; 2290 2291 if (!psp->securedisplay_context.context.initialized) 2292 return -EINVAL; 2293 2294 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2295 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2296 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2297 return -EINVAL; 2298 2299 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2300 2301 return ret; 2302 } 2303 /* SECUREDISPLAY end */ 2304 2305 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2306 { 2307 struct psp_context *psp = &adev->psp; 2308 int ret = 0; 2309 2310 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2311 ret = psp->funcs->wait_for_bootloader(psp); 2312 2313 return ret; 2314 } 2315 2316 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2317 { 2318 if (psp->funcs && 2319 psp->funcs->get_ras_capability) { 2320 return psp->funcs->get_ras_capability(psp); 2321 } else { 2322 return false; 2323 } 2324 } 2325 2326 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2327 { 2328 struct psp_context *psp = &adev->psp; 2329 2330 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2331 return false; 2332 2333 if (psp->funcs && psp->funcs->is_reload_needed) 2334 return psp->funcs->is_reload_needed(psp); 2335 2336 return false; 2337 } 2338 2339 static int psp_hw_start(struct psp_context *psp) 2340 { 2341 struct amdgpu_device *adev = psp->adev; 2342 int ret; 2343 2344 if (!amdgpu_sriov_vf(adev)) { 2345 if ((is_psp_fw_valid(psp->kdb)) && 2346 (psp->funcs->bootloader_load_kdb != NULL)) { 2347 ret = psp_bootloader_load_kdb(psp); 2348 if (ret) { 2349 dev_err(adev->dev, "PSP load kdb failed!\n"); 2350 return ret; 2351 } 2352 } 2353 2354 if ((is_psp_fw_valid(psp->spl)) && 2355 (psp->funcs->bootloader_load_spl != NULL)) { 2356 ret = psp_bootloader_load_spl(psp); 2357 if (ret) { 2358 dev_err(adev->dev, "PSP load spl failed!\n"); 2359 return ret; 2360 } 2361 } 2362 2363 if ((is_psp_fw_valid(psp->sys)) && 2364 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2365 ret = psp_bootloader_load_sysdrv(psp); 2366 if (ret) { 2367 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2368 return ret; 2369 } 2370 } 2371 2372 if ((is_psp_fw_valid(psp->soc_drv)) && 2373 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2374 ret = psp_bootloader_load_soc_drv(psp); 2375 if (ret) { 2376 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2377 return ret; 2378 } 2379 } 2380 2381 if ((is_psp_fw_valid(psp->intf_drv)) && 2382 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2383 ret = psp_bootloader_load_intf_drv(psp); 2384 if (ret) { 2385 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2386 return ret; 2387 } 2388 } 2389 2390 if ((is_psp_fw_valid(psp->dbg_drv)) && 2391 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2392 ret = psp_bootloader_load_dbg_drv(psp); 2393 if (ret) { 2394 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2395 return ret; 2396 } 2397 } 2398 2399 if ((is_psp_fw_valid(psp->ras_drv)) && 2400 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2401 ret = psp_bootloader_load_ras_drv(psp); 2402 if (ret) { 2403 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2404 return ret; 2405 } 2406 } 2407 2408 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2409 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2410 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2411 if (ret) { 2412 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2413 return ret; 2414 } 2415 } 2416 2417 if ((is_psp_fw_valid(psp->spdm_drv)) && 2418 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2419 ret = psp_bootloader_load_spdm_drv(psp); 2420 if (ret) { 2421 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2422 return ret; 2423 } 2424 } 2425 2426 if ((is_psp_fw_valid(psp->sos)) && 2427 (psp->funcs->bootloader_load_sos != NULL)) { 2428 ret = psp_bootloader_load_sos(psp); 2429 if (ret) { 2430 dev_err(adev->dev, "PSP load sos failed!\n"); 2431 return ret; 2432 } 2433 } 2434 } 2435 2436 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2437 if (ret) { 2438 dev_err(adev->dev, "PSP create ring failed!\n"); 2439 return ret; 2440 } 2441 2442 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2443 goto skip_pin_bo; 2444 2445 if (!psp->boot_time_tmr || psp->autoload_supported) { 2446 ret = psp_tmr_init(psp); 2447 if (ret) { 2448 dev_err(adev->dev, "PSP tmr init failed!\n"); 2449 return ret; 2450 } 2451 } 2452 2453 skip_pin_bo: 2454 /* 2455 * For ASICs with DF Cstate management centralized 2456 * to PMFW, TMR setup should be performed after PMFW 2457 * loaded and before other non-psp firmware loaded. 2458 */ 2459 if (psp->pmfw_centralized_cstate_management) { 2460 ret = psp_load_smu_fw(psp); 2461 if (ret) 2462 return ret; 2463 } 2464 2465 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2466 ret = psp_tmr_load(psp); 2467 if (ret) { 2468 dev_err(adev->dev, "PSP load tmr failed!\n"); 2469 return ret; 2470 } 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2477 enum psp_gfx_fw_type *type) 2478 { 2479 switch (ucode->ucode_id) { 2480 case AMDGPU_UCODE_ID_CAP: 2481 *type = GFX_FW_TYPE_CAP; 2482 break; 2483 case AMDGPU_UCODE_ID_SDMA0: 2484 *type = GFX_FW_TYPE_SDMA0; 2485 break; 2486 case AMDGPU_UCODE_ID_SDMA1: 2487 *type = GFX_FW_TYPE_SDMA1; 2488 break; 2489 case AMDGPU_UCODE_ID_SDMA2: 2490 *type = GFX_FW_TYPE_SDMA2; 2491 break; 2492 case AMDGPU_UCODE_ID_SDMA3: 2493 *type = GFX_FW_TYPE_SDMA3; 2494 break; 2495 case AMDGPU_UCODE_ID_SDMA4: 2496 *type = GFX_FW_TYPE_SDMA4; 2497 break; 2498 case AMDGPU_UCODE_ID_SDMA5: 2499 *type = GFX_FW_TYPE_SDMA5; 2500 break; 2501 case AMDGPU_UCODE_ID_SDMA6: 2502 *type = GFX_FW_TYPE_SDMA6; 2503 break; 2504 case AMDGPU_UCODE_ID_SDMA7: 2505 *type = GFX_FW_TYPE_SDMA7; 2506 break; 2507 case AMDGPU_UCODE_ID_CP_MES: 2508 *type = GFX_FW_TYPE_CP_MES; 2509 break; 2510 case AMDGPU_UCODE_ID_CP_MES_DATA: 2511 *type = GFX_FW_TYPE_MES_STACK; 2512 break; 2513 case AMDGPU_UCODE_ID_CP_MES1: 2514 *type = GFX_FW_TYPE_CP_MES_KIQ; 2515 break; 2516 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2517 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2518 break; 2519 case AMDGPU_UCODE_ID_CP_CE: 2520 *type = GFX_FW_TYPE_CP_CE; 2521 break; 2522 case AMDGPU_UCODE_ID_CP_PFP: 2523 *type = GFX_FW_TYPE_CP_PFP; 2524 break; 2525 case AMDGPU_UCODE_ID_CP_ME: 2526 *type = GFX_FW_TYPE_CP_ME; 2527 break; 2528 case AMDGPU_UCODE_ID_CP_MEC1: 2529 *type = GFX_FW_TYPE_CP_MEC; 2530 break; 2531 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2532 *type = GFX_FW_TYPE_CP_MEC_ME1; 2533 break; 2534 case AMDGPU_UCODE_ID_CP_MEC2: 2535 *type = GFX_FW_TYPE_CP_MEC; 2536 break; 2537 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2538 *type = GFX_FW_TYPE_CP_MEC_ME2; 2539 break; 2540 case AMDGPU_UCODE_ID_RLC_P: 2541 *type = GFX_FW_TYPE_RLC_P; 2542 break; 2543 case AMDGPU_UCODE_ID_RLC_V: 2544 *type = GFX_FW_TYPE_RLC_V; 2545 break; 2546 case AMDGPU_UCODE_ID_RLC_G: 2547 *type = GFX_FW_TYPE_RLC_G; 2548 break; 2549 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2550 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2551 break; 2552 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2553 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2554 break; 2555 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2556 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2557 break; 2558 case AMDGPU_UCODE_ID_RLC_IRAM: 2559 *type = GFX_FW_TYPE_RLC_IRAM; 2560 break; 2561 case AMDGPU_UCODE_ID_RLC_DRAM: 2562 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2563 break; 2564 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2565 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2566 break; 2567 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2568 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2569 break; 2570 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2571 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2572 break; 2573 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2574 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2575 break; 2576 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2577 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2578 break; 2579 case AMDGPU_UCODE_ID_SMC: 2580 *type = GFX_FW_TYPE_SMU; 2581 break; 2582 case AMDGPU_UCODE_ID_PPTABLE: 2583 *type = GFX_FW_TYPE_PPTABLE; 2584 break; 2585 case AMDGPU_UCODE_ID_UVD: 2586 *type = GFX_FW_TYPE_UVD; 2587 break; 2588 case AMDGPU_UCODE_ID_UVD1: 2589 *type = GFX_FW_TYPE_UVD1; 2590 break; 2591 case AMDGPU_UCODE_ID_VCE: 2592 *type = GFX_FW_TYPE_VCE; 2593 break; 2594 case AMDGPU_UCODE_ID_VCN: 2595 *type = GFX_FW_TYPE_VCN; 2596 break; 2597 case AMDGPU_UCODE_ID_VCN1: 2598 *type = GFX_FW_TYPE_VCN1; 2599 break; 2600 case AMDGPU_UCODE_ID_DMCU_ERAM: 2601 *type = GFX_FW_TYPE_DMCU_ERAM; 2602 break; 2603 case AMDGPU_UCODE_ID_DMCU_INTV: 2604 *type = GFX_FW_TYPE_DMCU_ISR; 2605 break; 2606 case AMDGPU_UCODE_ID_VCN0_RAM: 2607 *type = GFX_FW_TYPE_VCN0_RAM; 2608 break; 2609 case AMDGPU_UCODE_ID_VCN1_RAM: 2610 *type = GFX_FW_TYPE_VCN1_RAM; 2611 break; 2612 case AMDGPU_UCODE_ID_DMCUB: 2613 *type = GFX_FW_TYPE_DMUB; 2614 break; 2615 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2616 case AMDGPU_UCODE_ID_SDMA_RS64: 2617 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2618 break; 2619 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2620 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2621 break; 2622 case AMDGPU_UCODE_ID_IMU_I: 2623 *type = GFX_FW_TYPE_IMU_I; 2624 break; 2625 case AMDGPU_UCODE_ID_IMU_D: 2626 *type = GFX_FW_TYPE_IMU_D; 2627 break; 2628 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2629 *type = GFX_FW_TYPE_RS64_PFP; 2630 break; 2631 case AMDGPU_UCODE_ID_CP_RS64_ME: 2632 *type = GFX_FW_TYPE_RS64_ME; 2633 break; 2634 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2635 *type = GFX_FW_TYPE_RS64_MEC; 2636 break; 2637 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2638 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2639 break; 2640 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2641 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2642 break; 2643 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2644 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2645 break; 2646 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2647 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2648 break; 2649 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2650 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2651 break; 2652 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2653 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2654 break; 2655 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2656 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2657 break; 2658 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2659 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2660 break; 2661 case AMDGPU_UCODE_ID_VPE_CTX: 2662 *type = GFX_FW_TYPE_VPEC_FW1; 2663 break; 2664 case AMDGPU_UCODE_ID_VPE_CTL: 2665 *type = GFX_FW_TYPE_VPEC_FW2; 2666 break; 2667 case AMDGPU_UCODE_ID_VPE: 2668 *type = GFX_FW_TYPE_VPE; 2669 break; 2670 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2671 *type = GFX_FW_TYPE_UMSCH_UCODE; 2672 break; 2673 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2674 *type = GFX_FW_TYPE_UMSCH_DATA; 2675 break; 2676 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2677 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2678 break; 2679 case AMDGPU_UCODE_ID_P2S_TABLE: 2680 *type = GFX_FW_TYPE_P2S_TABLE; 2681 break; 2682 case AMDGPU_UCODE_ID_JPEG_RAM: 2683 *type = GFX_FW_TYPE_JPEG_RAM; 2684 break; 2685 case AMDGPU_UCODE_ID_ISP: 2686 *type = GFX_FW_TYPE_ISP; 2687 break; 2688 case AMDGPU_UCODE_ID_MAXIMUM: 2689 default: 2690 return -EINVAL; 2691 } 2692 2693 return 0; 2694 } 2695 2696 static void psp_print_fw_hdr(struct psp_context *psp, 2697 struct amdgpu_firmware_info *ucode) 2698 { 2699 struct amdgpu_device *adev = psp->adev; 2700 struct common_firmware_header *hdr; 2701 2702 switch (ucode->ucode_id) { 2703 case AMDGPU_UCODE_ID_SDMA0: 2704 case AMDGPU_UCODE_ID_SDMA1: 2705 case AMDGPU_UCODE_ID_SDMA2: 2706 case AMDGPU_UCODE_ID_SDMA3: 2707 case AMDGPU_UCODE_ID_SDMA4: 2708 case AMDGPU_UCODE_ID_SDMA5: 2709 case AMDGPU_UCODE_ID_SDMA6: 2710 case AMDGPU_UCODE_ID_SDMA7: 2711 hdr = (struct common_firmware_header *) 2712 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2713 amdgpu_ucode_print_sdma_hdr(hdr); 2714 break; 2715 case AMDGPU_UCODE_ID_CP_CE: 2716 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2717 amdgpu_ucode_print_gfx_hdr(hdr); 2718 break; 2719 case AMDGPU_UCODE_ID_CP_PFP: 2720 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2721 amdgpu_ucode_print_gfx_hdr(hdr); 2722 break; 2723 case AMDGPU_UCODE_ID_CP_ME: 2724 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2725 amdgpu_ucode_print_gfx_hdr(hdr); 2726 break; 2727 case AMDGPU_UCODE_ID_CP_MEC1: 2728 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2729 amdgpu_ucode_print_gfx_hdr(hdr); 2730 break; 2731 case AMDGPU_UCODE_ID_RLC_G: 2732 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2733 amdgpu_ucode_print_rlc_hdr(hdr); 2734 break; 2735 case AMDGPU_UCODE_ID_SMC: 2736 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2737 amdgpu_ucode_print_smc_hdr(hdr); 2738 break; 2739 default: 2740 break; 2741 } 2742 } 2743 2744 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2745 struct amdgpu_firmware_info *ucode, 2746 struct psp_gfx_cmd_resp *cmd) 2747 { 2748 int ret; 2749 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2750 2751 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2752 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2753 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2754 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2755 2756 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2757 if (ret) 2758 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2759 2760 return ret; 2761 } 2762 2763 int psp_execute_ip_fw_load(struct psp_context *psp, 2764 struct amdgpu_firmware_info *ucode) 2765 { 2766 int ret = 0; 2767 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2768 2769 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2770 if (!ret) { 2771 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2772 psp->fence_buf_mc_addr); 2773 } 2774 2775 release_psp_cmd_buf(psp); 2776 2777 return ret; 2778 } 2779 2780 static int psp_load_p2s_table(struct psp_context *psp) 2781 { 2782 int ret; 2783 struct amdgpu_device *adev = psp->adev; 2784 struct amdgpu_firmware_info *ucode = 2785 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2786 2787 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2788 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2789 return 0; 2790 2791 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2792 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2793 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2794 0x0036003C; 2795 if (psp->sos.fw_version < supp_vers) 2796 return 0; 2797 } 2798 2799 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2800 return 0; 2801 2802 ret = psp_execute_ip_fw_load(psp, ucode); 2803 2804 return ret; 2805 } 2806 2807 static int psp_load_smu_fw(struct psp_context *psp) 2808 { 2809 int ret; 2810 struct amdgpu_device *adev = psp->adev; 2811 struct amdgpu_firmware_info *ucode = 2812 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2813 struct amdgpu_ras *ras = psp->ras_context.ras; 2814 2815 /* 2816 * Skip SMU FW reloading in case of using BACO for runpm only, 2817 * as SMU is always alive. 2818 */ 2819 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2820 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2821 return 0; 2822 2823 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2824 return 0; 2825 2826 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2827 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2828 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2829 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2830 if (ret) 2831 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2832 } 2833 2834 ret = psp_execute_ip_fw_load(psp, ucode); 2835 2836 if (ret) 2837 dev_err(adev->dev, "PSP load smu failed!\n"); 2838 2839 return ret; 2840 } 2841 2842 static bool fw_load_skip_check(struct psp_context *psp, 2843 struct amdgpu_firmware_info *ucode) 2844 { 2845 if (!ucode->fw || !ucode->ucode_size) 2846 return true; 2847 2848 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2849 return true; 2850 2851 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2852 (psp_smu_reload_quirk(psp) || 2853 psp->autoload_supported || 2854 psp->pmfw_centralized_cstate_management)) 2855 return true; 2856 2857 if (amdgpu_sriov_vf(psp->adev) && 2858 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2859 return true; 2860 2861 if (psp->autoload_supported && 2862 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2863 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2864 /* skip mec JT when autoload is enabled */ 2865 return true; 2866 2867 return false; 2868 } 2869 2870 int psp_load_fw_list(struct psp_context *psp, 2871 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2872 { 2873 int ret = 0, i; 2874 struct amdgpu_firmware_info *ucode; 2875 2876 for (i = 0; i < ucode_count; ++i) { 2877 ucode = ucode_list[i]; 2878 psp_print_fw_hdr(psp, ucode); 2879 ret = psp_execute_ip_fw_load(psp, ucode); 2880 if (ret) 2881 return ret; 2882 } 2883 return ret; 2884 } 2885 2886 static int psp_load_non_psp_fw(struct psp_context *psp) 2887 { 2888 int i, ret; 2889 struct amdgpu_firmware_info *ucode; 2890 struct amdgpu_device *adev = psp->adev; 2891 2892 if (psp->autoload_supported && 2893 !psp->pmfw_centralized_cstate_management) { 2894 ret = psp_load_smu_fw(psp); 2895 if (ret) 2896 return ret; 2897 } 2898 2899 /* Load P2S table first if it's available */ 2900 psp_load_p2s_table(psp); 2901 2902 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2903 ucode = &adev->firmware.ucode[i]; 2904 2905 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2906 !fw_load_skip_check(psp, ucode)) { 2907 ret = psp_load_smu_fw(psp); 2908 if (ret) 2909 return ret; 2910 continue; 2911 } 2912 2913 if (fw_load_skip_check(psp, ucode)) 2914 continue; 2915 2916 if (psp->autoload_supported && 2917 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 2918 IP_VERSION(11, 0, 7) || 2919 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2920 IP_VERSION(11, 0, 11) || 2921 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2922 IP_VERSION(11, 0, 12)) && 2923 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2924 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2925 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2926 /* PSP only receive one SDMA fw for sienna_cichlid, 2927 * as all four sdma fw are same 2928 */ 2929 continue; 2930 2931 psp_print_fw_hdr(psp, ucode); 2932 2933 ret = psp_execute_ip_fw_load(psp, ucode); 2934 if (ret) 2935 return ret; 2936 2937 /* Start rlc autoload after psp received all the gfx firmware */ 2938 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2939 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2940 ret = psp_rlc_autoload_start(psp); 2941 if (ret) { 2942 dev_err(adev->dev, "Failed to start rlc autoload\n"); 2943 return ret; 2944 } 2945 } 2946 } 2947 2948 return 0; 2949 } 2950 2951 static int psp_load_fw(struct amdgpu_device *adev) 2952 { 2953 int ret; 2954 struct psp_context *psp = &adev->psp; 2955 2956 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2957 /* should not destroy ring, only stop */ 2958 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2959 } else { 2960 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2961 2962 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2963 if (ret) { 2964 dev_err(adev->dev, "PSP ring init failed!\n"); 2965 goto failed; 2966 } 2967 } 2968 2969 ret = psp_hw_start(psp); 2970 if (ret) 2971 goto failed; 2972 2973 ret = psp_load_non_psp_fw(psp); 2974 if (ret) 2975 goto failed1; 2976 2977 ret = psp_asd_initialize(psp); 2978 if (ret) { 2979 dev_err(adev->dev, "PSP load asd failed!\n"); 2980 goto failed1; 2981 } 2982 2983 ret = psp_rl_load(adev); 2984 if (ret) { 2985 dev_err(adev->dev, "PSP load RL failed!\n"); 2986 goto failed1; 2987 } 2988 2989 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2990 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2991 ret = psp_xgmi_initialize(psp, false, true); 2992 /* Warning the XGMI seesion initialize failure 2993 * Instead of stop driver initialization 2994 */ 2995 if (ret) 2996 dev_err(psp->adev->dev, 2997 "XGMI: Failed to initialize XGMI session\n"); 2998 } 2999 } 3000 3001 if (psp->ta_fw) { 3002 ret = psp_ras_initialize(psp); 3003 if (ret) 3004 dev_err(psp->adev->dev, 3005 "RAS: Failed to initialize RAS\n"); 3006 3007 ret = psp_hdcp_initialize(psp); 3008 if (ret) 3009 dev_err(psp->adev->dev, 3010 "HDCP: Failed to initialize HDCP\n"); 3011 3012 ret = psp_dtm_initialize(psp); 3013 if (ret) 3014 dev_err(psp->adev->dev, 3015 "DTM: Failed to initialize DTM\n"); 3016 3017 ret = psp_rap_initialize(psp); 3018 if (ret) 3019 dev_err(psp->adev->dev, 3020 "RAP: Failed to initialize RAP\n"); 3021 3022 ret = psp_securedisplay_initialize(psp); 3023 if (ret) 3024 dev_err(psp->adev->dev, 3025 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3026 } 3027 3028 return 0; 3029 3030 failed1: 3031 psp_free_shared_bufs(psp); 3032 failed: 3033 /* 3034 * all cleanup jobs (xgmi terminate, ras terminate, 3035 * ring destroy, cmd/fence/fw buffers destory, 3036 * psp->cmd destory) are delayed to psp_hw_fini 3037 */ 3038 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3039 return ret; 3040 } 3041 3042 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3043 { 3044 int ret; 3045 struct amdgpu_device *adev = ip_block->adev; 3046 3047 mutex_lock(&adev->firmware.mutex); 3048 3049 ret = amdgpu_ucode_init_bo(adev); 3050 if (ret) 3051 goto failed; 3052 3053 ret = psp_load_fw(adev); 3054 if (ret) { 3055 dev_err(adev->dev, "PSP firmware loading failed\n"); 3056 goto failed; 3057 } 3058 3059 mutex_unlock(&adev->firmware.mutex); 3060 return 0; 3061 3062 failed: 3063 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3064 mutex_unlock(&adev->firmware.mutex); 3065 return -EINVAL; 3066 } 3067 3068 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3069 { 3070 struct amdgpu_device *adev = ip_block->adev; 3071 struct psp_context *psp = &adev->psp; 3072 3073 if (psp->ta_fw) { 3074 psp_ras_terminate(psp); 3075 psp_securedisplay_terminate(psp); 3076 psp_rap_terminate(psp); 3077 psp_dtm_terminate(psp); 3078 psp_hdcp_terminate(psp); 3079 3080 if (adev->gmc.xgmi.num_physical_nodes > 1) 3081 psp_xgmi_terminate(psp); 3082 } 3083 3084 psp_asd_terminate(psp); 3085 psp_tmr_terminate(psp); 3086 3087 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3088 3089 return 0; 3090 } 3091 3092 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3093 { 3094 int ret = 0; 3095 struct amdgpu_device *adev = ip_block->adev; 3096 struct psp_context *psp = &adev->psp; 3097 3098 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3099 psp->xgmi_context.context.initialized) { 3100 ret = psp_xgmi_terminate(psp); 3101 if (ret) { 3102 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3103 goto out; 3104 } 3105 } 3106 3107 if (psp->ta_fw) { 3108 ret = psp_ras_terminate(psp); 3109 if (ret) { 3110 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3111 goto out; 3112 } 3113 ret = psp_hdcp_terminate(psp); 3114 if (ret) { 3115 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3116 goto out; 3117 } 3118 ret = psp_dtm_terminate(psp); 3119 if (ret) { 3120 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3121 goto out; 3122 } 3123 ret = psp_rap_terminate(psp); 3124 if (ret) { 3125 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3126 goto out; 3127 } 3128 ret = psp_securedisplay_terminate(psp); 3129 if (ret) { 3130 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3131 goto out; 3132 } 3133 } 3134 3135 ret = psp_asd_terminate(psp); 3136 if (ret) { 3137 dev_err(adev->dev, "Failed to terminate asd\n"); 3138 goto out; 3139 } 3140 3141 ret = psp_tmr_terminate(psp); 3142 if (ret) { 3143 dev_err(adev->dev, "Failed to terminate tmr\n"); 3144 goto out; 3145 } 3146 3147 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3148 if (ret) 3149 dev_err(adev->dev, "PSP ring stop failed\n"); 3150 3151 out: 3152 return ret; 3153 } 3154 3155 static int psp_resume(struct amdgpu_ip_block *ip_block) 3156 { 3157 int ret; 3158 struct amdgpu_device *adev = ip_block->adev; 3159 struct psp_context *psp = &adev->psp; 3160 3161 dev_info(adev->dev, "PSP is resuming...\n"); 3162 3163 if (psp->mem_train_ctx.enable_mem_training) { 3164 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3165 if (ret) { 3166 dev_err(adev->dev, "Failed to process memory training!\n"); 3167 return ret; 3168 } 3169 } 3170 3171 mutex_lock(&adev->firmware.mutex); 3172 3173 ret = amdgpu_ucode_init_bo(adev); 3174 if (ret) 3175 goto failed; 3176 3177 ret = psp_hw_start(psp); 3178 if (ret) 3179 goto failed; 3180 3181 ret = psp_load_non_psp_fw(psp); 3182 if (ret) 3183 goto failed; 3184 3185 ret = psp_asd_initialize(psp); 3186 if (ret) { 3187 dev_err(adev->dev, "PSP load asd failed!\n"); 3188 goto failed; 3189 } 3190 3191 ret = psp_rl_load(adev); 3192 if (ret) { 3193 dev_err(adev->dev, "PSP load RL failed!\n"); 3194 goto failed; 3195 } 3196 3197 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3198 ret = psp_xgmi_initialize(psp, false, true); 3199 /* Warning the XGMI seesion initialize failure 3200 * Instead of stop driver initialization 3201 */ 3202 if (ret) 3203 dev_err(psp->adev->dev, 3204 "XGMI: Failed to initialize XGMI session\n"); 3205 } 3206 3207 if (psp->ta_fw) { 3208 ret = psp_ras_initialize(psp); 3209 if (ret) 3210 dev_err(psp->adev->dev, 3211 "RAS: Failed to initialize RAS\n"); 3212 3213 ret = psp_hdcp_initialize(psp); 3214 if (ret) 3215 dev_err(psp->adev->dev, 3216 "HDCP: Failed to initialize HDCP\n"); 3217 3218 ret = psp_dtm_initialize(psp); 3219 if (ret) 3220 dev_err(psp->adev->dev, 3221 "DTM: Failed to initialize DTM\n"); 3222 3223 ret = psp_rap_initialize(psp); 3224 if (ret) 3225 dev_err(psp->adev->dev, 3226 "RAP: Failed to initialize RAP\n"); 3227 3228 ret = psp_securedisplay_initialize(psp); 3229 if (ret) 3230 dev_err(psp->adev->dev, 3231 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3232 } 3233 3234 mutex_unlock(&adev->firmware.mutex); 3235 3236 return 0; 3237 3238 failed: 3239 dev_err(adev->dev, "PSP resume failed\n"); 3240 mutex_unlock(&adev->firmware.mutex); 3241 return ret; 3242 } 3243 3244 int psp_gpu_reset(struct amdgpu_device *adev) 3245 { 3246 int ret; 3247 3248 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3249 return 0; 3250 3251 mutex_lock(&adev->psp.mutex); 3252 ret = psp_mode1_reset(&adev->psp); 3253 mutex_unlock(&adev->psp.mutex); 3254 3255 return ret; 3256 } 3257 3258 int psp_rlc_autoload_start(struct psp_context *psp) 3259 { 3260 int ret; 3261 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3262 3263 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3264 3265 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3266 psp->fence_buf_mc_addr); 3267 3268 release_psp_cmd_buf(psp); 3269 3270 return ret; 3271 } 3272 3273 int psp_ring_cmd_submit(struct psp_context *psp, 3274 uint64_t cmd_buf_mc_addr, 3275 uint64_t fence_mc_addr, 3276 int index) 3277 { 3278 unsigned int psp_write_ptr_reg = 0; 3279 struct psp_gfx_rb_frame *write_frame; 3280 struct psp_ring *ring = &psp->km_ring; 3281 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3282 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3283 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3284 struct amdgpu_device *adev = psp->adev; 3285 uint32_t ring_size_dw = ring->ring_size / 4; 3286 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3287 3288 /* KM (GPCOM) prepare write pointer */ 3289 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3290 3291 /* Update KM RB frame pointer to new frame */ 3292 /* write_frame ptr increments by size of rb_frame in bytes */ 3293 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3294 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3295 write_frame = ring_buffer_start; 3296 else 3297 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3298 /* Check invalid write_frame ptr address */ 3299 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3300 dev_err(adev->dev, 3301 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3302 ring_buffer_start, ring_buffer_end, write_frame); 3303 dev_err(adev->dev, 3304 "write_frame is pointing to address out of bounds\n"); 3305 return -EINVAL; 3306 } 3307 3308 /* Initialize KM RB frame */ 3309 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3310 3311 /* Update KM RB frame */ 3312 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3313 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3314 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3315 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3316 write_frame->fence_value = index; 3317 amdgpu_device_flush_hdp(adev, NULL); 3318 3319 /* Update the write Pointer in DWORDs */ 3320 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3321 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3322 return 0; 3323 } 3324 3325 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3326 { 3327 struct amdgpu_device *adev = psp->adev; 3328 const struct psp_firmware_header_v1_0 *asd_hdr; 3329 int err = 0; 3330 3331 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3332 "amdgpu/%s_asd.bin", chip_name); 3333 if (err) 3334 goto out; 3335 3336 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3337 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3338 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3339 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3340 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3341 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3342 return 0; 3343 out: 3344 amdgpu_ucode_release(&adev->psp.asd_fw); 3345 return err; 3346 } 3347 3348 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3349 { 3350 struct amdgpu_device *adev = psp->adev; 3351 const struct psp_firmware_header_v1_0 *toc_hdr; 3352 int err = 0; 3353 3354 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3355 "amdgpu/%s_toc.bin", chip_name); 3356 if (err) 3357 goto out; 3358 3359 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3360 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3361 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3362 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3363 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3364 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3365 return 0; 3366 out: 3367 amdgpu_ucode_release(&adev->psp.toc_fw); 3368 return err; 3369 } 3370 3371 static int parse_sos_bin_descriptor(struct psp_context *psp, 3372 const struct psp_fw_bin_desc *desc, 3373 const struct psp_firmware_header_v2_0 *sos_hdr) 3374 { 3375 uint8_t *ucode_start_addr = NULL; 3376 3377 if (!psp || !desc || !sos_hdr) 3378 return -EINVAL; 3379 3380 ucode_start_addr = (uint8_t *)sos_hdr + 3381 le32_to_cpu(desc->offset_bytes) + 3382 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3383 3384 switch (desc->fw_type) { 3385 case PSP_FW_TYPE_PSP_SOS: 3386 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3387 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3388 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3389 psp->sos.start_addr = ucode_start_addr; 3390 break; 3391 case PSP_FW_TYPE_PSP_SYS_DRV: 3392 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3393 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3394 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3395 psp->sys.start_addr = ucode_start_addr; 3396 break; 3397 case PSP_FW_TYPE_PSP_KDB: 3398 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3399 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3400 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3401 psp->kdb.start_addr = ucode_start_addr; 3402 break; 3403 case PSP_FW_TYPE_PSP_TOC: 3404 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3405 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3406 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3407 psp->toc.start_addr = ucode_start_addr; 3408 break; 3409 case PSP_FW_TYPE_PSP_SPL: 3410 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3411 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3412 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3413 psp->spl.start_addr = ucode_start_addr; 3414 break; 3415 case PSP_FW_TYPE_PSP_RL: 3416 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3417 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3418 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3419 psp->rl.start_addr = ucode_start_addr; 3420 break; 3421 case PSP_FW_TYPE_PSP_SOC_DRV: 3422 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3423 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3424 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3425 psp->soc_drv.start_addr = ucode_start_addr; 3426 break; 3427 case PSP_FW_TYPE_PSP_INTF_DRV: 3428 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3429 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3430 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3431 psp->intf_drv.start_addr = ucode_start_addr; 3432 break; 3433 case PSP_FW_TYPE_PSP_DBG_DRV: 3434 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3435 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3436 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3437 psp->dbg_drv.start_addr = ucode_start_addr; 3438 break; 3439 case PSP_FW_TYPE_PSP_RAS_DRV: 3440 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3441 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3442 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3443 psp->ras_drv.start_addr = ucode_start_addr; 3444 break; 3445 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3446 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3447 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3448 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3449 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3450 break; 3451 case PSP_FW_TYPE_PSP_SPDM_DRV: 3452 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 3453 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 3454 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3455 psp->spdm_drv.start_addr = ucode_start_addr; 3456 break; 3457 default: 3458 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3459 break; 3460 } 3461 3462 return 0; 3463 } 3464 3465 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3466 { 3467 const struct psp_firmware_header_v1_0 *sos_hdr; 3468 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3469 uint8_t *ucode_array_start_addr; 3470 3471 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3472 ucode_array_start_addr = (uint8_t *)sos_hdr + 3473 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3474 3475 if (adev->gmc.xgmi.connected_to_cpu || 3476 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3477 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3478 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3479 3480 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3481 adev->psp.sys.start_addr = ucode_array_start_addr; 3482 3483 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3484 adev->psp.sos.start_addr = ucode_array_start_addr + 3485 le32_to_cpu(sos_hdr->sos.offset_bytes); 3486 } else { 3487 /* Load alternate PSP SOS FW */ 3488 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3489 3490 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3491 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3492 3493 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3494 adev->psp.sys.start_addr = ucode_array_start_addr + 3495 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3496 3497 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3498 adev->psp.sos.start_addr = ucode_array_start_addr + 3499 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3500 } 3501 3502 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3503 dev_warn(adev->dev, "PSP SOS FW not available"); 3504 return -EINVAL; 3505 } 3506 3507 return 0; 3508 } 3509 3510 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3511 { 3512 struct amdgpu_device *adev = psp->adev; 3513 const struct psp_firmware_header_v1_0 *sos_hdr; 3514 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3515 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3516 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3517 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3518 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 3519 int fw_index, fw_bin_count, start_index = 0; 3520 const struct psp_fw_bin_desc *fw_bin; 3521 uint8_t *ucode_array_start_addr; 3522 int err = 0; 3523 3524 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3525 "amdgpu/%s_sos.bin", chip_name); 3526 if (err) 3527 goto out; 3528 3529 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3530 ucode_array_start_addr = (uint8_t *)sos_hdr + 3531 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3532 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3533 3534 switch (sos_hdr->header.header_version_major) { 3535 case 1: 3536 err = psp_init_sos_base_fw(adev); 3537 if (err) 3538 goto out; 3539 3540 if (sos_hdr->header.header_version_minor == 1) { 3541 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3542 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3543 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3544 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3545 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3546 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3547 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3548 } 3549 if (sos_hdr->header.header_version_minor == 2) { 3550 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3551 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3552 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3553 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3554 } 3555 if (sos_hdr->header.header_version_minor == 3) { 3556 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3557 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3558 adev->psp.toc.start_addr = ucode_array_start_addr + 3559 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3560 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3561 adev->psp.kdb.start_addr = ucode_array_start_addr + 3562 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3563 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3564 adev->psp.spl.start_addr = ucode_array_start_addr + 3565 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3566 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3567 adev->psp.rl.start_addr = ucode_array_start_addr + 3568 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3569 } 3570 break; 3571 case 2: 3572 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3573 3574 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 3575 3576 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 3577 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3578 err = -EINVAL; 3579 goto out; 3580 } 3581 3582 if (sos_hdr_v2_0->header.header_version_minor == 1) { 3583 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 3584 3585 fw_bin = sos_hdr_v2_1->psp_fw_bin; 3586 3587 if (psp_is_aux_sos_load_required(psp)) 3588 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3589 else 3590 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3591 3592 } else { 3593 fw_bin = sos_hdr_v2_0->psp_fw_bin; 3594 } 3595 3596 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 3597 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 3598 sos_hdr_v2_0); 3599 if (err) 3600 goto out; 3601 } 3602 break; 3603 default: 3604 dev_err(adev->dev, 3605 "unsupported psp sos firmware\n"); 3606 err = -EINVAL; 3607 goto out; 3608 } 3609 3610 return 0; 3611 out: 3612 amdgpu_ucode_release(&adev->psp.sos_fw); 3613 3614 return err; 3615 } 3616 3617 static bool is_ta_fw_applicable(struct psp_context *psp, 3618 const struct psp_fw_bin_desc *desc) 3619 { 3620 struct amdgpu_device *adev = psp->adev; 3621 uint32_t fw_version; 3622 3623 switch (desc->fw_type) { 3624 case TA_FW_TYPE_PSP_XGMI: 3625 case TA_FW_TYPE_PSP_XGMI_AUX: 3626 /* for now, AUX TA only exists on 13.0.6 ta bin, 3627 * from v20.00.0x.14 3628 */ 3629 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3630 IP_VERSION(13, 0, 6)) { 3631 fw_version = le32_to_cpu(desc->fw_version); 3632 3633 if (adev->flags & AMD_IS_APU && 3634 (fw_version & 0xff) >= 0x14) 3635 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 3636 else 3637 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 3638 } 3639 break; 3640 default: 3641 break; 3642 } 3643 3644 return true; 3645 } 3646 3647 static int parse_ta_bin_descriptor(struct psp_context *psp, 3648 const struct psp_fw_bin_desc *desc, 3649 const struct ta_firmware_header_v2_0 *ta_hdr) 3650 { 3651 uint8_t *ucode_start_addr = NULL; 3652 3653 if (!psp || !desc || !ta_hdr) 3654 return -EINVAL; 3655 3656 if (!is_ta_fw_applicable(psp, desc)) 3657 return 0; 3658 3659 ucode_start_addr = (uint8_t *)ta_hdr + 3660 le32_to_cpu(desc->offset_bytes) + 3661 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3662 3663 switch (desc->fw_type) { 3664 case TA_FW_TYPE_PSP_ASD: 3665 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3666 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3667 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3668 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3669 break; 3670 case TA_FW_TYPE_PSP_XGMI: 3671 case TA_FW_TYPE_PSP_XGMI_AUX: 3672 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3673 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3674 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3675 break; 3676 case TA_FW_TYPE_PSP_RAS: 3677 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3678 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3679 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3680 break; 3681 case TA_FW_TYPE_PSP_HDCP: 3682 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3683 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3684 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3685 break; 3686 case TA_FW_TYPE_PSP_DTM: 3687 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3688 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3689 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3690 break; 3691 case TA_FW_TYPE_PSP_RAP: 3692 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3693 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3694 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3695 break; 3696 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3697 psp->securedisplay_context.context.bin_desc.fw_version = 3698 le32_to_cpu(desc->fw_version); 3699 psp->securedisplay_context.context.bin_desc.size_bytes = 3700 le32_to_cpu(desc->size_bytes); 3701 psp->securedisplay_context.context.bin_desc.start_addr = 3702 ucode_start_addr; 3703 break; 3704 default: 3705 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3706 break; 3707 } 3708 3709 return 0; 3710 } 3711 3712 static int parse_ta_v1_microcode(struct psp_context *psp) 3713 { 3714 const struct ta_firmware_header_v1_0 *ta_hdr; 3715 struct amdgpu_device *adev = psp->adev; 3716 3717 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3718 3719 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3720 return -EINVAL; 3721 3722 adev->psp.xgmi_context.context.bin_desc.fw_version = 3723 le32_to_cpu(ta_hdr->xgmi.fw_version); 3724 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3725 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3726 adev->psp.xgmi_context.context.bin_desc.start_addr = 3727 (uint8_t *)ta_hdr + 3728 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3729 3730 adev->psp.ras_context.context.bin_desc.fw_version = 3731 le32_to_cpu(ta_hdr->ras.fw_version); 3732 adev->psp.ras_context.context.bin_desc.size_bytes = 3733 le32_to_cpu(ta_hdr->ras.size_bytes); 3734 adev->psp.ras_context.context.bin_desc.start_addr = 3735 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3736 le32_to_cpu(ta_hdr->ras.offset_bytes); 3737 3738 adev->psp.hdcp_context.context.bin_desc.fw_version = 3739 le32_to_cpu(ta_hdr->hdcp.fw_version); 3740 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3741 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3742 adev->psp.hdcp_context.context.bin_desc.start_addr = 3743 (uint8_t *)ta_hdr + 3744 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3745 3746 adev->psp.dtm_context.context.bin_desc.fw_version = 3747 le32_to_cpu(ta_hdr->dtm.fw_version); 3748 adev->psp.dtm_context.context.bin_desc.size_bytes = 3749 le32_to_cpu(ta_hdr->dtm.size_bytes); 3750 adev->psp.dtm_context.context.bin_desc.start_addr = 3751 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3752 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3753 3754 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3755 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3756 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3757 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3758 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3759 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3760 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3761 3762 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3763 3764 return 0; 3765 } 3766 3767 static int parse_ta_v2_microcode(struct psp_context *psp) 3768 { 3769 const struct ta_firmware_header_v2_0 *ta_hdr; 3770 struct amdgpu_device *adev = psp->adev; 3771 int err = 0; 3772 int ta_index = 0; 3773 3774 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3775 3776 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3777 return -EINVAL; 3778 3779 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3780 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3781 return -EINVAL; 3782 } 3783 3784 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3785 err = parse_ta_bin_descriptor(psp, 3786 &ta_hdr->ta_fw_bin[ta_index], 3787 ta_hdr); 3788 if (err) 3789 return err; 3790 } 3791 3792 return 0; 3793 } 3794 3795 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3796 { 3797 const struct common_firmware_header *hdr; 3798 struct amdgpu_device *adev = psp->adev; 3799 int err; 3800 3801 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3802 "amdgpu/%s_ta.bin", chip_name); 3803 if (err) 3804 return err; 3805 3806 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3807 switch (le16_to_cpu(hdr->header_version_major)) { 3808 case 1: 3809 err = parse_ta_v1_microcode(psp); 3810 break; 3811 case 2: 3812 err = parse_ta_v2_microcode(psp); 3813 break; 3814 default: 3815 dev_err(adev->dev, "unsupported TA header version\n"); 3816 err = -EINVAL; 3817 } 3818 3819 if (err) 3820 amdgpu_ucode_release(&adev->psp.ta_fw); 3821 3822 return err; 3823 } 3824 3825 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3826 { 3827 struct amdgpu_device *adev = psp->adev; 3828 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3829 struct amdgpu_firmware_info *info = NULL; 3830 int err = 0; 3831 3832 if (!amdgpu_sriov_vf(adev)) { 3833 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3834 return -EINVAL; 3835 } 3836 3837 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 3838 "amdgpu/%s_cap.bin", chip_name); 3839 if (err) { 3840 if (err == -ENODEV) { 3841 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3842 err = 0; 3843 } else { 3844 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3845 } 3846 goto out; 3847 } 3848 3849 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3850 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3851 info->fw = adev->psp.cap_fw; 3852 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3853 adev->psp.cap_fw->data; 3854 adev->firmware.fw_size += ALIGN( 3855 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3856 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3857 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3858 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3859 3860 return 0; 3861 3862 out: 3863 amdgpu_ucode_release(&adev->psp.cap_fw); 3864 return err; 3865 } 3866 3867 int psp_config_sq_perfmon(struct psp_context *psp, 3868 uint32_t xcp_id, bool core_override_enable, 3869 bool reg_override_enable, bool perfmon_override_enable) 3870 { 3871 int ret; 3872 3873 if (amdgpu_sriov_vf(psp->adev)) 3874 return 0; 3875 3876 if (xcp_id > MAX_XCP) { 3877 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 3878 return -EINVAL; 3879 } 3880 3881 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 3882 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 3883 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 3884 return -EINVAL; 3885 } 3886 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3887 3888 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 3889 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 3890 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 3891 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 3892 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 3893 3894 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 3895 if (ret) 3896 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 3897 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 3898 3899 release_psp_cmd_buf(psp); 3900 return ret; 3901 } 3902 3903 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3904 enum amd_clockgating_state state) 3905 { 3906 return 0; 3907 } 3908 3909 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 3910 enum amd_powergating_state state) 3911 { 3912 return 0; 3913 } 3914 3915 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3916 struct device_attribute *attr, 3917 char *buf) 3918 { 3919 struct drm_device *ddev = dev_get_drvdata(dev); 3920 struct amdgpu_device *adev = drm_to_adev(ddev); 3921 struct amdgpu_ip_block *ip_block; 3922 uint32_t fw_ver; 3923 int ret; 3924 3925 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 3926 if (!ip_block || !ip_block->status.late_initialized) { 3927 dev_info(adev->dev, "PSP block is not ready yet\n."); 3928 return -EBUSY; 3929 } 3930 3931 mutex_lock(&adev->psp.mutex); 3932 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3933 mutex_unlock(&adev->psp.mutex); 3934 3935 if (ret) { 3936 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 3937 return ret; 3938 } 3939 3940 return sysfs_emit(buf, "%x\n", fw_ver); 3941 } 3942 3943 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3944 struct device_attribute *attr, 3945 const char *buf, 3946 size_t count) 3947 { 3948 struct drm_device *ddev = dev_get_drvdata(dev); 3949 struct amdgpu_device *adev = drm_to_adev(ddev); 3950 int ret, idx; 3951 const struct firmware *usbc_pd_fw; 3952 struct amdgpu_bo *fw_buf_bo = NULL; 3953 uint64_t fw_pri_mc_addr; 3954 void *fw_pri_cpu_addr; 3955 struct amdgpu_ip_block *ip_block; 3956 3957 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 3958 if (!ip_block || !ip_block->status.late_initialized) { 3959 dev_err(adev->dev, "PSP block is not ready yet."); 3960 return -EBUSY; 3961 } 3962 3963 if (!drm_dev_enter(ddev, &idx)) 3964 return -ENODEV; 3965 3966 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 3967 "amdgpu/%s", buf); 3968 if (ret) 3969 goto fail; 3970 3971 /* LFB address which is aligned to 1MB boundary per PSP request */ 3972 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3973 AMDGPU_GEM_DOMAIN_VRAM | 3974 AMDGPU_GEM_DOMAIN_GTT, 3975 &fw_buf_bo, &fw_pri_mc_addr, 3976 &fw_pri_cpu_addr); 3977 if (ret) 3978 goto rel_buf; 3979 3980 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3981 3982 mutex_lock(&adev->psp.mutex); 3983 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3984 mutex_unlock(&adev->psp.mutex); 3985 3986 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3987 3988 rel_buf: 3989 amdgpu_ucode_release(&usbc_pd_fw); 3990 fail: 3991 if (ret) { 3992 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 3993 count = ret; 3994 } 3995 3996 drm_dev_exit(idx); 3997 return count; 3998 } 3999 4000 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4001 { 4002 int idx; 4003 4004 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4005 return; 4006 4007 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4008 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4009 4010 drm_dev_exit(idx); 4011 } 4012 4013 /** 4014 * DOC: usbc_pd_fw 4015 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4016 * this file will trigger the update process. 4017 */ 4018 static DEVICE_ATTR(usbc_pd_fw, 0644, 4019 psp_usbc_pd_fw_sysfs_read, 4020 psp_usbc_pd_fw_sysfs_write); 4021 4022 int is_psp_fw_valid(struct psp_bin_desc bin) 4023 { 4024 return bin.size_bytes; 4025 } 4026 4027 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4028 const struct bin_attribute *bin_attr, 4029 char *buffer, loff_t pos, size_t count) 4030 { 4031 struct device *dev = kobj_to_dev(kobj); 4032 struct drm_device *ddev = dev_get_drvdata(dev); 4033 struct amdgpu_device *adev = drm_to_adev(ddev); 4034 4035 adev->psp.vbflash_done = false; 4036 4037 /* Safeguard against memory drain */ 4038 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4039 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4040 kvfree(adev->psp.vbflash_tmp_buf); 4041 adev->psp.vbflash_tmp_buf = NULL; 4042 adev->psp.vbflash_image_size = 0; 4043 return -ENOMEM; 4044 } 4045 4046 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4047 if (!adev->psp.vbflash_tmp_buf) { 4048 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4049 if (!adev->psp.vbflash_tmp_buf) 4050 return -ENOMEM; 4051 } 4052 4053 mutex_lock(&adev->psp.mutex); 4054 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4055 adev->psp.vbflash_image_size += count; 4056 mutex_unlock(&adev->psp.mutex); 4057 4058 dev_dbg(adev->dev, "IFWI staged for update\n"); 4059 4060 return count; 4061 } 4062 4063 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4064 const struct bin_attribute *bin_attr, char *buffer, 4065 loff_t pos, size_t count) 4066 { 4067 struct device *dev = kobj_to_dev(kobj); 4068 struct drm_device *ddev = dev_get_drvdata(dev); 4069 struct amdgpu_device *adev = drm_to_adev(ddev); 4070 struct amdgpu_bo *fw_buf_bo = NULL; 4071 uint64_t fw_pri_mc_addr; 4072 void *fw_pri_cpu_addr; 4073 int ret; 4074 4075 if (adev->psp.vbflash_image_size == 0) 4076 return -EINVAL; 4077 4078 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4079 4080 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4081 AMDGPU_GPU_PAGE_SIZE, 4082 AMDGPU_GEM_DOMAIN_VRAM, 4083 &fw_buf_bo, 4084 &fw_pri_mc_addr, 4085 &fw_pri_cpu_addr); 4086 if (ret) 4087 goto rel_buf; 4088 4089 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4090 4091 mutex_lock(&adev->psp.mutex); 4092 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4093 mutex_unlock(&adev->psp.mutex); 4094 4095 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4096 4097 rel_buf: 4098 kvfree(adev->psp.vbflash_tmp_buf); 4099 adev->psp.vbflash_tmp_buf = NULL; 4100 adev->psp.vbflash_image_size = 0; 4101 4102 if (ret) { 4103 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4104 return ret; 4105 } 4106 4107 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4108 return 0; 4109 } 4110 4111 /** 4112 * DOC: psp_vbflash 4113 * Writing to this file will stage an IFWI for update. Reading from this file 4114 * will trigger the update process. 4115 */ 4116 static const struct bin_attribute psp_vbflash_bin_attr = { 4117 .attr = {.name = "psp_vbflash", .mode = 0660}, 4118 .size = 0, 4119 .write_new = amdgpu_psp_vbflash_write, 4120 .read_new = amdgpu_psp_vbflash_read, 4121 }; 4122 4123 /** 4124 * DOC: psp_vbflash_status 4125 * The status of the flash process. 4126 * 0: IFWI flash not complete. 4127 * 1: IFWI flash complete. 4128 */ 4129 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4130 struct device_attribute *attr, 4131 char *buf) 4132 { 4133 struct drm_device *ddev = dev_get_drvdata(dev); 4134 struct amdgpu_device *adev = drm_to_adev(ddev); 4135 uint32_t vbflash_status; 4136 4137 vbflash_status = psp_vbflash_status(&adev->psp); 4138 if (!adev->psp.vbflash_done) 4139 vbflash_status = 0; 4140 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4141 vbflash_status = 1; 4142 4143 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4144 } 4145 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4146 4147 static const struct bin_attribute *const bin_flash_attrs[] = { 4148 &psp_vbflash_bin_attr, 4149 NULL 4150 }; 4151 4152 static struct attribute *flash_attrs[] = { 4153 &dev_attr_psp_vbflash_status.attr, 4154 &dev_attr_usbc_pd_fw.attr, 4155 NULL 4156 }; 4157 4158 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4159 { 4160 struct device *dev = kobj_to_dev(kobj); 4161 struct drm_device *ddev = dev_get_drvdata(dev); 4162 struct amdgpu_device *adev = drm_to_adev(ddev); 4163 4164 if (attr == &dev_attr_usbc_pd_fw.attr) 4165 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4166 4167 return adev->psp.sup_ifwi_up ? 0440 : 0; 4168 } 4169 4170 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4171 const struct bin_attribute *attr, 4172 int idx) 4173 { 4174 struct device *dev = kobj_to_dev(kobj); 4175 struct drm_device *ddev = dev_get_drvdata(dev); 4176 struct amdgpu_device *adev = drm_to_adev(ddev); 4177 4178 return adev->psp.sup_ifwi_up ? 0660 : 0; 4179 } 4180 4181 const struct attribute_group amdgpu_flash_attr_group = { 4182 .attrs = flash_attrs, 4183 .bin_attrs_new = bin_flash_attrs, 4184 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4185 .is_visible = amdgpu_flash_attr_is_visible, 4186 }; 4187 4188 const struct amd_ip_funcs psp_ip_funcs = { 4189 .name = "psp", 4190 .early_init = psp_early_init, 4191 .sw_init = psp_sw_init, 4192 .sw_fini = psp_sw_fini, 4193 .hw_init = psp_hw_init, 4194 .hw_fini = psp_hw_fini, 4195 .suspend = psp_suspend, 4196 .resume = psp_resume, 4197 .set_clockgating_state = psp_set_clockgating_state, 4198 .set_powergating_state = psp_set_powergating_state, 4199 }; 4200 4201 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4202 .type = AMD_IP_BLOCK_TYPE_PSP, 4203 .major = 3, 4204 .minor = 1, 4205 .rev = 0, 4206 .funcs = &psp_ip_funcs, 4207 }; 4208 4209 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4210 .type = AMD_IP_BLOCK_TYPE_PSP, 4211 .major = 10, 4212 .minor = 0, 4213 .rev = 0, 4214 .funcs = &psp_ip_funcs, 4215 }; 4216 4217 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4218 .type = AMD_IP_BLOCK_TYPE_PSP, 4219 .major = 11, 4220 .minor = 0, 4221 .rev = 0, 4222 .funcs = &psp_ip_funcs, 4223 }; 4224 4225 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4226 .type = AMD_IP_BLOCK_TYPE_PSP, 4227 .major = 11, 4228 .minor = 0, 4229 .rev = 8, 4230 .funcs = &psp_ip_funcs, 4231 }; 4232 4233 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4234 .type = AMD_IP_BLOCK_TYPE_PSP, 4235 .major = 12, 4236 .minor = 0, 4237 .rev = 0, 4238 .funcs = &psp_ip_funcs, 4239 }; 4240 4241 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4242 .type = AMD_IP_BLOCK_TYPE_PSP, 4243 .major = 13, 4244 .minor = 0, 4245 .rev = 0, 4246 .funcs = &psp_ip_funcs, 4247 }; 4248 4249 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4250 .type = AMD_IP_BLOCK_TYPE_PSP, 4251 .major = 13, 4252 .minor = 0, 4253 .rev = 4, 4254 .funcs = &psp_ip_funcs, 4255 }; 4256 4257 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4258 .type = AMD_IP_BLOCK_TYPE_PSP, 4259 .major = 14, 4260 .minor = 0, 4261 .rev = 0, 4262 .funcs = &psp_ip_funcs, 4263 }; 4264