1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 case IP_VERSION(15, 0, 5): 279 case IP_VERSION(15, 0, 9): 280 psp_v15_0_0_set_psp_funcs(psp); 281 psp->boot_time_tmr = false; 282 break; 283 case IP_VERSION(15, 0, 8): 284 psp_v15_0_8_set_psp_funcs(psp); 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 psp->adev = adev; 291 292 adev->psp_timeout = 20000; 293 294 psp_check_pmfw_centralized_cstate_management(psp); 295 296 if (amdgpu_sriov_vf(adev)) 297 return psp_init_sriov_microcode(psp); 298 else 299 return psp_init_microcode(psp); 300 } 301 302 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 303 { 304 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 305 &mem_ctx->shared_buf); 306 mem_ctx->shared_bo = NULL; 307 } 308 309 static void psp_free_shared_bufs(struct psp_context *psp) 310 { 311 void *tmr_buf; 312 void **pptr; 313 314 /* free TMR memory buffer */ 315 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 316 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 317 psp->tmr_bo = NULL; 318 319 /* free xgmi shared memory */ 320 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 321 322 /* free ras shared memory */ 323 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 324 325 /* free hdcp shared memory */ 326 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 327 328 /* free dtm shared memory */ 329 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 330 331 /* free rap shared memory */ 332 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 333 334 /* free securedisplay shared memory */ 335 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 336 337 338 } 339 340 static void psp_memory_training_fini(struct psp_context *psp) 341 { 342 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 343 344 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 345 kfree(ctx->sys_cache); 346 ctx->sys_cache = NULL; 347 } 348 349 static int psp_memory_training_init(struct psp_context *psp) 350 { 351 int ret; 352 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 353 354 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 355 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 356 return 0; 357 } 358 359 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 360 if (ctx->sys_cache == NULL) { 361 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 362 ret = -ENOMEM; 363 goto Err_out; 364 } 365 366 dev_dbg(psp->adev->dev, 367 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 368 ctx->train_data_size, 369 ctx->p2c_train_data_offset, 370 ctx->c2p_train_data_offset); 371 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 372 return 0; 373 374 Err_out: 375 psp_memory_training_fini(psp); 376 return ret; 377 } 378 379 /* 380 * Helper funciton to query psp runtime database entry 381 * 382 * @adev: amdgpu_device pointer 383 * @entry_type: the type of psp runtime database entry 384 * @db_entry: runtime database entry pointer 385 * 386 * Return false if runtime database doesn't exit or entry is invalid 387 * or true if the specific database entry is found, and copy to @db_entry 388 */ 389 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 390 enum psp_runtime_entry_type entry_type, 391 void *db_entry) 392 { 393 uint64_t db_header_pos, db_dir_pos; 394 struct psp_runtime_data_header db_header = {0}; 395 struct psp_runtime_data_directory db_dir = {0}; 396 bool ret = false; 397 int i; 398 399 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 401 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 402 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 403 return false; 404 405 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 406 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 407 408 /* read runtime db header from vram */ 409 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 410 sizeof(struct psp_runtime_data_header), false); 411 412 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 413 /* runtime db doesn't exist, exit */ 414 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 415 return false; 416 } 417 418 /* read runtime database entry from vram */ 419 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 420 sizeof(struct psp_runtime_data_directory), false); 421 422 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 423 /* invalid db entry count, exit */ 424 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 425 return false; 426 } 427 428 /* look up for requested entry type */ 429 for (i = 0; i < db_dir.entry_count && !ret; i++) { 430 if (db_dir.entry_list[i].entry_type == entry_type) { 431 switch (entry_type) { 432 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 433 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 434 /* invalid db entry size */ 435 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 436 return false; 437 } 438 /* read runtime database entry */ 439 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 440 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 441 ret = true; 442 break; 443 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 444 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 445 /* invalid db entry size */ 446 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 447 return false; 448 } 449 /* read runtime database entry */ 450 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 451 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 452 ret = true; 453 break; 454 default: 455 ret = false; 456 break; 457 } 458 } 459 } 460 461 return ret; 462 } 463 464 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 465 { 466 struct amdgpu_device *adev = ip_block->adev; 467 struct psp_context *psp = &adev->psp; 468 int ret; 469 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 470 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 471 struct psp_runtime_scpm_entry scpm_entry; 472 473 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 474 if (!psp->cmd) { 475 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 476 return -ENOMEM; 477 } 478 479 adev->psp.xgmi_context.supports_extended_data = 480 !adev->gmc.xgmi.connected_to_cpu && 481 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 482 483 memset(&scpm_entry, 0, sizeof(scpm_entry)); 484 if ((psp_get_runtime_db_entry(adev, 485 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 486 &scpm_entry)) && 487 (scpm_entry.scpm_status != SCPM_DISABLE)) { 488 adev->scpm_enabled = true; 489 adev->scpm_status = scpm_entry.scpm_status; 490 } else { 491 adev->scpm_enabled = false; 492 adev->scpm_status = SCPM_DISABLE; 493 } 494 495 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 496 497 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 498 if (psp_get_runtime_db_entry(adev, 499 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 500 &boot_cfg_entry)) { 501 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 502 if ((psp->boot_cfg_bitmask) & 503 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 504 /* If psp runtime database exists, then 505 * only enable two stage memory training 506 * when TWO_STAGE_DRAM_TRAINING bit is set 507 * in runtime database 508 */ 509 mem_training_ctx->enable_mem_training = true; 510 } 511 512 } else { 513 /* If psp runtime database doesn't exist or is 514 * invalid, force enable two stage memory training 515 */ 516 mem_training_ctx->enable_mem_training = true; 517 } 518 519 if (mem_training_ctx->enable_mem_training) { 520 ret = psp_memory_training_init(psp); 521 if (ret) { 522 dev_err(adev->dev, "Failed to initialize memory training!\n"); 523 return ret; 524 } 525 526 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 527 if (ret) { 528 dev_err(adev->dev, "Failed to process memory training!\n"); 529 return ret; 530 } 531 } 532 533 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 534 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 535 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 536 &psp->fw_pri_bo, 537 &psp->fw_pri_mc_addr, 538 &psp->fw_pri_buf); 539 if (ret) 540 return ret; 541 542 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 543 AMDGPU_GEM_DOMAIN_VRAM | 544 AMDGPU_GEM_DOMAIN_GTT, 545 &psp->fence_buf_bo, 546 &psp->fence_buf_mc_addr, 547 &psp->fence_buf); 548 if (ret) 549 goto failed1; 550 551 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 552 AMDGPU_GEM_DOMAIN_VRAM | 553 AMDGPU_GEM_DOMAIN_GTT, 554 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 555 (void **)&psp->cmd_buf_mem); 556 if (ret) 557 goto failed2; 558 559 return 0; 560 561 failed2: 562 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 563 &psp->fence_buf_mc_addr, &psp->fence_buf); 564 failed1: 565 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 566 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 567 return ret; 568 } 569 570 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 571 { 572 struct amdgpu_device *adev = ip_block->adev; 573 struct psp_context *psp = &adev->psp; 574 575 psp_memory_training_fini(psp); 576 577 amdgpu_ucode_release(&psp->sos_fw); 578 amdgpu_ucode_release(&psp->asd_fw); 579 amdgpu_ucode_release(&psp->ta_fw); 580 amdgpu_ucode_release(&psp->cap_fw); 581 amdgpu_ucode_release(&psp->toc_fw); 582 583 kfree(psp->cmd); 584 psp->cmd = NULL; 585 586 psp_free_shared_bufs(psp); 587 588 if (psp->km_ring.ring_mem) 589 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 590 &psp->km_ring.ring_mem_mc_addr, 591 (void **)&psp->km_ring.ring_mem); 592 593 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 594 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 595 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 596 &psp->fence_buf_mc_addr, &psp->fence_buf); 597 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 598 (void **)&psp->cmd_buf_mem); 599 600 return 0; 601 } 602 603 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 604 uint32_t mask, uint32_t flags) 605 { 606 bool check_changed = flags & PSP_WAITREG_CHANGED; 607 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 608 uint32_t val; 609 int i; 610 struct amdgpu_device *adev = psp->adev; 611 612 if (psp->adev->no_hw_access) 613 return 0; 614 615 for (i = 0; i < adev->usec_timeout; i++) { 616 val = RREG32(reg_index); 617 if (check_changed) { 618 if (val != reg_val) 619 return 0; 620 } else { 621 if ((val & mask) == reg_val) 622 return 0; 623 } 624 udelay(1); 625 } 626 627 if (verbose) 628 dev_err(adev->dev, 629 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 630 reg_index, mask, val, reg_val); 631 632 return -ETIME; 633 } 634 635 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 636 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 637 { 638 uint32_t val; 639 int i; 640 struct amdgpu_device *adev = psp->adev; 641 642 if (psp->adev->no_hw_access) 643 return 0; 644 645 for (i = 0; i < msec_timeout; i++) { 646 val = RREG32(reg_index); 647 if ((val & mask) == reg_val) 648 return 0; 649 msleep(1); 650 } 651 652 return -ETIME; 653 } 654 655 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 656 { 657 switch (cmd_id) { 658 case GFX_CMD_ID_LOAD_TA: 659 return "LOAD_TA"; 660 case GFX_CMD_ID_UNLOAD_TA: 661 return "UNLOAD_TA"; 662 case GFX_CMD_ID_INVOKE_CMD: 663 return "INVOKE_CMD"; 664 case GFX_CMD_ID_LOAD_ASD: 665 return "LOAD_ASD"; 666 case GFX_CMD_ID_SETUP_TMR: 667 return "SETUP_TMR"; 668 case GFX_CMD_ID_LOAD_IP_FW: 669 return "LOAD_IP_FW"; 670 case GFX_CMD_ID_DESTROY_TMR: 671 return "DESTROY_TMR"; 672 case GFX_CMD_ID_SAVE_RESTORE: 673 return "SAVE_RESTORE_IP_FW"; 674 case GFX_CMD_ID_SETUP_VMR: 675 return "SETUP_VMR"; 676 case GFX_CMD_ID_DESTROY_VMR: 677 return "DESTROY_VMR"; 678 case GFX_CMD_ID_PROG_REG: 679 return "PROG_REG"; 680 case GFX_CMD_ID_GET_FW_ATTESTATION: 681 return "GET_FW_ATTESTATION"; 682 case GFX_CMD_ID_LOAD_TOC: 683 return "ID_LOAD_TOC"; 684 case GFX_CMD_ID_AUTOLOAD_RLC: 685 return "AUTOLOAD_RLC"; 686 case GFX_CMD_ID_BOOT_CFG: 687 return "BOOT_CFG"; 688 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 689 return "CONFIG_SQ_PERFMON"; 690 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 691 return "FB_FW_RESERV_ADDR"; 692 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 693 return "FB_FW_RESERV_EXT_ADDR"; 694 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 695 return "SPATIAL_PARTITION"; 696 case GFX_CMD_ID_FB_NPS_MODE: 697 return "NPS_MODE_CHANGE"; 698 case GFX_CMD_ID_PERF_HW: 699 return "PERF MONITORING HW"; 700 default: 701 return "UNKNOWN CMD"; 702 } 703 } 704 705 static bool psp_err_warn(struct psp_context *psp) 706 { 707 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 708 709 /* This response indicates reg list is already loaded */ 710 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 711 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 712 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 713 cmd->resp.status == TEE_ERROR_CANCEL) 714 return false; 715 716 return true; 717 } 718 719 static int 720 psp_cmd_submit_buf(struct psp_context *psp, 721 struct amdgpu_firmware_info *ucode, 722 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 723 { 724 int ret; 725 int index; 726 int timeout = psp->adev->psp_timeout; 727 bool ras_intr = false; 728 bool skip_unsupport = false; 729 730 if (psp->adev->no_hw_access) 731 return 0; 732 733 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 734 735 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 736 737 index = atomic_inc_return(&psp->fence_value); 738 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 739 if (ret) { 740 atomic_dec(&psp->fence_value); 741 goto exit; 742 } 743 744 amdgpu_device_invalidate_hdp(psp->adev, NULL); 745 while (*((unsigned int *)psp->fence_buf) != index) { 746 if (--timeout == 0) 747 break; 748 /* 749 * Shouldn't wait for timeout when err_event_athub occurs, 750 * because gpu reset thread triggered and lock resource should 751 * be released for psp resume sequence. 752 */ 753 ras_intr = amdgpu_ras_intr_triggered(); 754 if (ras_intr) 755 break; 756 usleep_range(60, 100); 757 amdgpu_device_invalidate_hdp(psp->adev, NULL); 758 } 759 760 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 761 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 762 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 763 764 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 765 766 /* In some cases, psp response status is not 0 even there is no 767 * problem while the command is submitted. Some version of PSP FW 768 * doesn't write 0 to that field. 769 * So here we would like to only print a warning instead of an error 770 * during psp initialization to avoid breaking hw_init and it doesn't 771 * return -EINVAL. 772 */ 773 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 774 if (ucode) 775 dev_warn(psp->adev->dev, 776 "failed to load ucode %s(0x%X) ", 777 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 778 if (psp_err_warn(psp)) 779 dev_warn( 780 psp->adev->dev, 781 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 782 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 783 psp->cmd_buf_mem->cmd_id, 784 psp->cmd_buf_mem->resp.status); 785 /* If any firmware (including CAP) load fails under SRIOV, it should 786 * return failure to stop the VF from initializing. 787 * Also return failure in case of timeout 788 */ 789 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 790 ret = -EINVAL; 791 goto exit; 792 } 793 } 794 795 if (ucode) { 796 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 797 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 798 } 799 800 exit: 801 return ret; 802 } 803 804 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 805 { 806 struct psp_gfx_cmd_resp *cmd = psp->cmd; 807 808 mutex_lock(&psp->mutex); 809 810 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 811 812 return cmd; 813 } 814 815 static void release_psp_cmd_buf(struct psp_context *psp) 816 { 817 mutex_unlock(&psp->mutex); 818 } 819 820 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 821 struct psp_gfx_cmd_resp *cmd, 822 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 823 { 824 struct amdgpu_device *adev = psp->adev; 825 uint32_t size = 0; 826 uint64_t tmr_pa = 0; 827 828 if (tmr_bo) { 829 size = amdgpu_bo_size(tmr_bo); 830 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 831 } 832 833 if (amdgpu_sriov_vf(psp->adev)) 834 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 835 else 836 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 837 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 838 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 839 cmd->cmd.cmd_setup_tmr.buf_size = size; 840 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 841 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 842 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 843 } 844 845 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 846 uint64_t pri_buf_mc, uint32_t size) 847 { 848 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 849 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 850 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 851 cmd->cmd.cmd_load_toc.toc_size = size; 852 } 853 854 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 855 static int psp_load_toc(struct psp_context *psp, 856 uint32_t *tmr_size) 857 { 858 int ret; 859 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 860 861 /* Copy toc to psp firmware private buffer */ 862 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 863 if (ret) { 864 release_psp_cmd_buf(psp); 865 return ret; 866 } 867 868 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 869 870 ret = psp_cmd_submit_buf(psp, NULL, cmd, 871 psp->fence_buf_mc_addr); 872 if (!ret) 873 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 874 875 release_psp_cmd_buf(psp); 876 877 return ret; 878 } 879 880 /* Set up Trusted Memory Region */ 881 static int psp_tmr_init(struct psp_context *psp) 882 { 883 int ret = 0; 884 int tmr_size; 885 void *tmr_buf; 886 void **pptr; 887 888 /* 889 * According to HW engineer, they prefer the TMR address be "naturally 890 * aligned" , e.g. the start address be an integer divide of TMR size. 891 * 892 * Note: this memory need be reserved till the driver 893 * uninitializes. 894 */ 895 tmr_size = PSP_TMR_SIZE(psp->adev); 896 897 /* For ASICs support RLC autoload, psp will parse the toc 898 * and calculate the total size of TMR needed 899 */ 900 if (!amdgpu_sriov_vf(psp->adev) && 901 psp->toc.start_addr && 902 psp->toc.size_bytes && 903 psp->fw_pri_buf) { 904 ret = psp_load_toc(psp, &tmr_size); 905 if (ret) { 906 dev_err(psp->adev->dev, "Failed to load toc\n"); 907 return ret; 908 } 909 } 910 911 if (!psp->tmr_bo && !psp->boot_time_tmr) { 912 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 913 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 914 PSP_TMR_ALIGNMENT, 915 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 916 &psp->tmr_bo, &psp->tmr_mc_addr, 917 pptr); 918 } 919 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 920 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 921 922 return ret; 923 } 924 925 static bool psp_skip_tmr(struct psp_context *psp) 926 { 927 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 928 929 if (amdgpu_sriov_vf(psp->adev)) 930 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 931 else 932 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 933 } 934 935 static int psp_tmr_load(struct psp_context *psp) 936 { 937 int ret; 938 struct psp_gfx_cmd_resp *cmd; 939 940 if (psp_skip_tmr(psp)) 941 return 0; 942 943 cmd = acquire_psp_cmd_buf(psp); 944 945 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 946 if (psp->tmr_bo) 947 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 948 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 949 950 ret = psp_cmd_submit_buf(psp, NULL, cmd, 951 psp->fence_buf_mc_addr); 952 953 release_psp_cmd_buf(psp); 954 955 return ret; 956 } 957 958 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 959 struct psp_gfx_cmd_resp *cmd) 960 { 961 if (amdgpu_sriov_vf(psp->adev)) 962 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 963 else 964 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 965 } 966 967 static int psp_tmr_unload(struct psp_context *psp) 968 { 969 int ret; 970 struct psp_gfx_cmd_resp *cmd; 971 972 if (psp_skip_tmr(psp)) 973 return 0; 974 975 cmd = acquire_psp_cmd_buf(psp); 976 977 psp_prep_tmr_unload_cmd_buf(psp, cmd); 978 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 979 980 ret = psp_cmd_submit_buf(psp, NULL, cmd, 981 psp->fence_buf_mc_addr); 982 983 release_psp_cmd_buf(psp); 984 985 return ret; 986 } 987 988 static int psp_tmr_terminate(struct psp_context *psp) 989 { 990 return psp_tmr_unload(psp); 991 } 992 993 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 994 uint64_t *output_ptr) 995 { 996 int ret; 997 struct psp_gfx_cmd_resp *cmd; 998 999 if (!output_ptr) 1000 return -EINVAL; 1001 1002 if (amdgpu_sriov_vf(psp->adev)) 1003 return 0; 1004 1005 cmd = acquire_psp_cmd_buf(psp); 1006 1007 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1008 1009 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1010 psp->fence_buf_mc_addr); 1011 1012 if (!ret) { 1013 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1014 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1015 } 1016 1017 release_psp_cmd_buf(psp); 1018 1019 return ret; 1020 } 1021 1022 static int psp_get_fw_reservation_info(struct psp_context *psp, 1023 uint32_t cmd_id, 1024 uint64_t *addr, 1025 uint32_t *size) 1026 { 1027 int ret; 1028 uint32_t status; 1029 struct psp_gfx_cmd_resp *cmd; 1030 1031 cmd = acquire_psp_cmd_buf(psp); 1032 1033 cmd->cmd_id = cmd_id; 1034 1035 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1036 psp->fence_buf_mc_addr); 1037 if (ret) { 1038 release_psp_cmd_buf(psp); 1039 return ret; 1040 } 1041 1042 status = cmd->resp.status; 1043 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1044 release_psp_cmd_buf(psp); 1045 *addr = 0; 1046 *size = 0; 1047 return 0; 1048 } 1049 1050 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1051 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1052 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1053 1054 release_psp_cmd_buf(psp); 1055 1056 return 0; 1057 } 1058 1059 int psp_update_fw_reservation(struct psp_context *psp) 1060 { 1061 int ret; 1062 uint64_t reserv_addr, reserv_addr_ext; 1063 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1064 struct amdgpu_device *adev = psp->adev; 1065 1066 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1067 1068 if (amdgpu_sriov_vf(psp->adev)) 1069 return 0; 1070 1071 switch (mp0_ip_ver) { 1072 case IP_VERSION(14, 0, 2): 1073 if (adev->psp.sos.fw_version < 0x3b0e0d) 1074 return 0; 1075 break; 1076 1077 case IP_VERSION(14, 0, 3): 1078 if (adev->psp.sos.fw_version < 0x3a0e14) 1079 return 0; 1080 break; 1081 1082 default: 1083 return 0; 1084 } 1085 1086 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1087 if (ret) 1088 return ret; 1089 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1090 if (ret) 1091 return ret; 1092 1093 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1094 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1095 return 0; 1096 } 1097 1098 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1099 1100 reserv_size = roundup(reserv_size, SZ_1M); 1101 1102 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1103 reserv_addr, reserv_size, false); 1104 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1105 if (ret) { 1106 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1107 return ret; 1108 } 1109 1110 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1111 1112 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1113 reserv_addr_ext, reserv_size_ext, false); 1114 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1115 if (ret) { 1116 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1124 { 1125 struct psp_context *psp = &adev->psp; 1126 struct psp_gfx_cmd_resp *cmd; 1127 int ret; 1128 1129 if (amdgpu_sriov_vf(adev)) 1130 return 0; 1131 1132 cmd = acquire_psp_cmd_buf(psp); 1133 1134 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1135 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1136 1137 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1138 if (!ret) { 1139 *boot_cfg = 1140 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1141 } 1142 1143 release_psp_cmd_buf(psp); 1144 1145 return ret; 1146 } 1147 1148 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1149 { 1150 int ret; 1151 struct psp_context *psp = &adev->psp; 1152 struct psp_gfx_cmd_resp *cmd; 1153 1154 if (amdgpu_sriov_vf(adev)) 1155 return 0; 1156 1157 cmd = acquire_psp_cmd_buf(psp); 1158 1159 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1160 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1161 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1162 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1163 1164 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1165 1166 release_psp_cmd_buf(psp); 1167 1168 return ret; 1169 } 1170 1171 static int psp_rl_load(struct amdgpu_device *adev) 1172 { 1173 int ret; 1174 struct psp_context *psp = &adev->psp; 1175 struct psp_gfx_cmd_resp *cmd; 1176 1177 if (!is_psp_fw_valid(psp->rl)) 1178 return 0; 1179 1180 cmd = acquire_psp_cmd_buf(psp); 1181 1182 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1183 if (ret) { 1184 release_psp_cmd_buf(psp); 1185 return ret; 1186 } 1187 1188 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1189 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1190 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1191 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1192 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1193 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1195 1196 release_psp_cmd_buf(psp); 1197 1198 return ret; 1199 } 1200 1201 int psp_memory_partition(struct psp_context *psp, int mode) 1202 { 1203 struct psp_gfx_cmd_resp *cmd; 1204 int ret; 1205 1206 if (amdgpu_sriov_vf(psp->adev)) 1207 return 0; 1208 1209 cmd = acquire_psp_cmd_buf(psp); 1210 1211 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1212 cmd->cmd.cmd_memory_part.mode = mode; 1213 1214 dev_info(psp->adev->dev, 1215 "Requesting %d memory partition change through PSP", mode); 1216 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1217 if (ret) 1218 dev_err(psp->adev->dev, 1219 "PSP request failed to change to NPS%d mode\n", mode); 1220 1221 release_psp_cmd_buf(psp); 1222 1223 return ret; 1224 } 1225 1226 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev) 1227 { 1228 int ret; 1229 struct psp_context *psp = &adev->psp; 1230 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1231 1232 cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL; 1233 1234 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1235 if (ret) { 1236 dev_err(psp->adev->dev, 1237 "PSP request failed to set mmuhub eco sec level with ret=%d\n", ret); 1238 release_psp_cmd_buf(psp); 1239 return ret; 1240 } 1241 1242 if (cmd->resp.status) { 1243 dev_err(psp->adev->dev, 1244 "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response status: 0x%X\n", 1245 cmd->cmd_id, cmd->resp.status); 1246 ret = -EIO; 1247 } 1248 release_psp_cmd_buf(psp); 1249 1250 return ret; 1251 } 1252 1253 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1254 uint32_t *ptl_fmt) 1255 { 1256 struct amdgpu_device *adev = psp->adev; 1257 1258 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1259 return -EINVAL; 1260 1261 switch (fmt) { 1262 case AMDGPU_PTL_FMT_I8: 1263 *ptl_fmt = GFX_FTYPE_I8; 1264 break; 1265 case AMDGPU_PTL_FMT_F16: 1266 *ptl_fmt = GFX_FTYPE_F16; 1267 break; 1268 case AMDGPU_PTL_FMT_BF16: 1269 *ptl_fmt = GFX_FTYPE_BF16; 1270 break; 1271 case AMDGPU_PTL_FMT_F32: 1272 *ptl_fmt = GFX_FTYPE_F32; 1273 break; 1274 case AMDGPU_PTL_FMT_F64: 1275 *ptl_fmt = GFX_FTYPE_F64; 1276 break; 1277 case AMDGPU_PTL_FMT_F8: 1278 *ptl_fmt = GFX_FTYPE_F8; 1279 break; 1280 case AMDGPU_PTL_FMT_VECTOR: 1281 *ptl_fmt = GFX_FTYPE_VECTOR; 1282 break; 1283 default: 1284 return -EINVAL; 1285 } 1286 1287 return 0; 1288 } 1289 1290 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1291 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1292 { 1293 struct psp_gfx_cmd_resp *cmd; 1294 struct amdgpu_ptl *ptl = &psp->ptl; 1295 int ret; 1296 1297 cmd = acquire_psp_cmd_buf(psp); 1298 1299 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1300 cmd->cmd.cmd_req_perf_hw.req = req_code; 1301 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1302 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1303 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1304 1305 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1306 if (ret) 1307 goto out; 1308 1309 /* 1310 * Check response status explicitly to avoid 1311 * updating cached PTL state with invalid data. 1312 */ 1313 if (cmd->resp.status) { 1314 dev_err(psp->adev->dev, 1315 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1316 req_code, cmd->resp.status, 1317 cmd->resp.uresp.perf_hw_info.resp); 1318 ret = -EIO; 1319 goto out; 1320 } 1321 1322 /* Parse response */ 1323 switch (req_code) { 1324 case PSP_PTL_PERF_MON_QUERY: 1325 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1326 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1327 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1328 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1329 *ptl_state, *fmt1, *fmt2); 1330 break; 1331 case PSP_PTL_PERF_MON_SET: 1332 /* Update cached state only on success */ 1333 ptl->enabled = *ptl_state; 1334 ptl->fmt1 = *fmt1; 1335 ptl->fmt2 = *fmt2; 1336 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1337 *ptl_state, *fmt1, *fmt2); 1338 break; 1339 } 1340 1341 out: 1342 release_psp_cmd_buf(psp); 1343 return ret; 1344 } 1345 1346 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1347 uint32_t *ptl_state, 1348 enum amdgpu_ptl_fmt *fmt1, 1349 enum amdgpu_ptl_fmt *fmt2) 1350 { 1351 uint32_t ptl_fmt1, ptl_fmt2; 1352 struct psp_context *psp; 1353 struct amdgpu_ptl *ptl; 1354 int ret; 1355 1356 if (!adev || !ptl_state || !fmt1 || !fmt2) 1357 return -EINVAL; 1358 1359 if (amdgpu_sriov_vf(adev)) 1360 return 0; 1361 1362 psp = &adev->psp; 1363 ptl = &psp->ptl; 1364 1365 if (ptl->permanently_disabled && *ptl_state == 1) 1366 return 0; 1367 1368 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1369 psp->sos.fw_version < 0x0036081a) 1370 return -EOPNOTSUPP; 1371 1372 /* Verify formats */ 1373 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1374 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1375 return -EINVAL; 1376 1377 /* 1378 * Add check to skip if state and formats are identical to current ones 1379 */ 1380 if (req_code == PSP_PTL_PERF_MON_SET && 1381 ptl->enabled == *ptl_state && 1382 ptl->fmt1 == ptl_fmt1 && 1383 ptl->fmt2 == ptl_fmt2) 1384 return 0; 1385 1386 /* If enabling PTL, check disable bitmap */ 1387 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1388 if (!bitmap_empty(ptl->disable_bitmap, 1389 AMDGPU_PTL_DISABLE_MAX)) { 1390 dev_dbg(adev->dev, 1391 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1392 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1393 ptl->disable_bitmap), 1394 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1395 ptl->disable_bitmap), 1396 atomic_read(&ptl->disable_ref)); 1397 return 0; 1398 } 1399 } 1400 1401 if (req_code == PSP_PTL_PERF_MON_SET) { 1402 amdgpu_amdkfd_stop_sched_all(adev); 1403 /* Wait for GFX engine idle before PTL state transition */ 1404 ret = amdgpu_device_ip_wait_for_idle(adev, 1405 AMD_IP_BLOCK_TYPE_GFX); 1406 if (ret) { 1407 amdgpu_amdkfd_start_sched_all(adev); 1408 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1409 return ret; 1410 } 1411 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1412 amdgpu_amdkfd_start_sched_all(adev); 1413 } else { 1414 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1415 } 1416 1417 return ret; 1418 } 1419 1420 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1421 { 1422 int i; 1423 1424 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1425 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1426 return (enum amdgpu_ptl_fmt)i; 1427 } 1428 1429 return AMDGPU_PTL_FMT_INVALID; 1430 } 1431 1432 static ssize_t ptl_supported_formats_show(struct device *dev, 1433 struct device_attribute *attr, char *buf) 1434 { 1435 ssize_t len = 0; 1436 1437 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1438 const char *fmt = amdgpu_ptl_fmt_str[i]; 1439 1440 len += sysfs_emit_at(buf, len, "%s%s", 1441 fmt ? fmt : "UNKNOWN", 1442 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1443 } 1444 1445 return len; 1446 } 1447 1448 static ssize_t ptl_enable_store(struct device *dev, 1449 struct device_attribute *attr, 1450 const char *buf, size_t count) 1451 { 1452 struct drm_device *ddev = dev_get_drvdata(dev); 1453 struct amdgpu_device *adev = drm_to_adev(ddev); 1454 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1455 uint32_t ptl_state, fmt1, fmt2; 1456 int ret; 1457 bool enable; 1458 bool bit_changed = false; 1459 1460 mutex_lock(&ptl->mutex); 1461 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1462 enable = true; 1463 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1464 enable = false; 1465 } else { 1466 mutex_unlock(&ptl->mutex); 1467 return -EINVAL; 1468 } 1469 1470 /* Block enable when permanently disabled */ 1471 if (ptl->permanently_disabled) { 1472 mutex_unlock(&ptl->mutex); 1473 return -EPERM; 1474 } 1475 1476 fmt1 = ptl->fmt1; 1477 fmt2 = ptl->fmt2; 1478 ptl_state = enable ? 1 : 0; 1479 1480 if (enable) 1481 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1482 ptl->disable_bitmap); 1483 1484 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1485 if (ret) { 1486 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1487 if (enable && bit_changed) 1488 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1489 mutex_unlock(&ptl->mutex); 1490 return ret; 1491 } 1492 1493 if (!enable) 1494 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1495 1496 mutex_unlock(&ptl->mutex); 1497 1498 return count; 1499 } 1500 1501 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1502 { 1503 struct drm_device *ddev = dev_get_drvdata(dev); 1504 struct amdgpu_device *adev = drm_to_adev(ddev); 1505 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1506 1507 if (ptl->permanently_disabled) 1508 return sysfs_emit(buf, "permanently disabled\n"); 1509 1510 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1511 } 1512 1513 static ssize_t ptl_format_store(struct device *dev, 1514 struct device_attribute *attr, 1515 const char *buf, size_t count) 1516 { 1517 struct drm_device *ddev = dev_get_drvdata(dev); 1518 struct amdgpu_device *adev = drm_to_adev(ddev); 1519 char fmt1_str[8], fmt2_str[8]; 1520 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1521 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1522 uint32_t ptl_state, fmt1, fmt2; 1523 int ret; 1524 1525 /* Only allow format update when PTL is enabled */ 1526 if (!ptl->enabled) 1527 return -EPERM; 1528 1529 mutex_lock(&ptl->mutex); 1530 /* Parse input, expecting "FMT1,FMT2" */ 1531 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1532 mutex_unlock(&ptl->mutex); 1533 return -EINVAL; 1534 } 1535 1536 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1537 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1538 1539 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1540 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1541 fmt1_enum == fmt2_enum) { 1542 mutex_unlock(&ptl->mutex); 1543 return -EINVAL; 1544 } 1545 1546 ptl_state = ptl->enabled; 1547 fmt1 = fmt1_enum; 1548 fmt2 = fmt2_enum; 1549 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1550 if (ret) { 1551 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1552 mutex_unlock(&ptl->mutex); 1553 return ret; 1554 } 1555 mutex_unlock(&ptl->mutex); 1556 1557 return count; 1558 } 1559 1560 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1561 { 1562 struct drm_device *ddev = dev_get_drvdata(dev); 1563 struct amdgpu_device *adev = drm_to_adev(ddev); 1564 struct psp_context *psp = &adev->psp; 1565 1566 return sysfs_emit(buf, "%s,%s\n", 1567 amdgpu_ptl_fmt_str[psp->ptl.fmt1], 1568 amdgpu_ptl_fmt_str[psp->ptl.fmt2]); 1569 } 1570 1571 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1572 { 1573 struct device *dev = kobj_to_dev(kobj); 1574 struct drm_device *ddev = dev_get_drvdata(dev); 1575 struct amdgpu_device *adev = drm_to_adev(ddev); 1576 1577 /* Only show PTL sysfs files if PTL hardware is supported */ 1578 if (!adev->psp.ptl.hw_supported) 1579 return 0; 1580 1581 return attr->mode; 1582 } 1583 1584 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1585 { 1586 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1587 int ret; 1588 1589 if (!ptl->hw_supported) 1590 return 0; 1591 1592 if (ptl->ptl_sysfs_created) 1593 return 0; 1594 1595 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1596 if (!ret) 1597 ptl->ptl_sysfs_created = true; 1598 1599 return ret; 1600 } 1601 1602 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1603 { 1604 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1605 1606 if (!ptl->hw_supported) 1607 return; 1608 1609 if (!ptl->ptl_sysfs_created) 1610 return; 1611 1612 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1613 ptl->ptl_sysfs_created = false; 1614 } 1615 1616 int psp_spatial_partition(struct psp_context *psp, int mode) 1617 { 1618 struct psp_gfx_cmd_resp *cmd; 1619 int ret; 1620 1621 if (amdgpu_sriov_vf(psp->adev)) 1622 return 0; 1623 1624 cmd = acquire_psp_cmd_buf(psp); 1625 1626 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1627 cmd->cmd.cmd_spatial_part.mode = mode; 1628 1629 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1630 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1631 1632 release_psp_cmd_buf(psp); 1633 1634 return ret; 1635 } 1636 1637 static int psp_asd_initialize(struct psp_context *psp) 1638 { 1639 int ret; 1640 1641 /* If PSP version doesn't match ASD version, asd loading will be failed. 1642 * add workaround to bypass it for sriov now. 1643 * TODO: add version check to make it common 1644 */ 1645 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1646 return 0; 1647 1648 /* bypass asd if display hardware is not available */ 1649 if (!amdgpu_device_has_display_hardware(psp->adev) && 1650 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1651 return 0; 1652 1653 psp->asd_context.mem_context.shared_mc_addr = 0; 1654 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1655 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1656 1657 ret = psp_ta_load(psp, &psp->asd_context); 1658 if (!ret) 1659 psp->asd_context.initialized = true; 1660 1661 return ret; 1662 } 1663 1664 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1665 uint32_t session_id) 1666 { 1667 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1668 cmd->cmd.cmd_unload_ta.session_id = session_id; 1669 } 1670 1671 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1672 { 1673 int ret; 1674 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1675 1676 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1677 1678 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1679 1680 context->resp_status = cmd->resp.status; 1681 1682 release_psp_cmd_buf(psp); 1683 1684 return ret; 1685 } 1686 1687 static int psp_asd_terminate(struct psp_context *psp) 1688 { 1689 int ret; 1690 1691 if (amdgpu_sriov_vf(psp->adev)) 1692 return 0; 1693 1694 if (!psp->asd_context.initialized) 1695 return 0; 1696 1697 ret = psp_ta_unload(psp, &psp->asd_context); 1698 if (!ret) 1699 psp->asd_context.initialized = false; 1700 1701 return ret; 1702 } 1703 1704 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1705 uint32_t id, uint32_t value) 1706 { 1707 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1708 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1709 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1710 } 1711 1712 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1713 uint32_t value) 1714 { 1715 struct psp_gfx_cmd_resp *cmd; 1716 int ret = 0; 1717 1718 if (reg >= PSP_REG_LAST) 1719 return -EINVAL; 1720 1721 cmd = acquire_psp_cmd_buf(psp); 1722 1723 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1724 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1725 if (ret) 1726 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1727 1728 release_psp_cmd_buf(psp); 1729 1730 return ret; 1731 } 1732 1733 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1734 uint64_t ta_bin_mc, 1735 struct ta_context *context) 1736 { 1737 cmd->cmd_id = context->ta_load_type; 1738 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1739 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1740 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1741 1742 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1743 lower_32_bits(context->mem_context.shared_mc_addr); 1744 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1745 upper_32_bits(context->mem_context.shared_mc_addr); 1746 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1747 } 1748 1749 int psp_ta_init_shared_buf(struct psp_context *psp, 1750 struct ta_mem_context *mem_ctx) 1751 { 1752 /* 1753 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1754 * physical) for ta to host memory 1755 */ 1756 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1757 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1758 AMDGPU_GEM_DOMAIN_GTT, 1759 &mem_ctx->shared_bo, 1760 &mem_ctx->shared_mc_addr, 1761 &mem_ctx->shared_buf); 1762 } 1763 1764 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1765 uint32_t ta_cmd_id, 1766 uint32_t session_id) 1767 { 1768 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1769 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1770 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1771 } 1772 1773 int psp_ta_invoke(struct psp_context *psp, 1774 uint32_t ta_cmd_id, 1775 struct ta_context *context) 1776 { 1777 int ret; 1778 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1779 1780 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1781 1782 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1783 psp->fence_buf_mc_addr); 1784 1785 context->resp_status = cmd->resp.status; 1786 1787 release_psp_cmd_buf(psp); 1788 1789 return ret; 1790 } 1791 1792 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1793 { 1794 int ret; 1795 struct psp_gfx_cmd_resp *cmd; 1796 1797 cmd = acquire_psp_cmd_buf(psp); 1798 1799 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 1800 context->bin_desc.size_bytes); 1801 if (ret) { 1802 release_psp_cmd_buf(psp); 1803 return ret; 1804 } 1805 1806 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1807 context->mem_context.shared_bo) 1808 context->mem_context.shared_mc_addr = 1809 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1810 1811 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1812 1813 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1814 psp->fence_buf_mc_addr); 1815 1816 context->resp_status = cmd->resp.status; 1817 1818 if (!ret) 1819 context->session_id = cmd->resp.session_id; 1820 1821 release_psp_cmd_buf(psp); 1822 1823 return ret; 1824 } 1825 1826 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1827 { 1828 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1829 } 1830 1831 int psp_xgmi_terminate(struct psp_context *psp) 1832 { 1833 int ret; 1834 struct amdgpu_device *adev = psp->adev; 1835 1836 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1837 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1838 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1839 adev->gmc.xgmi.connected_to_cpu)) 1840 return 0; 1841 1842 if (!psp->xgmi_context.context.initialized) 1843 return 0; 1844 1845 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1846 1847 psp->xgmi_context.context.initialized = false; 1848 1849 return ret; 1850 } 1851 1852 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1853 { 1854 struct ta_xgmi_shared_memory *xgmi_cmd; 1855 int ret; 1856 1857 if (!psp->ta_fw || 1858 !psp->xgmi_context.context.bin_desc.size_bytes || 1859 !psp->xgmi_context.context.bin_desc.start_addr) 1860 return -ENOENT; 1861 1862 if (!load_ta) 1863 goto invoke; 1864 1865 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1866 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1867 1868 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1869 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1870 if (ret) 1871 return ret; 1872 } 1873 1874 /* Load XGMI TA */ 1875 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1876 if (!ret) 1877 psp->xgmi_context.context.initialized = true; 1878 else 1879 return ret; 1880 1881 invoke: 1882 /* Initialize XGMI session */ 1883 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1884 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1885 xgmi_cmd->flag_extend_link_record = set_extended_data; 1886 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1887 1888 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1889 /* note down the capbility flag for XGMI TA */ 1890 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1891 1892 return ret; 1893 } 1894 1895 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1896 { 1897 struct ta_xgmi_shared_memory *xgmi_cmd; 1898 int ret; 1899 1900 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1901 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1902 1903 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1904 1905 /* Invoke xgmi ta to get hive id */ 1906 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1907 if (ret) 1908 return ret; 1909 1910 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1911 1912 return 0; 1913 } 1914 1915 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1916 { 1917 struct ta_xgmi_shared_memory *xgmi_cmd; 1918 int ret; 1919 1920 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1921 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1922 1923 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1924 1925 /* Invoke xgmi ta to get the node id */ 1926 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1927 if (ret) 1928 return ret; 1929 1930 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1931 1932 return 0; 1933 } 1934 1935 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1936 { 1937 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1938 IP_VERSION(13, 0, 2) && 1939 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1940 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1941 IP_VERSION(13, 0, 6); 1942 } 1943 1944 /* 1945 * Chips that support extended topology information require the driver to 1946 * reflect topology information in the opposite direction. This is 1947 * because the TA has already exceeded its link record limit and if the 1948 * TA holds bi-directional information, the driver would have to do 1949 * multiple fetches instead of just two. 1950 */ 1951 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1952 struct psp_xgmi_node_info node_info) 1953 { 1954 struct amdgpu_device *mirror_adev; 1955 struct amdgpu_hive_info *hive; 1956 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1957 uint64_t dst_node_id = node_info.node_id; 1958 uint8_t dst_num_hops = node_info.num_hops; 1959 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1960 uint8_t dst_num_links = node_info.num_links; 1961 1962 hive = amdgpu_get_xgmi_hive(psp->adev); 1963 if (WARN_ON(!hive)) 1964 return; 1965 1966 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1967 struct psp_xgmi_topology_info *mirror_top_info; 1968 int j; 1969 1970 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1971 continue; 1972 1973 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1974 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1975 if (mirror_top_info->nodes[j].node_id != src_node_id) 1976 continue; 1977 1978 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1979 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1980 /* prevent 0 num_links value re-reflection since reflection 1981 * criteria is based on num_hops (direct or indirect). 1982 */ 1983 if (dst_num_links) { 1984 mirror_top_info->nodes[j].num_links = dst_num_links; 1985 /* swap src and dst due to frame of reference */ 1986 for (int k = 0; k < dst_num_links; k++) { 1987 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1988 node_info.port_num[k].dst_xgmi_port_num; 1989 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1990 node_info.port_num[k].src_xgmi_port_num; 1991 } 1992 } 1993 1994 break; 1995 } 1996 1997 break; 1998 } 1999 2000 amdgpu_put_xgmi_hive(hive); 2001 } 2002 2003 int psp_xgmi_get_topology_info(struct psp_context *psp, 2004 int number_devices, 2005 struct psp_xgmi_topology_info *topology, 2006 bool get_extended_data) 2007 { 2008 struct ta_xgmi_shared_memory *xgmi_cmd; 2009 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2010 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 2011 int i; 2012 int ret; 2013 2014 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2015 return -EINVAL; 2016 2017 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2018 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2019 xgmi_cmd->flag_extend_link_record = get_extended_data; 2020 2021 /* Fill in the shared memory with topology information as input */ 2022 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2023 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 2024 topology_info_input->num_nodes = number_devices; 2025 2026 for (i = 0; i < topology_info_input->num_nodes; i++) { 2027 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2028 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2029 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2030 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2031 } 2032 2033 /* Invoke xgmi ta to get the topology information */ 2034 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2035 if (ret) 2036 return ret; 2037 2038 /* Read the output topology information from the shared memory */ 2039 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2040 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2041 for (i = 0; i < topology->num_nodes; i++) { 2042 /* extended data will either be 0 or equal to non-extended data */ 2043 if (topology_info_output->nodes[i].num_hops) 2044 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2045 2046 /* non-extended data gets everything here so no need to update */ 2047 if (!get_extended_data) { 2048 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2049 topology->nodes[i].is_sharing_enabled = 2050 topology_info_output->nodes[i].is_sharing_enabled; 2051 topology->nodes[i].sdma_engine = 2052 topology_info_output->nodes[i].sdma_engine; 2053 } 2054 2055 } 2056 2057 /* Invoke xgmi ta again to get the link information */ 2058 if (psp_xgmi_peer_link_info_supported(psp)) { 2059 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2060 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2061 bool requires_reflection = 2062 (psp->xgmi_context.supports_extended_data && 2063 get_extended_data) || 2064 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2065 IP_VERSION(13, 0, 6) || 2066 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2067 IP_VERSION(13, 0, 14) || 2068 amdgpu_sriov_vf(psp->adev); 2069 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || 2070 amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 2071 2072 /* popluate the shared output buffer rather than the cmd input buffer 2073 * with node_ids as the input for GET_PEER_LINKS command execution. 2074 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2075 * The same requirement for GET_EXTEND_PEER_LINKS command. 2076 */ 2077 if (ta_port_num_support) { 2078 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2079 2080 for (i = 0; i < topology->num_nodes; i++) 2081 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2082 2083 link_extend_info_output->num_nodes = topology->num_nodes; 2084 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2085 } else { 2086 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2087 2088 for (i = 0; i < topology->num_nodes; i++) 2089 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2090 2091 link_info_output->num_nodes = topology->num_nodes; 2092 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2093 } 2094 2095 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2096 if (ret) 2097 return ret; 2098 2099 for (i = 0; i < topology->num_nodes; i++) { 2100 uint8_t node_num_links = ta_port_num_support ? 2101 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2102 /* accumulate num_links on extended data */ 2103 if (get_extended_data) { 2104 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2105 } else { 2106 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2107 topology->nodes[i].num_links : node_num_links; 2108 } 2109 /* popluate the connected port num info if supported and available */ 2110 if (ta_port_num_support && topology->nodes[i].num_links) { 2111 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2112 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2113 } 2114 2115 /* reflect the topology information for bi-directionality */ 2116 if (requires_reflection && topology->nodes[i].num_hops) 2117 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2118 } 2119 } 2120 2121 return 0; 2122 } 2123 2124 int psp_xgmi_set_topology_info(struct psp_context *psp, 2125 int number_devices, 2126 struct psp_xgmi_topology_info *topology) 2127 { 2128 struct ta_xgmi_shared_memory *xgmi_cmd; 2129 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2130 int i; 2131 2132 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2133 return -EINVAL; 2134 2135 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2136 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2137 2138 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2139 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2140 topology_info_input->num_nodes = number_devices; 2141 2142 for (i = 0; i < topology_info_input->num_nodes; i++) { 2143 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2144 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2145 topology_info_input->nodes[i].is_sharing_enabled = 1; 2146 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2147 } 2148 2149 /* Invoke xgmi ta to set topology information */ 2150 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2151 } 2152 2153 // ras begin 2154 static void psp_ras_ta_check_status(struct psp_context *psp) 2155 { 2156 struct ta_ras_shared_memory *ras_cmd = 2157 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2158 2159 switch (ras_cmd->ras_status) { 2160 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2161 dev_warn(psp->adev->dev, 2162 "RAS WARNING: cmd failed due to unsupported ip\n"); 2163 break; 2164 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2165 dev_warn(psp->adev->dev, 2166 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2167 break; 2168 case TA_RAS_STATUS__SUCCESS: 2169 break; 2170 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2171 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2172 dev_warn(psp->adev->dev, 2173 "RAS WARNING: Inject error to critical region is not allowed\n"); 2174 break; 2175 default: 2176 dev_warn(psp->adev->dev, 2177 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2178 break; 2179 } 2180 } 2181 2182 static int psp_ras_send_cmd(struct psp_context *psp, 2183 enum ras_command cmd_id, void *in, void *out) 2184 { 2185 struct ta_ras_shared_memory *ras_cmd; 2186 uint32_t cmd = cmd_id; 2187 int ret = 0; 2188 2189 if (!in) 2190 return -EINVAL; 2191 2192 mutex_lock(&psp->ras_context.mutex); 2193 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2194 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2195 2196 switch (cmd) { 2197 case TA_RAS_COMMAND__ENABLE_FEATURES: 2198 case TA_RAS_COMMAND__DISABLE_FEATURES: 2199 memcpy(&ras_cmd->ras_in_message, 2200 in, sizeof(ras_cmd->ras_in_message)); 2201 break; 2202 case TA_RAS_COMMAND__TRIGGER_ERROR: 2203 memcpy(&ras_cmd->ras_in_message.trigger_error, 2204 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2205 break; 2206 case TA_RAS_COMMAND__QUERY_ADDRESS: 2207 memcpy(&ras_cmd->ras_in_message.address, 2208 in, sizeof(ras_cmd->ras_in_message.address)); 2209 break; 2210 default: 2211 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2212 ret = -EINVAL; 2213 goto err_out; 2214 } 2215 2216 ras_cmd->cmd_id = cmd; 2217 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2218 2219 switch (cmd) { 2220 case TA_RAS_COMMAND__TRIGGER_ERROR: 2221 if (!ret && out) 2222 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2223 break; 2224 case TA_RAS_COMMAND__QUERY_ADDRESS: 2225 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2226 ret = -EINVAL; 2227 else if (out) 2228 memcpy(out, 2229 &ras_cmd->ras_out_message.address, 2230 sizeof(ras_cmd->ras_out_message.address)); 2231 break; 2232 default: 2233 break; 2234 } 2235 2236 err_out: 2237 mutex_unlock(&psp->ras_context.mutex); 2238 2239 return ret; 2240 } 2241 2242 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2243 { 2244 struct ta_ras_shared_memory *ras_cmd; 2245 int ret; 2246 2247 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2248 2249 /* 2250 * TODO: bypass the loading in sriov for now 2251 */ 2252 if (amdgpu_sriov_vf(psp->adev)) 2253 return 0; 2254 2255 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2256 2257 if (amdgpu_ras_intr_triggered()) 2258 return ret; 2259 2260 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2261 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2262 return -EINVAL; 2263 } 2264 2265 if (!ret) { 2266 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2267 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2268 2269 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2270 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2271 dev_warn(psp->adev->dev, 2272 "RAS internal register access blocked\n"); 2273 2274 psp_ras_ta_check_status(psp); 2275 } 2276 2277 return ret; 2278 } 2279 2280 int psp_ras_enable_features(struct psp_context *psp, 2281 union ta_ras_cmd_input *info, bool enable) 2282 { 2283 enum ras_command cmd_id; 2284 int ret; 2285 2286 if (!psp->ras_context.context.initialized || !info) 2287 return -EINVAL; 2288 2289 cmd_id = enable ? 2290 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2291 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2292 if (ret) 2293 return -EINVAL; 2294 2295 return 0; 2296 } 2297 2298 int psp_ras_terminate(struct psp_context *psp) 2299 { 2300 int ret; 2301 2302 /* 2303 * TODO: bypass the terminate in sriov for now 2304 */ 2305 if (amdgpu_sriov_vf(psp->adev)) 2306 return 0; 2307 2308 if (!psp->ras_context.context.initialized) 2309 return 0; 2310 2311 ret = psp_ta_unload(psp, &psp->ras_context.context); 2312 2313 psp->ras_context.context.initialized = false; 2314 2315 mutex_destroy(&psp->ras_context.mutex); 2316 2317 return ret; 2318 } 2319 2320 int psp_ras_initialize(struct psp_context *psp) 2321 { 2322 int ret; 2323 uint32_t boot_cfg = 0xFF; 2324 struct amdgpu_device *adev = psp->adev; 2325 struct ta_ras_shared_memory *ras_cmd; 2326 2327 /* 2328 * TODO: bypass the initialize in sriov for now 2329 */ 2330 if (amdgpu_sriov_vf(adev)) 2331 return 0; 2332 2333 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2334 !adev->psp.ras_context.context.bin_desc.start_addr) { 2335 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2336 return 0; 2337 } 2338 2339 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2340 /* query GECC enablement status from boot config 2341 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2342 */ 2343 ret = psp_boot_config_get(adev, &boot_cfg); 2344 if (ret) 2345 dev_warn(adev->dev, "PSP get boot config failed\n"); 2346 2347 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2348 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2349 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2350 dev_warn(adev->dev, 2351 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2352 } else { 2353 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2354 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2355 if (boot_cfg == 1) { 2356 dev_info(adev->dev, "GECC is enabled\n"); 2357 } else { 2358 /* enable GECC in next boot cycle if it is disabled 2359 * in boot config, or force enable GECC if failed to 2360 * get boot configuration 2361 */ 2362 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2363 if (ret) 2364 dev_warn(adev->dev, "PSP set boot config failed\n"); 2365 else 2366 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2367 } 2368 } else { 2369 if (!boot_cfg) { 2370 if (!adev->ras_default_ecc_enabled && 2371 amdgpu_ras_enable != 1 && 2372 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2373 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2374 else 2375 dev_info(adev->dev, "GECC is disabled\n"); 2376 } else { 2377 /* disable GECC in next boot cycle if ras is 2378 * disabled by module parameter amdgpu_ras_enable 2379 * and/or amdgpu_ras_mask, or boot_config_get call 2380 * is failed 2381 */ 2382 ret = psp_boot_config_set(adev, 0); 2383 if (ret) 2384 dev_warn(adev->dev, "PSP set boot config failed\n"); 2385 else 2386 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2387 } 2388 } 2389 } 2390 } 2391 2392 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2393 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2394 2395 if (!psp->ras_context.context.mem_context.shared_buf) { 2396 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2397 if (ret) 2398 return ret; 2399 } 2400 2401 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2402 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2403 2404 if (amdgpu_ras_is_poison_mode_supported(adev)) 2405 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2406 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2407 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2408 ras_cmd->ras_in_message.init_flags.xcc_mask = 2409 adev->gfx.xcc_mask; 2410 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2411 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2412 ras_cmd->ras_in_message.init_flags.nps_mode = 2413 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2414 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2415 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2416 2417 ret = psp_ta_load(psp, &psp->ras_context.context); 2418 2419 if (!ret && !ras_cmd->ras_status) { 2420 psp->ras_context.context.initialized = true; 2421 mutex_init(&psp->ras_context.mutex); 2422 } else { 2423 if (ras_cmd->ras_status) 2424 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2425 2426 /* fail to load RAS TA */ 2427 psp->ras_context.context.initialized = false; 2428 } 2429 2430 return ret; 2431 } 2432 2433 int psp_ras_trigger_error(struct psp_context *psp, 2434 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2435 { 2436 struct amdgpu_device *adev = psp->adev; 2437 int ret; 2438 uint32_t dev_mask; 2439 uint32_t ras_status = 0; 2440 2441 if (!psp->ras_context.context.initialized || !info) 2442 return -EINVAL; 2443 2444 switch (info->block_id) { 2445 case TA_RAS_BLOCK__GFX: 2446 dev_mask = GET_MASK(GC, instance_mask); 2447 break; 2448 case TA_RAS_BLOCK__SDMA: 2449 dev_mask = GET_MASK(SDMA0, instance_mask); 2450 break; 2451 case TA_RAS_BLOCK__VCN: 2452 case TA_RAS_BLOCK__JPEG: 2453 dev_mask = GET_MASK(VCN, instance_mask); 2454 break; 2455 default: 2456 dev_mask = instance_mask; 2457 break; 2458 } 2459 2460 /* reuse sub_block_index for backward compatibility */ 2461 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2462 dev_mask &= AMDGPU_RAS_INST_MASK; 2463 info->sub_block_index |= dev_mask; 2464 2465 ret = psp_ras_send_cmd(psp, 2466 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2467 if (ret) 2468 return -EINVAL; 2469 2470 /* If err_event_athub occurs error inject was successful, however 2471 * return status from TA is no long reliable 2472 */ 2473 if (amdgpu_ras_intr_triggered()) 2474 return 0; 2475 2476 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2477 return -EACCES; 2478 else if (ras_status) 2479 return -EINVAL; 2480 2481 return 0; 2482 } 2483 2484 int psp_ras_query_address(struct psp_context *psp, 2485 struct ta_ras_query_address_input *addr_in, 2486 struct ta_ras_query_address_output *addr_out) 2487 { 2488 int ret; 2489 2490 if (!psp->ras_context.context.initialized || 2491 !addr_in || !addr_out) 2492 return -EINVAL; 2493 2494 ret = psp_ras_send_cmd(psp, 2495 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2496 2497 return ret; 2498 } 2499 // ras end 2500 2501 // HDCP start 2502 static int psp_hdcp_initialize(struct psp_context *psp) 2503 { 2504 int ret; 2505 2506 /* 2507 * TODO: bypass the initialize in sriov for now 2508 */ 2509 if (amdgpu_sriov_vf(psp->adev)) 2510 return 0; 2511 2512 /* bypass hdcp initialization if dmu is harvested */ 2513 if (!amdgpu_device_has_display_hardware(psp->adev)) 2514 return 0; 2515 2516 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2517 !psp->hdcp_context.context.bin_desc.start_addr) { 2518 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2519 return 0; 2520 } 2521 2522 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2523 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2524 2525 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2526 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2527 if (ret) 2528 return ret; 2529 } 2530 2531 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2532 if (!ret) { 2533 psp->hdcp_context.context.initialized = true; 2534 mutex_init(&psp->hdcp_context.mutex); 2535 } 2536 2537 return ret; 2538 } 2539 2540 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2541 { 2542 /* 2543 * TODO: bypass the loading in sriov for now 2544 */ 2545 if (amdgpu_sriov_vf(psp->adev)) 2546 return 0; 2547 2548 if (!psp->hdcp_context.context.initialized) 2549 return 0; 2550 2551 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2552 } 2553 2554 static int psp_hdcp_terminate(struct psp_context *psp) 2555 { 2556 int ret; 2557 2558 /* 2559 * TODO: bypass the terminate in sriov for now 2560 */ 2561 if (amdgpu_sriov_vf(psp->adev)) 2562 return 0; 2563 2564 if (!psp->hdcp_context.context.initialized) 2565 return 0; 2566 2567 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2568 2569 psp->hdcp_context.context.initialized = false; 2570 2571 return ret; 2572 } 2573 // HDCP end 2574 2575 // DTM start 2576 static int psp_dtm_initialize(struct psp_context *psp) 2577 { 2578 int ret; 2579 2580 /* 2581 * TODO: bypass the initialize in sriov for now 2582 */ 2583 if (amdgpu_sriov_vf(psp->adev)) 2584 return 0; 2585 2586 /* bypass dtm initialization if dmu is harvested */ 2587 if (!amdgpu_device_has_display_hardware(psp->adev)) 2588 return 0; 2589 2590 if (!psp->dtm_context.context.bin_desc.size_bytes || 2591 !psp->dtm_context.context.bin_desc.start_addr) { 2592 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2593 return 0; 2594 } 2595 2596 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2597 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2598 2599 if (!psp->dtm_context.context.mem_context.shared_buf) { 2600 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2601 if (ret) 2602 return ret; 2603 } 2604 2605 ret = psp_ta_load(psp, &psp->dtm_context.context); 2606 if (!ret) { 2607 psp->dtm_context.context.initialized = true; 2608 mutex_init(&psp->dtm_context.mutex); 2609 } 2610 2611 return ret; 2612 } 2613 2614 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2615 { 2616 /* 2617 * TODO: bypass the loading in sriov for now 2618 */ 2619 if (amdgpu_sriov_vf(psp->adev)) 2620 return 0; 2621 2622 if (!psp->dtm_context.context.initialized) 2623 return 0; 2624 2625 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2626 } 2627 2628 static int psp_dtm_terminate(struct psp_context *psp) 2629 { 2630 int ret; 2631 2632 /* 2633 * TODO: bypass the terminate in sriov for now 2634 */ 2635 if (amdgpu_sriov_vf(psp->adev)) 2636 return 0; 2637 2638 if (!psp->dtm_context.context.initialized) 2639 return 0; 2640 2641 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2642 2643 psp->dtm_context.context.initialized = false; 2644 2645 return ret; 2646 } 2647 // DTM end 2648 2649 // RAP start 2650 static int psp_rap_initialize(struct psp_context *psp) 2651 { 2652 int ret; 2653 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2654 2655 /* 2656 * TODO: bypass the initialize in sriov for now 2657 */ 2658 if (amdgpu_sriov_vf(psp->adev)) 2659 return 0; 2660 2661 if (!psp->rap_context.context.bin_desc.size_bytes || 2662 !psp->rap_context.context.bin_desc.start_addr) { 2663 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2664 return 0; 2665 } 2666 2667 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2668 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2669 2670 if (!psp->rap_context.context.mem_context.shared_buf) { 2671 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2672 if (ret) 2673 return ret; 2674 } 2675 2676 ret = psp_ta_load(psp, &psp->rap_context.context); 2677 if (!ret) { 2678 psp->rap_context.context.initialized = true; 2679 mutex_init(&psp->rap_context.mutex); 2680 } else 2681 return ret; 2682 2683 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2684 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2685 psp_rap_terminate(psp); 2686 /* free rap shared memory */ 2687 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2688 2689 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2690 ret, status); 2691 2692 return ret; 2693 } 2694 2695 return 0; 2696 } 2697 2698 static int psp_rap_terminate(struct psp_context *psp) 2699 { 2700 int ret; 2701 2702 if (!psp->rap_context.context.initialized) 2703 return 0; 2704 2705 ret = psp_ta_unload(psp, &psp->rap_context.context); 2706 2707 psp->rap_context.context.initialized = false; 2708 2709 return ret; 2710 } 2711 2712 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2713 { 2714 struct ta_rap_shared_memory *rap_cmd; 2715 int ret = 0; 2716 2717 if (!psp->rap_context.context.initialized) 2718 return 0; 2719 2720 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2721 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2722 return -EINVAL; 2723 2724 mutex_lock(&psp->rap_context.mutex); 2725 2726 rap_cmd = (struct ta_rap_shared_memory *) 2727 psp->rap_context.context.mem_context.shared_buf; 2728 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2729 2730 rap_cmd->cmd_id = ta_cmd_id; 2731 rap_cmd->validation_method_id = METHOD_A; 2732 2733 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2734 if (ret) 2735 goto out_unlock; 2736 2737 if (status) 2738 *status = rap_cmd->rap_status; 2739 2740 out_unlock: 2741 mutex_unlock(&psp->rap_context.mutex); 2742 2743 return ret; 2744 } 2745 // RAP end 2746 2747 /* securedisplay start */ 2748 static int psp_securedisplay_initialize(struct psp_context *psp) 2749 { 2750 int ret; 2751 struct ta_securedisplay_cmd *securedisplay_cmd; 2752 2753 /* 2754 * TODO: bypass the initialize in sriov for now 2755 */ 2756 if (amdgpu_sriov_vf(psp->adev)) 2757 return 0; 2758 2759 /* bypass securedisplay initialization if dmu is harvested */ 2760 if (!amdgpu_device_has_display_hardware(psp->adev)) 2761 return 0; 2762 2763 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2764 !psp->securedisplay_context.context.bin_desc.start_addr) { 2765 dev_info(psp->adev->dev, 2766 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2767 return 0; 2768 } 2769 2770 psp->securedisplay_context.context.mem_context.shared_mem_size = 2771 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2772 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2773 2774 if (!psp->securedisplay_context.context.initialized) { 2775 ret = psp_ta_init_shared_buf(psp, 2776 &psp->securedisplay_context.context.mem_context); 2777 if (ret) 2778 return ret; 2779 } 2780 2781 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2782 if (!ret && !psp->securedisplay_context.context.resp_status) { 2783 psp->securedisplay_context.context.initialized = true; 2784 mutex_init(&psp->securedisplay_context.mutex); 2785 } else { 2786 /* don't try again */ 2787 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2788 return ret; 2789 } 2790 2791 mutex_lock(&psp->securedisplay_context.mutex); 2792 2793 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2794 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2795 2796 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2797 2798 mutex_unlock(&psp->securedisplay_context.mutex); 2799 2800 if (ret) { 2801 psp_securedisplay_terminate(psp); 2802 /* free securedisplay shared memory */ 2803 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2804 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2805 return -EINVAL; 2806 } 2807 2808 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2809 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2810 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2811 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2812 /* don't try again */ 2813 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2814 } 2815 2816 return 0; 2817 } 2818 2819 static int psp_securedisplay_terminate(struct psp_context *psp) 2820 { 2821 int ret; 2822 2823 /* 2824 * TODO:bypass the terminate in sriov for now 2825 */ 2826 if (amdgpu_sriov_vf(psp->adev)) 2827 return 0; 2828 2829 if (!psp->securedisplay_context.context.initialized) 2830 return 0; 2831 2832 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2833 2834 psp->securedisplay_context.context.initialized = false; 2835 2836 return ret; 2837 } 2838 2839 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2840 { 2841 int ret; 2842 2843 if (!psp->securedisplay_context.context.initialized) 2844 return -EINVAL; 2845 2846 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2847 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2848 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2849 return -EINVAL; 2850 2851 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2852 2853 return ret; 2854 } 2855 /* SECUREDISPLAY end */ 2856 2857 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2858 { 2859 struct psp_context *psp = &adev->psp; 2860 int ret = 0; 2861 2862 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2863 ret = psp->funcs->wait_for_bootloader(psp); 2864 2865 return ret; 2866 } 2867 2868 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2869 { 2870 if (psp->funcs && 2871 psp->funcs->get_ras_capability) { 2872 return psp->funcs->get_ras_capability(psp); 2873 } else { 2874 return false; 2875 } 2876 } 2877 2878 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2879 { 2880 struct psp_context *psp = &adev->psp; 2881 2882 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2883 return false; 2884 2885 if (psp->funcs && psp->funcs->is_reload_needed) 2886 return psp->funcs->is_reload_needed(psp); 2887 2888 return false; 2889 } 2890 2891 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2892 { 2893 struct psp_context *psp = &adev->psp; 2894 2895 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2896 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2897 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2898 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2899 } 2900 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2901 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2902 } 2903 2904 static int psp_hw_start(struct psp_context *psp) 2905 { 2906 struct amdgpu_device *adev = psp->adev; 2907 int ret; 2908 2909 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2910 psp_update_gpu_addresses(adev); 2911 2912 if (!amdgpu_sriov_vf(adev)) { 2913 if ((is_psp_fw_valid(psp->kdb)) && 2914 (psp->funcs->bootloader_load_kdb != NULL)) { 2915 ret = psp_bootloader_load_kdb(psp); 2916 if (ret) { 2917 dev_err(adev->dev, "PSP load kdb failed!\n"); 2918 return ret; 2919 } 2920 } 2921 2922 if ((is_psp_fw_valid(psp->spl)) && 2923 (psp->funcs->bootloader_load_spl != NULL)) { 2924 ret = psp_bootloader_load_spl(psp); 2925 if (ret) { 2926 dev_err(adev->dev, "PSP load spl failed!\n"); 2927 return ret; 2928 } 2929 } 2930 2931 if ((is_psp_fw_valid(psp->sys)) && 2932 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2933 ret = psp_bootloader_load_sysdrv(psp); 2934 if (ret) { 2935 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2936 return ret; 2937 } 2938 } 2939 2940 if ((is_psp_fw_valid(psp->soc_drv)) && 2941 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2942 ret = psp_bootloader_load_soc_drv(psp); 2943 if (ret) { 2944 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2945 return ret; 2946 } 2947 } 2948 2949 if ((is_psp_fw_valid(psp->intf_drv)) && 2950 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2951 ret = psp_bootloader_load_intf_drv(psp); 2952 if (ret) { 2953 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2954 return ret; 2955 } 2956 } 2957 2958 if ((is_psp_fw_valid(psp->dbg_drv)) && 2959 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2960 ret = psp_bootloader_load_dbg_drv(psp); 2961 if (ret) { 2962 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2963 return ret; 2964 } 2965 } 2966 2967 if ((is_psp_fw_valid(psp->ras_drv)) && 2968 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2969 ret = psp_bootloader_load_ras_drv(psp); 2970 if (ret) { 2971 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2972 return ret; 2973 } 2974 } 2975 2976 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2977 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2978 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2979 if (ret) { 2980 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2981 return ret; 2982 } 2983 } 2984 2985 if ((is_psp_fw_valid(psp->spdm_drv)) && 2986 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2987 ret = psp_bootloader_load_spdm_drv(psp); 2988 if (ret) { 2989 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2990 return ret; 2991 } 2992 } 2993 2994 if ((is_psp_fw_valid(psp->sos)) && 2995 (psp->funcs->bootloader_load_sos != NULL)) { 2996 ret = psp_bootloader_load_sos(psp); 2997 if (ret) { 2998 dev_err(adev->dev, "PSP load sos failed!\n"); 2999 return ret; 3000 } 3001 } 3002 } 3003 3004 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 3005 if (ret) { 3006 dev_err(adev->dev, "PSP create ring failed!\n"); 3007 return ret; 3008 } 3009 3010 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3011 ret = psp_update_fw_reservation(psp); 3012 if (ret) { 3013 dev_err(adev->dev, "update fw reservation failed!\n"); 3014 return ret; 3015 } 3016 } 3017 3018 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 3019 goto skip_pin_bo; 3020 3021 if (!psp->boot_time_tmr || psp->autoload_supported) { 3022 ret = psp_tmr_init(psp); 3023 if (ret) { 3024 dev_err(adev->dev, "PSP tmr init failed!\n"); 3025 return ret; 3026 } 3027 } 3028 3029 skip_pin_bo: 3030 /* 3031 * For ASICs with DF Cstate management centralized 3032 * to PMFW, TMR setup should be performed after PMFW 3033 * loaded and before other non-psp firmware loaded. 3034 */ 3035 if (psp->pmfw_centralized_cstate_management) { 3036 ret = psp_load_smu_fw(psp); 3037 if (ret) 3038 return ret; 3039 } 3040 3041 ret = psp_tmr_load(psp); 3042 if (ret) { 3043 dev_err(adev->dev, "PSP load tmr failed!\n"); 3044 return ret; 3045 } 3046 3047 return 0; 3048 } 3049 3050 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3051 enum psp_gfx_fw_type *type) 3052 { 3053 switch (ucode->ucode_id) { 3054 case AMDGPU_UCODE_ID_CAP: 3055 *type = GFX_FW_TYPE_CAP; 3056 break; 3057 case AMDGPU_UCODE_ID_SDMA0: 3058 *type = GFX_FW_TYPE_SDMA0; 3059 break; 3060 case AMDGPU_UCODE_ID_SDMA1: 3061 *type = GFX_FW_TYPE_SDMA1; 3062 break; 3063 case AMDGPU_UCODE_ID_SDMA2: 3064 *type = GFX_FW_TYPE_SDMA2; 3065 break; 3066 case AMDGPU_UCODE_ID_SDMA3: 3067 *type = GFX_FW_TYPE_SDMA3; 3068 break; 3069 case AMDGPU_UCODE_ID_SDMA4: 3070 *type = GFX_FW_TYPE_SDMA4; 3071 break; 3072 case AMDGPU_UCODE_ID_SDMA5: 3073 *type = GFX_FW_TYPE_SDMA5; 3074 break; 3075 case AMDGPU_UCODE_ID_SDMA6: 3076 *type = GFX_FW_TYPE_SDMA6; 3077 break; 3078 case AMDGPU_UCODE_ID_SDMA7: 3079 *type = GFX_FW_TYPE_SDMA7; 3080 break; 3081 case AMDGPU_UCODE_ID_CP_MES: 3082 *type = GFX_FW_TYPE_CP_MES; 3083 break; 3084 case AMDGPU_UCODE_ID_CP_MES_DATA: 3085 *type = GFX_FW_TYPE_MES_STACK; 3086 break; 3087 case AMDGPU_UCODE_ID_CP_MES1: 3088 *type = GFX_FW_TYPE_CP_MES_KIQ; 3089 break; 3090 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3091 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3092 break; 3093 case AMDGPU_UCODE_ID_CP_CE: 3094 *type = GFX_FW_TYPE_CP_CE; 3095 break; 3096 case AMDGPU_UCODE_ID_CP_PFP: 3097 *type = GFX_FW_TYPE_CP_PFP; 3098 break; 3099 case AMDGPU_UCODE_ID_CP_ME: 3100 *type = GFX_FW_TYPE_CP_ME; 3101 break; 3102 case AMDGPU_UCODE_ID_CP_MEC1: 3103 *type = GFX_FW_TYPE_CP_MEC; 3104 break; 3105 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3106 *type = GFX_FW_TYPE_CP_MEC_ME1; 3107 break; 3108 case AMDGPU_UCODE_ID_CP_MEC2: 3109 *type = GFX_FW_TYPE_CP_MEC; 3110 break; 3111 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3112 *type = GFX_FW_TYPE_CP_MEC_ME2; 3113 break; 3114 case AMDGPU_UCODE_ID_RLC_P: 3115 *type = GFX_FW_TYPE_RLC_P; 3116 break; 3117 case AMDGPU_UCODE_ID_RLC_V: 3118 *type = GFX_FW_TYPE_RLC_V; 3119 break; 3120 case AMDGPU_UCODE_ID_RLC_G: 3121 *type = GFX_FW_TYPE_RLC_G; 3122 break; 3123 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3124 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3125 break; 3126 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3127 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3128 break; 3129 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3130 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3131 break; 3132 case AMDGPU_UCODE_ID_RLC_IRAM: 3133 *type = GFX_FW_TYPE_RLC_IRAM; 3134 break; 3135 case AMDGPU_UCODE_ID_RLC_DRAM: 3136 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3137 break; 3138 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3139 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3140 break; 3141 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3142 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3143 break; 3144 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3145 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3146 break; 3147 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3148 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3149 break; 3150 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3151 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3152 break; 3153 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3154 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3155 break; 3156 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3157 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3158 break; 3159 case AMDGPU_UCODE_ID_SMC: 3160 *type = GFX_FW_TYPE_SMU; 3161 break; 3162 case AMDGPU_UCODE_ID_PPTABLE: 3163 *type = GFX_FW_TYPE_PPTABLE; 3164 break; 3165 case AMDGPU_UCODE_ID_UVD: 3166 *type = GFX_FW_TYPE_UVD; 3167 break; 3168 case AMDGPU_UCODE_ID_UVD1: 3169 *type = GFX_FW_TYPE_UVD1; 3170 break; 3171 case AMDGPU_UCODE_ID_VCE: 3172 *type = GFX_FW_TYPE_VCE; 3173 break; 3174 case AMDGPU_UCODE_ID_VCN: 3175 *type = GFX_FW_TYPE_VCN; 3176 break; 3177 case AMDGPU_UCODE_ID_VCN1: 3178 *type = GFX_FW_TYPE_VCN1; 3179 break; 3180 case AMDGPU_UCODE_ID_DMCU_ERAM: 3181 *type = GFX_FW_TYPE_DMCU_ERAM; 3182 break; 3183 case AMDGPU_UCODE_ID_DMCU_INTV: 3184 *type = GFX_FW_TYPE_DMCU_ISR; 3185 break; 3186 case AMDGPU_UCODE_ID_VCN0_RAM: 3187 *type = GFX_FW_TYPE_VCN0_RAM; 3188 break; 3189 case AMDGPU_UCODE_ID_VCN1_RAM: 3190 *type = GFX_FW_TYPE_VCN1_RAM; 3191 break; 3192 case AMDGPU_UCODE_ID_DMCUB: 3193 *type = GFX_FW_TYPE_DMUB; 3194 break; 3195 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3196 case AMDGPU_UCODE_ID_SDMA_RS64: 3197 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3198 break; 3199 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3200 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3201 break; 3202 case AMDGPU_UCODE_ID_IMU_I: 3203 *type = GFX_FW_TYPE_IMU_I; 3204 break; 3205 case AMDGPU_UCODE_ID_IMU_D: 3206 *type = GFX_FW_TYPE_IMU_D; 3207 break; 3208 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3209 *type = GFX_FW_TYPE_RS64_PFP; 3210 break; 3211 case AMDGPU_UCODE_ID_CP_RS64_ME: 3212 *type = GFX_FW_TYPE_RS64_ME; 3213 break; 3214 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3215 *type = GFX_FW_TYPE_RS64_MEC; 3216 break; 3217 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3218 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3219 break; 3220 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3221 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3222 break; 3223 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3224 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3225 break; 3226 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3227 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3228 break; 3229 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3230 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3231 break; 3232 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3233 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3234 break; 3235 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3236 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3237 break; 3238 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3239 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3240 break; 3241 case AMDGPU_UCODE_ID_VPE_CTX: 3242 *type = GFX_FW_TYPE_VPEC_FW1; 3243 break; 3244 case AMDGPU_UCODE_ID_VPE_CTL: 3245 *type = GFX_FW_TYPE_VPEC_FW2; 3246 break; 3247 case AMDGPU_UCODE_ID_VPE: 3248 *type = GFX_FW_TYPE_VPE; 3249 break; 3250 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3251 *type = GFX_FW_TYPE_UMSCH_UCODE; 3252 break; 3253 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3254 *type = GFX_FW_TYPE_UMSCH_DATA; 3255 break; 3256 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3257 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3258 break; 3259 case AMDGPU_UCODE_ID_P2S_TABLE: 3260 *type = GFX_FW_TYPE_P2S_TABLE; 3261 break; 3262 case AMDGPU_UCODE_ID_JPEG_RAM: 3263 *type = GFX_FW_TYPE_JPEG_RAM; 3264 break; 3265 case AMDGPU_UCODE_ID_ISP: 3266 *type = GFX_FW_TYPE_ISP; 3267 break; 3268 case AMDGPU_UCODE_ID_MAXIMUM: 3269 default: 3270 return -EINVAL; 3271 } 3272 3273 return 0; 3274 } 3275 3276 static void psp_print_fw_hdr(struct psp_context *psp, 3277 struct amdgpu_firmware_info *ucode) 3278 { 3279 struct amdgpu_device *adev = psp->adev; 3280 struct common_firmware_header *hdr; 3281 3282 switch (ucode->ucode_id) { 3283 case AMDGPU_UCODE_ID_SDMA0: 3284 case AMDGPU_UCODE_ID_SDMA1: 3285 case AMDGPU_UCODE_ID_SDMA2: 3286 case AMDGPU_UCODE_ID_SDMA3: 3287 case AMDGPU_UCODE_ID_SDMA4: 3288 case AMDGPU_UCODE_ID_SDMA5: 3289 case AMDGPU_UCODE_ID_SDMA6: 3290 case AMDGPU_UCODE_ID_SDMA7: 3291 hdr = (struct common_firmware_header *) 3292 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3293 amdgpu_ucode_print_sdma_hdr(hdr); 3294 break; 3295 case AMDGPU_UCODE_ID_CP_CE: 3296 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3297 amdgpu_ucode_print_gfx_hdr(hdr); 3298 break; 3299 case AMDGPU_UCODE_ID_CP_PFP: 3300 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3301 amdgpu_ucode_print_gfx_hdr(hdr); 3302 break; 3303 case AMDGPU_UCODE_ID_CP_ME: 3304 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3305 amdgpu_ucode_print_gfx_hdr(hdr); 3306 break; 3307 case AMDGPU_UCODE_ID_CP_MEC1: 3308 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3309 amdgpu_ucode_print_gfx_hdr(hdr); 3310 break; 3311 case AMDGPU_UCODE_ID_RLC_G: 3312 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3313 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3314 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3315 amdgpu_ucode_print_rlc_hdr(hdr); 3316 break; 3317 case AMDGPU_UCODE_ID_SMC: 3318 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3319 amdgpu_ucode_print_smc_hdr(hdr); 3320 break; 3321 default: 3322 break; 3323 } 3324 } 3325 3326 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3327 struct amdgpu_firmware_info *ucode, 3328 struct psp_gfx_cmd_resp *cmd) 3329 { 3330 int ret; 3331 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3332 3333 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3334 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3335 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3336 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3337 3338 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3339 if (ret) 3340 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3341 return ret; 3342 } 3343 3344 int psp_execute_ip_fw_load(struct psp_context *psp, 3345 struct amdgpu_firmware_info *ucode) 3346 { 3347 int ret = 0; 3348 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3349 3350 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3351 if (!ret) { 3352 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3353 psp->fence_buf_mc_addr); 3354 } 3355 3356 release_psp_cmd_buf(psp); 3357 3358 return ret; 3359 } 3360 3361 static int psp_load_p2s_table(struct psp_context *psp) 3362 { 3363 int ret; 3364 struct amdgpu_device *adev = psp->adev; 3365 struct amdgpu_firmware_info *ucode = 3366 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3367 3368 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3369 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3370 return 0; 3371 3372 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3373 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3374 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3375 0x0036003C; 3376 if (psp->sos.fw_version < supp_vers) 3377 return 0; 3378 } 3379 3380 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3381 return 0; 3382 3383 ret = psp_execute_ip_fw_load(psp, ucode); 3384 3385 return ret; 3386 } 3387 3388 static int psp_load_smu_fw(struct psp_context *psp) 3389 { 3390 int ret; 3391 struct amdgpu_device *adev = psp->adev; 3392 struct amdgpu_firmware_info *ucode = 3393 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3394 struct amdgpu_ras *ras = psp->ras_context.ras; 3395 3396 /* 3397 * Skip SMU FW reloading in case of using BACO for runpm only, 3398 * as SMU is always alive. 3399 */ 3400 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3401 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3402 return 0; 3403 3404 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3405 return 0; 3406 3407 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3408 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3409 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3410 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3411 if (ret) 3412 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3413 } 3414 3415 ret = psp_execute_ip_fw_load(psp, ucode); 3416 3417 if (ret) 3418 dev_err(adev->dev, "PSP load smu failed!\n"); 3419 3420 return ret; 3421 } 3422 3423 static bool fw_load_skip_check(struct psp_context *psp, 3424 struct amdgpu_firmware_info *ucode) 3425 { 3426 if (!ucode->fw || !ucode->ucode_size) 3427 return true; 3428 3429 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3430 return true; 3431 3432 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3433 (psp_smu_reload_quirk(psp) || 3434 psp->autoload_supported || 3435 psp->pmfw_centralized_cstate_management)) 3436 return true; 3437 3438 if (amdgpu_sriov_vf(psp->adev) && 3439 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3440 return true; 3441 3442 if (psp->autoload_supported && 3443 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3444 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3445 /* skip mec JT when autoload is enabled */ 3446 return true; 3447 3448 return false; 3449 } 3450 3451 int psp_load_fw_list(struct psp_context *psp, 3452 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3453 { 3454 int ret = 0, i; 3455 struct amdgpu_firmware_info *ucode; 3456 3457 for (i = 0; i < ucode_count; ++i) { 3458 ucode = ucode_list[i]; 3459 psp_print_fw_hdr(psp, ucode); 3460 ret = psp_execute_ip_fw_load(psp, ucode); 3461 if (ret) 3462 return ret; 3463 } 3464 return ret; 3465 } 3466 3467 static int psp_load_non_psp_fw(struct psp_context *psp) 3468 { 3469 int i, ret; 3470 struct amdgpu_firmware_info *ucode; 3471 struct amdgpu_device *adev = psp->adev; 3472 3473 if (psp->autoload_supported && 3474 !psp->pmfw_centralized_cstate_management) { 3475 ret = psp_load_smu_fw(psp); 3476 if (ret) 3477 return ret; 3478 } 3479 3480 /* Load P2S table first if it's available */ 3481 psp_load_p2s_table(psp); 3482 3483 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3484 ucode = &adev->firmware.ucode[i]; 3485 3486 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3487 !fw_load_skip_check(psp, ucode)) { 3488 ret = psp_load_smu_fw(psp); 3489 if (ret) 3490 return ret; 3491 continue; 3492 } 3493 3494 if (fw_load_skip_check(psp, ucode)) 3495 continue; 3496 3497 if (psp->autoload_supported && 3498 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3499 IP_VERSION(11, 0, 7) || 3500 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3501 IP_VERSION(11, 0, 11) || 3502 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3503 IP_VERSION(11, 0, 12) || 3504 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3505 IP_VERSION(15, 0, 0) || 3506 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3507 IP_VERSION(15, 0, 5) || 3508 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3509 IP_VERSION(15, 0, 8) || 3510 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3511 IP_VERSION(15, 0, 9)) && 3512 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3513 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3514 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3515 /* PSP only receive one SDMA fw for sienna_cichlid, 3516 * as all four sdma fw are same 3517 */ 3518 continue; 3519 3520 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3521 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3522 IP_VERSION(15, 0, 8) && 3523 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3524 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3525 continue; 3526 3527 psp_print_fw_hdr(psp, ucode); 3528 3529 ret = psp_execute_ip_fw_load(psp, ucode); 3530 if (ret) 3531 return ret; 3532 3533 /* Start rlc autoload after psp received all the gfx firmware */ 3534 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3535 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3536 ret = psp_rlc_autoload_start(psp); 3537 if (ret) { 3538 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3539 return ret; 3540 } 3541 } 3542 } 3543 3544 return 0; 3545 } 3546 3547 static int psp_load_fw(struct amdgpu_device *adev) 3548 { 3549 int ret; 3550 struct psp_context *psp = &adev->psp; 3551 3552 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3553 /* should not destroy ring, only stop */ 3554 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3555 } else { 3556 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3557 3558 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3559 if (ret) { 3560 dev_err(adev->dev, "PSP ring init failed!\n"); 3561 goto failed; 3562 } 3563 } 3564 3565 ret = psp_hw_start(psp); 3566 if (ret) 3567 goto failed; 3568 3569 ret = psp_load_non_psp_fw(psp); 3570 if (ret) 3571 goto failed1; 3572 3573 ret = psp_asd_initialize(psp); 3574 if (ret) { 3575 dev_err(adev->dev, "PSP load asd failed!\n"); 3576 goto failed1; 3577 } 3578 3579 ret = psp_rl_load(adev); 3580 if (ret) { 3581 dev_err(adev->dev, "PSP load RL failed!\n"); 3582 goto failed1; 3583 } 3584 3585 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3586 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3587 ret = psp_xgmi_initialize(psp, false, true); 3588 /* Warning the XGMI seesion initialize failure 3589 * Instead of stop driver initialization 3590 */ 3591 if (ret) 3592 dev_err(psp->adev->dev, 3593 "XGMI: Failed to initialize XGMI session\n"); 3594 } 3595 } 3596 3597 if (psp->ta_fw) { 3598 ret = psp_ras_initialize(psp); 3599 if (ret) 3600 dev_err(psp->adev->dev, 3601 "RAS: Failed to initialize RAS\n"); 3602 3603 ret = psp_hdcp_initialize(psp); 3604 if (ret) 3605 dev_err(psp->adev->dev, 3606 "HDCP: Failed to initialize HDCP\n"); 3607 3608 ret = psp_dtm_initialize(psp); 3609 if (ret) 3610 dev_err(psp->adev->dev, 3611 "DTM: Failed to initialize DTM\n"); 3612 3613 ret = psp_rap_initialize(psp); 3614 if (ret) 3615 dev_err(psp->adev->dev, 3616 "RAP: Failed to initialize RAP\n"); 3617 3618 ret = psp_securedisplay_initialize(psp); 3619 if (ret) 3620 dev_err(psp->adev->dev, 3621 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3622 } 3623 3624 return 0; 3625 3626 failed1: 3627 psp_free_shared_bufs(psp); 3628 failed: 3629 /* 3630 * all cleanup jobs (xgmi terminate, ras terminate, 3631 * ring destroy, cmd/fence/fw buffers destory, 3632 * psp->cmd destory) are delayed to psp_hw_fini 3633 */ 3634 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3635 return ret; 3636 } 3637 3638 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3639 { 3640 int ret; 3641 struct amdgpu_device *adev = ip_block->adev; 3642 3643 mutex_lock(&adev->firmware.mutex); 3644 3645 ret = amdgpu_ucode_init_bo(adev); 3646 if (ret) 3647 goto failed; 3648 3649 ret = psp_load_fw(adev); 3650 if (ret) { 3651 dev_err(adev->dev, "PSP firmware loading failed\n"); 3652 goto failed; 3653 } 3654 3655 mutex_unlock(&adev->firmware.mutex); 3656 return 0; 3657 3658 failed: 3659 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3660 mutex_unlock(&adev->firmware.mutex); 3661 return -EINVAL; 3662 } 3663 3664 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3665 { 3666 struct amdgpu_device *adev = ip_block->adev; 3667 struct psp_context *psp = &adev->psp; 3668 3669 if (psp->ta_fw) { 3670 psp_ras_terminate(psp); 3671 psp_securedisplay_terminate(psp); 3672 psp_rap_terminate(psp); 3673 psp_dtm_terminate(psp); 3674 psp_hdcp_terminate(psp); 3675 3676 if (adev->gmc.xgmi.num_physical_nodes > 1) 3677 psp_xgmi_terminate(psp); 3678 } 3679 3680 psp_asd_terminate(psp); 3681 psp_tmr_terminate(psp); 3682 3683 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3684 3685 return 0; 3686 } 3687 3688 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3689 { 3690 int ret = 0; 3691 struct amdgpu_device *adev = ip_block->adev; 3692 struct psp_context *psp = &adev->psp; 3693 3694 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3695 psp->xgmi_context.context.initialized) { 3696 ret = psp_xgmi_terminate(psp); 3697 if (ret) { 3698 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3699 goto out; 3700 } 3701 } 3702 3703 if (psp->ta_fw) { 3704 ret = psp_ras_terminate(psp); 3705 if (ret) { 3706 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3707 goto out; 3708 } 3709 ret = psp_hdcp_terminate(psp); 3710 if (ret) { 3711 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3712 goto out; 3713 } 3714 ret = psp_dtm_terminate(psp); 3715 if (ret) { 3716 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3717 goto out; 3718 } 3719 ret = psp_rap_terminate(psp); 3720 if (ret) { 3721 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3722 goto out; 3723 } 3724 ret = psp_securedisplay_terminate(psp); 3725 if (ret) { 3726 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3727 goto out; 3728 } 3729 } 3730 3731 ret = psp_asd_terminate(psp); 3732 if (ret) { 3733 dev_err(adev->dev, "Failed to terminate asd\n"); 3734 goto out; 3735 } 3736 3737 ret = psp_tmr_terminate(psp); 3738 if (ret) { 3739 dev_err(adev->dev, "Failed to terminate tmr\n"); 3740 goto out; 3741 } 3742 3743 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3744 if (ret) 3745 dev_err(adev->dev, "PSP ring stop failed\n"); 3746 3747 out: 3748 return ret; 3749 } 3750 3751 static int psp_resume(struct amdgpu_ip_block *ip_block) 3752 { 3753 int ret; 3754 struct amdgpu_device *adev = ip_block->adev; 3755 struct psp_context *psp = &adev->psp; 3756 3757 dev_info(adev->dev, "PSP is resuming...\n"); 3758 3759 if (psp->mem_train_ctx.enable_mem_training) { 3760 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3761 if (ret) { 3762 dev_err(adev->dev, "Failed to process memory training!\n"); 3763 return ret; 3764 } 3765 } 3766 3767 mutex_lock(&adev->firmware.mutex); 3768 3769 ret = amdgpu_ucode_init_bo(adev); 3770 if (ret) 3771 goto failed; 3772 3773 ret = psp_hw_start(psp); 3774 if (ret) 3775 goto failed; 3776 3777 ret = psp_load_non_psp_fw(psp); 3778 if (ret) 3779 goto failed; 3780 3781 ret = psp_asd_initialize(psp); 3782 if (ret) { 3783 dev_err(adev->dev, "PSP load asd failed!\n"); 3784 goto failed; 3785 } 3786 3787 ret = psp_rl_load(adev); 3788 if (ret) { 3789 dev_err(adev->dev, "PSP load RL failed!\n"); 3790 goto failed; 3791 } 3792 3793 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3794 ret = psp_xgmi_initialize(psp, false, true); 3795 /* Warning the XGMI seesion initialize failure 3796 * Instead of stop driver initialization 3797 */ 3798 if (ret) 3799 dev_err(psp->adev->dev, 3800 "XGMI: Failed to initialize XGMI session\n"); 3801 } 3802 3803 if (psp->ta_fw) { 3804 ret = psp_ras_initialize(psp); 3805 if (ret) 3806 dev_err(psp->adev->dev, 3807 "RAS: Failed to initialize RAS\n"); 3808 3809 ret = psp_hdcp_initialize(psp); 3810 if (ret) 3811 dev_err(psp->adev->dev, 3812 "HDCP: Failed to initialize HDCP\n"); 3813 3814 ret = psp_dtm_initialize(psp); 3815 if (ret) 3816 dev_err(psp->adev->dev, 3817 "DTM: Failed to initialize DTM\n"); 3818 3819 ret = psp_rap_initialize(psp); 3820 if (ret) 3821 dev_err(psp->adev->dev, 3822 "RAP: Failed to initialize RAP\n"); 3823 3824 ret = psp_securedisplay_initialize(psp); 3825 if (ret) 3826 dev_err(psp->adev->dev, 3827 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3828 } 3829 3830 mutex_unlock(&adev->firmware.mutex); 3831 3832 return 0; 3833 3834 failed: 3835 dev_err(adev->dev, "PSP resume failed\n"); 3836 mutex_unlock(&adev->firmware.mutex); 3837 return ret; 3838 } 3839 3840 int psp_gpu_reset(struct amdgpu_device *adev) 3841 { 3842 int ret; 3843 3844 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3845 return 0; 3846 3847 mutex_lock(&adev->psp.mutex); 3848 ret = psp_mode1_reset(&adev->psp); 3849 mutex_unlock(&adev->psp.mutex); 3850 3851 return ret; 3852 } 3853 3854 int psp_rlc_autoload_start(struct psp_context *psp) 3855 { 3856 int ret; 3857 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3858 3859 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3860 3861 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3862 psp->fence_buf_mc_addr); 3863 3864 release_psp_cmd_buf(psp); 3865 3866 return ret; 3867 } 3868 3869 int psp_ring_cmd_submit(struct psp_context *psp, 3870 uint64_t cmd_buf_mc_addr, 3871 uint64_t fence_mc_addr, 3872 int index) 3873 { 3874 unsigned int psp_write_ptr_reg = 0; 3875 struct psp_gfx_rb_frame *write_frame; 3876 struct psp_ring *ring = &psp->km_ring; 3877 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3878 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3879 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3880 struct amdgpu_device *adev = psp->adev; 3881 uint32_t ring_size_dw = ring->ring_size / 4; 3882 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3883 3884 /* KM (GPCOM) prepare write pointer */ 3885 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3886 3887 /* Update KM RB frame pointer to new frame */ 3888 /* write_frame ptr increments by size of rb_frame in bytes */ 3889 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3890 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3891 write_frame = ring_buffer_start; 3892 else 3893 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3894 /* Check invalid write_frame ptr address */ 3895 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3896 dev_err(adev->dev, 3897 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3898 ring_buffer_start, ring_buffer_end, write_frame); 3899 dev_err(adev->dev, 3900 "write_frame is pointing to address out of bounds\n"); 3901 return -EINVAL; 3902 } 3903 3904 /* Initialize KM RB frame */ 3905 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3906 3907 /* Update KM RB frame */ 3908 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3909 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3910 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3911 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3912 write_frame->fence_value = index; 3913 amdgpu_device_flush_hdp(adev, NULL); 3914 3915 /* Update the write Pointer in DWORDs */ 3916 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3917 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3918 return 0; 3919 } 3920 3921 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3922 { 3923 struct amdgpu_device *adev = psp->adev; 3924 const struct psp_firmware_header_v1_0 *asd_hdr; 3925 int err = 0; 3926 3927 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3928 "amdgpu/%s_asd.bin", chip_name); 3929 if (err) 3930 goto out; 3931 3932 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3933 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3934 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3935 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3936 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3937 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3938 return 0; 3939 out: 3940 amdgpu_ucode_release(&adev->psp.asd_fw); 3941 return err; 3942 } 3943 3944 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3945 { 3946 struct amdgpu_device *adev = psp->adev; 3947 const struct psp_firmware_header_v1_0 *toc_hdr; 3948 int err = 0; 3949 3950 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3951 adev->rev_id == 0) 3952 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3953 "amdgpu/%s_toc_1.bin", chip_name); 3954 else 3955 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3956 "amdgpu/%s_toc.bin", chip_name); 3957 if (err) 3958 goto out; 3959 3960 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3961 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3962 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3963 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3964 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3965 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3966 return 0; 3967 out: 3968 amdgpu_ucode_release(&adev->psp.toc_fw); 3969 return err; 3970 } 3971 3972 static int parse_sos_bin_descriptor(struct psp_context *psp, 3973 const struct psp_fw_bin_desc *desc, 3974 const struct psp_firmware_header_v2_0 *sos_hdr) 3975 { 3976 uint8_t *ucode_start_addr = NULL; 3977 3978 if (!psp || !desc || !sos_hdr) 3979 return -EINVAL; 3980 3981 ucode_start_addr = (uint8_t *)sos_hdr + 3982 le32_to_cpu(desc->offset_bytes) + 3983 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3984 3985 switch (desc->fw_type) { 3986 case PSP_FW_TYPE_PSP_SOS: 3987 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3988 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3989 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3990 psp->sos.start_addr = ucode_start_addr; 3991 break; 3992 case PSP_FW_TYPE_PSP_SYS_DRV: 3993 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3994 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3995 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3996 psp->sys.start_addr = ucode_start_addr; 3997 break; 3998 case PSP_FW_TYPE_PSP_KDB: 3999 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 4000 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 4001 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 4002 psp->kdb.start_addr = ucode_start_addr; 4003 break; 4004 case PSP_FW_TYPE_PSP_TOC: 4005 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 4006 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 4007 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 4008 psp->toc.start_addr = ucode_start_addr; 4009 break; 4010 case PSP_FW_TYPE_PSP_SPL: 4011 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 4012 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 4013 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 4014 psp->spl.start_addr = ucode_start_addr; 4015 break; 4016 case PSP_FW_TYPE_PSP_RL: 4017 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 4018 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 4019 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 4020 psp->rl.start_addr = ucode_start_addr; 4021 break; 4022 case PSP_FW_TYPE_PSP_SOC_DRV: 4023 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 4024 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 4025 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4026 psp->soc_drv.start_addr = ucode_start_addr; 4027 break; 4028 case PSP_FW_TYPE_PSP_INTF_DRV: 4029 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 4030 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 4031 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4032 psp->intf_drv.start_addr = ucode_start_addr; 4033 break; 4034 case PSP_FW_TYPE_PSP_DBG_DRV: 4035 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4036 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4037 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4038 psp->dbg_drv.start_addr = ucode_start_addr; 4039 break; 4040 case PSP_FW_TYPE_PSP_RAS_DRV: 4041 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4042 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4043 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4044 psp->ras_drv.start_addr = ucode_start_addr; 4045 break; 4046 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4047 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4048 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4049 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4050 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4051 break; 4052 case PSP_FW_TYPE_PSP_SPDM_DRV: 4053 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4054 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4055 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4056 psp->spdm_drv.start_addr = ucode_start_addr; 4057 break; 4058 default: 4059 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4060 break; 4061 } 4062 4063 return 0; 4064 } 4065 4066 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4067 { 4068 const struct psp_firmware_header_v1_0 *sos_hdr; 4069 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4070 uint8_t *ucode_array_start_addr; 4071 4072 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4073 ucode_array_start_addr = (uint8_t *)sos_hdr + 4074 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4075 4076 if (adev->gmc.xgmi.connected_to_cpu || 4077 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4078 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4079 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4080 4081 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4082 adev->psp.sys.start_addr = ucode_array_start_addr; 4083 4084 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4085 adev->psp.sos.start_addr = ucode_array_start_addr + 4086 le32_to_cpu(sos_hdr->sos.offset_bytes); 4087 } else { 4088 /* Load alternate PSP SOS FW */ 4089 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4090 4091 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4092 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4093 4094 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4095 adev->psp.sys.start_addr = ucode_array_start_addr + 4096 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4097 4098 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4099 adev->psp.sos.start_addr = ucode_array_start_addr + 4100 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4101 } 4102 4103 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4104 dev_warn(adev->dev, "PSP SOS FW not available"); 4105 return -EINVAL; 4106 } 4107 4108 return 0; 4109 } 4110 4111 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4112 { 4113 struct amdgpu_device *adev = psp->adev; 4114 const struct psp_firmware_header_v1_0 *sos_hdr; 4115 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4116 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4117 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4118 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4119 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4120 int fw_index, fw_bin_count, start_index = 0; 4121 const struct psp_fw_bin_desc *fw_bin; 4122 uint8_t *ucode_array_start_addr; 4123 int err = 0; 4124 4125 if (amdgpu_is_kicker_fw(adev)) 4126 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4127 "amdgpu/%s_sos_kicker.bin", chip_name); 4128 else 4129 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4130 "amdgpu/%s_sos.bin", chip_name); 4131 if (err) 4132 goto out; 4133 4134 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4135 ucode_array_start_addr = (uint8_t *)sos_hdr + 4136 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4137 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4138 4139 switch (sos_hdr->header.header_version_major) { 4140 case 1: 4141 err = psp_init_sos_base_fw(adev); 4142 if (err) 4143 goto out; 4144 4145 if (sos_hdr->header.header_version_minor == 1) { 4146 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4147 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4148 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4149 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4150 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4151 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4152 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4153 } 4154 if (sos_hdr->header.header_version_minor == 2) { 4155 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4156 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4157 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4158 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4159 } 4160 if (sos_hdr->header.header_version_minor == 3) { 4161 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4162 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4163 adev->psp.toc.start_addr = ucode_array_start_addr + 4164 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4165 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4166 adev->psp.kdb.start_addr = ucode_array_start_addr + 4167 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4168 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4169 adev->psp.spl.start_addr = ucode_array_start_addr + 4170 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4171 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4172 adev->psp.rl.start_addr = ucode_array_start_addr + 4173 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4174 } 4175 break; 4176 case 2: 4177 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4178 4179 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4180 4181 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4182 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4183 err = -EINVAL; 4184 goto out; 4185 } 4186 4187 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4188 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4189 4190 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4191 4192 if (psp_is_aux_sos_load_required(psp)) 4193 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4194 else 4195 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4196 4197 } else { 4198 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4199 } 4200 4201 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4202 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4203 sos_hdr_v2_0); 4204 if (err) 4205 goto out; 4206 } 4207 break; 4208 default: 4209 dev_err(adev->dev, 4210 "unsupported psp sos firmware\n"); 4211 err = -EINVAL; 4212 goto out; 4213 } 4214 4215 return 0; 4216 out: 4217 amdgpu_ucode_release(&adev->psp.sos_fw); 4218 4219 return err; 4220 } 4221 4222 static bool is_ta_fw_applicable(struct psp_context *psp, 4223 const struct psp_fw_bin_desc *desc) 4224 { 4225 struct amdgpu_device *adev = psp->adev; 4226 uint32_t fw_version; 4227 4228 switch (desc->fw_type) { 4229 case TA_FW_TYPE_PSP_XGMI: 4230 case TA_FW_TYPE_PSP_XGMI_AUX: 4231 /* for now, AUX TA only exists on 13.0.6 ta bin, 4232 * from v20.00.0x.14 4233 */ 4234 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4235 IP_VERSION(13, 0, 6)) { 4236 fw_version = le32_to_cpu(desc->fw_version); 4237 4238 if (adev->flags & AMD_IS_APU && 4239 (fw_version & 0xff) >= 0x14) 4240 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4241 else 4242 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4243 } 4244 break; 4245 default: 4246 break; 4247 } 4248 4249 return true; 4250 } 4251 4252 static int parse_ta_bin_descriptor(struct psp_context *psp, 4253 const struct psp_fw_bin_desc *desc, 4254 const struct ta_firmware_header_v2_0 *ta_hdr) 4255 { 4256 uint8_t *ucode_start_addr = NULL; 4257 4258 if (!psp || !desc || !ta_hdr) 4259 return -EINVAL; 4260 4261 if (!is_ta_fw_applicable(psp, desc)) 4262 return 0; 4263 4264 ucode_start_addr = (uint8_t *)ta_hdr + 4265 le32_to_cpu(desc->offset_bytes) + 4266 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4267 4268 switch (desc->fw_type) { 4269 case TA_FW_TYPE_PSP_ASD: 4270 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4271 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4272 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4273 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4274 break; 4275 case TA_FW_TYPE_PSP_XGMI: 4276 case TA_FW_TYPE_PSP_XGMI_AUX: 4277 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4278 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4279 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4280 break; 4281 case TA_FW_TYPE_PSP_RAS: 4282 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4283 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4284 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4285 break; 4286 case TA_FW_TYPE_PSP_HDCP: 4287 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4288 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4289 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4290 break; 4291 case TA_FW_TYPE_PSP_DTM: 4292 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4293 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4294 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4295 break; 4296 case TA_FW_TYPE_PSP_RAP: 4297 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4298 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4299 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4300 break; 4301 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4302 psp->securedisplay_context.context.bin_desc.fw_version = 4303 le32_to_cpu(desc->fw_version); 4304 psp->securedisplay_context.context.bin_desc.size_bytes = 4305 le32_to_cpu(desc->size_bytes); 4306 psp->securedisplay_context.context.bin_desc.start_addr = 4307 ucode_start_addr; 4308 break; 4309 default: 4310 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4311 break; 4312 } 4313 4314 return 0; 4315 } 4316 4317 static int parse_ta_v1_microcode(struct psp_context *psp) 4318 { 4319 const struct ta_firmware_header_v1_0 *ta_hdr; 4320 struct amdgpu_device *adev = psp->adev; 4321 4322 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4323 4324 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4325 return -EINVAL; 4326 4327 adev->psp.xgmi_context.context.bin_desc.fw_version = 4328 le32_to_cpu(ta_hdr->xgmi.fw_version); 4329 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4330 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4331 adev->psp.xgmi_context.context.bin_desc.start_addr = 4332 (uint8_t *)ta_hdr + 4333 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4334 4335 adev->psp.ras_context.context.bin_desc.fw_version = 4336 le32_to_cpu(ta_hdr->ras.fw_version); 4337 adev->psp.ras_context.context.bin_desc.size_bytes = 4338 le32_to_cpu(ta_hdr->ras.size_bytes); 4339 adev->psp.ras_context.context.bin_desc.start_addr = 4340 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4341 le32_to_cpu(ta_hdr->ras.offset_bytes); 4342 4343 adev->psp.hdcp_context.context.bin_desc.fw_version = 4344 le32_to_cpu(ta_hdr->hdcp.fw_version); 4345 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4346 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4347 adev->psp.hdcp_context.context.bin_desc.start_addr = 4348 (uint8_t *)ta_hdr + 4349 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4350 4351 adev->psp.dtm_context.context.bin_desc.fw_version = 4352 le32_to_cpu(ta_hdr->dtm.fw_version); 4353 adev->psp.dtm_context.context.bin_desc.size_bytes = 4354 le32_to_cpu(ta_hdr->dtm.size_bytes); 4355 adev->psp.dtm_context.context.bin_desc.start_addr = 4356 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4357 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4358 4359 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4360 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4361 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4362 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4363 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4364 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4365 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4366 4367 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4368 4369 return 0; 4370 } 4371 4372 static int parse_ta_v2_microcode(struct psp_context *psp) 4373 { 4374 const struct ta_firmware_header_v2_0 *ta_hdr; 4375 struct amdgpu_device *adev = psp->adev; 4376 int err = 0; 4377 int ta_index = 0; 4378 4379 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4380 4381 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4382 return -EINVAL; 4383 4384 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4385 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4386 return -EINVAL; 4387 } 4388 4389 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4390 err = parse_ta_bin_descriptor(psp, 4391 &ta_hdr->ta_fw_bin[ta_index], 4392 ta_hdr); 4393 if (err) 4394 return err; 4395 } 4396 4397 return 0; 4398 } 4399 4400 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4401 { 4402 const struct common_firmware_header *hdr; 4403 struct amdgpu_device *adev = psp->adev; 4404 int err; 4405 4406 if (amdgpu_is_kicker_fw(adev)) 4407 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4408 "amdgpu/%s_ta_kicker.bin", chip_name); 4409 else 4410 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4411 "amdgpu/%s_ta.bin", chip_name); 4412 if (err) 4413 return err; 4414 4415 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4416 switch (le16_to_cpu(hdr->header_version_major)) { 4417 case 1: 4418 err = parse_ta_v1_microcode(psp); 4419 break; 4420 case 2: 4421 err = parse_ta_v2_microcode(psp); 4422 break; 4423 default: 4424 dev_err(adev->dev, "unsupported TA header version\n"); 4425 err = -EINVAL; 4426 } 4427 4428 if (err) 4429 amdgpu_ucode_release(&adev->psp.ta_fw); 4430 4431 return err; 4432 } 4433 4434 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4435 { 4436 struct amdgpu_device *adev = psp->adev; 4437 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4438 struct amdgpu_firmware_info *info = NULL; 4439 int err = 0; 4440 4441 if (!amdgpu_sriov_vf(adev)) { 4442 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4443 return -EINVAL; 4444 } 4445 4446 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4447 "amdgpu/%s_cap.bin", chip_name); 4448 if (err) { 4449 if (err == -ENODEV) { 4450 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4451 err = 0; 4452 } else { 4453 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4454 } 4455 goto out; 4456 } 4457 4458 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4459 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4460 info->fw = adev->psp.cap_fw; 4461 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4462 adev->psp.cap_fw->data; 4463 adev->firmware.fw_size += ALIGN( 4464 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4465 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4466 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4467 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4468 4469 return 0; 4470 4471 out: 4472 amdgpu_ucode_release(&adev->psp.cap_fw); 4473 return err; 4474 } 4475 4476 int psp_config_sq_perfmon(struct psp_context *psp, 4477 uint32_t xcp_id, bool core_override_enable, 4478 bool reg_override_enable, bool perfmon_override_enable) 4479 { 4480 int ret; 4481 4482 if (amdgpu_sriov_vf(psp->adev)) 4483 return 0; 4484 4485 if (xcp_id > MAX_XCP) { 4486 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4487 return -EINVAL; 4488 } 4489 4490 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4491 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4492 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4493 return -EINVAL; 4494 } 4495 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4496 4497 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4498 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4499 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4500 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4501 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4502 4503 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4504 if (ret) 4505 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4506 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4507 4508 release_psp_cmd_buf(psp); 4509 return ret; 4510 } 4511 4512 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4513 enum amd_clockgating_state state) 4514 { 4515 return 0; 4516 } 4517 4518 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4519 enum amd_powergating_state state) 4520 { 4521 return 0; 4522 } 4523 4524 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4525 struct device_attribute *attr, 4526 char *buf) 4527 { 4528 struct drm_device *ddev = dev_get_drvdata(dev); 4529 struct amdgpu_device *adev = drm_to_adev(ddev); 4530 struct amdgpu_ip_block *ip_block; 4531 uint32_t fw_ver; 4532 int ret; 4533 4534 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4535 if (!ip_block || !ip_block->status.late_initialized) { 4536 dev_info(adev->dev, "PSP block is not ready yet\n."); 4537 return -EBUSY; 4538 } 4539 4540 mutex_lock(&adev->psp.mutex); 4541 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4542 mutex_unlock(&adev->psp.mutex); 4543 4544 if (ret) { 4545 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4546 return ret; 4547 } 4548 4549 return sysfs_emit(buf, "%x\n", fw_ver); 4550 } 4551 4552 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4553 struct device_attribute *attr, 4554 const char *buf, 4555 size_t count) 4556 { 4557 struct drm_device *ddev = dev_get_drvdata(dev); 4558 struct amdgpu_device *adev = drm_to_adev(ddev); 4559 int ret, idx; 4560 const struct firmware *usbc_pd_fw; 4561 struct amdgpu_bo *fw_buf_bo = NULL; 4562 uint64_t fw_pri_mc_addr; 4563 void *fw_pri_cpu_addr; 4564 struct amdgpu_ip_block *ip_block; 4565 4566 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4567 if (!ip_block || !ip_block->status.late_initialized) { 4568 dev_err(adev->dev, "PSP block is not ready yet."); 4569 return -EBUSY; 4570 } 4571 4572 if (!drm_dev_enter(ddev, &idx)) 4573 return -ENODEV; 4574 4575 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4576 "amdgpu/%s", buf); 4577 if (ret) 4578 goto fail; 4579 4580 /* LFB address which is aligned to 1MB boundary per PSP request */ 4581 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4582 AMDGPU_GEM_DOMAIN_VRAM | 4583 AMDGPU_GEM_DOMAIN_GTT, 4584 &fw_buf_bo, &fw_pri_mc_addr, 4585 &fw_pri_cpu_addr); 4586 if (ret) 4587 goto rel_buf; 4588 4589 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4590 4591 mutex_lock(&adev->psp.mutex); 4592 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4593 mutex_unlock(&adev->psp.mutex); 4594 4595 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4596 4597 rel_buf: 4598 amdgpu_ucode_release(&usbc_pd_fw); 4599 fail: 4600 if (ret) { 4601 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4602 count = ret; 4603 } 4604 4605 drm_dev_exit(idx); 4606 return count; 4607 } 4608 4609 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4610 { 4611 int idx; 4612 4613 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4614 return -ENODEV; 4615 4616 if (!bin_size || bin_size > PSP_1_MEG) { 4617 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 4618 drm_dev_exit(idx); 4619 return -EINVAL; 4620 } 4621 4622 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4623 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4624 4625 drm_dev_exit(idx); 4626 return 0; 4627 } 4628 4629 /** 4630 * DOC: usbc_pd_fw 4631 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4632 * this file will trigger the update process. 4633 */ 4634 static DEVICE_ATTR(usbc_pd_fw, 0644, 4635 psp_usbc_pd_fw_sysfs_read, 4636 psp_usbc_pd_fw_sysfs_write); 4637 /** 4638 * DOC: PTL sysfs attributes 4639 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4640 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4641 * formats for each GPU. 4642 */ 4643 static DEVICE_ATTR(ptl_enable, 0644, 4644 ptl_enable_show, ptl_enable_store); 4645 static DEVICE_ATTR(ptl_format, 0644, 4646 ptl_format_show, ptl_format_store); 4647 static DEVICE_ATTR(ptl_supported_formats, 0444, 4648 ptl_supported_formats_show, NULL); 4649 4650 static struct attribute *ptl_attrs[] = { 4651 &dev_attr_ptl_enable.attr, 4652 &dev_attr_ptl_format.attr, 4653 &dev_attr_ptl_supported_formats.attr, 4654 NULL, 4655 }; 4656 4657 const struct attribute_group amdgpu_ptl_attr_group = { 4658 .name = "ptl", 4659 .attrs = ptl_attrs, 4660 .is_visible = amdgpu_ptl_is_visible, 4661 }; 4662 4663 int is_psp_fw_valid(struct psp_bin_desc bin) 4664 { 4665 return bin.size_bytes; 4666 } 4667 4668 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4669 const struct bin_attribute *bin_attr, 4670 char *buffer, loff_t pos, size_t count) 4671 { 4672 struct device *dev = kobj_to_dev(kobj); 4673 struct drm_device *ddev = dev_get_drvdata(dev); 4674 struct amdgpu_device *adev = drm_to_adev(ddev); 4675 4676 adev->psp.vbflash_done = false; 4677 4678 /* Safeguard against memory drain */ 4679 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4680 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4681 kvfree(adev->psp.vbflash_tmp_buf); 4682 adev->psp.vbflash_tmp_buf = NULL; 4683 adev->psp.vbflash_image_size = 0; 4684 return -ENOMEM; 4685 } 4686 4687 mutex_lock(&adev->psp.mutex); 4688 4689 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4690 if (!adev->psp.vbflash_tmp_buf) { 4691 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4692 if (!adev->psp.vbflash_tmp_buf) { 4693 mutex_unlock(&adev->psp.mutex); 4694 return -ENOMEM; 4695 } 4696 } 4697 4698 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4699 adev->psp.vbflash_image_size += count; 4700 mutex_unlock(&adev->psp.mutex); 4701 4702 dev_dbg(adev->dev, "IFWI staged for update\n"); 4703 4704 return count; 4705 } 4706 4707 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4708 const struct bin_attribute *bin_attr, char *buffer, 4709 loff_t pos, size_t count) 4710 { 4711 struct device *dev = kobj_to_dev(kobj); 4712 struct drm_device *ddev = dev_get_drvdata(dev); 4713 struct amdgpu_device *adev = drm_to_adev(ddev); 4714 struct amdgpu_bo *fw_buf_bo = NULL; 4715 uint64_t fw_pri_mc_addr; 4716 void *fw_pri_cpu_addr; 4717 int ret; 4718 4719 if (adev->psp.vbflash_image_size == 0) 4720 return -EINVAL; 4721 4722 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4723 4724 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4725 AMDGPU_GPU_PAGE_SIZE, 4726 AMDGPU_GEM_DOMAIN_VRAM, 4727 &fw_buf_bo, 4728 &fw_pri_mc_addr, 4729 &fw_pri_cpu_addr); 4730 if (ret) 4731 goto rel_buf; 4732 4733 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4734 4735 mutex_lock(&adev->psp.mutex); 4736 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4737 mutex_unlock(&adev->psp.mutex); 4738 4739 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4740 4741 rel_buf: 4742 kvfree(adev->psp.vbflash_tmp_buf); 4743 adev->psp.vbflash_tmp_buf = NULL; 4744 adev->psp.vbflash_image_size = 0; 4745 4746 if (ret) { 4747 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4748 return ret; 4749 } 4750 4751 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4752 return 0; 4753 } 4754 4755 /** 4756 * DOC: psp_vbflash 4757 * Writing to this file will stage an IFWI for update. Reading from this file 4758 * will trigger the update process. 4759 */ 4760 static const struct bin_attribute psp_vbflash_bin_attr = { 4761 .attr = {.name = "psp_vbflash", .mode = 0660}, 4762 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 4763 .write = amdgpu_psp_vbflash_write, 4764 .read = amdgpu_psp_vbflash_read, 4765 }; 4766 4767 /** 4768 * DOC: psp_vbflash_status 4769 * The status of the flash process. 4770 * 0: IFWI flash not complete. 4771 * 1: IFWI flash complete. 4772 */ 4773 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4774 struct device_attribute *attr, 4775 char *buf) 4776 { 4777 struct drm_device *ddev = dev_get_drvdata(dev); 4778 struct amdgpu_device *adev = drm_to_adev(ddev); 4779 uint32_t vbflash_status; 4780 4781 vbflash_status = psp_vbflash_status(&adev->psp); 4782 if (!adev->psp.vbflash_done) 4783 vbflash_status = 0; 4784 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4785 vbflash_status = 1; 4786 4787 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4788 } 4789 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4790 4791 static const struct bin_attribute *const bin_flash_attrs[] = { 4792 &psp_vbflash_bin_attr, 4793 NULL 4794 }; 4795 4796 static struct attribute *flash_attrs[] = { 4797 &dev_attr_psp_vbflash_status.attr, 4798 &dev_attr_usbc_pd_fw.attr, 4799 NULL 4800 }; 4801 4802 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4803 { 4804 struct device *dev = kobj_to_dev(kobj); 4805 struct drm_device *ddev = dev_get_drvdata(dev); 4806 struct amdgpu_device *adev = drm_to_adev(ddev); 4807 4808 if (attr == &dev_attr_usbc_pd_fw.attr) 4809 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4810 4811 return adev->psp.sup_ifwi_up ? 0440 : 0; 4812 } 4813 4814 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4815 const struct bin_attribute *attr, 4816 int idx) 4817 { 4818 struct device *dev = kobj_to_dev(kobj); 4819 struct drm_device *ddev = dev_get_drvdata(dev); 4820 struct amdgpu_device *adev = drm_to_adev(ddev); 4821 4822 return adev->psp.sup_ifwi_up ? 0660 : 0; 4823 } 4824 4825 const struct attribute_group amdgpu_flash_attr_group = { 4826 .attrs = flash_attrs, 4827 .bin_attrs = bin_flash_attrs, 4828 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4829 .is_visible = amdgpu_flash_attr_is_visible, 4830 }; 4831 4832 #if defined(CONFIG_DEBUG_FS) 4833 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4834 { 4835 struct amdgpu_device *adev = filp->f_inode->i_private; 4836 struct spirom_bo *bo_triplet; 4837 int ret; 4838 4839 /* serialize the open() file calling */ 4840 if (!mutex_trylock(&adev->psp.mutex)) 4841 return -EBUSY; 4842 4843 /* 4844 * make sure only one userpace process is alive for dumping so that 4845 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4846 * let's say the case where one process try opening the file while 4847 * another one has proceeded to read or release. In this way, eliminate 4848 * the use of mutex for read() or release() callback as well. 4849 */ 4850 if (adev->psp.spirom_dump_trip) { 4851 mutex_unlock(&adev->psp.mutex); 4852 return -EBUSY; 4853 } 4854 4855 bo_triplet = kzalloc_obj(struct spirom_bo); 4856 if (!bo_triplet) { 4857 mutex_unlock(&adev->psp.mutex); 4858 return -ENOMEM; 4859 } 4860 4861 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4862 AMDGPU_GPU_PAGE_SIZE, 4863 AMDGPU_GEM_DOMAIN_GTT, 4864 &bo_triplet->bo, 4865 &bo_triplet->mc_addr, 4866 &bo_triplet->cpu_addr); 4867 if (ret) 4868 goto rel_trip; 4869 4870 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4871 if (ret) 4872 goto rel_bo; 4873 4874 adev->psp.spirom_dump_trip = bo_triplet; 4875 mutex_unlock(&adev->psp.mutex); 4876 return 0; 4877 rel_bo: 4878 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4879 &bo_triplet->cpu_addr); 4880 rel_trip: 4881 kfree(bo_triplet); 4882 mutex_unlock(&adev->psp.mutex); 4883 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4884 return ret; 4885 } 4886 4887 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4888 loff_t *pos) 4889 { 4890 struct amdgpu_device *adev = filp->f_inode->i_private; 4891 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4892 4893 if (!bo_triplet) 4894 return -EINVAL; 4895 4896 return simple_read_from_buffer(buf, 4897 size, 4898 pos, bo_triplet->cpu_addr, 4899 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4900 } 4901 4902 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4903 { 4904 struct amdgpu_device *adev = filp->f_inode->i_private; 4905 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4906 4907 if (bo_triplet) { 4908 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4909 &bo_triplet->cpu_addr); 4910 kfree(bo_triplet); 4911 } 4912 4913 adev->psp.spirom_dump_trip = NULL; 4914 return 0; 4915 } 4916 4917 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4918 .owner = THIS_MODULE, 4919 .open = psp_read_spirom_debugfs_open, 4920 .read = psp_read_spirom_debugfs_read, 4921 .release = psp_read_spirom_debugfs_release, 4922 .llseek = default_llseek, 4923 }; 4924 #endif 4925 4926 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4927 { 4928 #if defined(CONFIG_DEBUG_FS) 4929 struct drm_minor *minor = adev_to_drm(adev)->primary; 4930 4931 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4932 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4933 #endif 4934 } 4935 4936 const struct amd_ip_funcs psp_ip_funcs = { 4937 .name = "psp", 4938 .early_init = psp_early_init, 4939 .sw_init = psp_sw_init, 4940 .sw_fini = psp_sw_fini, 4941 .hw_init = psp_hw_init, 4942 .hw_fini = psp_hw_fini, 4943 .suspend = psp_suspend, 4944 .resume = psp_resume, 4945 .set_clockgating_state = psp_set_clockgating_state, 4946 .set_powergating_state = psp_set_powergating_state, 4947 }; 4948 4949 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4950 .type = AMD_IP_BLOCK_TYPE_PSP, 4951 .major = 3, 4952 .minor = 1, 4953 .rev = 0, 4954 .funcs = &psp_ip_funcs, 4955 }; 4956 4957 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4958 .type = AMD_IP_BLOCK_TYPE_PSP, 4959 .major = 10, 4960 .minor = 0, 4961 .rev = 0, 4962 .funcs = &psp_ip_funcs, 4963 }; 4964 4965 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4966 .type = AMD_IP_BLOCK_TYPE_PSP, 4967 .major = 11, 4968 .minor = 0, 4969 .rev = 0, 4970 .funcs = &psp_ip_funcs, 4971 }; 4972 4973 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4974 .type = AMD_IP_BLOCK_TYPE_PSP, 4975 .major = 11, 4976 .minor = 0, 4977 .rev = 8, 4978 .funcs = &psp_ip_funcs, 4979 }; 4980 4981 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4982 .type = AMD_IP_BLOCK_TYPE_PSP, 4983 .major = 12, 4984 .minor = 0, 4985 .rev = 0, 4986 .funcs = &psp_ip_funcs, 4987 }; 4988 4989 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4990 .type = AMD_IP_BLOCK_TYPE_PSP, 4991 .major = 13, 4992 .minor = 0, 4993 .rev = 0, 4994 .funcs = &psp_ip_funcs, 4995 }; 4996 4997 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4998 .type = AMD_IP_BLOCK_TYPE_PSP, 4999 .major = 13, 5000 .minor = 0, 5001 .rev = 4, 5002 .funcs = &psp_ip_funcs, 5003 }; 5004 5005 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 5006 .type = AMD_IP_BLOCK_TYPE_PSP, 5007 .major = 14, 5008 .minor = 0, 5009 .rev = 0, 5010 .funcs = &psp_ip_funcs, 5011 }; 5012 5013 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 5014 .type = AMD_IP_BLOCK_TYPE_PSP, 5015 .major = 15, 5016 .minor = 0, 5017 .rev = 0, 5018 .funcs = &psp_ip_funcs, 5019 }; 5020 5021 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 5022 .type = AMD_IP_BLOCK_TYPE_PSP, 5023 .major = 15, 5024 .minor = 0, 5025 .rev = 8, 5026 .funcs = &psp_ip_funcs, 5027 }; 5028