1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 ret = psp_init_cap_microcode(psp, ucode_prefix); 149 ret &= psp_init_ta_microcode(psp, ucode_prefix); 150 break; 151 case IP_VERSION(13, 0, 10): 152 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 153 ret = psp_init_cap_microcode(psp, ucode_prefix); 154 break; 155 default: 156 return -EINVAL; 157 } 158 return ret; 159 } 160 161 static int psp_early_init(void *handle) 162 { 163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 164 struct psp_context *psp = &adev->psp; 165 166 psp->autoload_supported = true; 167 psp->boot_time_tmr = true; 168 169 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 170 case IP_VERSION(9, 0, 0): 171 psp_v3_1_set_psp_funcs(psp); 172 psp->autoload_supported = false; 173 psp->boot_time_tmr = false; 174 break; 175 case IP_VERSION(10, 0, 0): 176 case IP_VERSION(10, 0, 1): 177 psp_v10_0_set_psp_funcs(psp); 178 psp->autoload_supported = false; 179 psp->boot_time_tmr = false; 180 break; 181 case IP_VERSION(11, 0, 2): 182 case IP_VERSION(11, 0, 4): 183 psp_v11_0_set_psp_funcs(psp); 184 psp->autoload_supported = false; 185 psp->boot_time_tmr = false; 186 break; 187 case IP_VERSION(11, 0, 0): 188 case IP_VERSION(11, 0, 7): 189 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 190 fallthrough; 191 case IP_VERSION(11, 0, 5): 192 case IP_VERSION(11, 0, 9): 193 case IP_VERSION(11, 0, 11): 194 case IP_VERSION(11, 5, 0): 195 case IP_VERSION(11, 0, 12): 196 case IP_VERSION(11, 0, 13): 197 psp_v11_0_set_psp_funcs(psp); 198 psp->boot_time_tmr = false; 199 break; 200 case IP_VERSION(11, 0, 3): 201 case IP_VERSION(12, 0, 1): 202 psp_v12_0_set_psp_funcs(psp); 203 psp->autoload_supported = false; 204 psp->boot_time_tmr = false; 205 break; 206 case IP_VERSION(13, 0, 2): 207 psp->boot_time_tmr = false; 208 fallthrough; 209 case IP_VERSION(13, 0, 6): 210 psp_v13_0_set_psp_funcs(psp); 211 psp->autoload_supported = false; 212 break; 213 case IP_VERSION(13, 0, 1): 214 case IP_VERSION(13, 0, 3): 215 case IP_VERSION(13, 0, 5): 216 case IP_VERSION(13, 0, 8): 217 case IP_VERSION(13, 0, 11): 218 case IP_VERSION(14, 0, 0): 219 case IP_VERSION(14, 0, 1): 220 psp_v13_0_set_psp_funcs(psp); 221 psp->boot_time_tmr = false; 222 break; 223 case IP_VERSION(11, 0, 8): 224 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 225 psp_v11_0_8_set_psp_funcs(psp); 226 } 227 psp->autoload_supported = false; 228 psp->boot_time_tmr = false; 229 break; 230 case IP_VERSION(13, 0, 0): 231 case IP_VERSION(13, 0, 7): 232 case IP_VERSION(13, 0, 10): 233 psp_v13_0_set_psp_funcs(psp); 234 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 235 psp->boot_time_tmr = false; 236 break; 237 case IP_VERSION(13, 0, 4): 238 psp_v13_0_4_set_psp_funcs(psp); 239 psp->boot_time_tmr = false; 240 break; 241 case IP_VERSION(14, 0, 2): 242 case IP_VERSION(14, 0, 3): 243 psp_v14_0_set_psp_funcs(psp); 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 psp->adev = adev; 250 251 adev->psp_timeout = 20000; 252 253 psp_check_pmfw_centralized_cstate_management(psp); 254 255 if (amdgpu_sriov_vf(adev)) 256 return psp_init_sriov_microcode(psp); 257 else 258 return psp_init_microcode(psp); 259 } 260 261 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 262 { 263 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 264 &mem_ctx->shared_buf); 265 mem_ctx->shared_bo = NULL; 266 } 267 268 static void psp_free_shared_bufs(struct psp_context *psp) 269 { 270 void *tmr_buf; 271 void **pptr; 272 273 /* free TMR memory buffer */ 274 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 275 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 276 psp->tmr_bo = NULL; 277 278 /* free xgmi shared memory */ 279 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 280 281 /* free ras shared memory */ 282 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 283 284 /* free hdcp shared memory */ 285 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 286 287 /* free dtm shared memory */ 288 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 289 290 /* free rap shared memory */ 291 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 292 293 /* free securedisplay shared memory */ 294 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 295 296 297 } 298 299 static void psp_memory_training_fini(struct psp_context *psp) 300 { 301 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 302 303 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 304 kfree(ctx->sys_cache); 305 ctx->sys_cache = NULL; 306 } 307 308 static int psp_memory_training_init(struct psp_context *psp) 309 { 310 int ret; 311 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 312 313 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 314 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 315 return 0; 316 } 317 318 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 319 if (ctx->sys_cache == NULL) { 320 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 321 ret = -ENOMEM; 322 goto Err_out; 323 } 324 325 dev_dbg(psp->adev->dev, 326 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 327 ctx->train_data_size, 328 ctx->p2c_train_data_offset, 329 ctx->c2p_train_data_offset); 330 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 331 return 0; 332 333 Err_out: 334 psp_memory_training_fini(psp); 335 return ret; 336 } 337 338 /* 339 * Helper funciton to query psp runtime database entry 340 * 341 * @adev: amdgpu_device pointer 342 * @entry_type: the type of psp runtime database entry 343 * @db_entry: runtime database entry pointer 344 * 345 * Return false if runtime database doesn't exit or entry is invalid 346 * or true if the specific database entry is found, and copy to @db_entry 347 */ 348 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 349 enum psp_runtime_entry_type entry_type, 350 void *db_entry) 351 { 352 uint64_t db_header_pos, db_dir_pos; 353 struct psp_runtime_data_header db_header = {0}; 354 struct psp_runtime_data_directory db_dir = {0}; 355 bool ret = false; 356 int i; 357 358 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) 359 return false; 360 361 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 362 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 363 364 /* read runtime db header from vram */ 365 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 366 sizeof(struct psp_runtime_data_header), false); 367 368 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 369 /* runtime db doesn't exist, exit */ 370 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 371 return false; 372 } 373 374 /* read runtime database entry from vram */ 375 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 376 sizeof(struct psp_runtime_data_directory), false); 377 378 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 379 /* invalid db entry count, exit */ 380 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 381 return false; 382 } 383 384 /* look up for requested entry type */ 385 for (i = 0; i < db_dir.entry_count && !ret; i++) { 386 if (db_dir.entry_list[i].entry_type == entry_type) { 387 switch (entry_type) { 388 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 389 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 390 /* invalid db entry size */ 391 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 392 return false; 393 } 394 /* read runtime database entry */ 395 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 396 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 397 ret = true; 398 break; 399 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 400 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 401 /* invalid db entry size */ 402 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 403 return false; 404 } 405 /* read runtime database entry */ 406 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 407 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 408 ret = true; 409 break; 410 default: 411 ret = false; 412 break; 413 } 414 } 415 } 416 417 return ret; 418 } 419 420 static int psp_sw_init(void *handle) 421 { 422 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 423 struct psp_context *psp = &adev->psp; 424 int ret; 425 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 426 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 427 struct psp_runtime_scpm_entry scpm_entry; 428 429 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 430 if (!psp->cmd) { 431 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 432 ret = -ENOMEM; 433 } 434 435 adev->psp.xgmi_context.supports_extended_data = 436 !adev->gmc.xgmi.connected_to_cpu && 437 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 438 439 memset(&scpm_entry, 0, sizeof(scpm_entry)); 440 if ((psp_get_runtime_db_entry(adev, 441 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 442 &scpm_entry)) && 443 (scpm_entry.scpm_status != SCPM_DISABLE)) { 444 adev->scpm_enabled = true; 445 adev->scpm_status = scpm_entry.scpm_status; 446 } else { 447 adev->scpm_enabled = false; 448 adev->scpm_status = SCPM_DISABLE; 449 } 450 451 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 452 453 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 454 if (psp_get_runtime_db_entry(adev, 455 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 456 &boot_cfg_entry)) { 457 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 458 if ((psp->boot_cfg_bitmask) & 459 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 460 /* If psp runtime database exists, then 461 * only enable two stage memory training 462 * when TWO_STAGE_DRAM_TRAINING bit is set 463 * in runtime database 464 */ 465 mem_training_ctx->enable_mem_training = true; 466 } 467 468 } else { 469 /* If psp runtime database doesn't exist or is 470 * invalid, force enable two stage memory training 471 */ 472 mem_training_ctx->enable_mem_training = true; 473 } 474 475 if (mem_training_ctx->enable_mem_training) { 476 ret = psp_memory_training_init(psp); 477 if (ret) { 478 dev_err(adev->dev, "Failed to initialize memory training!\n"); 479 return ret; 480 } 481 482 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 483 if (ret) { 484 dev_err(adev->dev, "Failed to process memory training!\n"); 485 return ret; 486 } 487 } 488 489 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 490 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 491 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 492 &psp->fw_pri_bo, 493 &psp->fw_pri_mc_addr, 494 &psp->fw_pri_buf); 495 if (ret) 496 return ret; 497 498 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 499 AMDGPU_GEM_DOMAIN_VRAM | 500 AMDGPU_GEM_DOMAIN_GTT, 501 &psp->fence_buf_bo, 502 &psp->fence_buf_mc_addr, 503 &psp->fence_buf); 504 if (ret) 505 goto failed1; 506 507 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 508 AMDGPU_GEM_DOMAIN_VRAM | 509 AMDGPU_GEM_DOMAIN_GTT, 510 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 511 (void **)&psp->cmd_buf_mem); 512 if (ret) 513 goto failed2; 514 515 return 0; 516 517 failed2: 518 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 519 &psp->fence_buf_mc_addr, &psp->fence_buf); 520 failed1: 521 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 522 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 523 return ret; 524 } 525 526 static int psp_sw_fini(void *handle) 527 { 528 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 529 struct psp_context *psp = &adev->psp; 530 struct psp_gfx_cmd_resp *cmd = psp->cmd; 531 532 psp_memory_training_fini(psp); 533 534 amdgpu_ucode_release(&psp->sos_fw); 535 amdgpu_ucode_release(&psp->asd_fw); 536 amdgpu_ucode_release(&psp->ta_fw); 537 amdgpu_ucode_release(&psp->cap_fw); 538 amdgpu_ucode_release(&psp->toc_fw); 539 540 kfree(cmd); 541 cmd = NULL; 542 543 psp_free_shared_bufs(psp); 544 545 if (psp->km_ring.ring_mem) 546 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 547 &psp->km_ring.ring_mem_mc_addr, 548 (void **)&psp->km_ring.ring_mem); 549 550 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 551 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 552 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 553 &psp->fence_buf_mc_addr, &psp->fence_buf); 554 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 555 (void **)&psp->cmd_buf_mem); 556 557 return 0; 558 } 559 560 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 561 uint32_t reg_val, uint32_t mask, bool check_changed) 562 { 563 uint32_t val; 564 int i; 565 struct amdgpu_device *adev = psp->adev; 566 567 if (psp->adev->no_hw_access) 568 return 0; 569 570 for (i = 0; i < adev->usec_timeout; i++) { 571 val = RREG32(reg_index); 572 if (check_changed) { 573 if (val != reg_val) 574 return 0; 575 } else { 576 if ((val & mask) == reg_val) 577 return 0; 578 } 579 udelay(1); 580 } 581 582 return -ETIME; 583 } 584 585 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 586 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 587 { 588 uint32_t val; 589 int i; 590 struct amdgpu_device *adev = psp->adev; 591 592 if (psp->adev->no_hw_access) 593 return 0; 594 595 for (i = 0; i < msec_timeout; i++) { 596 val = RREG32(reg_index); 597 if ((val & mask) == reg_val) 598 return 0; 599 msleep(1); 600 } 601 602 return -ETIME; 603 } 604 605 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 606 { 607 switch (cmd_id) { 608 case GFX_CMD_ID_LOAD_TA: 609 return "LOAD_TA"; 610 case GFX_CMD_ID_UNLOAD_TA: 611 return "UNLOAD_TA"; 612 case GFX_CMD_ID_INVOKE_CMD: 613 return "INVOKE_CMD"; 614 case GFX_CMD_ID_LOAD_ASD: 615 return "LOAD_ASD"; 616 case GFX_CMD_ID_SETUP_TMR: 617 return "SETUP_TMR"; 618 case GFX_CMD_ID_LOAD_IP_FW: 619 return "LOAD_IP_FW"; 620 case GFX_CMD_ID_DESTROY_TMR: 621 return "DESTROY_TMR"; 622 case GFX_CMD_ID_SAVE_RESTORE: 623 return "SAVE_RESTORE_IP_FW"; 624 case GFX_CMD_ID_SETUP_VMR: 625 return "SETUP_VMR"; 626 case GFX_CMD_ID_DESTROY_VMR: 627 return "DESTROY_VMR"; 628 case GFX_CMD_ID_PROG_REG: 629 return "PROG_REG"; 630 case GFX_CMD_ID_GET_FW_ATTESTATION: 631 return "GET_FW_ATTESTATION"; 632 case GFX_CMD_ID_LOAD_TOC: 633 return "ID_LOAD_TOC"; 634 case GFX_CMD_ID_AUTOLOAD_RLC: 635 return "AUTOLOAD_RLC"; 636 case GFX_CMD_ID_BOOT_CFG: 637 return "BOOT_CFG"; 638 default: 639 return "UNKNOWN CMD"; 640 } 641 } 642 643 static int 644 psp_cmd_submit_buf(struct psp_context *psp, 645 struct amdgpu_firmware_info *ucode, 646 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 647 { 648 int ret; 649 int index; 650 int timeout = psp->adev->psp_timeout; 651 bool ras_intr = false; 652 bool skip_unsupport = false; 653 654 if (psp->adev->no_hw_access) 655 return 0; 656 657 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 658 659 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 660 661 index = atomic_inc_return(&psp->fence_value); 662 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 663 if (ret) { 664 atomic_dec(&psp->fence_value); 665 goto exit; 666 } 667 668 amdgpu_device_invalidate_hdp(psp->adev, NULL); 669 while (*((unsigned int *)psp->fence_buf) != index) { 670 if (--timeout == 0) 671 break; 672 /* 673 * Shouldn't wait for timeout when err_event_athub occurs, 674 * because gpu reset thread triggered and lock resource should 675 * be released for psp resume sequence. 676 */ 677 ras_intr = amdgpu_ras_intr_triggered(); 678 if (ras_intr) 679 break; 680 usleep_range(10, 100); 681 amdgpu_device_invalidate_hdp(psp->adev, NULL); 682 } 683 684 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 685 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 686 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 687 688 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 689 690 /* In some cases, psp response status is not 0 even there is no 691 * problem while the command is submitted. Some version of PSP FW 692 * doesn't write 0 to that field. 693 * So here we would like to only print a warning instead of an error 694 * during psp initialization to avoid breaking hw_init and it doesn't 695 * return -EINVAL. 696 */ 697 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 698 if (ucode) 699 dev_warn(psp->adev->dev, 700 "failed to load ucode %s(0x%X) ", 701 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 702 dev_warn(psp->adev->dev, 703 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 704 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 705 psp->cmd_buf_mem->resp.status); 706 /* If any firmware (including CAP) load fails under SRIOV, it should 707 * return failure to stop the VF from initializing. 708 * Also return failure in case of timeout 709 */ 710 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 711 ret = -EINVAL; 712 goto exit; 713 } 714 } 715 716 if (ucode) { 717 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 718 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 719 } 720 721 exit: 722 return ret; 723 } 724 725 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 726 { 727 struct psp_gfx_cmd_resp *cmd = psp->cmd; 728 729 mutex_lock(&psp->mutex); 730 731 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 732 733 return cmd; 734 } 735 736 static void release_psp_cmd_buf(struct psp_context *psp) 737 { 738 mutex_unlock(&psp->mutex); 739 } 740 741 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 742 struct psp_gfx_cmd_resp *cmd, 743 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 744 { 745 struct amdgpu_device *adev = psp->adev; 746 uint32_t size = 0; 747 uint64_t tmr_pa = 0; 748 749 if (tmr_bo) { 750 size = amdgpu_bo_size(tmr_bo); 751 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 752 } 753 754 if (amdgpu_sriov_vf(psp->adev)) 755 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 756 else 757 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 758 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 759 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 760 cmd->cmd.cmd_setup_tmr.buf_size = size; 761 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 762 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 763 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 764 } 765 766 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 767 uint64_t pri_buf_mc, uint32_t size) 768 { 769 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 770 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 771 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 772 cmd->cmd.cmd_load_toc.toc_size = size; 773 } 774 775 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 776 static int psp_load_toc(struct psp_context *psp, 777 uint32_t *tmr_size) 778 { 779 int ret; 780 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 781 782 /* Copy toc to psp firmware private buffer */ 783 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 784 785 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 786 787 ret = psp_cmd_submit_buf(psp, NULL, cmd, 788 psp->fence_buf_mc_addr); 789 if (!ret) 790 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 791 792 release_psp_cmd_buf(psp); 793 794 return ret; 795 } 796 797 /* Set up Trusted Memory Region */ 798 static int psp_tmr_init(struct psp_context *psp) 799 { 800 int ret = 0; 801 int tmr_size; 802 void *tmr_buf; 803 void **pptr; 804 805 /* 806 * According to HW engineer, they prefer the TMR address be "naturally 807 * aligned" , e.g. the start address be an integer divide of TMR size. 808 * 809 * Note: this memory need be reserved till the driver 810 * uninitializes. 811 */ 812 tmr_size = PSP_TMR_SIZE(psp->adev); 813 814 /* For ASICs support RLC autoload, psp will parse the toc 815 * and calculate the total size of TMR needed 816 */ 817 if (!amdgpu_sriov_vf(psp->adev) && 818 psp->toc.start_addr && 819 psp->toc.size_bytes && 820 psp->fw_pri_buf) { 821 ret = psp_load_toc(psp, &tmr_size); 822 if (ret) { 823 dev_err(psp->adev->dev, "Failed to load toc\n"); 824 return ret; 825 } 826 } 827 828 if (!psp->tmr_bo && !psp->boot_time_tmr) { 829 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 830 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 831 PSP_TMR_ALIGNMENT, 832 AMDGPU_HAS_VRAM(psp->adev) ? 833 AMDGPU_GEM_DOMAIN_VRAM : 834 AMDGPU_GEM_DOMAIN_GTT, 835 &psp->tmr_bo, &psp->tmr_mc_addr, 836 pptr); 837 } 838 839 return ret; 840 } 841 842 static bool psp_skip_tmr(struct psp_context *psp) 843 { 844 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 845 case IP_VERSION(11, 0, 9): 846 case IP_VERSION(11, 0, 7): 847 case IP_VERSION(13, 0, 2): 848 case IP_VERSION(13, 0, 6): 849 case IP_VERSION(13, 0, 10): 850 return true; 851 default: 852 return false; 853 } 854 } 855 856 static int psp_tmr_load(struct psp_context *psp) 857 { 858 int ret; 859 struct psp_gfx_cmd_resp *cmd; 860 861 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 862 * Already set up by host driver. 863 */ 864 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 865 return 0; 866 867 cmd = acquire_psp_cmd_buf(psp); 868 869 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 870 if (psp->tmr_bo) 871 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 872 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 873 874 ret = psp_cmd_submit_buf(psp, NULL, cmd, 875 psp->fence_buf_mc_addr); 876 877 release_psp_cmd_buf(psp); 878 879 return ret; 880 } 881 882 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 883 struct psp_gfx_cmd_resp *cmd) 884 { 885 if (amdgpu_sriov_vf(psp->adev)) 886 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 887 else 888 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 889 } 890 891 static int psp_tmr_unload(struct psp_context *psp) 892 { 893 int ret; 894 struct psp_gfx_cmd_resp *cmd; 895 896 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 897 * as TMR is not loaded at all 898 */ 899 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 900 return 0; 901 902 cmd = acquire_psp_cmd_buf(psp); 903 904 psp_prep_tmr_unload_cmd_buf(psp, cmd); 905 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 906 907 ret = psp_cmd_submit_buf(psp, NULL, cmd, 908 psp->fence_buf_mc_addr); 909 910 release_psp_cmd_buf(psp); 911 912 return ret; 913 } 914 915 static int psp_tmr_terminate(struct psp_context *psp) 916 { 917 return psp_tmr_unload(psp); 918 } 919 920 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 921 uint64_t *output_ptr) 922 { 923 int ret; 924 struct psp_gfx_cmd_resp *cmd; 925 926 if (!output_ptr) 927 return -EINVAL; 928 929 if (amdgpu_sriov_vf(psp->adev)) 930 return 0; 931 932 cmd = acquire_psp_cmd_buf(psp); 933 934 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 935 936 ret = psp_cmd_submit_buf(psp, NULL, cmd, 937 psp->fence_buf_mc_addr); 938 939 if (!ret) { 940 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 941 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 942 } 943 944 release_psp_cmd_buf(psp); 945 946 return ret; 947 } 948 949 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 950 { 951 struct psp_context *psp = &adev->psp; 952 struct psp_gfx_cmd_resp *cmd; 953 int ret; 954 955 if (amdgpu_sriov_vf(adev)) 956 return 0; 957 958 cmd = acquire_psp_cmd_buf(psp); 959 960 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 961 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 962 963 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 964 if (!ret) { 965 *boot_cfg = 966 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 967 } 968 969 release_psp_cmd_buf(psp); 970 971 return ret; 972 } 973 974 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 975 { 976 int ret; 977 struct psp_context *psp = &adev->psp; 978 struct psp_gfx_cmd_resp *cmd; 979 980 if (amdgpu_sriov_vf(adev)) 981 return 0; 982 983 cmd = acquire_psp_cmd_buf(psp); 984 985 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 986 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 987 cmd->cmd.boot_cfg.boot_config = boot_cfg; 988 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 989 990 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 991 992 release_psp_cmd_buf(psp); 993 994 return ret; 995 } 996 997 static int psp_rl_load(struct amdgpu_device *adev) 998 { 999 int ret; 1000 struct psp_context *psp = &adev->psp; 1001 struct psp_gfx_cmd_resp *cmd; 1002 1003 if (!is_psp_fw_valid(psp->rl)) 1004 return 0; 1005 1006 cmd = acquire_psp_cmd_buf(psp); 1007 1008 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1009 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1010 1011 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1012 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1013 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1014 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1015 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1016 1017 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1018 1019 release_psp_cmd_buf(psp); 1020 1021 return ret; 1022 } 1023 1024 int psp_spatial_partition(struct psp_context *psp, int mode) 1025 { 1026 struct psp_gfx_cmd_resp *cmd; 1027 int ret; 1028 1029 if (amdgpu_sriov_vf(psp->adev)) 1030 return 0; 1031 1032 cmd = acquire_psp_cmd_buf(psp); 1033 1034 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1035 cmd->cmd.cmd_spatial_part.mode = mode; 1036 1037 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1038 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1039 1040 release_psp_cmd_buf(psp); 1041 1042 return ret; 1043 } 1044 1045 static int psp_asd_initialize(struct psp_context *psp) 1046 { 1047 int ret; 1048 1049 /* If PSP version doesn't match ASD version, asd loading will be failed. 1050 * add workaround to bypass it for sriov now. 1051 * TODO: add version check to make it common 1052 */ 1053 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1054 return 0; 1055 1056 psp->asd_context.mem_context.shared_mc_addr = 0; 1057 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1058 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1059 1060 ret = psp_ta_load(psp, &psp->asd_context); 1061 if (!ret) 1062 psp->asd_context.initialized = true; 1063 1064 return ret; 1065 } 1066 1067 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1068 uint32_t session_id) 1069 { 1070 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1071 cmd->cmd.cmd_unload_ta.session_id = session_id; 1072 } 1073 1074 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1075 { 1076 int ret; 1077 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1078 1079 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1080 1081 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1082 1083 context->resp_status = cmd->resp.status; 1084 1085 release_psp_cmd_buf(psp); 1086 1087 return ret; 1088 } 1089 1090 static int psp_asd_terminate(struct psp_context *psp) 1091 { 1092 int ret; 1093 1094 if (amdgpu_sriov_vf(psp->adev)) 1095 return 0; 1096 1097 if (!psp->asd_context.initialized) 1098 return 0; 1099 1100 ret = psp_ta_unload(psp, &psp->asd_context); 1101 if (!ret) 1102 psp->asd_context.initialized = false; 1103 1104 return ret; 1105 } 1106 1107 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1108 uint32_t id, uint32_t value) 1109 { 1110 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1111 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1112 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1113 } 1114 1115 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1116 uint32_t value) 1117 { 1118 struct psp_gfx_cmd_resp *cmd; 1119 int ret = 0; 1120 1121 if (reg >= PSP_REG_LAST) 1122 return -EINVAL; 1123 1124 cmd = acquire_psp_cmd_buf(psp); 1125 1126 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1127 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1128 if (ret) 1129 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1130 1131 release_psp_cmd_buf(psp); 1132 1133 return ret; 1134 } 1135 1136 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1137 uint64_t ta_bin_mc, 1138 struct ta_context *context) 1139 { 1140 cmd->cmd_id = context->ta_load_type; 1141 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1142 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1143 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1144 1145 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1146 lower_32_bits(context->mem_context.shared_mc_addr); 1147 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1148 upper_32_bits(context->mem_context.shared_mc_addr); 1149 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1150 } 1151 1152 int psp_ta_init_shared_buf(struct psp_context *psp, 1153 struct ta_mem_context *mem_ctx) 1154 { 1155 /* 1156 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1157 * physical) for ta to host memory 1158 */ 1159 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1160 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1161 AMDGPU_GEM_DOMAIN_GTT, 1162 &mem_ctx->shared_bo, 1163 &mem_ctx->shared_mc_addr, 1164 &mem_ctx->shared_buf); 1165 } 1166 1167 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1168 uint32_t ta_cmd_id, 1169 uint32_t session_id) 1170 { 1171 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1172 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1173 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1174 } 1175 1176 int psp_ta_invoke(struct psp_context *psp, 1177 uint32_t ta_cmd_id, 1178 struct ta_context *context) 1179 { 1180 int ret; 1181 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1182 1183 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1184 1185 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1186 psp->fence_buf_mc_addr); 1187 1188 context->resp_status = cmd->resp.status; 1189 1190 release_psp_cmd_buf(psp); 1191 1192 return ret; 1193 } 1194 1195 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1196 { 1197 int ret; 1198 struct psp_gfx_cmd_resp *cmd; 1199 1200 cmd = acquire_psp_cmd_buf(psp); 1201 1202 psp_copy_fw(psp, context->bin_desc.start_addr, 1203 context->bin_desc.size_bytes); 1204 1205 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1206 1207 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1208 psp->fence_buf_mc_addr); 1209 1210 context->resp_status = cmd->resp.status; 1211 1212 if (!ret) 1213 context->session_id = cmd->resp.session_id; 1214 1215 release_psp_cmd_buf(psp); 1216 1217 return ret; 1218 } 1219 1220 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1221 { 1222 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1223 } 1224 1225 int psp_xgmi_terminate(struct psp_context *psp) 1226 { 1227 int ret; 1228 struct amdgpu_device *adev = psp->adev; 1229 1230 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1231 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1232 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1233 adev->gmc.xgmi.connected_to_cpu)) 1234 return 0; 1235 1236 if (!psp->xgmi_context.context.initialized) 1237 return 0; 1238 1239 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1240 1241 psp->xgmi_context.context.initialized = false; 1242 1243 return ret; 1244 } 1245 1246 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1247 { 1248 struct ta_xgmi_shared_memory *xgmi_cmd; 1249 int ret; 1250 1251 if (!psp->ta_fw || 1252 !psp->xgmi_context.context.bin_desc.size_bytes || 1253 !psp->xgmi_context.context.bin_desc.start_addr) 1254 return -ENOENT; 1255 1256 if (!load_ta) 1257 goto invoke; 1258 1259 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1260 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1261 1262 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1263 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1264 if (ret) 1265 return ret; 1266 } 1267 1268 /* Load XGMI TA */ 1269 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1270 if (!ret) 1271 psp->xgmi_context.context.initialized = true; 1272 else 1273 return ret; 1274 1275 invoke: 1276 /* Initialize XGMI session */ 1277 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1278 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1279 xgmi_cmd->flag_extend_link_record = set_extended_data; 1280 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1281 1282 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1283 /* note down the capbility flag for XGMI TA */ 1284 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1285 1286 return ret; 1287 } 1288 1289 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1290 { 1291 struct ta_xgmi_shared_memory *xgmi_cmd; 1292 int ret; 1293 1294 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1295 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1296 1297 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1298 1299 /* Invoke xgmi ta to get hive id */ 1300 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1301 if (ret) 1302 return ret; 1303 1304 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1305 1306 return 0; 1307 } 1308 1309 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1310 { 1311 struct ta_xgmi_shared_memory *xgmi_cmd; 1312 int ret; 1313 1314 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1315 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1316 1317 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1318 1319 /* Invoke xgmi ta to get the node id */ 1320 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1321 if (ret) 1322 return ret; 1323 1324 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1325 1326 return 0; 1327 } 1328 1329 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1330 { 1331 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1332 IP_VERSION(13, 0, 2) && 1333 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1334 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1335 IP_VERSION(13, 0, 6); 1336 } 1337 1338 /* 1339 * Chips that support extended topology information require the driver to 1340 * reflect topology information in the opposite direction. This is 1341 * because the TA has already exceeded its link record limit and if the 1342 * TA holds bi-directional information, the driver would have to do 1343 * multiple fetches instead of just two. 1344 */ 1345 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1346 struct psp_xgmi_node_info node_info) 1347 { 1348 struct amdgpu_device *mirror_adev; 1349 struct amdgpu_hive_info *hive; 1350 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1351 uint64_t dst_node_id = node_info.node_id; 1352 uint8_t dst_num_hops = node_info.num_hops; 1353 uint8_t dst_num_links = node_info.num_links; 1354 1355 hive = amdgpu_get_xgmi_hive(psp->adev); 1356 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1357 struct psp_xgmi_topology_info *mirror_top_info; 1358 int j; 1359 1360 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1361 continue; 1362 1363 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1364 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1365 if (mirror_top_info->nodes[j].node_id != src_node_id) 1366 continue; 1367 1368 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1369 /* 1370 * prevent 0 num_links value re-reflection since reflection 1371 * criteria is based on num_hops (direct or indirect). 1372 * 1373 */ 1374 if (dst_num_links) 1375 mirror_top_info->nodes[j].num_links = dst_num_links; 1376 1377 break; 1378 } 1379 1380 break; 1381 } 1382 1383 amdgpu_put_xgmi_hive(hive); 1384 } 1385 1386 int psp_xgmi_get_topology_info(struct psp_context *psp, 1387 int number_devices, 1388 struct psp_xgmi_topology_info *topology, 1389 bool get_extended_data) 1390 { 1391 struct ta_xgmi_shared_memory *xgmi_cmd; 1392 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1393 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1394 int i; 1395 int ret; 1396 1397 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1398 return -EINVAL; 1399 1400 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1401 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1402 xgmi_cmd->flag_extend_link_record = get_extended_data; 1403 1404 /* Fill in the shared memory with topology information as input */ 1405 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1406 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1407 topology_info_input->num_nodes = number_devices; 1408 1409 for (i = 0; i < topology_info_input->num_nodes; i++) { 1410 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1411 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1412 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1413 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1414 } 1415 1416 /* Invoke xgmi ta to get the topology information */ 1417 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1418 if (ret) 1419 return ret; 1420 1421 /* Read the output topology information from the shared memory */ 1422 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1423 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1424 for (i = 0; i < topology->num_nodes; i++) { 1425 /* extended data will either be 0 or equal to non-extended data */ 1426 if (topology_info_output->nodes[i].num_hops) 1427 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1428 1429 /* non-extended data gets everything here so no need to update */ 1430 if (!get_extended_data) { 1431 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1432 topology->nodes[i].is_sharing_enabled = 1433 topology_info_output->nodes[i].is_sharing_enabled; 1434 topology->nodes[i].sdma_engine = 1435 topology_info_output->nodes[i].sdma_engine; 1436 } 1437 1438 } 1439 1440 /* Invoke xgmi ta again to get the link information */ 1441 if (psp_xgmi_peer_link_info_supported(psp)) { 1442 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1443 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1444 bool requires_reflection = 1445 (psp->xgmi_context.supports_extended_data && 1446 get_extended_data) || 1447 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1448 IP_VERSION(13, 0, 6); 1449 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1450 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1451 1452 /* popluate the shared output buffer rather than the cmd input buffer 1453 * with node_ids as the input for GET_PEER_LINKS command execution. 1454 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1455 * The same requirement for GET_EXTEND_PEER_LINKS command. 1456 */ 1457 if (ta_port_num_support) { 1458 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1459 1460 for (i = 0; i < topology->num_nodes; i++) 1461 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1462 1463 link_extend_info_output->num_nodes = topology->num_nodes; 1464 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1465 } else { 1466 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1467 1468 for (i = 0; i < topology->num_nodes; i++) 1469 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1470 1471 link_info_output->num_nodes = topology->num_nodes; 1472 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1473 } 1474 1475 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1476 if (ret) 1477 return ret; 1478 1479 for (i = 0; i < topology->num_nodes; i++) { 1480 uint8_t node_num_links = ta_port_num_support ? 1481 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1482 /* accumulate num_links on extended data */ 1483 if (get_extended_data) { 1484 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1485 } else { 1486 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1487 topology->nodes[i].num_links : node_num_links; 1488 } 1489 /* popluate the connected port num info if supported and available */ 1490 if (ta_port_num_support && topology->nodes[i].num_links) { 1491 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1492 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1493 } 1494 1495 /* reflect the topology information for bi-directionality */ 1496 if (requires_reflection && topology->nodes[i].num_hops) 1497 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1498 } 1499 } 1500 1501 return 0; 1502 } 1503 1504 int psp_xgmi_set_topology_info(struct psp_context *psp, 1505 int number_devices, 1506 struct psp_xgmi_topology_info *topology) 1507 { 1508 struct ta_xgmi_shared_memory *xgmi_cmd; 1509 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1510 int i; 1511 1512 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1513 return -EINVAL; 1514 1515 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1516 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1517 1518 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1519 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1520 topology_info_input->num_nodes = number_devices; 1521 1522 for (i = 0; i < topology_info_input->num_nodes; i++) { 1523 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1524 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1525 topology_info_input->nodes[i].is_sharing_enabled = 1; 1526 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1527 } 1528 1529 /* Invoke xgmi ta to set topology information */ 1530 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1531 } 1532 1533 // ras begin 1534 static void psp_ras_ta_check_status(struct psp_context *psp) 1535 { 1536 struct ta_ras_shared_memory *ras_cmd = 1537 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1538 1539 switch (ras_cmd->ras_status) { 1540 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1541 dev_warn(psp->adev->dev, 1542 "RAS WARNING: cmd failed due to unsupported ip\n"); 1543 break; 1544 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1545 dev_warn(psp->adev->dev, 1546 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1547 break; 1548 case TA_RAS_STATUS__SUCCESS: 1549 break; 1550 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1551 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1552 dev_warn(psp->adev->dev, 1553 "RAS WARNING: Inject error to critical region is not allowed\n"); 1554 break; 1555 default: 1556 dev_warn(psp->adev->dev, 1557 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1558 break; 1559 } 1560 } 1561 1562 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1563 { 1564 struct ta_ras_shared_memory *ras_cmd; 1565 int ret; 1566 1567 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1568 1569 /* 1570 * TODO: bypass the loading in sriov for now 1571 */ 1572 if (amdgpu_sriov_vf(psp->adev)) 1573 return 0; 1574 1575 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1576 1577 if (amdgpu_ras_intr_triggered()) 1578 return ret; 1579 1580 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1581 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1582 return -EINVAL; 1583 } 1584 1585 if (!ret) { 1586 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1587 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1588 1589 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1590 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1591 dev_warn(psp->adev->dev, 1592 "RAS internal register access blocked\n"); 1593 1594 psp_ras_ta_check_status(psp); 1595 } 1596 1597 return ret; 1598 } 1599 1600 int psp_ras_enable_features(struct psp_context *psp, 1601 union ta_ras_cmd_input *info, bool enable) 1602 { 1603 struct ta_ras_shared_memory *ras_cmd; 1604 int ret; 1605 1606 if (!psp->ras_context.context.initialized) 1607 return -EINVAL; 1608 1609 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1610 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1611 1612 if (enable) 1613 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1614 else 1615 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1616 1617 ras_cmd->ras_in_message = *info; 1618 1619 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1620 if (ret) 1621 return -EINVAL; 1622 1623 return 0; 1624 } 1625 1626 int psp_ras_terminate(struct psp_context *psp) 1627 { 1628 int ret; 1629 1630 /* 1631 * TODO: bypass the terminate in sriov for now 1632 */ 1633 if (amdgpu_sriov_vf(psp->adev)) 1634 return 0; 1635 1636 if (!psp->ras_context.context.initialized) 1637 return 0; 1638 1639 ret = psp_ta_unload(psp, &psp->ras_context.context); 1640 1641 psp->ras_context.context.initialized = false; 1642 1643 return ret; 1644 } 1645 1646 int psp_ras_initialize(struct psp_context *psp) 1647 { 1648 int ret; 1649 uint32_t boot_cfg = 0xFF; 1650 struct amdgpu_device *adev = psp->adev; 1651 struct ta_ras_shared_memory *ras_cmd; 1652 1653 /* 1654 * TODO: bypass the initialize in sriov for now 1655 */ 1656 if (amdgpu_sriov_vf(adev)) 1657 return 0; 1658 1659 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1660 !adev->psp.ras_context.context.bin_desc.start_addr) { 1661 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1662 return 0; 1663 } 1664 1665 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1666 /* query GECC enablement status from boot config 1667 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1668 */ 1669 ret = psp_boot_config_get(adev, &boot_cfg); 1670 if (ret) 1671 dev_warn(adev->dev, "PSP get boot config failed\n"); 1672 1673 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1674 if (!boot_cfg) { 1675 dev_info(adev->dev, "GECC is disabled\n"); 1676 } else { 1677 /* disable GECC in next boot cycle if ras is 1678 * disabled by module parameter amdgpu_ras_enable 1679 * and/or amdgpu_ras_mask, or boot_config_get call 1680 * is failed 1681 */ 1682 ret = psp_boot_config_set(adev, 0); 1683 if (ret) 1684 dev_warn(adev->dev, "PSP set boot config failed\n"); 1685 else 1686 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1687 } 1688 } else { 1689 if (boot_cfg == 1) { 1690 dev_info(adev->dev, "GECC is enabled\n"); 1691 } else { 1692 /* enable GECC in next boot cycle if it is disabled 1693 * in boot config, or force enable GECC if failed to 1694 * get boot configuration 1695 */ 1696 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1697 if (ret) 1698 dev_warn(adev->dev, "PSP set boot config failed\n"); 1699 else 1700 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1701 } 1702 } 1703 } 1704 1705 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1706 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1707 1708 if (!psp->ras_context.context.mem_context.shared_buf) { 1709 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1710 if (ret) 1711 return ret; 1712 } 1713 1714 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1715 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1716 1717 if (amdgpu_ras_is_poison_mode_supported(adev)) 1718 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1719 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1720 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1721 ras_cmd->ras_in_message.init_flags.xcc_mask = 1722 adev->gfx.xcc_mask; 1723 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1724 1725 ret = psp_ta_load(psp, &psp->ras_context.context); 1726 1727 if (!ret && !ras_cmd->ras_status) 1728 psp->ras_context.context.initialized = true; 1729 else { 1730 if (ras_cmd->ras_status) 1731 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1732 1733 /* fail to load RAS TA */ 1734 psp->ras_context.context.initialized = false; 1735 } 1736 1737 return ret; 1738 } 1739 1740 int psp_ras_trigger_error(struct psp_context *psp, 1741 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1742 { 1743 struct ta_ras_shared_memory *ras_cmd; 1744 struct amdgpu_device *adev = psp->adev; 1745 int ret; 1746 uint32_t dev_mask; 1747 1748 if (!psp->ras_context.context.initialized) 1749 return -EINVAL; 1750 1751 switch (info->block_id) { 1752 case TA_RAS_BLOCK__GFX: 1753 dev_mask = GET_MASK(GC, instance_mask); 1754 break; 1755 case TA_RAS_BLOCK__SDMA: 1756 dev_mask = GET_MASK(SDMA0, instance_mask); 1757 break; 1758 case TA_RAS_BLOCK__VCN: 1759 case TA_RAS_BLOCK__JPEG: 1760 dev_mask = GET_MASK(VCN, instance_mask); 1761 break; 1762 default: 1763 dev_mask = instance_mask; 1764 break; 1765 } 1766 1767 /* reuse sub_block_index for backward compatibility */ 1768 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1769 dev_mask &= AMDGPU_RAS_INST_MASK; 1770 info->sub_block_index |= dev_mask; 1771 1772 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1773 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1774 1775 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1776 ras_cmd->ras_in_message.trigger_error = *info; 1777 1778 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1779 if (ret) 1780 return -EINVAL; 1781 1782 /* If err_event_athub occurs error inject was successful, however 1783 * return status from TA is no long reliable 1784 */ 1785 if (amdgpu_ras_intr_triggered()) 1786 return 0; 1787 1788 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1789 return -EACCES; 1790 else if (ras_cmd->ras_status) 1791 return -EINVAL; 1792 1793 return 0; 1794 } 1795 1796 int psp_ras_query_address(struct psp_context *psp, 1797 struct ta_ras_query_address_input *addr_in, 1798 struct ta_ras_query_address_output *addr_out) 1799 { 1800 struct ta_ras_shared_memory *ras_cmd; 1801 int ret; 1802 1803 if (!psp->ras_context.context.initialized) 1804 return -EINVAL; 1805 1806 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1807 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1808 1809 ras_cmd->cmd_id = TA_RAS_COMMAND__QUERY_ADDRESS; 1810 ras_cmd->ras_in_message.address = *addr_in; 1811 1812 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1813 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1814 return -EINVAL; 1815 1816 *addr_out = ras_cmd->ras_out_message.address; 1817 1818 return 0; 1819 } 1820 // ras end 1821 1822 // HDCP start 1823 static int psp_hdcp_initialize(struct psp_context *psp) 1824 { 1825 int ret; 1826 1827 /* 1828 * TODO: bypass the initialize in sriov for now 1829 */ 1830 if (amdgpu_sriov_vf(psp->adev)) 1831 return 0; 1832 1833 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1834 !psp->hdcp_context.context.bin_desc.start_addr) { 1835 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1836 return 0; 1837 } 1838 1839 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1840 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1841 1842 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1843 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1844 if (ret) 1845 return ret; 1846 } 1847 1848 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1849 if (!ret) { 1850 psp->hdcp_context.context.initialized = true; 1851 mutex_init(&psp->hdcp_context.mutex); 1852 } 1853 1854 return ret; 1855 } 1856 1857 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1858 { 1859 /* 1860 * TODO: bypass the loading in sriov for now 1861 */ 1862 if (amdgpu_sriov_vf(psp->adev)) 1863 return 0; 1864 1865 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1866 } 1867 1868 static int psp_hdcp_terminate(struct psp_context *psp) 1869 { 1870 int ret; 1871 1872 /* 1873 * TODO: bypass the terminate in sriov for now 1874 */ 1875 if (amdgpu_sriov_vf(psp->adev)) 1876 return 0; 1877 1878 if (!psp->hdcp_context.context.initialized) 1879 return 0; 1880 1881 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1882 1883 psp->hdcp_context.context.initialized = false; 1884 1885 return ret; 1886 } 1887 // HDCP end 1888 1889 // DTM start 1890 static int psp_dtm_initialize(struct psp_context *psp) 1891 { 1892 int ret; 1893 1894 /* 1895 * TODO: bypass the initialize in sriov for now 1896 */ 1897 if (amdgpu_sriov_vf(psp->adev)) 1898 return 0; 1899 1900 if (!psp->dtm_context.context.bin_desc.size_bytes || 1901 !psp->dtm_context.context.bin_desc.start_addr) { 1902 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1903 return 0; 1904 } 1905 1906 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1907 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1908 1909 if (!psp->dtm_context.context.mem_context.shared_buf) { 1910 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1911 if (ret) 1912 return ret; 1913 } 1914 1915 ret = psp_ta_load(psp, &psp->dtm_context.context); 1916 if (!ret) { 1917 psp->dtm_context.context.initialized = true; 1918 mutex_init(&psp->dtm_context.mutex); 1919 } 1920 1921 return ret; 1922 } 1923 1924 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1925 { 1926 /* 1927 * TODO: bypass the loading in sriov for now 1928 */ 1929 if (amdgpu_sriov_vf(psp->adev)) 1930 return 0; 1931 1932 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1933 } 1934 1935 static int psp_dtm_terminate(struct psp_context *psp) 1936 { 1937 int ret; 1938 1939 /* 1940 * TODO: bypass the terminate in sriov for now 1941 */ 1942 if (amdgpu_sriov_vf(psp->adev)) 1943 return 0; 1944 1945 if (!psp->dtm_context.context.initialized) 1946 return 0; 1947 1948 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1949 1950 psp->dtm_context.context.initialized = false; 1951 1952 return ret; 1953 } 1954 // DTM end 1955 1956 // RAP start 1957 static int psp_rap_initialize(struct psp_context *psp) 1958 { 1959 int ret; 1960 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1961 1962 /* 1963 * TODO: bypass the initialize in sriov for now 1964 */ 1965 if (amdgpu_sriov_vf(psp->adev)) 1966 return 0; 1967 1968 if (!psp->rap_context.context.bin_desc.size_bytes || 1969 !psp->rap_context.context.bin_desc.start_addr) { 1970 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1971 return 0; 1972 } 1973 1974 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1975 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1976 1977 if (!psp->rap_context.context.mem_context.shared_buf) { 1978 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1979 if (ret) 1980 return ret; 1981 } 1982 1983 ret = psp_ta_load(psp, &psp->rap_context.context); 1984 if (!ret) { 1985 psp->rap_context.context.initialized = true; 1986 mutex_init(&psp->rap_context.mutex); 1987 } else 1988 return ret; 1989 1990 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1991 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1992 psp_rap_terminate(psp); 1993 /* free rap shared memory */ 1994 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1995 1996 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1997 ret, status); 1998 1999 return ret; 2000 } 2001 2002 return 0; 2003 } 2004 2005 static int psp_rap_terminate(struct psp_context *psp) 2006 { 2007 int ret; 2008 2009 if (!psp->rap_context.context.initialized) 2010 return 0; 2011 2012 ret = psp_ta_unload(psp, &psp->rap_context.context); 2013 2014 psp->rap_context.context.initialized = false; 2015 2016 return ret; 2017 } 2018 2019 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2020 { 2021 struct ta_rap_shared_memory *rap_cmd; 2022 int ret = 0; 2023 2024 if (!psp->rap_context.context.initialized) 2025 return 0; 2026 2027 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2028 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2029 return -EINVAL; 2030 2031 mutex_lock(&psp->rap_context.mutex); 2032 2033 rap_cmd = (struct ta_rap_shared_memory *) 2034 psp->rap_context.context.mem_context.shared_buf; 2035 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2036 2037 rap_cmd->cmd_id = ta_cmd_id; 2038 rap_cmd->validation_method_id = METHOD_A; 2039 2040 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2041 if (ret) 2042 goto out_unlock; 2043 2044 if (status) 2045 *status = rap_cmd->rap_status; 2046 2047 out_unlock: 2048 mutex_unlock(&psp->rap_context.mutex); 2049 2050 return ret; 2051 } 2052 // RAP end 2053 2054 /* securedisplay start */ 2055 static int psp_securedisplay_initialize(struct psp_context *psp) 2056 { 2057 int ret; 2058 struct ta_securedisplay_cmd *securedisplay_cmd; 2059 2060 /* 2061 * TODO: bypass the initialize in sriov for now 2062 */ 2063 if (amdgpu_sriov_vf(psp->adev)) 2064 return 0; 2065 2066 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2067 !psp->securedisplay_context.context.bin_desc.start_addr) { 2068 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2069 return 0; 2070 } 2071 2072 psp->securedisplay_context.context.mem_context.shared_mem_size = 2073 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2074 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2075 2076 if (!psp->securedisplay_context.context.initialized) { 2077 ret = psp_ta_init_shared_buf(psp, 2078 &psp->securedisplay_context.context.mem_context); 2079 if (ret) 2080 return ret; 2081 } 2082 2083 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2084 if (!ret) { 2085 psp->securedisplay_context.context.initialized = true; 2086 mutex_init(&psp->securedisplay_context.mutex); 2087 } else 2088 return ret; 2089 2090 mutex_lock(&psp->securedisplay_context.mutex); 2091 2092 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2093 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2094 2095 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2096 2097 mutex_unlock(&psp->securedisplay_context.mutex); 2098 2099 if (ret) { 2100 psp_securedisplay_terminate(psp); 2101 /* free securedisplay shared memory */ 2102 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2103 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2104 return -EINVAL; 2105 } 2106 2107 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2108 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2109 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2110 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2111 /* don't try again */ 2112 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2113 } 2114 2115 return 0; 2116 } 2117 2118 static int psp_securedisplay_terminate(struct psp_context *psp) 2119 { 2120 int ret; 2121 2122 /* 2123 * TODO:bypass the terminate in sriov for now 2124 */ 2125 if (amdgpu_sriov_vf(psp->adev)) 2126 return 0; 2127 2128 if (!psp->securedisplay_context.context.initialized) 2129 return 0; 2130 2131 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2132 2133 psp->securedisplay_context.context.initialized = false; 2134 2135 return ret; 2136 } 2137 2138 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2139 { 2140 int ret; 2141 2142 if (!psp->securedisplay_context.context.initialized) 2143 return -EINVAL; 2144 2145 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2146 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2147 return -EINVAL; 2148 2149 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2150 2151 return ret; 2152 } 2153 /* SECUREDISPLAY end */ 2154 2155 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2156 { 2157 struct psp_context *psp = &adev->psp; 2158 int ret = 0; 2159 2160 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2161 ret = psp->funcs->wait_for_bootloader(psp); 2162 2163 return ret; 2164 } 2165 2166 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2167 { 2168 if (psp->funcs && 2169 psp->funcs->get_ras_capability) { 2170 return psp->funcs->get_ras_capability(psp); 2171 } else { 2172 return false; 2173 } 2174 } 2175 2176 static int psp_hw_start(struct psp_context *psp) 2177 { 2178 struct amdgpu_device *adev = psp->adev; 2179 int ret; 2180 2181 if (!amdgpu_sriov_vf(adev)) { 2182 if ((is_psp_fw_valid(psp->kdb)) && 2183 (psp->funcs->bootloader_load_kdb != NULL)) { 2184 ret = psp_bootloader_load_kdb(psp); 2185 if (ret) { 2186 dev_err(adev->dev, "PSP load kdb failed!\n"); 2187 return ret; 2188 } 2189 } 2190 2191 if ((is_psp_fw_valid(psp->spl)) && 2192 (psp->funcs->bootloader_load_spl != NULL)) { 2193 ret = psp_bootloader_load_spl(psp); 2194 if (ret) { 2195 dev_err(adev->dev, "PSP load spl failed!\n"); 2196 return ret; 2197 } 2198 } 2199 2200 if ((is_psp_fw_valid(psp->sys)) && 2201 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2202 ret = psp_bootloader_load_sysdrv(psp); 2203 if (ret) { 2204 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2205 return ret; 2206 } 2207 } 2208 2209 if ((is_psp_fw_valid(psp->soc_drv)) && 2210 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2211 ret = psp_bootloader_load_soc_drv(psp); 2212 if (ret) { 2213 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2214 return ret; 2215 } 2216 } 2217 2218 if ((is_psp_fw_valid(psp->intf_drv)) && 2219 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2220 ret = psp_bootloader_load_intf_drv(psp); 2221 if (ret) { 2222 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2223 return ret; 2224 } 2225 } 2226 2227 if ((is_psp_fw_valid(psp->dbg_drv)) && 2228 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2229 ret = psp_bootloader_load_dbg_drv(psp); 2230 if (ret) { 2231 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2232 return ret; 2233 } 2234 } 2235 2236 if ((is_psp_fw_valid(psp->ras_drv)) && 2237 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2238 ret = psp_bootloader_load_ras_drv(psp); 2239 if (ret) { 2240 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2241 return ret; 2242 } 2243 } 2244 2245 if ((is_psp_fw_valid(psp->sos)) && 2246 (psp->funcs->bootloader_load_sos != NULL)) { 2247 ret = psp_bootloader_load_sos(psp); 2248 if (ret) { 2249 dev_err(adev->dev, "PSP load sos failed!\n"); 2250 return ret; 2251 } 2252 } 2253 } 2254 2255 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2256 if (ret) { 2257 dev_err(adev->dev, "PSP create ring failed!\n"); 2258 return ret; 2259 } 2260 2261 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2262 goto skip_pin_bo; 2263 2264 if (!psp->boot_time_tmr || psp->autoload_supported) { 2265 ret = psp_tmr_init(psp); 2266 if (ret) { 2267 dev_err(adev->dev, "PSP tmr init failed!\n"); 2268 return ret; 2269 } 2270 } 2271 2272 skip_pin_bo: 2273 /* 2274 * For ASICs with DF Cstate management centralized 2275 * to PMFW, TMR setup should be performed after PMFW 2276 * loaded and before other non-psp firmware loaded. 2277 */ 2278 if (psp->pmfw_centralized_cstate_management) { 2279 ret = psp_load_smu_fw(psp); 2280 if (ret) 2281 return ret; 2282 } 2283 2284 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2285 ret = psp_tmr_load(psp); 2286 if (ret) { 2287 dev_err(adev->dev, "PSP load tmr failed!\n"); 2288 return ret; 2289 } 2290 } 2291 2292 return 0; 2293 } 2294 2295 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2296 enum psp_gfx_fw_type *type) 2297 { 2298 switch (ucode->ucode_id) { 2299 case AMDGPU_UCODE_ID_CAP: 2300 *type = GFX_FW_TYPE_CAP; 2301 break; 2302 case AMDGPU_UCODE_ID_SDMA0: 2303 *type = GFX_FW_TYPE_SDMA0; 2304 break; 2305 case AMDGPU_UCODE_ID_SDMA1: 2306 *type = GFX_FW_TYPE_SDMA1; 2307 break; 2308 case AMDGPU_UCODE_ID_SDMA2: 2309 *type = GFX_FW_TYPE_SDMA2; 2310 break; 2311 case AMDGPU_UCODE_ID_SDMA3: 2312 *type = GFX_FW_TYPE_SDMA3; 2313 break; 2314 case AMDGPU_UCODE_ID_SDMA4: 2315 *type = GFX_FW_TYPE_SDMA4; 2316 break; 2317 case AMDGPU_UCODE_ID_SDMA5: 2318 *type = GFX_FW_TYPE_SDMA5; 2319 break; 2320 case AMDGPU_UCODE_ID_SDMA6: 2321 *type = GFX_FW_TYPE_SDMA6; 2322 break; 2323 case AMDGPU_UCODE_ID_SDMA7: 2324 *type = GFX_FW_TYPE_SDMA7; 2325 break; 2326 case AMDGPU_UCODE_ID_CP_MES: 2327 *type = GFX_FW_TYPE_CP_MES; 2328 break; 2329 case AMDGPU_UCODE_ID_CP_MES_DATA: 2330 *type = GFX_FW_TYPE_MES_STACK; 2331 break; 2332 case AMDGPU_UCODE_ID_CP_MES1: 2333 *type = GFX_FW_TYPE_CP_MES_KIQ; 2334 break; 2335 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2336 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2337 break; 2338 case AMDGPU_UCODE_ID_CP_CE: 2339 *type = GFX_FW_TYPE_CP_CE; 2340 break; 2341 case AMDGPU_UCODE_ID_CP_PFP: 2342 *type = GFX_FW_TYPE_CP_PFP; 2343 break; 2344 case AMDGPU_UCODE_ID_CP_ME: 2345 *type = GFX_FW_TYPE_CP_ME; 2346 break; 2347 case AMDGPU_UCODE_ID_CP_MEC1: 2348 *type = GFX_FW_TYPE_CP_MEC; 2349 break; 2350 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2351 *type = GFX_FW_TYPE_CP_MEC_ME1; 2352 break; 2353 case AMDGPU_UCODE_ID_CP_MEC2: 2354 *type = GFX_FW_TYPE_CP_MEC; 2355 break; 2356 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2357 *type = GFX_FW_TYPE_CP_MEC_ME2; 2358 break; 2359 case AMDGPU_UCODE_ID_RLC_P: 2360 *type = GFX_FW_TYPE_RLC_P; 2361 break; 2362 case AMDGPU_UCODE_ID_RLC_V: 2363 *type = GFX_FW_TYPE_RLC_V; 2364 break; 2365 case AMDGPU_UCODE_ID_RLC_G: 2366 *type = GFX_FW_TYPE_RLC_G; 2367 break; 2368 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2369 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2370 break; 2371 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2372 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2373 break; 2374 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2375 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2376 break; 2377 case AMDGPU_UCODE_ID_RLC_IRAM: 2378 *type = GFX_FW_TYPE_RLC_IRAM; 2379 break; 2380 case AMDGPU_UCODE_ID_RLC_DRAM: 2381 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2382 break; 2383 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2384 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2385 break; 2386 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2387 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2388 break; 2389 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2390 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2391 break; 2392 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2393 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2394 break; 2395 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2396 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2397 break; 2398 case AMDGPU_UCODE_ID_SMC: 2399 *type = GFX_FW_TYPE_SMU; 2400 break; 2401 case AMDGPU_UCODE_ID_PPTABLE: 2402 *type = GFX_FW_TYPE_PPTABLE; 2403 break; 2404 case AMDGPU_UCODE_ID_UVD: 2405 *type = GFX_FW_TYPE_UVD; 2406 break; 2407 case AMDGPU_UCODE_ID_UVD1: 2408 *type = GFX_FW_TYPE_UVD1; 2409 break; 2410 case AMDGPU_UCODE_ID_VCE: 2411 *type = GFX_FW_TYPE_VCE; 2412 break; 2413 case AMDGPU_UCODE_ID_VCN: 2414 *type = GFX_FW_TYPE_VCN; 2415 break; 2416 case AMDGPU_UCODE_ID_VCN1: 2417 *type = GFX_FW_TYPE_VCN1; 2418 break; 2419 case AMDGPU_UCODE_ID_DMCU_ERAM: 2420 *type = GFX_FW_TYPE_DMCU_ERAM; 2421 break; 2422 case AMDGPU_UCODE_ID_DMCU_INTV: 2423 *type = GFX_FW_TYPE_DMCU_ISR; 2424 break; 2425 case AMDGPU_UCODE_ID_VCN0_RAM: 2426 *type = GFX_FW_TYPE_VCN0_RAM; 2427 break; 2428 case AMDGPU_UCODE_ID_VCN1_RAM: 2429 *type = GFX_FW_TYPE_VCN1_RAM; 2430 break; 2431 case AMDGPU_UCODE_ID_DMCUB: 2432 *type = GFX_FW_TYPE_DMUB; 2433 break; 2434 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2435 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2436 break; 2437 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2438 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2439 break; 2440 case AMDGPU_UCODE_ID_IMU_I: 2441 *type = GFX_FW_TYPE_IMU_I; 2442 break; 2443 case AMDGPU_UCODE_ID_IMU_D: 2444 *type = GFX_FW_TYPE_IMU_D; 2445 break; 2446 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2447 *type = GFX_FW_TYPE_RS64_PFP; 2448 break; 2449 case AMDGPU_UCODE_ID_CP_RS64_ME: 2450 *type = GFX_FW_TYPE_RS64_ME; 2451 break; 2452 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2453 *type = GFX_FW_TYPE_RS64_MEC; 2454 break; 2455 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2456 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2457 break; 2458 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2459 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2460 break; 2461 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2462 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2463 break; 2464 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2465 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2466 break; 2467 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2468 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2469 break; 2470 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2471 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2472 break; 2473 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2474 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2475 break; 2476 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2477 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2478 break; 2479 case AMDGPU_UCODE_ID_VPE_CTX: 2480 *type = GFX_FW_TYPE_VPEC_FW1; 2481 break; 2482 case AMDGPU_UCODE_ID_VPE_CTL: 2483 *type = GFX_FW_TYPE_VPEC_FW2; 2484 break; 2485 case AMDGPU_UCODE_ID_VPE: 2486 *type = GFX_FW_TYPE_VPE; 2487 break; 2488 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2489 *type = GFX_FW_TYPE_UMSCH_UCODE; 2490 break; 2491 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2492 *type = GFX_FW_TYPE_UMSCH_DATA; 2493 break; 2494 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2495 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2496 break; 2497 case AMDGPU_UCODE_ID_P2S_TABLE: 2498 *type = GFX_FW_TYPE_P2S_TABLE; 2499 break; 2500 case AMDGPU_UCODE_ID_JPEG_RAM: 2501 *type = GFX_FW_TYPE_JPEG_RAM; 2502 break; 2503 case AMDGPU_UCODE_ID_MAXIMUM: 2504 default: 2505 return -EINVAL; 2506 } 2507 2508 return 0; 2509 } 2510 2511 static void psp_print_fw_hdr(struct psp_context *psp, 2512 struct amdgpu_firmware_info *ucode) 2513 { 2514 struct amdgpu_device *adev = psp->adev; 2515 struct common_firmware_header *hdr; 2516 2517 switch (ucode->ucode_id) { 2518 case AMDGPU_UCODE_ID_SDMA0: 2519 case AMDGPU_UCODE_ID_SDMA1: 2520 case AMDGPU_UCODE_ID_SDMA2: 2521 case AMDGPU_UCODE_ID_SDMA3: 2522 case AMDGPU_UCODE_ID_SDMA4: 2523 case AMDGPU_UCODE_ID_SDMA5: 2524 case AMDGPU_UCODE_ID_SDMA6: 2525 case AMDGPU_UCODE_ID_SDMA7: 2526 hdr = (struct common_firmware_header *) 2527 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2528 amdgpu_ucode_print_sdma_hdr(hdr); 2529 break; 2530 case AMDGPU_UCODE_ID_CP_CE: 2531 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2532 amdgpu_ucode_print_gfx_hdr(hdr); 2533 break; 2534 case AMDGPU_UCODE_ID_CP_PFP: 2535 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2536 amdgpu_ucode_print_gfx_hdr(hdr); 2537 break; 2538 case AMDGPU_UCODE_ID_CP_ME: 2539 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2540 amdgpu_ucode_print_gfx_hdr(hdr); 2541 break; 2542 case AMDGPU_UCODE_ID_CP_MEC1: 2543 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2544 amdgpu_ucode_print_gfx_hdr(hdr); 2545 break; 2546 case AMDGPU_UCODE_ID_RLC_G: 2547 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2548 amdgpu_ucode_print_rlc_hdr(hdr); 2549 break; 2550 case AMDGPU_UCODE_ID_SMC: 2551 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2552 amdgpu_ucode_print_smc_hdr(hdr); 2553 break; 2554 default: 2555 break; 2556 } 2557 } 2558 2559 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2560 struct amdgpu_firmware_info *ucode, 2561 struct psp_gfx_cmd_resp *cmd) 2562 { 2563 int ret; 2564 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2565 2566 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2567 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2568 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2569 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2570 2571 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2572 if (ret) 2573 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2574 2575 return ret; 2576 } 2577 2578 int psp_execute_ip_fw_load(struct psp_context *psp, 2579 struct amdgpu_firmware_info *ucode) 2580 { 2581 int ret = 0; 2582 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2583 2584 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2585 if (!ret) { 2586 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2587 psp->fence_buf_mc_addr); 2588 } 2589 2590 release_psp_cmd_buf(psp); 2591 2592 return ret; 2593 } 2594 2595 static int psp_load_p2s_table(struct psp_context *psp) 2596 { 2597 int ret; 2598 struct amdgpu_device *adev = psp->adev; 2599 struct amdgpu_firmware_info *ucode = 2600 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2601 2602 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2603 return 0; 2604 2605 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) { 2606 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2607 0x0036003C; 2608 if (psp->sos.fw_version < supp_vers) 2609 return 0; 2610 } 2611 2612 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2613 return 0; 2614 2615 ret = psp_execute_ip_fw_load(psp, ucode); 2616 2617 return ret; 2618 } 2619 2620 static int psp_load_smu_fw(struct psp_context *psp) 2621 { 2622 int ret; 2623 struct amdgpu_device *adev = psp->adev; 2624 struct amdgpu_firmware_info *ucode = 2625 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2626 struct amdgpu_ras *ras = psp->ras_context.ras; 2627 2628 /* 2629 * Skip SMU FW reloading in case of using BACO for runpm only, 2630 * as SMU is always alive. 2631 */ 2632 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2633 return 0; 2634 2635 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2636 return 0; 2637 2638 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2639 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2640 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2641 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2642 if (ret) 2643 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2644 } 2645 2646 ret = psp_execute_ip_fw_load(psp, ucode); 2647 2648 if (ret) 2649 dev_err(adev->dev, "PSP load smu failed!\n"); 2650 2651 return ret; 2652 } 2653 2654 static bool fw_load_skip_check(struct psp_context *psp, 2655 struct amdgpu_firmware_info *ucode) 2656 { 2657 if (!ucode->fw || !ucode->ucode_size) 2658 return true; 2659 2660 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2661 return true; 2662 2663 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2664 (psp_smu_reload_quirk(psp) || 2665 psp->autoload_supported || 2666 psp->pmfw_centralized_cstate_management)) 2667 return true; 2668 2669 if (amdgpu_sriov_vf(psp->adev) && 2670 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2671 return true; 2672 2673 if (psp->autoload_supported && 2674 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2675 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2676 /* skip mec JT when autoload is enabled */ 2677 return true; 2678 2679 return false; 2680 } 2681 2682 int psp_load_fw_list(struct psp_context *psp, 2683 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2684 { 2685 int ret = 0, i; 2686 struct amdgpu_firmware_info *ucode; 2687 2688 for (i = 0; i < ucode_count; ++i) { 2689 ucode = ucode_list[i]; 2690 psp_print_fw_hdr(psp, ucode); 2691 ret = psp_execute_ip_fw_load(psp, ucode); 2692 if (ret) 2693 return ret; 2694 } 2695 return ret; 2696 } 2697 2698 static int psp_load_non_psp_fw(struct psp_context *psp) 2699 { 2700 int i, ret; 2701 struct amdgpu_firmware_info *ucode; 2702 struct amdgpu_device *adev = psp->adev; 2703 2704 if (psp->autoload_supported && 2705 !psp->pmfw_centralized_cstate_management) { 2706 ret = psp_load_smu_fw(psp); 2707 if (ret) 2708 return ret; 2709 } 2710 2711 /* Load P2S table first if it's available */ 2712 psp_load_p2s_table(psp); 2713 2714 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2715 ucode = &adev->firmware.ucode[i]; 2716 2717 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2718 !fw_load_skip_check(psp, ucode)) { 2719 ret = psp_load_smu_fw(psp); 2720 if (ret) 2721 return ret; 2722 continue; 2723 } 2724 2725 if (fw_load_skip_check(psp, ucode)) 2726 continue; 2727 2728 if (psp->autoload_supported && 2729 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 2730 IP_VERSION(11, 0, 7) || 2731 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2732 IP_VERSION(11, 0, 11) || 2733 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2734 IP_VERSION(11, 0, 12)) && 2735 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2736 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2737 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2738 /* PSP only receive one SDMA fw for sienna_cichlid, 2739 * as all four sdma fw are same 2740 */ 2741 continue; 2742 2743 psp_print_fw_hdr(psp, ucode); 2744 2745 ret = psp_execute_ip_fw_load(psp, ucode); 2746 if (ret) 2747 return ret; 2748 2749 /* Start rlc autoload after psp recieved all the gfx firmware */ 2750 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2751 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2752 ret = psp_rlc_autoload_start(psp); 2753 if (ret) { 2754 dev_err(adev->dev, "Failed to start rlc autoload\n"); 2755 return ret; 2756 } 2757 } 2758 } 2759 2760 return 0; 2761 } 2762 2763 static int psp_load_fw(struct amdgpu_device *adev) 2764 { 2765 int ret; 2766 struct psp_context *psp = &adev->psp; 2767 2768 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2769 /* should not destroy ring, only stop */ 2770 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2771 } else { 2772 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2773 2774 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2775 if (ret) { 2776 dev_err(adev->dev, "PSP ring init failed!\n"); 2777 goto failed; 2778 } 2779 } 2780 2781 ret = psp_hw_start(psp); 2782 if (ret) 2783 goto failed; 2784 2785 ret = psp_load_non_psp_fw(psp); 2786 if (ret) 2787 goto failed1; 2788 2789 ret = psp_asd_initialize(psp); 2790 if (ret) { 2791 dev_err(adev->dev, "PSP load asd failed!\n"); 2792 goto failed1; 2793 } 2794 2795 ret = psp_rl_load(adev); 2796 if (ret) { 2797 dev_err(adev->dev, "PSP load RL failed!\n"); 2798 goto failed1; 2799 } 2800 2801 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2802 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2803 ret = psp_xgmi_initialize(psp, false, true); 2804 /* Warning the XGMI seesion initialize failure 2805 * Instead of stop driver initialization 2806 */ 2807 if (ret) 2808 dev_err(psp->adev->dev, 2809 "XGMI: Failed to initialize XGMI session\n"); 2810 } 2811 } 2812 2813 if (psp->ta_fw) { 2814 ret = psp_ras_initialize(psp); 2815 if (ret) 2816 dev_err(psp->adev->dev, 2817 "RAS: Failed to initialize RAS\n"); 2818 2819 ret = psp_hdcp_initialize(psp); 2820 if (ret) 2821 dev_err(psp->adev->dev, 2822 "HDCP: Failed to initialize HDCP\n"); 2823 2824 ret = psp_dtm_initialize(psp); 2825 if (ret) 2826 dev_err(psp->adev->dev, 2827 "DTM: Failed to initialize DTM\n"); 2828 2829 ret = psp_rap_initialize(psp); 2830 if (ret) 2831 dev_err(psp->adev->dev, 2832 "RAP: Failed to initialize RAP\n"); 2833 2834 ret = psp_securedisplay_initialize(psp); 2835 if (ret) 2836 dev_err(psp->adev->dev, 2837 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2838 } 2839 2840 return 0; 2841 2842 failed1: 2843 psp_free_shared_bufs(psp); 2844 failed: 2845 /* 2846 * all cleanup jobs (xgmi terminate, ras terminate, 2847 * ring destroy, cmd/fence/fw buffers destory, 2848 * psp->cmd destory) are delayed to psp_hw_fini 2849 */ 2850 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2851 return ret; 2852 } 2853 2854 static int psp_hw_init(void *handle) 2855 { 2856 int ret; 2857 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2858 2859 mutex_lock(&adev->firmware.mutex); 2860 /* 2861 * This sequence is just used on hw_init only once, no need on 2862 * resume. 2863 */ 2864 ret = amdgpu_ucode_init_bo(adev); 2865 if (ret) 2866 goto failed; 2867 2868 ret = psp_load_fw(adev); 2869 if (ret) { 2870 dev_err(adev->dev, "PSP firmware loading failed\n"); 2871 goto failed; 2872 } 2873 2874 mutex_unlock(&adev->firmware.mutex); 2875 return 0; 2876 2877 failed: 2878 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2879 mutex_unlock(&adev->firmware.mutex); 2880 return -EINVAL; 2881 } 2882 2883 static int psp_hw_fini(void *handle) 2884 { 2885 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2886 struct psp_context *psp = &adev->psp; 2887 2888 if (psp->ta_fw) { 2889 psp_ras_terminate(psp); 2890 psp_securedisplay_terminate(psp); 2891 psp_rap_terminate(psp); 2892 psp_dtm_terminate(psp); 2893 psp_hdcp_terminate(psp); 2894 2895 if (adev->gmc.xgmi.num_physical_nodes > 1) 2896 psp_xgmi_terminate(psp); 2897 } 2898 2899 psp_asd_terminate(psp); 2900 psp_tmr_terminate(psp); 2901 2902 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2903 2904 return 0; 2905 } 2906 2907 static int psp_suspend(void *handle) 2908 { 2909 int ret = 0; 2910 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2911 struct psp_context *psp = &adev->psp; 2912 2913 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2914 psp->xgmi_context.context.initialized) { 2915 ret = psp_xgmi_terminate(psp); 2916 if (ret) { 2917 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 2918 goto out; 2919 } 2920 } 2921 2922 if (psp->ta_fw) { 2923 ret = psp_ras_terminate(psp); 2924 if (ret) { 2925 dev_err(adev->dev, "Failed to terminate ras ta\n"); 2926 goto out; 2927 } 2928 ret = psp_hdcp_terminate(psp); 2929 if (ret) { 2930 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 2931 goto out; 2932 } 2933 ret = psp_dtm_terminate(psp); 2934 if (ret) { 2935 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 2936 goto out; 2937 } 2938 ret = psp_rap_terminate(psp); 2939 if (ret) { 2940 dev_err(adev->dev, "Failed to terminate rap ta\n"); 2941 goto out; 2942 } 2943 ret = psp_securedisplay_terminate(psp); 2944 if (ret) { 2945 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 2946 goto out; 2947 } 2948 } 2949 2950 ret = psp_asd_terminate(psp); 2951 if (ret) { 2952 dev_err(adev->dev, "Failed to terminate asd\n"); 2953 goto out; 2954 } 2955 2956 ret = psp_tmr_terminate(psp); 2957 if (ret) { 2958 dev_err(adev->dev, "Failed to terminate tmr\n"); 2959 goto out; 2960 } 2961 2962 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2963 if (ret) 2964 dev_err(adev->dev, "PSP ring stop failed\n"); 2965 2966 out: 2967 return ret; 2968 } 2969 2970 static int psp_resume(void *handle) 2971 { 2972 int ret; 2973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2974 struct psp_context *psp = &adev->psp; 2975 2976 dev_info(adev->dev, "PSP is resuming...\n"); 2977 2978 if (psp->mem_train_ctx.enable_mem_training) { 2979 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2980 if (ret) { 2981 dev_err(adev->dev, "Failed to process memory training!\n"); 2982 return ret; 2983 } 2984 } 2985 2986 mutex_lock(&adev->firmware.mutex); 2987 2988 ret = psp_hw_start(psp); 2989 if (ret) 2990 goto failed; 2991 2992 ret = psp_load_non_psp_fw(psp); 2993 if (ret) 2994 goto failed; 2995 2996 ret = psp_asd_initialize(psp); 2997 if (ret) { 2998 dev_err(adev->dev, "PSP load asd failed!\n"); 2999 goto failed; 3000 } 3001 3002 ret = psp_rl_load(adev); 3003 if (ret) { 3004 dev_err(adev->dev, "PSP load RL failed!\n"); 3005 goto failed; 3006 } 3007 3008 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3009 ret = psp_xgmi_initialize(psp, false, true); 3010 /* Warning the XGMI seesion initialize failure 3011 * Instead of stop driver initialization 3012 */ 3013 if (ret) 3014 dev_err(psp->adev->dev, 3015 "XGMI: Failed to initialize XGMI session\n"); 3016 } 3017 3018 if (psp->ta_fw) { 3019 ret = psp_ras_initialize(psp); 3020 if (ret) 3021 dev_err(psp->adev->dev, 3022 "RAS: Failed to initialize RAS\n"); 3023 3024 ret = psp_hdcp_initialize(psp); 3025 if (ret) 3026 dev_err(psp->adev->dev, 3027 "HDCP: Failed to initialize HDCP\n"); 3028 3029 ret = psp_dtm_initialize(psp); 3030 if (ret) 3031 dev_err(psp->adev->dev, 3032 "DTM: Failed to initialize DTM\n"); 3033 3034 ret = psp_rap_initialize(psp); 3035 if (ret) 3036 dev_err(psp->adev->dev, 3037 "RAP: Failed to initialize RAP\n"); 3038 3039 ret = psp_securedisplay_initialize(psp); 3040 if (ret) 3041 dev_err(psp->adev->dev, 3042 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3043 } 3044 3045 mutex_unlock(&adev->firmware.mutex); 3046 3047 return 0; 3048 3049 failed: 3050 dev_err(adev->dev, "PSP resume failed\n"); 3051 mutex_unlock(&adev->firmware.mutex); 3052 return ret; 3053 } 3054 3055 int psp_gpu_reset(struct amdgpu_device *adev) 3056 { 3057 int ret; 3058 3059 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3060 return 0; 3061 3062 mutex_lock(&adev->psp.mutex); 3063 ret = psp_mode1_reset(&adev->psp); 3064 mutex_unlock(&adev->psp.mutex); 3065 3066 return ret; 3067 } 3068 3069 int psp_rlc_autoload_start(struct psp_context *psp) 3070 { 3071 int ret; 3072 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3073 3074 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3075 3076 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3077 psp->fence_buf_mc_addr); 3078 3079 release_psp_cmd_buf(psp); 3080 3081 return ret; 3082 } 3083 3084 int psp_ring_cmd_submit(struct psp_context *psp, 3085 uint64_t cmd_buf_mc_addr, 3086 uint64_t fence_mc_addr, 3087 int index) 3088 { 3089 unsigned int psp_write_ptr_reg = 0; 3090 struct psp_gfx_rb_frame *write_frame; 3091 struct psp_ring *ring = &psp->km_ring; 3092 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3093 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3094 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3095 struct amdgpu_device *adev = psp->adev; 3096 uint32_t ring_size_dw = ring->ring_size / 4; 3097 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3098 3099 /* KM (GPCOM) prepare write pointer */ 3100 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3101 3102 /* Update KM RB frame pointer to new frame */ 3103 /* write_frame ptr increments by size of rb_frame in bytes */ 3104 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3105 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3106 write_frame = ring_buffer_start; 3107 else 3108 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3109 /* Check invalid write_frame ptr address */ 3110 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3111 dev_err(adev->dev, 3112 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3113 ring_buffer_start, ring_buffer_end, write_frame); 3114 dev_err(adev->dev, 3115 "write_frame is pointing to address out of bounds\n"); 3116 return -EINVAL; 3117 } 3118 3119 /* Initialize KM RB frame */ 3120 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3121 3122 /* Update KM RB frame */ 3123 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3124 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3125 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3126 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3127 write_frame->fence_value = index; 3128 amdgpu_device_flush_hdp(adev, NULL); 3129 3130 /* Update the write Pointer in DWORDs */ 3131 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3132 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3133 return 0; 3134 } 3135 3136 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3137 { 3138 struct amdgpu_device *adev = psp->adev; 3139 char fw_name[PSP_FW_NAME_LEN]; 3140 const struct psp_firmware_header_v1_0 *asd_hdr; 3141 int err = 0; 3142 3143 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 3144 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 3145 if (err) 3146 goto out; 3147 3148 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3149 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3150 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3151 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3152 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3153 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3154 return 0; 3155 out: 3156 amdgpu_ucode_release(&adev->psp.asd_fw); 3157 return err; 3158 } 3159 3160 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3161 { 3162 struct amdgpu_device *adev = psp->adev; 3163 char fw_name[PSP_FW_NAME_LEN]; 3164 const struct psp_firmware_header_v1_0 *toc_hdr; 3165 int err = 0; 3166 3167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3168 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 3169 if (err) 3170 goto out; 3171 3172 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3173 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3174 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3175 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3176 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3177 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3178 return 0; 3179 out: 3180 amdgpu_ucode_release(&adev->psp.toc_fw); 3181 return err; 3182 } 3183 3184 static int parse_sos_bin_descriptor(struct psp_context *psp, 3185 const struct psp_fw_bin_desc *desc, 3186 const struct psp_firmware_header_v2_0 *sos_hdr) 3187 { 3188 uint8_t *ucode_start_addr = NULL; 3189 3190 if (!psp || !desc || !sos_hdr) 3191 return -EINVAL; 3192 3193 ucode_start_addr = (uint8_t *)sos_hdr + 3194 le32_to_cpu(desc->offset_bytes) + 3195 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3196 3197 switch (desc->fw_type) { 3198 case PSP_FW_TYPE_PSP_SOS: 3199 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3200 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3201 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3202 psp->sos.start_addr = ucode_start_addr; 3203 break; 3204 case PSP_FW_TYPE_PSP_SYS_DRV: 3205 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3206 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3207 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3208 psp->sys.start_addr = ucode_start_addr; 3209 break; 3210 case PSP_FW_TYPE_PSP_KDB: 3211 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3212 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3213 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3214 psp->kdb.start_addr = ucode_start_addr; 3215 break; 3216 case PSP_FW_TYPE_PSP_TOC: 3217 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3218 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3219 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3220 psp->toc.start_addr = ucode_start_addr; 3221 break; 3222 case PSP_FW_TYPE_PSP_SPL: 3223 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3224 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3225 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3226 psp->spl.start_addr = ucode_start_addr; 3227 break; 3228 case PSP_FW_TYPE_PSP_RL: 3229 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3230 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3231 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3232 psp->rl.start_addr = ucode_start_addr; 3233 break; 3234 case PSP_FW_TYPE_PSP_SOC_DRV: 3235 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3236 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3237 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3238 psp->soc_drv.start_addr = ucode_start_addr; 3239 break; 3240 case PSP_FW_TYPE_PSP_INTF_DRV: 3241 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3242 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3243 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3244 psp->intf_drv.start_addr = ucode_start_addr; 3245 break; 3246 case PSP_FW_TYPE_PSP_DBG_DRV: 3247 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3248 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3249 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3250 psp->dbg_drv.start_addr = ucode_start_addr; 3251 break; 3252 case PSP_FW_TYPE_PSP_RAS_DRV: 3253 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3254 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3255 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3256 psp->ras_drv.start_addr = ucode_start_addr; 3257 break; 3258 default: 3259 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3260 break; 3261 } 3262 3263 return 0; 3264 } 3265 3266 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3267 { 3268 const struct psp_firmware_header_v1_0 *sos_hdr; 3269 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3270 uint8_t *ucode_array_start_addr; 3271 3272 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3273 ucode_array_start_addr = (uint8_t *)sos_hdr + 3274 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3275 3276 if (adev->gmc.xgmi.connected_to_cpu || 3277 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3278 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3279 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3280 3281 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3282 adev->psp.sys.start_addr = ucode_array_start_addr; 3283 3284 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3285 adev->psp.sos.start_addr = ucode_array_start_addr + 3286 le32_to_cpu(sos_hdr->sos.offset_bytes); 3287 } else { 3288 /* Load alternate PSP SOS FW */ 3289 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3290 3291 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3292 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3293 3294 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3295 adev->psp.sys.start_addr = ucode_array_start_addr + 3296 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3297 3298 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3299 adev->psp.sos.start_addr = ucode_array_start_addr + 3300 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3301 } 3302 3303 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3304 dev_warn(adev->dev, "PSP SOS FW not available"); 3305 return -EINVAL; 3306 } 3307 3308 return 0; 3309 } 3310 3311 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3312 { 3313 struct amdgpu_device *adev = psp->adev; 3314 char fw_name[PSP_FW_NAME_LEN]; 3315 const struct psp_firmware_header_v1_0 *sos_hdr; 3316 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3317 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3318 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3319 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3320 int err = 0; 3321 uint8_t *ucode_array_start_addr; 3322 int fw_index = 0; 3323 3324 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3325 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3326 if (err) 3327 goto out; 3328 3329 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3330 ucode_array_start_addr = (uint8_t *)sos_hdr + 3331 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3332 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3333 3334 switch (sos_hdr->header.header_version_major) { 3335 case 1: 3336 err = psp_init_sos_base_fw(adev); 3337 if (err) 3338 goto out; 3339 3340 if (sos_hdr->header.header_version_minor == 1) { 3341 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3342 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3343 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3344 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3345 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3346 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3347 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3348 } 3349 if (sos_hdr->header.header_version_minor == 2) { 3350 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3351 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3352 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3353 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3354 } 3355 if (sos_hdr->header.header_version_minor == 3) { 3356 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3357 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3358 adev->psp.toc.start_addr = ucode_array_start_addr + 3359 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3360 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3361 adev->psp.kdb.start_addr = ucode_array_start_addr + 3362 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3363 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3364 adev->psp.spl.start_addr = ucode_array_start_addr + 3365 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3366 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3367 adev->psp.rl.start_addr = ucode_array_start_addr + 3368 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3369 } 3370 break; 3371 case 2: 3372 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3373 3374 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3375 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3376 err = -EINVAL; 3377 goto out; 3378 } 3379 3380 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3381 err = parse_sos_bin_descriptor(psp, 3382 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3383 sos_hdr_v2_0); 3384 if (err) 3385 goto out; 3386 } 3387 break; 3388 default: 3389 dev_err(adev->dev, 3390 "unsupported psp sos firmware\n"); 3391 err = -EINVAL; 3392 goto out; 3393 } 3394 3395 return 0; 3396 out: 3397 amdgpu_ucode_release(&adev->psp.sos_fw); 3398 3399 return err; 3400 } 3401 3402 static int parse_ta_bin_descriptor(struct psp_context *psp, 3403 const struct psp_fw_bin_desc *desc, 3404 const struct ta_firmware_header_v2_0 *ta_hdr) 3405 { 3406 uint8_t *ucode_start_addr = NULL; 3407 3408 if (!psp || !desc || !ta_hdr) 3409 return -EINVAL; 3410 3411 ucode_start_addr = (uint8_t *)ta_hdr + 3412 le32_to_cpu(desc->offset_bytes) + 3413 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3414 3415 switch (desc->fw_type) { 3416 case TA_FW_TYPE_PSP_ASD: 3417 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3418 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3419 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3420 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3421 break; 3422 case TA_FW_TYPE_PSP_XGMI: 3423 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3424 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3425 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3426 break; 3427 case TA_FW_TYPE_PSP_RAS: 3428 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3429 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3430 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3431 break; 3432 case TA_FW_TYPE_PSP_HDCP: 3433 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3434 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3435 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3436 break; 3437 case TA_FW_TYPE_PSP_DTM: 3438 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3439 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3440 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3441 break; 3442 case TA_FW_TYPE_PSP_RAP: 3443 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3444 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3445 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3446 break; 3447 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3448 psp->securedisplay_context.context.bin_desc.fw_version = 3449 le32_to_cpu(desc->fw_version); 3450 psp->securedisplay_context.context.bin_desc.size_bytes = 3451 le32_to_cpu(desc->size_bytes); 3452 psp->securedisplay_context.context.bin_desc.start_addr = 3453 ucode_start_addr; 3454 break; 3455 default: 3456 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3457 break; 3458 } 3459 3460 return 0; 3461 } 3462 3463 static int parse_ta_v1_microcode(struct psp_context *psp) 3464 { 3465 const struct ta_firmware_header_v1_0 *ta_hdr; 3466 struct amdgpu_device *adev = psp->adev; 3467 3468 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3469 3470 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3471 return -EINVAL; 3472 3473 adev->psp.xgmi_context.context.bin_desc.fw_version = 3474 le32_to_cpu(ta_hdr->xgmi.fw_version); 3475 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3476 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3477 adev->psp.xgmi_context.context.bin_desc.start_addr = 3478 (uint8_t *)ta_hdr + 3479 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3480 3481 adev->psp.ras_context.context.bin_desc.fw_version = 3482 le32_to_cpu(ta_hdr->ras.fw_version); 3483 adev->psp.ras_context.context.bin_desc.size_bytes = 3484 le32_to_cpu(ta_hdr->ras.size_bytes); 3485 adev->psp.ras_context.context.bin_desc.start_addr = 3486 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3487 le32_to_cpu(ta_hdr->ras.offset_bytes); 3488 3489 adev->psp.hdcp_context.context.bin_desc.fw_version = 3490 le32_to_cpu(ta_hdr->hdcp.fw_version); 3491 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3492 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3493 adev->psp.hdcp_context.context.bin_desc.start_addr = 3494 (uint8_t *)ta_hdr + 3495 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3496 3497 adev->psp.dtm_context.context.bin_desc.fw_version = 3498 le32_to_cpu(ta_hdr->dtm.fw_version); 3499 adev->psp.dtm_context.context.bin_desc.size_bytes = 3500 le32_to_cpu(ta_hdr->dtm.size_bytes); 3501 adev->psp.dtm_context.context.bin_desc.start_addr = 3502 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3503 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3504 3505 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3506 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3507 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3508 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3509 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3510 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3511 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3512 3513 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3514 3515 return 0; 3516 } 3517 3518 static int parse_ta_v2_microcode(struct psp_context *psp) 3519 { 3520 const struct ta_firmware_header_v2_0 *ta_hdr; 3521 struct amdgpu_device *adev = psp->adev; 3522 int err = 0; 3523 int ta_index = 0; 3524 3525 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3526 3527 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3528 return -EINVAL; 3529 3530 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3531 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3532 return -EINVAL; 3533 } 3534 3535 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3536 err = parse_ta_bin_descriptor(psp, 3537 &ta_hdr->ta_fw_bin[ta_index], 3538 ta_hdr); 3539 if (err) 3540 return err; 3541 } 3542 3543 return 0; 3544 } 3545 3546 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3547 { 3548 const struct common_firmware_header *hdr; 3549 struct amdgpu_device *adev = psp->adev; 3550 char fw_name[PSP_FW_NAME_LEN]; 3551 int err; 3552 3553 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3554 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3555 if (err) 3556 return err; 3557 3558 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3559 switch (le16_to_cpu(hdr->header_version_major)) { 3560 case 1: 3561 err = parse_ta_v1_microcode(psp); 3562 break; 3563 case 2: 3564 err = parse_ta_v2_microcode(psp); 3565 break; 3566 default: 3567 dev_err(adev->dev, "unsupported TA header version\n"); 3568 err = -EINVAL; 3569 } 3570 3571 if (err) 3572 amdgpu_ucode_release(&adev->psp.ta_fw); 3573 3574 return err; 3575 } 3576 3577 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3578 { 3579 struct amdgpu_device *adev = psp->adev; 3580 char fw_name[PSP_FW_NAME_LEN]; 3581 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3582 struct amdgpu_firmware_info *info = NULL; 3583 int err = 0; 3584 3585 if (!amdgpu_sriov_vf(adev)) { 3586 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3587 return -EINVAL; 3588 } 3589 3590 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3591 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3592 if (err) { 3593 if (err == -ENODEV) { 3594 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3595 err = 0; 3596 goto out; 3597 } 3598 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3599 } 3600 3601 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3602 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3603 info->fw = adev->psp.cap_fw; 3604 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3605 adev->psp.cap_fw->data; 3606 adev->firmware.fw_size += ALIGN( 3607 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3608 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3609 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3610 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3611 3612 return 0; 3613 3614 out: 3615 amdgpu_ucode_release(&adev->psp.cap_fw); 3616 return err; 3617 } 3618 3619 static int psp_set_clockgating_state(void *handle, 3620 enum amd_clockgating_state state) 3621 { 3622 return 0; 3623 } 3624 3625 static int psp_set_powergating_state(void *handle, 3626 enum amd_powergating_state state) 3627 { 3628 return 0; 3629 } 3630 3631 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3632 struct device_attribute *attr, 3633 char *buf) 3634 { 3635 struct drm_device *ddev = dev_get_drvdata(dev); 3636 struct amdgpu_device *adev = drm_to_adev(ddev); 3637 uint32_t fw_ver; 3638 int ret; 3639 3640 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3641 dev_info(adev->dev, "PSP block is not ready yet\n."); 3642 return -EBUSY; 3643 } 3644 3645 mutex_lock(&adev->psp.mutex); 3646 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3647 mutex_unlock(&adev->psp.mutex); 3648 3649 if (ret) { 3650 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 3651 return ret; 3652 } 3653 3654 return sysfs_emit(buf, "%x\n", fw_ver); 3655 } 3656 3657 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3658 struct device_attribute *attr, 3659 const char *buf, 3660 size_t count) 3661 { 3662 struct drm_device *ddev = dev_get_drvdata(dev); 3663 struct amdgpu_device *adev = drm_to_adev(ddev); 3664 int ret, idx; 3665 char fw_name[100]; 3666 const struct firmware *usbc_pd_fw; 3667 struct amdgpu_bo *fw_buf_bo = NULL; 3668 uint64_t fw_pri_mc_addr; 3669 void *fw_pri_cpu_addr; 3670 3671 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3672 dev_err(adev->dev, "PSP block is not ready yet."); 3673 return -EBUSY; 3674 } 3675 3676 if (!drm_dev_enter(ddev, &idx)) 3677 return -ENODEV; 3678 3679 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3680 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3681 if (ret) 3682 goto fail; 3683 3684 /* LFB address which is aligned to 1MB boundary per PSP request */ 3685 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3686 AMDGPU_GEM_DOMAIN_VRAM | 3687 AMDGPU_GEM_DOMAIN_GTT, 3688 &fw_buf_bo, &fw_pri_mc_addr, 3689 &fw_pri_cpu_addr); 3690 if (ret) 3691 goto rel_buf; 3692 3693 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3694 3695 mutex_lock(&adev->psp.mutex); 3696 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3697 mutex_unlock(&adev->psp.mutex); 3698 3699 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3700 3701 rel_buf: 3702 release_firmware(usbc_pd_fw); 3703 fail: 3704 if (ret) { 3705 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 3706 count = ret; 3707 } 3708 3709 drm_dev_exit(idx); 3710 return count; 3711 } 3712 3713 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3714 { 3715 int idx; 3716 3717 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3718 return; 3719 3720 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3721 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3722 3723 drm_dev_exit(idx); 3724 } 3725 3726 /** 3727 * DOC: usbc_pd_fw 3728 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3729 * this file will trigger the update process. 3730 */ 3731 static DEVICE_ATTR(usbc_pd_fw, 0644, 3732 psp_usbc_pd_fw_sysfs_read, 3733 psp_usbc_pd_fw_sysfs_write); 3734 3735 int is_psp_fw_valid(struct psp_bin_desc bin) 3736 { 3737 return bin.size_bytes; 3738 } 3739 3740 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3741 struct bin_attribute *bin_attr, 3742 char *buffer, loff_t pos, size_t count) 3743 { 3744 struct device *dev = kobj_to_dev(kobj); 3745 struct drm_device *ddev = dev_get_drvdata(dev); 3746 struct amdgpu_device *adev = drm_to_adev(ddev); 3747 3748 adev->psp.vbflash_done = false; 3749 3750 /* Safeguard against memory drain */ 3751 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3752 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 3753 kvfree(adev->psp.vbflash_tmp_buf); 3754 adev->psp.vbflash_tmp_buf = NULL; 3755 adev->psp.vbflash_image_size = 0; 3756 return -ENOMEM; 3757 } 3758 3759 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3760 if (!adev->psp.vbflash_tmp_buf) { 3761 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3762 if (!adev->psp.vbflash_tmp_buf) 3763 return -ENOMEM; 3764 } 3765 3766 mutex_lock(&adev->psp.mutex); 3767 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3768 adev->psp.vbflash_image_size += count; 3769 mutex_unlock(&adev->psp.mutex); 3770 3771 dev_dbg(adev->dev, "IFWI staged for update\n"); 3772 3773 return count; 3774 } 3775 3776 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3777 struct bin_attribute *bin_attr, char *buffer, 3778 loff_t pos, size_t count) 3779 { 3780 struct device *dev = kobj_to_dev(kobj); 3781 struct drm_device *ddev = dev_get_drvdata(dev); 3782 struct amdgpu_device *adev = drm_to_adev(ddev); 3783 struct amdgpu_bo *fw_buf_bo = NULL; 3784 uint64_t fw_pri_mc_addr; 3785 void *fw_pri_cpu_addr; 3786 int ret; 3787 3788 if (adev->psp.vbflash_image_size == 0) 3789 return -EINVAL; 3790 3791 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 3792 3793 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3794 AMDGPU_GPU_PAGE_SIZE, 3795 AMDGPU_GEM_DOMAIN_VRAM, 3796 &fw_buf_bo, 3797 &fw_pri_mc_addr, 3798 &fw_pri_cpu_addr); 3799 if (ret) 3800 goto rel_buf; 3801 3802 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3803 3804 mutex_lock(&adev->psp.mutex); 3805 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3806 mutex_unlock(&adev->psp.mutex); 3807 3808 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3809 3810 rel_buf: 3811 kvfree(adev->psp.vbflash_tmp_buf); 3812 adev->psp.vbflash_tmp_buf = NULL; 3813 adev->psp.vbflash_image_size = 0; 3814 3815 if (ret) { 3816 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 3817 return ret; 3818 } 3819 3820 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 3821 return 0; 3822 } 3823 3824 /** 3825 * DOC: psp_vbflash 3826 * Writing to this file will stage an IFWI for update. Reading from this file 3827 * will trigger the update process. 3828 */ 3829 static struct bin_attribute psp_vbflash_bin_attr = { 3830 .attr = {.name = "psp_vbflash", .mode = 0660}, 3831 .size = 0, 3832 .write = amdgpu_psp_vbflash_write, 3833 .read = amdgpu_psp_vbflash_read, 3834 }; 3835 3836 /** 3837 * DOC: psp_vbflash_status 3838 * The status of the flash process. 3839 * 0: IFWI flash not complete. 3840 * 1: IFWI flash complete. 3841 */ 3842 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3843 struct device_attribute *attr, 3844 char *buf) 3845 { 3846 struct drm_device *ddev = dev_get_drvdata(dev); 3847 struct amdgpu_device *adev = drm_to_adev(ddev); 3848 uint32_t vbflash_status; 3849 3850 vbflash_status = psp_vbflash_status(&adev->psp); 3851 if (!adev->psp.vbflash_done) 3852 vbflash_status = 0; 3853 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3854 vbflash_status = 1; 3855 3856 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3857 } 3858 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3859 3860 static struct bin_attribute *bin_flash_attrs[] = { 3861 &psp_vbflash_bin_attr, 3862 NULL 3863 }; 3864 3865 static struct attribute *flash_attrs[] = { 3866 &dev_attr_psp_vbflash_status.attr, 3867 &dev_attr_usbc_pd_fw.attr, 3868 NULL 3869 }; 3870 3871 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 3872 { 3873 struct device *dev = kobj_to_dev(kobj); 3874 struct drm_device *ddev = dev_get_drvdata(dev); 3875 struct amdgpu_device *adev = drm_to_adev(ddev); 3876 3877 if (attr == &dev_attr_usbc_pd_fw.attr) 3878 return adev->psp.sup_pd_fw_up ? 0660 : 0; 3879 3880 return adev->psp.sup_ifwi_up ? 0440 : 0; 3881 } 3882 3883 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 3884 struct bin_attribute *attr, 3885 int idx) 3886 { 3887 struct device *dev = kobj_to_dev(kobj); 3888 struct drm_device *ddev = dev_get_drvdata(dev); 3889 struct amdgpu_device *adev = drm_to_adev(ddev); 3890 3891 return adev->psp.sup_ifwi_up ? 0660 : 0; 3892 } 3893 3894 const struct attribute_group amdgpu_flash_attr_group = { 3895 .attrs = flash_attrs, 3896 .bin_attrs = bin_flash_attrs, 3897 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 3898 .is_visible = amdgpu_flash_attr_is_visible, 3899 }; 3900 3901 const struct amd_ip_funcs psp_ip_funcs = { 3902 .name = "psp", 3903 .early_init = psp_early_init, 3904 .late_init = NULL, 3905 .sw_init = psp_sw_init, 3906 .sw_fini = psp_sw_fini, 3907 .hw_init = psp_hw_init, 3908 .hw_fini = psp_hw_fini, 3909 .suspend = psp_suspend, 3910 .resume = psp_resume, 3911 .is_idle = NULL, 3912 .check_soft_reset = NULL, 3913 .wait_for_idle = NULL, 3914 .soft_reset = NULL, 3915 .set_clockgating_state = psp_set_clockgating_state, 3916 .set_powergating_state = psp_set_powergating_state, 3917 }; 3918 3919 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3920 .type = AMD_IP_BLOCK_TYPE_PSP, 3921 .major = 3, 3922 .minor = 1, 3923 .rev = 0, 3924 .funcs = &psp_ip_funcs, 3925 }; 3926 3927 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3928 .type = AMD_IP_BLOCK_TYPE_PSP, 3929 .major = 10, 3930 .minor = 0, 3931 .rev = 0, 3932 .funcs = &psp_ip_funcs, 3933 }; 3934 3935 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3936 .type = AMD_IP_BLOCK_TYPE_PSP, 3937 .major = 11, 3938 .minor = 0, 3939 .rev = 0, 3940 .funcs = &psp_ip_funcs, 3941 }; 3942 3943 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3944 .type = AMD_IP_BLOCK_TYPE_PSP, 3945 .major = 11, 3946 .minor = 0, 3947 .rev = 8, 3948 .funcs = &psp_ip_funcs, 3949 }; 3950 3951 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3952 .type = AMD_IP_BLOCK_TYPE_PSP, 3953 .major = 12, 3954 .minor = 0, 3955 .rev = 0, 3956 .funcs = &psp_ip_funcs, 3957 }; 3958 3959 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3960 .type = AMD_IP_BLOCK_TYPE_PSP, 3961 .major = 13, 3962 .minor = 0, 3963 .rev = 0, 3964 .funcs = &psp_ip_funcs, 3965 }; 3966 3967 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3968 .type = AMD_IP_BLOCK_TYPE_PSP, 3969 .major = 13, 3970 .minor = 0, 3971 .rev = 4, 3972 .funcs = &psp_ip_funcs, 3973 }; 3974 3975 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 3976 .type = AMD_IP_BLOCK_TYPE_PSP, 3977 .major = 14, 3978 .minor = 0, 3979 .rev = 0, 3980 .funcs = &psp_ip_funcs, 3981 }; 3982