1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 psp_v15_0_0_set_psp_funcs(psp); 279 psp->boot_time_tmr = false; 280 break; 281 case IP_VERSION(15, 0, 8): 282 psp_v15_0_8_set_psp_funcs(psp); 283 break; 284 default: 285 return -EINVAL; 286 } 287 288 psp->adev = adev; 289 290 adev->psp_timeout = 20000; 291 292 psp_check_pmfw_centralized_cstate_management(psp); 293 294 if (amdgpu_sriov_vf(adev)) 295 return psp_init_sriov_microcode(psp); 296 else 297 return psp_init_microcode(psp); 298 } 299 300 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 301 { 302 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 303 &mem_ctx->shared_buf); 304 mem_ctx->shared_bo = NULL; 305 } 306 307 static void psp_free_shared_bufs(struct psp_context *psp) 308 { 309 void *tmr_buf; 310 void **pptr; 311 312 /* free TMR memory buffer */ 313 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 314 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 315 psp->tmr_bo = NULL; 316 317 /* free xgmi shared memory */ 318 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 319 320 /* free ras shared memory */ 321 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 322 323 /* free hdcp shared memory */ 324 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 325 326 /* free dtm shared memory */ 327 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 328 329 /* free rap shared memory */ 330 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 331 332 /* free securedisplay shared memory */ 333 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 334 335 336 } 337 338 static void psp_memory_training_fini(struct psp_context *psp) 339 { 340 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 341 342 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 343 kfree(ctx->sys_cache); 344 ctx->sys_cache = NULL; 345 } 346 347 static int psp_memory_training_init(struct psp_context *psp) 348 { 349 int ret; 350 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 351 352 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 353 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 354 return 0; 355 } 356 357 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 358 if (ctx->sys_cache == NULL) { 359 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 360 ret = -ENOMEM; 361 goto Err_out; 362 } 363 364 dev_dbg(psp->adev->dev, 365 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 366 ctx->train_data_size, 367 ctx->p2c_train_data_offset, 368 ctx->c2p_train_data_offset); 369 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 370 return 0; 371 372 Err_out: 373 psp_memory_training_fini(psp); 374 return ret; 375 } 376 377 /* 378 * Helper funciton to query psp runtime database entry 379 * 380 * @adev: amdgpu_device pointer 381 * @entry_type: the type of psp runtime database entry 382 * @db_entry: runtime database entry pointer 383 * 384 * Return false if runtime database doesn't exit or entry is invalid 385 * or true if the specific database entry is found, and copy to @db_entry 386 */ 387 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 388 enum psp_runtime_entry_type entry_type, 389 void *db_entry) 390 { 391 uint64_t db_header_pos, db_dir_pos; 392 struct psp_runtime_data_header db_header = {0}; 393 struct psp_runtime_data_directory db_dir = {0}; 394 bool ret = false; 395 int i; 396 397 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 398 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 399 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 401 return false; 402 403 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 404 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 405 406 /* read runtime db header from vram */ 407 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 408 sizeof(struct psp_runtime_data_header), false); 409 410 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 411 /* runtime db doesn't exist, exit */ 412 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 413 return false; 414 } 415 416 /* read runtime database entry from vram */ 417 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 418 sizeof(struct psp_runtime_data_directory), false); 419 420 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 421 /* invalid db entry count, exit */ 422 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 423 return false; 424 } 425 426 /* look up for requested entry type */ 427 for (i = 0; i < db_dir.entry_count && !ret; i++) { 428 if (db_dir.entry_list[i].entry_type == entry_type) { 429 switch (entry_type) { 430 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 431 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 432 /* invalid db entry size */ 433 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 434 return false; 435 } 436 /* read runtime database entry */ 437 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 438 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 439 ret = true; 440 break; 441 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 442 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 443 /* invalid db entry size */ 444 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 445 return false; 446 } 447 /* read runtime database entry */ 448 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 449 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 450 ret = true; 451 break; 452 default: 453 ret = false; 454 break; 455 } 456 } 457 } 458 459 return ret; 460 } 461 462 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 463 { 464 struct amdgpu_device *adev = ip_block->adev; 465 struct psp_context *psp = &adev->psp; 466 int ret; 467 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 468 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 469 struct psp_runtime_scpm_entry scpm_entry; 470 471 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 472 if (!psp->cmd) { 473 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 474 return -ENOMEM; 475 } 476 477 adev->psp.xgmi_context.supports_extended_data = 478 !adev->gmc.xgmi.connected_to_cpu && 479 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 480 481 memset(&scpm_entry, 0, sizeof(scpm_entry)); 482 if ((psp_get_runtime_db_entry(adev, 483 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 484 &scpm_entry)) && 485 (scpm_entry.scpm_status != SCPM_DISABLE)) { 486 adev->scpm_enabled = true; 487 adev->scpm_status = scpm_entry.scpm_status; 488 } else { 489 adev->scpm_enabled = false; 490 adev->scpm_status = SCPM_DISABLE; 491 } 492 493 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 494 495 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 496 if (psp_get_runtime_db_entry(adev, 497 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 498 &boot_cfg_entry)) { 499 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 500 if ((psp->boot_cfg_bitmask) & 501 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 502 /* If psp runtime database exists, then 503 * only enable two stage memory training 504 * when TWO_STAGE_DRAM_TRAINING bit is set 505 * in runtime database 506 */ 507 mem_training_ctx->enable_mem_training = true; 508 } 509 510 } else { 511 /* If psp runtime database doesn't exist or is 512 * invalid, force enable two stage memory training 513 */ 514 mem_training_ctx->enable_mem_training = true; 515 } 516 517 if (mem_training_ctx->enable_mem_training) { 518 ret = psp_memory_training_init(psp); 519 if (ret) { 520 dev_err(adev->dev, "Failed to initialize memory training!\n"); 521 return ret; 522 } 523 524 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 525 if (ret) { 526 dev_err(adev->dev, "Failed to process memory training!\n"); 527 return ret; 528 } 529 } 530 531 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 532 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 533 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 534 &psp->fw_pri_bo, 535 &psp->fw_pri_mc_addr, 536 &psp->fw_pri_buf); 537 if (ret) 538 return ret; 539 540 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 541 AMDGPU_GEM_DOMAIN_VRAM | 542 AMDGPU_GEM_DOMAIN_GTT, 543 &psp->fence_buf_bo, 544 &psp->fence_buf_mc_addr, 545 &psp->fence_buf); 546 if (ret) 547 goto failed1; 548 549 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 550 AMDGPU_GEM_DOMAIN_VRAM | 551 AMDGPU_GEM_DOMAIN_GTT, 552 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 553 (void **)&psp->cmd_buf_mem); 554 if (ret) 555 goto failed2; 556 557 return 0; 558 559 failed2: 560 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 561 &psp->fence_buf_mc_addr, &psp->fence_buf); 562 failed1: 563 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 564 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 565 return ret; 566 } 567 568 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 569 { 570 struct amdgpu_device *adev = ip_block->adev; 571 struct psp_context *psp = &adev->psp; 572 573 psp_memory_training_fini(psp); 574 575 amdgpu_ucode_release(&psp->sos_fw); 576 amdgpu_ucode_release(&psp->asd_fw); 577 amdgpu_ucode_release(&psp->ta_fw); 578 amdgpu_ucode_release(&psp->cap_fw); 579 amdgpu_ucode_release(&psp->toc_fw); 580 581 kfree(psp->cmd); 582 psp->cmd = NULL; 583 584 psp_free_shared_bufs(psp); 585 586 if (psp->km_ring.ring_mem) 587 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 588 &psp->km_ring.ring_mem_mc_addr, 589 (void **)&psp->km_ring.ring_mem); 590 591 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 592 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 593 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 594 &psp->fence_buf_mc_addr, &psp->fence_buf); 595 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 596 (void **)&psp->cmd_buf_mem); 597 598 return 0; 599 } 600 601 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 602 uint32_t mask, uint32_t flags) 603 { 604 bool check_changed = flags & PSP_WAITREG_CHANGED; 605 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 606 uint32_t val; 607 int i; 608 struct amdgpu_device *adev = psp->adev; 609 610 if (psp->adev->no_hw_access) 611 return 0; 612 613 for (i = 0; i < adev->usec_timeout; i++) { 614 val = RREG32(reg_index); 615 if (check_changed) { 616 if (val != reg_val) 617 return 0; 618 } else { 619 if ((val & mask) == reg_val) 620 return 0; 621 } 622 udelay(1); 623 } 624 625 if (verbose) 626 dev_err(adev->dev, 627 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 628 reg_index, mask, val, reg_val); 629 630 return -ETIME; 631 } 632 633 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 634 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 635 { 636 uint32_t val; 637 int i; 638 struct amdgpu_device *adev = psp->adev; 639 640 if (psp->adev->no_hw_access) 641 return 0; 642 643 for (i = 0; i < msec_timeout; i++) { 644 val = RREG32(reg_index); 645 if ((val & mask) == reg_val) 646 return 0; 647 msleep(1); 648 } 649 650 return -ETIME; 651 } 652 653 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 654 { 655 switch (cmd_id) { 656 case GFX_CMD_ID_LOAD_TA: 657 return "LOAD_TA"; 658 case GFX_CMD_ID_UNLOAD_TA: 659 return "UNLOAD_TA"; 660 case GFX_CMD_ID_INVOKE_CMD: 661 return "INVOKE_CMD"; 662 case GFX_CMD_ID_LOAD_ASD: 663 return "LOAD_ASD"; 664 case GFX_CMD_ID_SETUP_TMR: 665 return "SETUP_TMR"; 666 case GFX_CMD_ID_LOAD_IP_FW: 667 return "LOAD_IP_FW"; 668 case GFX_CMD_ID_DESTROY_TMR: 669 return "DESTROY_TMR"; 670 case GFX_CMD_ID_SAVE_RESTORE: 671 return "SAVE_RESTORE_IP_FW"; 672 case GFX_CMD_ID_SETUP_VMR: 673 return "SETUP_VMR"; 674 case GFX_CMD_ID_DESTROY_VMR: 675 return "DESTROY_VMR"; 676 case GFX_CMD_ID_PROG_REG: 677 return "PROG_REG"; 678 case GFX_CMD_ID_GET_FW_ATTESTATION: 679 return "GET_FW_ATTESTATION"; 680 case GFX_CMD_ID_LOAD_TOC: 681 return "ID_LOAD_TOC"; 682 case GFX_CMD_ID_AUTOLOAD_RLC: 683 return "AUTOLOAD_RLC"; 684 case GFX_CMD_ID_BOOT_CFG: 685 return "BOOT_CFG"; 686 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 687 return "CONFIG_SQ_PERFMON"; 688 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 689 return "FB_FW_RESERV_ADDR"; 690 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 691 return "FB_FW_RESERV_EXT_ADDR"; 692 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 693 return "SPATIAL_PARTITION"; 694 case GFX_CMD_ID_FB_NPS_MODE: 695 return "NPS_MODE_CHANGE"; 696 case GFX_CMD_ID_PERF_HW: 697 return "PERF MONITORING HW"; 698 default: 699 return "UNKNOWN CMD"; 700 } 701 } 702 703 static bool psp_err_warn(struct psp_context *psp) 704 { 705 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 706 707 /* This response indicates reg list is already loaded */ 708 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 709 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 710 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 711 cmd->resp.status == TEE_ERROR_CANCEL) 712 return false; 713 714 return true; 715 } 716 717 static int 718 psp_cmd_submit_buf(struct psp_context *psp, 719 struct amdgpu_firmware_info *ucode, 720 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 721 { 722 int ret; 723 int index; 724 int timeout = psp->adev->psp_timeout; 725 bool ras_intr = false; 726 bool skip_unsupport = false; 727 728 if (psp->adev->no_hw_access) 729 return 0; 730 731 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 732 733 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 734 735 index = atomic_inc_return(&psp->fence_value); 736 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 737 if (ret) { 738 atomic_dec(&psp->fence_value); 739 goto exit; 740 } 741 742 amdgpu_device_invalidate_hdp(psp->adev, NULL); 743 while (*((unsigned int *)psp->fence_buf) != index) { 744 if (--timeout == 0) 745 break; 746 /* 747 * Shouldn't wait for timeout when err_event_athub occurs, 748 * because gpu reset thread triggered and lock resource should 749 * be released for psp resume sequence. 750 */ 751 ras_intr = amdgpu_ras_intr_triggered(); 752 if (ras_intr) 753 break; 754 usleep_range(60, 100); 755 amdgpu_device_invalidate_hdp(psp->adev, NULL); 756 } 757 758 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 759 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 760 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 761 762 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 763 764 /* In some cases, psp response status is not 0 even there is no 765 * problem while the command is submitted. Some version of PSP FW 766 * doesn't write 0 to that field. 767 * So here we would like to only print a warning instead of an error 768 * during psp initialization to avoid breaking hw_init and it doesn't 769 * return -EINVAL. 770 */ 771 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 772 if (ucode) 773 dev_warn(psp->adev->dev, 774 "failed to load ucode %s(0x%X) ", 775 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 776 if (psp_err_warn(psp)) 777 dev_warn( 778 psp->adev->dev, 779 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 780 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 781 psp->cmd_buf_mem->cmd_id, 782 psp->cmd_buf_mem->resp.status); 783 /* If any firmware (including CAP) load fails under SRIOV, it should 784 * return failure to stop the VF from initializing. 785 * Also return failure in case of timeout 786 */ 787 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 788 ret = -EINVAL; 789 goto exit; 790 } 791 } 792 793 if (ucode) { 794 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 795 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 796 } 797 798 exit: 799 return ret; 800 } 801 802 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 803 { 804 struct psp_gfx_cmd_resp *cmd = psp->cmd; 805 806 mutex_lock(&psp->mutex); 807 808 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 809 810 return cmd; 811 } 812 813 static void release_psp_cmd_buf(struct psp_context *psp) 814 { 815 mutex_unlock(&psp->mutex); 816 } 817 818 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 819 struct psp_gfx_cmd_resp *cmd, 820 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 821 { 822 struct amdgpu_device *adev = psp->adev; 823 uint32_t size = 0; 824 uint64_t tmr_pa = 0; 825 826 if (tmr_bo) { 827 size = amdgpu_bo_size(tmr_bo); 828 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 829 } 830 831 if (amdgpu_sriov_vf(psp->adev)) 832 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 833 else 834 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 835 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 836 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 837 cmd->cmd.cmd_setup_tmr.buf_size = size; 838 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 839 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 840 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 841 } 842 843 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 844 uint64_t pri_buf_mc, uint32_t size) 845 { 846 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 847 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 848 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 849 cmd->cmd.cmd_load_toc.toc_size = size; 850 } 851 852 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 853 static int psp_load_toc(struct psp_context *psp, 854 uint32_t *tmr_size) 855 { 856 int ret; 857 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 858 859 /* Copy toc to psp firmware private buffer */ 860 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 861 if (ret) { 862 release_psp_cmd_buf(psp); 863 return ret; 864 } 865 866 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 867 868 ret = psp_cmd_submit_buf(psp, NULL, cmd, 869 psp->fence_buf_mc_addr); 870 if (!ret) 871 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 872 873 release_psp_cmd_buf(psp); 874 875 return ret; 876 } 877 878 /* Set up Trusted Memory Region */ 879 static int psp_tmr_init(struct psp_context *psp) 880 { 881 int ret = 0; 882 int tmr_size; 883 void *tmr_buf; 884 void **pptr; 885 886 /* 887 * According to HW engineer, they prefer the TMR address be "naturally 888 * aligned" , e.g. the start address be an integer divide of TMR size. 889 * 890 * Note: this memory need be reserved till the driver 891 * uninitializes. 892 */ 893 tmr_size = PSP_TMR_SIZE(psp->adev); 894 895 /* For ASICs support RLC autoload, psp will parse the toc 896 * and calculate the total size of TMR needed 897 */ 898 if (!amdgpu_sriov_vf(psp->adev) && 899 psp->toc.start_addr && 900 psp->toc.size_bytes && 901 psp->fw_pri_buf) { 902 ret = psp_load_toc(psp, &tmr_size); 903 if (ret) { 904 dev_err(psp->adev->dev, "Failed to load toc\n"); 905 return ret; 906 } 907 } 908 909 if (!psp->tmr_bo && !psp->boot_time_tmr) { 910 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 911 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 912 PSP_TMR_ALIGNMENT, 913 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 914 &psp->tmr_bo, &psp->tmr_mc_addr, 915 pptr); 916 } 917 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 918 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 919 920 return ret; 921 } 922 923 static bool psp_skip_tmr(struct psp_context *psp) 924 { 925 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 926 927 if (amdgpu_sriov_vf(psp->adev)) 928 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 929 else 930 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 931 } 932 933 static int psp_tmr_load(struct psp_context *psp) 934 { 935 int ret; 936 struct psp_gfx_cmd_resp *cmd; 937 938 if (psp_skip_tmr(psp)) 939 return 0; 940 941 cmd = acquire_psp_cmd_buf(psp); 942 943 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 944 if (psp->tmr_bo) 945 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 946 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 947 948 ret = psp_cmd_submit_buf(psp, NULL, cmd, 949 psp->fence_buf_mc_addr); 950 951 release_psp_cmd_buf(psp); 952 953 return ret; 954 } 955 956 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 957 struct psp_gfx_cmd_resp *cmd) 958 { 959 if (amdgpu_sriov_vf(psp->adev)) 960 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 961 else 962 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 963 } 964 965 static int psp_tmr_unload(struct psp_context *psp) 966 { 967 int ret; 968 struct psp_gfx_cmd_resp *cmd; 969 970 if (psp_skip_tmr(psp)) 971 return 0; 972 973 cmd = acquire_psp_cmd_buf(psp); 974 975 psp_prep_tmr_unload_cmd_buf(psp, cmd); 976 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 977 978 ret = psp_cmd_submit_buf(psp, NULL, cmd, 979 psp->fence_buf_mc_addr); 980 981 release_psp_cmd_buf(psp); 982 983 return ret; 984 } 985 986 static int psp_tmr_terminate(struct psp_context *psp) 987 { 988 return psp_tmr_unload(psp); 989 } 990 991 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 992 uint64_t *output_ptr) 993 { 994 int ret; 995 struct psp_gfx_cmd_resp *cmd; 996 997 if (!output_ptr) 998 return -EINVAL; 999 1000 if (amdgpu_sriov_vf(psp->adev)) 1001 return 0; 1002 1003 cmd = acquire_psp_cmd_buf(psp); 1004 1005 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1006 1007 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1008 psp->fence_buf_mc_addr); 1009 1010 if (!ret) { 1011 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1012 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1013 } 1014 1015 release_psp_cmd_buf(psp); 1016 1017 return ret; 1018 } 1019 1020 static int psp_get_fw_reservation_info(struct psp_context *psp, 1021 uint32_t cmd_id, 1022 uint64_t *addr, 1023 uint32_t *size) 1024 { 1025 int ret; 1026 uint32_t status; 1027 struct psp_gfx_cmd_resp *cmd; 1028 1029 cmd = acquire_psp_cmd_buf(psp); 1030 1031 cmd->cmd_id = cmd_id; 1032 1033 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1034 psp->fence_buf_mc_addr); 1035 if (ret) { 1036 release_psp_cmd_buf(psp); 1037 return ret; 1038 } 1039 1040 status = cmd->resp.status; 1041 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1042 release_psp_cmd_buf(psp); 1043 *addr = 0; 1044 *size = 0; 1045 return 0; 1046 } 1047 1048 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1049 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1050 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1051 1052 release_psp_cmd_buf(psp); 1053 1054 return 0; 1055 } 1056 1057 int psp_update_fw_reservation(struct psp_context *psp) 1058 { 1059 int ret; 1060 uint64_t reserv_addr, reserv_addr_ext; 1061 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1062 struct amdgpu_device *adev = psp->adev; 1063 1064 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1065 1066 if (amdgpu_sriov_vf(psp->adev)) 1067 return 0; 1068 1069 switch (mp0_ip_ver) { 1070 case IP_VERSION(14, 0, 2): 1071 if (adev->psp.sos.fw_version < 0x3b0e0d) 1072 return 0; 1073 break; 1074 1075 case IP_VERSION(14, 0, 3): 1076 if (adev->psp.sos.fw_version < 0x3a0e14) 1077 return 0; 1078 break; 1079 1080 default: 1081 return 0; 1082 } 1083 1084 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1085 if (ret) 1086 return ret; 1087 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1088 if (ret) 1089 return ret; 1090 1091 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1092 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1093 return 0; 1094 } 1095 1096 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1097 1098 reserv_size = roundup(reserv_size, SZ_1M); 1099 1100 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1101 reserv_addr, reserv_size, false); 1102 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1103 if (ret) { 1104 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1105 return ret; 1106 } 1107 1108 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1109 1110 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1111 reserv_addr_ext, reserv_size_ext, false); 1112 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1113 if (ret) { 1114 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1115 return ret; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1122 { 1123 struct psp_context *psp = &adev->psp; 1124 struct psp_gfx_cmd_resp *cmd; 1125 int ret; 1126 1127 if (amdgpu_sriov_vf(adev)) 1128 return 0; 1129 1130 cmd = acquire_psp_cmd_buf(psp); 1131 1132 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1133 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1134 1135 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1136 if (!ret) { 1137 *boot_cfg = 1138 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1139 } 1140 1141 release_psp_cmd_buf(psp); 1142 1143 return ret; 1144 } 1145 1146 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1147 { 1148 int ret; 1149 struct psp_context *psp = &adev->psp; 1150 struct psp_gfx_cmd_resp *cmd; 1151 1152 if (amdgpu_sriov_vf(adev)) 1153 return 0; 1154 1155 cmd = acquire_psp_cmd_buf(psp); 1156 1157 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1158 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1159 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1160 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1161 1162 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1163 1164 release_psp_cmd_buf(psp); 1165 1166 return ret; 1167 } 1168 1169 static int psp_rl_load(struct amdgpu_device *adev) 1170 { 1171 int ret; 1172 struct psp_context *psp = &adev->psp; 1173 struct psp_gfx_cmd_resp *cmd; 1174 1175 if (!is_psp_fw_valid(psp->rl)) 1176 return 0; 1177 1178 cmd = acquire_psp_cmd_buf(psp); 1179 1180 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1181 if (ret) { 1182 release_psp_cmd_buf(psp); 1183 return ret; 1184 } 1185 1186 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1187 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1188 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1189 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1190 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1191 1192 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1193 1194 release_psp_cmd_buf(psp); 1195 1196 return ret; 1197 } 1198 1199 int psp_memory_partition(struct psp_context *psp, int mode) 1200 { 1201 struct psp_gfx_cmd_resp *cmd; 1202 int ret; 1203 1204 if (amdgpu_sriov_vf(psp->adev)) 1205 return 0; 1206 1207 cmd = acquire_psp_cmd_buf(psp); 1208 1209 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1210 cmd->cmd.cmd_memory_part.mode = mode; 1211 1212 dev_info(psp->adev->dev, 1213 "Requesting %d memory partition change through PSP", mode); 1214 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1215 if (ret) 1216 dev_err(psp->adev->dev, 1217 "PSP request failed to change to NPS%d mode\n", mode); 1218 1219 release_psp_cmd_buf(psp); 1220 1221 return ret; 1222 } 1223 1224 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1225 uint32_t *ptl_fmt) 1226 { 1227 struct amdgpu_device *adev = psp->adev; 1228 1229 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1230 return -EINVAL; 1231 1232 switch (fmt) { 1233 case AMDGPU_PTL_FMT_I8: 1234 *ptl_fmt = GFX_FTYPE_I8; 1235 break; 1236 case AMDGPU_PTL_FMT_F16: 1237 *ptl_fmt = GFX_FTYPE_F16; 1238 break; 1239 case AMDGPU_PTL_FMT_BF16: 1240 *ptl_fmt = GFX_FTYPE_BF16; 1241 break; 1242 case AMDGPU_PTL_FMT_F32: 1243 *ptl_fmt = GFX_FTYPE_F32; 1244 break; 1245 case AMDGPU_PTL_FMT_F64: 1246 *ptl_fmt = GFX_FTYPE_F64; 1247 break; 1248 case AMDGPU_PTL_FMT_F8: 1249 *ptl_fmt = GFX_FTYPE_F8; 1250 break; 1251 case AMDGPU_PTL_FMT_VECTOR: 1252 *ptl_fmt = GFX_FTYPE_VECTOR; 1253 break; 1254 default: 1255 return -EINVAL; 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1262 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1263 { 1264 struct psp_gfx_cmd_resp *cmd; 1265 struct amdgpu_ptl *ptl = &psp->ptl; 1266 int ret; 1267 1268 cmd = acquire_psp_cmd_buf(psp); 1269 1270 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1271 cmd->cmd.cmd_req_perf_hw.req = req_code; 1272 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1273 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1274 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1275 1276 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1277 if (ret) 1278 goto out; 1279 1280 /* 1281 * Check response status explicitly to avoid 1282 * updating cached PTL state with invalid data. 1283 */ 1284 if (cmd->resp.status) { 1285 dev_err(psp->adev->dev, 1286 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1287 req_code, cmd->resp.status, 1288 cmd->resp.uresp.perf_hw_info.resp); 1289 ret = -EIO; 1290 goto out; 1291 } 1292 1293 /* Parse response */ 1294 switch (req_code) { 1295 case PSP_PTL_PERF_MON_QUERY: 1296 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1297 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1298 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1299 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1300 *ptl_state, *fmt1, *fmt2); 1301 break; 1302 case PSP_PTL_PERF_MON_SET: 1303 /* Update cached state only on success */ 1304 ptl->enabled = *ptl_state; 1305 ptl->fmt1 = *fmt1; 1306 ptl->fmt2 = *fmt2; 1307 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1308 *ptl_state, *fmt1, *fmt2); 1309 break; 1310 } 1311 1312 out: 1313 release_psp_cmd_buf(psp); 1314 return ret; 1315 } 1316 1317 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1318 uint32_t *ptl_state, 1319 enum amdgpu_ptl_fmt *fmt1, 1320 enum amdgpu_ptl_fmt *fmt2) 1321 { 1322 uint32_t ptl_fmt1, ptl_fmt2; 1323 struct psp_context *psp; 1324 struct amdgpu_ptl *ptl; 1325 int ret; 1326 1327 if (!adev || !ptl_state || !fmt1 || !fmt2) 1328 return -EINVAL; 1329 1330 if (amdgpu_sriov_vf(adev)) 1331 return 0; 1332 1333 psp = &adev->psp; 1334 ptl = &psp->ptl; 1335 1336 if (ptl->permanently_disabled && *ptl_state == 1) 1337 return 0; 1338 1339 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1340 psp->sos.fw_version < 0x0036081a) 1341 return -EOPNOTSUPP; 1342 1343 /* Verify formats */ 1344 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1345 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1346 return -EINVAL; 1347 1348 /* 1349 * Add check to skip if state and formats are identical to current ones 1350 */ 1351 if (req_code == PSP_PTL_PERF_MON_SET && 1352 ptl->enabled == *ptl_state && 1353 ptl->fmt1 == ptl_fmt1 && 1354 ptl->fmt2 == ptl_fmt2) 1355 return 0; 1356 1357 /* If enabling PTL, check disable bitmap */ 1358 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1359 if (!bitmap_empty(ptl->disable_bitmap, 1360 AMDGPU_PTL_DISABLE_MAX)) { 1361 dev_dbg(adev->dev, 1362 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1363 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1364 ptl->disable_bitmap), 1365 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1366 ptl->disable_bitmap), 1367 atomic_read(&ptl->disable_ref)); 1368 return 0; 1369 } 1370 } 1371 1372 if (req_code == PSP_PTL_PERF_MON_SET) { 1373 amdgpu_amdkfd_stop_sched_all(adev); 1374 /* Wait for GFX engine idle before PTL state transition */ 1375 ret = amdgpu_device_ip_wait_for_idle(adev, 1376 AMD_IP_BLOCK_TYPE_GFX); 1377 if (ret) { 1378 amdgpu_amdkfd_start_sched_all(adev); 1379 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1380 return ret; 1381 } 1382 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1383 amdgpu_amdkfd_start_sched_all(adev); 1384 } else { 1385 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1386 } 1387 1388 return ret; 1389 } 1390 1391 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1392 { 1393 int i; 1394 1395 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1396 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1397 return (enum amdgpu_ptl_fmt)i; 1398 } 1399 1400 return AMDGPU_PTL_FMT_INVALID; 1401 } 1402 1403 static ssize_t ptl_supported_formats_show(struct device *dev, 1404 struct device_attribute *attr, char *buf) 1405 { 1406 ssize_t len = 0; 1407 1408 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1409 const char *fmt = amdgpu_ptl_fmt_str[i]; 1410 1411 len += sysfs_emit_at(buf, len, "%s%s", 1412 fmt ? fmt : "UNKNOWN", 1413 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1414 } 1415 1416 return len; 1417 } 1418 1419 static ssize_t ptl_enable_store(struct device *dev, 1420 struct device_attribute *attr, 1421 const char *buf, size_t count) 1422 { 1423 struct drm_device *ddev = dev_get_drvdata(dev); 1424 struct amdgpu_device *adev = drm_to_adev(ddev); 1425 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1426 uint32_t ptl_state, fmt1, fmt2; 1427 int ret; 1428 bool enable; 1429 bool bit_changed = false; 1430 1431 mutex_lock(&ptl->mutex); 1432 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1433 enable = true; 1434 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1435 enable = false; 1436 } else { 1437 mutex_unlock(&ptl->mutex); 1438 return -EINVAL; 1439 } 1440 1441 /* Block enable when permanently disabled */ 1442 if (ptl->permanently_disabled) { 1443 mutex_unlock(&ptl->mutex); 1444 return -EPERM; 1445 } 1446 1447 fmt1 = ptl->fmt1; 1448 fmt2 = ptl->fmt2; 1449 ptl_state = enable ? 1 : 0; 1450 1451 if (enable) 1452 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1453 ptl->disable_bitmap); 1454 1455 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1456 if (ret) { 1457 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1458 if (enable && bit_changed) 1459 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1460 mutex_unlock(&ptl->mutex); 1461 return ret; 1462 } 1463 1464 if (!enable) 1465 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1466 1467 mutex_unlock(&ptl->mutex); 1468 1469 return count; 1470 } 1471 1472 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1473 { 1474 struct drm_device *ddev = dev_get_drvdata(dev); 1475 struct amdgpu_device *adev = drm_to_adev(ddev); 1476 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1477 1478 if (ptl->permanently_disabled) 1479 return sysfs_emit(buf, "permanently disabled\n"); 1480 1481 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1482 } 1483 1484 static ssize_t ptl_format_store(struct device *dev, 1485 struct device_attribute *attr, 1486 const char *buf, size_t count) 1487 { 1488 struct drm_device *ddev = dev_get_drvdata(dev); 1489 struct amdgpu_device *adev = drm_to_adev(ddev); 1490 char fmt1_str[8], fmt2_str[8]; 1491 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1492 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1493 uint32_t ptl_state, fmt1, fmt2; 1494 int ret; 1495 1496 /* Only allow format update when PTL is enabled */ 1497 if (!ptl->enabled) 1498 return -EPERM; 1499 1500 mutex_lock(&ptl->mutex); 1501 /* Parse input, expecting "FMT1,FMT2" */ 1502 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1503 mutex_unlock(&ptl->mutex); 1504 return -EINVAL; 1505 } 1506 1507 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1508 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1509 1510 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1511 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1512 fmt1_enum == fmt2_enum) { 1513 mutex_unlock(&ptl->mutex); 1514 return -EINVAL; 1515 } 1516 1517 ptl_state = ptl->enabled; 1518 fmt1 = fmt1_enum; 1519 fmt2 = fmt2_enum; 1520 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1521 if (ret) { 1522 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1523 mutex_unlock(&ptl->mutex); 1524 return ret; 1525 } 1526 mutex_unlock(&ptl->mutex); 1527 1528 return count; 1529 } 1530 1531 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1532 { 1533 struct drm_device *ddev = dev_get_drvdata(dev); 1534 struct amdgpu_device *adev = drm_to_adev(ddev); 1535 struct psp_context *psp = &adev->psp; 1536 1537 return sysfs_emit(buf, "%s,%s\n", 1538 amdgpu_ptl_fmt_str[psp->ptl.fmt1], 1539 amdgpu_ptl_fmt_str[psp->ptl.fmt2]); 1540 } 1541 1542 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1543 { 1544 struct device *dev = kobj_to_dev(kobj); 1545 struct drm_device *ddev = dev_get_drvdata(dev); 1546 struct amdgpu_device *adev = drm_to_adev(ddev); 1547 1548 /* Only show PTL sysfs files if PTL hardware is supported */ 1549 if (!adev->psp.ptl.hw_supported) 1550 return 0; 1551 1552 return attr->mode; 1553 } 1554 1555 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1556 { 1557 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1558 int ret; 1559 1560 if (!ptl->hw_supported) 1561 return 0; 1562 1563 if (ptl->ptl_sysfs_created) 1564 return 0; 1565 1566 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1567 if (!ret) 1568 ptl->ptl_sysfs_created = true; 1569 1570 return ret; 1571 } 1572 1573 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1574 { 1575 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1576 1577 if (!ptl->hw_supported) 1578 return; 1579 1580 if (!ptl->ptl_sysfs_created) 1581 return; 1582 1583 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1584 ptl->ptl_sysfs_created = false; 1585 } 1586 1587 int psp_spatial_partition(struct psp_context *psp, int mode) 1588 { 1589 struct psp_gfx_cmd_resp *cmd; 1590 int ret; 1591 1592 if (amdgpu_sriov_vf(psp->adev)) 1593 return 0; 1594 1595 cmd = acquire_psp_cmd_buf(psp); 1596 1597 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1598 cmd->cmd.cmd_spatial_part.mode = mode; 1599 1600 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1601 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1602 1603 release_psp_cmd_buf(psp); 1604 1605 return ret; 1606 } 1607 1608 static int psp_asd_initialize(struct psp_context *psp) 1609 { 1610 int ret; 1611 1612 /* If PSP version doesn't match ASD version, asd loading will be failed. 1613 * add workaround to bypass it for sriov now. 1614 * TODO: add version check to make it common 1615 */ 1616 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1617 return 0; 1618 1619 /* bypass asd if display hardware is not available */ 1620 if (!amdgpu_device_has_display_hardware(psp->adev) && 1621 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1622 return 0; 1623 1624 psp->asd_context.mem_context.shared_mc_addr = 0; 1625 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1626 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1627 1628 ret = psp_ta_load(psp, &psp->asd_context); 1629 if (!ret) 1630 psp->asd_context.initialized = true; 1631 1632 return ret; 1633 } 1634 1635 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1636 uint32_t session_id) 1637 { 1638 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1639 cmd->cmd.cmd_unload_ta.session_id = session_id; 1640 } 1641 1642 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1643 { 1644 int ret; 1645 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1646 1647 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1648 1649 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1650 1651 context->resp_status = cmd->resp.status; 1652 1653 release_psp_cmd_buf(psp); 1654 1655 return ret; 1656 } 1657 1658 static int psp_asd_terminate(struct psp_context *psp) 1659 { 1660 int ret; 1661 1662 if (amdgpu_sriov_vf(psp->adev)) 1663 return 0; 1664 1665 if (!psp->asd_context.initialized) 1666 return 0; 1667 1668 ret = psp_ta_unload(psp, &psp->asd_context); 1669 if (!ret) 1670 psp->asd_context.initialized = false; 1671 1672 return ret; 1673 } 1674 1675 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1676 uint32_t id, uint32_t value) 1677 { 1678 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1679 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1680 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1681 } 1682 1683 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1684 uint32_t value) 1685 { 1686 struct psp_gfx_cmd_resp *cmd; 1687 int ret = 0; 1688 1689 if (reg >= PSP_REG_LAST) 1690 return -EINVAL; 1691 1692 cmd = acquire_psp_cmd_buf(psp); 1693 1694 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1695 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1696 if (ret) 1697 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1698 1699 release_psp_cmd_buf(psp); 1700 1701 return ret; 1702 } 1703 1704 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1705 uint64_t ta_bin_mc, 1706 struct ta_context *context) 1707 { 1708 cmd->cmd_id = context->ta_load_type; 1709 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1710 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1711 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1712 1713 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1714 lower_32_bits(context->mem_context.shared_mc_addr); 1715 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1716 upper_32_bits(context->mem_context.shared_mc_addr); 1717 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1718 } 1719 1720 int psp_ta_init_shared_buf(struct psp_context *psp, 1721 struct ta_mem_context *mem_ctx) 1722 { 1723 /* 1724 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1725 * physical) for ta to host memory 1726 */ 1727 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1728 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1729 AMDGPU_GEM_DOMAIN_GTT, 1730 &mem_ctx->shared_bo, 1731 &mem_ctx->shared_mc_addr, 1732 &mem_ctx->shared_buf); 1733 } 1734 1735 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1736 uint32_t ta_cmd_id, 1737 uint32_t session_id) 1738 { 1739 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1740 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1741 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1742 } 1743 1744 int psp_ta_invoke(struct psp_context *psp, 1745 uint32_t ta_cmd_id, 1746 struct ta_context *context) 1747 { 1748 int ret; 1749 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1750 1751 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1752 1753 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1754 psp->fence_buf_mc_addr); 1755 1756 context->resp_status = cmd->resp.status; 1757 1758 release_psp_cmd_buf(psp); 1759 1760 return ret; 1761 } 1762 1763 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1764 { 1765 int ret; 1766 struct psp_gfx_cmd_resp *cmd; 1767 1768 cmd = acquire_psp_cmd_buf(psp); 1769 1770 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 1771 context->bin_desc.size_bytes); 1772 if (ret) { 1773 release_psp_cmd_buf(psp); 1774 return ret; 1775 } 1776 1777 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1778 context->mem_context.shared_bo) 1779 context->mem_context.shared_mc_addr = 1780 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1781 1782 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1783 1784 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1785 psp->fence_buf_mc_addr); 1786 1787 context->resp_status = cmd->resp.status; 1788 1789 if (!ret) 1790 context->session_id = cmd->resp.session_id; 1791 1792 release_psp_cmd_buf(psp); 1793 1794 return ret; 1795 } 1796 1797 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1798 { 1799 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1800 } 1801 1802 int psp_xgmi_terminate(struct psp_context *psp) 1803 { 1804 int ret; 1805 struct amdgpu_device *adev = psp->adev; 1806 1807 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1808 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1809 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1810 adev->gmc.xgmi.connected_to_cpu)) 1811 return 0; 1812 1813 if (!psp->xgmi_context.context.initialized) 1814 return 0; 1815 1816 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1817 1818 psp->xgmi_context.context.initialized = false; 1819 1820 return ret; 1821 } 1822 1823 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1824 { 1825 struct ta_xgmi_shared_memory *xgmi_cmd; 1826 int ret; 1827 1828 if (!psp->ta_fw || 1829 !psp->xgmi_context.context.bin_desc.size_bytes || 1830 !psp->xgmi_context.context.bin_desc.start_addr) 1831 return -ENOENT; 1832 1833 if (!load_ta) 1834 goto invoke; 1835 1836 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1837 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1838 1839 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1840 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1841 if (ret) 1842 return ret; 1843 } 1844 1845 /* Load XGMI TA */ 1846 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1847 if (!ret) 1848 psp->xgmi_context.context.initialized = true; 1849 else 1850 return ret; 1851 1852 invoke: 1853 /* Initialize XGMI session */ 1854 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1855 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1856 xgmi_cmd->flag_extend_link_record = set_extended_data; 1857 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1858 1859 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1860 /* note down the capbility flag for XGMI TA */ 1861 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1862 1863 return ret; 1864 } 1865 1866 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1867 { 1868 struct ta_xgmi_shared_memory *xgmi_cmd; 1869 int ret; 1870 1871 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1872 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1873 1874 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1875 1876 /* Invoke xgmi ta to get hive id */ 1877 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1878 if (ret) 1879 return ret; 1880 1881 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1882 1883 return 0; 1884 } 1885 1886 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1887 { 1888 struct ta_xgmi_shared_memory *xgmi_cmd; 1889 int ret; 1890 1891 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1892 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1893 1894 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1895 1896 /* Invoke xgmi ta to get the node id */ 1897 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1898 if (ret) 1899 return ret; 1900 1901 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1902 1903 return 0; 1904 } 1905 1906 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1907 { 1908 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1909 IP_VERSION(13, 0, 2) && 1910 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1911 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1912 IP_VERSION(13, 0, 6); 1913 } 1914 1915 /* 1916 * Chips that support extended topology information require the driver to 1917 * reflect topology information in the opposite direction. This is 1918 * because the TA has already exceeded its link record limit and if the 1919 * TA holds bi-directional information, the driver would have to do 1920 * multiple fetches instead of just two. 1921 */ 1922 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1923 struct psp_xgmi_node_info node_info) 1924 { 1925 struct amdgpu_device *mirror_adev; 1926 struct amdgpu_hive_info *hive; 1927 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1928 uint64_t dst_node_id = node_info.node_id; 1929 uint8_t dst_num_hops = node_info.num_hops; 1930 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1931 uint8_t dst_num_links = node_info.num_links; 1932 1933 hive = amdgpu_get_xgmi_hive(psp->adev); 1934 if (WARN_ON(!hive)) 1935 return; 1936 1937 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1938 struct psp_xgmi_topology_info *mirror_top_info; 1939 int j; 1940 1941 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1942 continue; 1943 1944 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1945 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1946 if (mirror_top_info->nodes[j].node_id != src_node_id) 1947 continue; 1948 1949 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1950 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1951 /* prevent 0 num_links value re-reflection since reflection 1952 * criteria is based on num_hops (direct or indirect). 1953 */ 1954 if (dst_num_links) { 1955 mirror_top_info->nodes[j].num_links = dst_num_links; 1956 /* swap src and dst due to frame of reference */ 1957 for (int k = 0; k < dst_num_links; k++) { 1958 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1959 node_info.port_num[k].dst_xgmi_port_num; 1960 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1961 node_info.port_num[k].src_xgmi_port_num; 1962 } 1963 } 1964 1965 break; 1966 } 1967 1968 break; 1969 } 1970 1971 amdgpu_put_xgmi_hive(hive); 1972 } 1973 1974 int psp_xgmi_get_topology_info(struct psp_context *psp, 1975 int number_devices, 1976 struct psp_xgmi_topology_info *topology, 1977 bool get_extended_data) 1978 { 1979 struct ta_xgmi_shared_memory *xgmi_cmd; 1980 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1981 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1982 int i; 1983 int ret; 1984 1985 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1986 return -EINVAL; 1987 1988 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1989 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1990 xgmi_cmd->flag_extend_link_record = get_extended_data; 1991 1992 /* Fill in the shared memory with topology information as input */ 1993 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1994 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1995 topology_info_input->num_nodes = number_devices; 1996 1997 for (i = 0; i < topology_info_input->num_nodes; i++) { 1998 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1999 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2000 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2001 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2002 } 2003 2004 /* Invoke xgmi ta to get the topology information */ 2005 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2006 if (ret) 2007 return ret; 2008 2009 /* Read the output topology information from the shared memory */ 2010 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2011 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2012 for (i = 0; i < topology->num_nodes; i++) { 2013 /* extended data will either be 0 or equal to non-extended data */ 2014 if (topology_info_output->nodes[i].num_hops) 2015 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2016 2017 /* non-extended data gets everything here so no need to update */ 2018 if (!get_extended_data) { 2019 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2020 topology->nodes[i].is_sharing_enabled = 2021 topology_info_output->nodes[i].is_sharing_enabled; 2022 topology->nodes[i].sdma_engine = 2023 topology_info_output->nodes[i].sdma_engine; 2024 } 2025 2026 } 2027 2028 /* Invoke xgmi ta again to get the link information */ 2029 if (psp_xgmi_peer_link_info_supported(psp)) { 2030 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2031 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2032 bool requires_reflection = 2033 (psp->xgmi_context.supports_extended_data && 2034 get_extended_data) || 2035 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2036 IP_VERSION(13, 0, 6) || 2037 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2038 IP_VERSION(13, 0, 14) || 2039 amdgpu_sriov_vf(psp->adev); 2040 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || 2041 amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 2042 2043 /* popluate the shared output buffer rather than the cmd input buffer 2044 * with node_ids as the input for GET_PEER_LINKS command execution. 2045 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2046 * The same requirement for GET_EXTEND_PEER_LINKS command. 2047 */ 2048 if (ta_port_num_support) { 2049 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2050 2051 for (i = 0; i < topology->num_nodes; i++) 2052 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2053 2054 link_extend_info_output->num_nodes = topology->num_nodes; 2055 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2056 } else { 2057 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2058 2059 for (i = 0; i < topology->num_nodes; i++) 2060 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2061 2062 link_info_output->num_nodes = topology->num_nodes; 2063 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2064 } 2065 2066 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2067 if (ret) 2068 return ret; 2069 2070 for (i = 0; i < topology->num_nodes; i++) { 2071 uint8_t node_num_links = ta_port_num_support ? 2072 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2073 /* accumulate num_links on extended data */ 2074 if (get_extended_data) { 2075 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2076 } else { 2077 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2078 topology->nodes[i].num_links : node_num_links; 2079 } 2080 /* popluate the connected port num info if supported and available */ 2081 if (ta_port_num_support && topology->nodes[i].num_links) { 2082 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2083 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2084 } 2085 2086 /* reflect the topology information for bi-directionality */ 2087 if (requires_reflection && topology->nodes[i].num_hops) 2088 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2089 } 2090 } 2091 2092 return 0; 2093 } 2094 2095 int psp_xgmi_set_topology_info(struct psp_context *psp, 2096 int number_devices, 2097 struct psp_xgmi_topology_info *topology) 2098 { 2099 struct ta_xgmi_shared_memory *xgmi_cmd; 2100 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2101 int i; 2102 2103 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2104 return -EINVAL; 2105 2106 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2107 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2108 2109 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2110 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2111 topology_info_input->num_nodes = number_devices; 2112 2113 for (i = 0; i < topology_info_input->num_nodes; i++) { 2114 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2115 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2116 topology_info_input->nodes[i].is_sharing_enabled = 1; 2117 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2118 } 2119 2120 /* Invoke xgmi ta to set topology information */ 2121 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2122 } 2123 2124 // ras begin 2125 static void psp_ras_ta_check_status(struct psp_context *psp) 2126 { 2127 struct ta_ras_shared_memory *ras_cmd = 2128 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2129 2130 switch (ras_cmd->ras_status) { 2131 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2132 dev_warn(psp->adev->dev, 2133 "RAS WARNING: cmd failed due to unsupported ip\n"); 2134 break; 2135 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2136 dev_warn(psp->adev->dev, 2137 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2138 break; 2139 case TA_RAS_STATUS__SUCCESS: 2140 break; 2141 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2142 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2143 dev_warn(psp->adev->dev, 2144 "RAS WARNING: Inject error to critical region is not allowed\n"); 2145 break; 2146 default: 2147 dev_warn(psp->adev->dev, 2148 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2149 break; 2150 } 2151 } 2152 2153 static int psp_ras_send_cmd(struct psp_context *psp, 2154 enum ras_command cmd_id, void *in, void *out) 2155 { 2156 struct ta_ras_shared_memory *ras_cmd; 2157 uint32_t cmd = cmd_id; 2158 int ret = 0; 2159 2160 if (!in) 2161 return -EINVAL; 2162 2163 mutex_lock(&psp->ras_context.mutex); 2164 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2165 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2166 2167 switch (cmd) { 2168 case TA_RAS_COMMAND__ENABLE_FEATURES: 2169 case TA_RAS_COMMAND__DISABLE_FEATURES: 2170 memcpy(&ras_cmd->ras_in_message, 2171 in, sizeof(ras_cmd->ras_in_message)); 2172 break; 2173 case TA_RAS_COMMAND__TRIGGER_ERROR: 2174 memcpy(&ras_cmd->ras_in_message.trigger_error, 2175 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2176 break; 2177 case TA_RAS_COMMAND__QUERY_ADDRESS: 2178 memcpy(&ras_cmd->ras_in_message.address, 2179 in, sizeof(ras_cmd->ras_in_message.address)); 2180 break; 2181 default: 2182 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2183 ret = -EINVAL; 2184 goto err_out; 2185 } 2186 2187 ras_cmd->cmd_id = cmd; 2188 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2189 2190 switch (cmd) { 2191 case TA_RAS_COMMAND__TRIGGER_ERROR: 2192 if (!ret && out) 2193 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2194 break; 2195 case TA_RAS_COMMAND__QUERY_ADDRESS: 2196 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2197 ret = -EINVAL; 2198 else if (out) 2199 memcpy(out, 2200 &ras_cmd->ras_out_message.address, 2201 sizeof(ras_cmd->ras_out_message.address)); 2202 break; 2203 default: 2204 break; 2205 } 2206 2207 err_out: 2208 mutex_unlock(&psp->ras_context.mutex); 2209 2210 return ret; 2211 } 2212 2213 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2214 { 2215 struct ta_ras_shared_memory *ras_cmd; 2216 int ret; 2217 2218 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2219 2220 /* 2221 * TODO: bypass the loading in sriov for now 2222 */ 2223 if (amdgpu_sriov_vf(psp->adev)) 2224 return 0; 2225 2226 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2227 2228 if (amdgpu_ras_intr_triggered()) 2229 return ret; 2230 2231 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2232 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2233 return -EINVAL; 2234 } 2235 2236 if (!ret) { 2237 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2238 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2239 2240 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2241 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2242 dev_warn(psp->adev->dev, 2243 "RAS internal register access blocked\n"); 2244 2245 psp_ras_ta_check_status(psp); 2246 } 2247 2248 return ret; 2249 } 2250 2251 int psp_ras_enable_features(struct psp_context *psp, 2252 union ta_ras_cmd_input *info, bool enable) 2253 { 2254 enum ras_command cmd_id; 2255 int ret; 2256 2257 if (!psp->ras_context.context.initialized || !info) 2258 return -EINVAL; 2259 2260 cmd_id = enable ? 2261 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2262 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2263 if (ret) 2264 return -EINVAL; 2265 2266 return 0; 2267 } 2268 2269 int psp_ras_terminate(struct psp_context *psp) 2270 { 2271 int ret; 2272 2273 /* 2274 * TODO: bypass the terminate in sriov for now 2275 */ 2276 if (amdgpu_sriov_vf(psp->adev)) 2277 return 0; 2278 2279 if (!psp->ras_context.context.initialized) 2280 return 0; 2281 2282 ret = psp_ta_unload(psp, &psp->ras_context.context); 2283 2284 psp->ras_context.context.initialized = false; 2285 2286 mutex_destroy(&psp->ras_context.mutex); 2287 2288 return ret; 2289 } 2290 2291 int psp_ras_initialize(struct psp_context *psp) 2292 { 2293 int ret; 2294 uint32_t boot_cfg = 0xFF; 2295 struct amdgpu_device *adev = psp->adev; 2296 struct ta_ras_shared_memory *ras_cmd; 2297 2298 /* 2299 * TODO: bypass the initialize in sriov for now 2300 */ 2301 if (amdgpu_sriov_vf(adev)) 2302 return 0; 2303 2304 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2305 !adev->psp.ras_context.context.bin_desc.start_addr) { 2306 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2307 return 0; 2308 } 2309 2310 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2311 /* query GECC enablement status from boot config 2312 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2313 */ 2314 ret = psp_boot_config_get(adev, &boot_cfg); 2315 if (ret) 2316 dev_warn(adev->dev, "PSP get boot config failed\n"); 2317 2318 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2319 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2320 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2321 dev_warn(adev->dev, 2322 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2323 } else { 2324 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2325 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2326 if (boot_cfg == 1) { 2327 dev_info(adev->dev, "GECC is enabled\n"); 2328 } else { 2329 /* enable GECC in next boot cycle if it is disabled 2330 * in boot config, or force enable GECC if failed to 2331 * get boot configuration 2332 */ 2333 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2334 if (ret) 2335 dev_warn(adev->dev, "PSP set boot config failed\n"); 2336 else 2337 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2338 } 2339 } else { 2340 if (!boot_cfg) { 2341 if (!adev->ras_default_ecc_enabled && 2342 amdgpu_ras_enable != 1 && 2343 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2344 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2345 else 2346 dev_info(adev->dev, "GECC is disabled\n"); 2347 } else { 2348 /* disable GECC in next boot cycle if ras is 2349 * disabled by module parameter amdgpu_ras_enable 2350 * and/or amdgpu_ras_mask, or boot_config_get call 2351 * is failed 2352 */ 2353 ret = psp_boot_config_set(adev, 0); 2354 if (ret) 2355 dev_warn(adev->dev, "PSP set boot config failed\n"); 2356 else 2357 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2358 } 2359 } 2360 } 2361 } 2362 2363 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2364 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2365 2366 if (!psp->ras_context.context.mem_context.shared_buf) { 2367 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2368 if (ret) 2369 return ret; 2370 } 2371 2372 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2373 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2374 2375 if (amdgpu_ras_is_poison_mode_supported(adev)) 2376 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2377 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2378 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2379 ras_cmd->ras_in_message.init_flags.xcc_mask = 2380 adev->gfx.xcc_mask; 2381 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2382 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2383 ras_cmd->ras_in_message.init_flags.nps_mode = 2384 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2385 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2386 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2387 2388 ret = psp_ta_load(psp, &psp->ras_context.context); 2389 2390 if (!ret && !ras_cmd->ras_status) { 2391 psp->ras_context.context.initialized = true; 2392 mutex_init(&psp->ras_context.mutex); 2393 } else { 2394 if (ras_cmd->ras_status) 2395 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2396 2397 /* fail to load RAS TA */ 2398 psp->ras_context.context.initialized = false; 2399 } 2400 2401 return ret; 2402 } 2403 2404 int psp_ras_trigger_error(struct psp_context *psp, 2405 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2406 { 2407 struct amdgpu_device *adev = psp->adev; 2408 int ret; 2409 uint32_t dev_mask; 2410 uint32_t ras_status = 0; 2411 2412 if (!psp->ras_context.context.initialized || !info) 2413 return -EINVAL; 2414 2415 switch (info->block_id) { 2416 case TA_RAS_BLOCK__GFX: 2417 dev_mask = GET_MASK(GC, instance_mask); 2418 break; 2419 case TA_RAS_BLOCK__SDMA: 2420 dev_mask = GET_MASK(SDMA0, instance_mask); 2421 break; 2422 case TA_RAS_BLOCK__VCN: 2423 case TA_RAS_BLOCK__JPEG: 2424 dev_mask = GET_MASK(VCN, instance_mask); 2425 break; 2426 default: 2427 dev_mask = instance_mask; 2428 break; 2429 } 2430 2431 /* reuse sub_block_index for backward compatibility */ 2432 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2433 dev_mask &= AMDGPU_RAS_INST_MASK; 2434 info->sub_block_index |= dev_mask; 2435 2436 ret = psp_ras_send_cmd(psp, 2437 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2438 if (ret) 2439 return -EINVAL; 2440 2441 /* If err_event_athub occurs error inject was successful, however 2442 * return status from TA is no long reliable 2443 */ 2444 if (amdgpu_ras_intr_triggered()) 2445 return 0; 2446 2447 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2448 return -EACCES; 2449 else if (ras_status) 2450 return -EINVAL; 2451 2452 return 0; 2453 } 2454 2455 int psp_ras_query_address(struct psp_context *psp, 2456 struct ta_ras_query_address_input *addr_in, 2457 struct ta_ras_query_address_output *addr_out) 2458 { 2459 int ret; 2460 2461 if (!psp->ras_context.context.initialized || 2462 !addr_in || !addr_out) 2463 return -EINVAL; 2464 2465 ret = psp_ras_send_cmd(psp, 2466 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2467 2468 return ret; 2469 } 2470 // ras end 2471 2472 // HDCP start 2473 static int psp_hdcp_initialize(struct psp_context *psp) 2474 { 2475 int ret; 2476 2477 /* 2478 * TODO: bypass the initialize in sriov for now 2479 */ 2480 if (amdgpu_sriov_vf(psp->adev)) 2481 return 0; 2482 2483 /* bypass hdcp initialization if dmu is harvested */ 2484 if (!amdgpu_device_has_display_hardware(psp->adev)) 2485 return 0; 2486 2487 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2488 !psp->hdcp_context.context.bin_desc.start_addr) { 2489 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2490 return 0; 2491 } 2492 2493 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2494 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2495 2496 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2497 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2498 if (ret) 2499 return ret; 2500 } 2501 2502 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2503 if (!ret) { 2504 psp->hdcp_context.context.initialized = true; 2505 mutex_init(&psp->hdcp_context.mutex); 2506 } 2507 2508 return ret; 2509 } 2510 2511 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2512 { 2513 /* 2514 * TODO: bypass the loading in sriov for now 2515 */ 2516 if (amdgpu_sriov_vf(psp->adev)) 2517 return 0; 2518 2519 if (!psp->hdcp_context.context.initialized) 2520 return 0; 2521 2522 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2523 } 2524 2525 static int psp_hdcp_terminate(struct psp_context *psp) 2526 { 2527 int ret; 2528 2529 /* 2530 * TODO: bypass the terminate in sriov for now 2531 */ 2532 if (amdgpu_sriov_vf(psp->adev)) 2533 return 0; 2534 2535 if (!psp->hdcp_context.context.initialized) 2536 return 0; 2537 2538 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2539 2540 psp->hdcp_context.context.initialized = false; 2541 2542 return ret; 2543 } 2544 // HDCP end 2545 2546 // DTM start 2547 static int psp_dtm_initialize(struct psp_context *psp) 2548 { 2549 int ret; 2550 2551 /* 2552 * TODO: bypass the initialize in sriov for now 2553 */ 2554 if (amdgpu_sriov_vf(psp->adev)) 2555 return 0; 2556 2557 /* bypass dtm initialization if dmu is harvested */ 2558 if (!amdgpu_device_has_display_hardware(psp->adev)) 2559 return 0; 2560 2561 if (!psp->dtm_context.context.bin_desc.size_bytes || 2562 !psp->dtm_context.context.bin_desc.start_addr) { 2563 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2564 return 0; 2565 } 2566 2567 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2568 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2569 2570 if (!psp->dtm_context.context.mem_context.shared_buf) { 2571 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2572 if (ret) 2573 return ret; 2574 } 2575 2576 ret = psp_ta_load(psp, &psp->dtm_context.context); 2577 if (!ret) { 2578 psp->dtm_context.context.initialized = true; 2579 mutex_init(&psp->dtm_context.mutex); 2580 } 2581 2582 return ret; 2583 } 2584 2585 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2586 { 2587 /* 2588 * TODO: bypass the loading in sriov for now 2589 */ 2590 if (amdgpu_sriov_vf(psp->adev)) 2591 return 0; 2592 2593 if (!psp->dtm_context.context.initialized) 2594 return 0; 2595 2596 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2597 } 2598 2599 static int psp_dtm_terminate(struct psp_context *psp) 2600 { 2601 int ret; 2602 2603 /* 2604 * TODO: bypass the terminate in sriov for now 2605 */ 2606 if (amdgpu_sriov_vf(psp->adev)) 2607 return 0; 2608 2609 if (!psp->dtm_context.context.initialized) 2610 return 0; 2611 2612 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2613 2614 psp->dtm_context.context.initialized = false; 2615 2616 return ret; 2617 } 2618 // DTM end 2619 2620 // RAP start 2621 static int psp_rap_initialize(struct psp_context *psp) 2622 { 2623 int ret; 2624 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2625 2626 /* 2627 * TODO: bypass the initialize in sriov for now 2628 */ 2629 if (amdgpu_sriov_vf(psp->adev)) 2630 return 0; 2631 2632 if (!psp->rap_context.context.bin_desc.size_bytes || 2633 !psp->rap_context.context.bin_desc.start_addr) { 2634 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2635 return 0; 2636 } 2637 2638 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2639 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2640 2641 if (!psp->rap_context.context.mem_context.shared_buf) { 2642 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2643 if (ret) 2644 return ret; 2645 } 2646 2647 ret = psp_ta_load(psp, &psp->rap_context.context); 2648 if (!ret) { 2649 psp->rap_context.context.initialized = true; 2650 mutex_init(&psp->rap_context.mutex); 2651 } else 2652 return ret; 2653 2654 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2655 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2656 psp_rap_terminate(psp); 2657 /* free rap shared memory */ 2658 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2659 2660 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2661 ret, status); 2662 2663 return ret; 2664 } 2665 2666 return 0; 2667 } 2668 2669 static int psp_rap_terminate(struct psp_context *psp) 2670 { 2671 int ret; 2672 2673 if (!psp->rap_context.context.initialized) 2674 return 0; 2675 2676 ret = psp_ta_unload(psp, &psp->rap_context.context); 2677 2678 psp->rap_context.context.initialized = false; 2679 2680 return ret; 2681 } 2682 2683 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2684 { 2685 struct ta_rap_shared_memory *rap_cmd; 2686 int ret = 0; 2687 2688 if (!psp->rap_context.context.initialized) 2689 return 0; 2690 2691 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2692 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2693 return -EINVAL; 2694 2695 mutex_lock(&psp->rap_context.mutex); 2696 2697 rap_cmd = (struct ta_rap_shared_memory *) 2698 psp->rap_context.context.mem_context.shared_buf; 2699 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2700 2701 rap_cmd->cmd_id = ta_cmd_id; 2702 rap_cmd->validation_method_id = METHOD_A; 2703 2704 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2705 if (ret) 2706 goto out_unlock; 2707 2708 if (status) 2709 *status = rap_cmd->rap_status; 2710 2711 out_unlock: 2712 mutex_unlock(&psp->rap_context.mutex); 2713 2714 return ret; 2715 } 2716 // RAP end 2717 2718 /* securedisplay start */ 2719 static int psp_securedisplay_initialize(struct psp_context *psp) 2720 { 2721 int ret; 2722 struct ta_securedisplay_cmd *securedisplay_cmd; 2723 2724 /* 2725 * TODO: bypass the initialize in sriov for now 2726 */ 2727 if (amdgpu_sriov_vf(psp->adev)) 2728 return 0; 2729 2730 /* bypass securedisplay initialization if dmu is harvested */ 2731 if (!amdgpu_device_has_display_hardware(psp->adev)) 2732 return 0; 2733 2734 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2735 !psp->securedisplay_context.context.bin_desc.start_addr) { 2736 dev_info(psp->adev->dev, 2737 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2738 return 0; 2739 } 2740 2741 psp->securedisplay_context.context.mem_context.shared_mem_size = 2742 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2743 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2744 2745 if (!psp->securedisplay_context.context.initialized) { 2746 ret = psp_ta_init_shared_buf(psp, 2747 &psp->securedisplay_context.context.mem_context); 2748 if (ret) 2749 return ret; 2750 } 2751 2752 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2753 if (!ret && !psp->securedisplay_context.context.resp_status) { 2754 psp->securedisplay_context.context.initialized = true; 2755 mutex_init(&psp->securedisplay_context.mutex); 2756 } else { 2757 /* don't try again */ 2758 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2759 return ret; 2760 } 2761 2762 mutex_lock(&psp->securedisplay_context.mutex); 2763 2764 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2765 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2766 2767 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2768 2769 mutex_unlock(&psp->securedisplay_context.mutex); 2770 2771 if (ret) { 2772 psp_securedisplay_terminate(psp); 2773 /* free securedisplay shared memory */ 2774 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2775 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2776 return -EINVAL; 2777 } 2778 2779 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2780 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2781 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2782 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2783 /* don't try again */ 2784 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2785 } 2786 2787 return 0; 2788 } 2789 2790 static int psp_securedisplay_terminate(struct psp_context *psp) 2791 { 2792 int ret; 2793 2794 /* 2795 * TODO:bypass the terminate in sriov for now 2796 */ 2797 if (amdgpu_sriov_vf(psp->adev)) 2798 return 0; 2799 2800 if (!psp->securedisplay_context.context.initialized) 2801 return 0; 2802 2803 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2804 2805 psp->securedisplay_context.context.initialized = false; 2806 2807 return ret; 2808 } 2809 2810 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2811 { 2812 int ret; 2813 2814 if (!psp->securedisplay_context.context.initialized) 2815 return -EINVAL; 2816 2817 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2818 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2819 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2820 return -EINVAL; 2821 2822 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2823 2824 return ret; 2825 } 2826 /* SECUREDISPLAY end */ 2827 2828 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2829 { 2830 struct psp_context *psp = &adev->psp; 2831 int ret = 0; 2832 2833 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2834 ret = psp->funcs->wait_for_bootloader(psp); 2835 2836 return ret; 2837 } 2838 2839 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2840 { 2841 if (psp->funcs && 2842 psp->funcs->get_ras_capability) { 2843 return psp->funcs->get_ras_capability(psp); 2844 } else { 2845 return false; 2846 } 2847 } 2848 2849 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2850 { 2851 struct psp_context *psp = &adev->psp; 2852 2853 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2854 return false; 2855 2856 if (psp->funcs && psp->funcs->is_reload_needed) 2857 return psp->funcs->is_reload_needed(psp); 2858 2859 return false; 2860 } 2861 2862 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2863 { 2864 struct psp_context *psp = &adev->psp; 2865 2866 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2867 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2868 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2869 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2870 } 2871 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2872 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2873 } 2874 2875 static int psp_hw_start(struct psp_context *psp) 2876 { 2877 struct amdgpu_device *adev = psp->adev; 2878 int ret; 2879 2880 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2881 psp_update_gpu_addresses(adev); 2882 2883 if (!amdgpu_sriov_vf(adev)) { 2884 if ((is_psp_fw_valid(psp->kdb)) && 2885 (psp->funcs->bootloader_load_kdb != NULL)) { 2886 ret = psp_bootloader_load_kdb(psp); 2887 if (ret) { 2888 dev_err(adev->dev, "PSP load kdb failed!\n"); 2889 return ret; 2890 } 2891 } 2892 2893 if ((is_psp_fw_valid(psp->spl)) && 2894 (psp->funcs->bootloader_load_spl != NULL)) { 2895 ret = psp_bootloader_load_spl(psp); 2896 if (ret) { 2897 dev_err(adev->dev, "PSP load spl failed!\n"); 2898 return ret; 2899 } 2900 } 2901 2902 if ((is_psp_fw_valid(psp->sys)) && 2903 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2904 ret = psp_bootloader_load_sysdrv(psp); 2905 if (ret) { 2906 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2907 return ret; 2908 } 2909 } 2910 2911 if ((is_psp_fw_valid(psp->soc_drv)) && 2912 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2913 ret = psp_bootloader_load_soc_drv(psp); 2914 if (ret) { 2915 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2916 return ret; 2917 } 2918 } 2919 2920 if ((is_psp_fw_valid(psp->intf_drv)) && 2921 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2922 ret = psp_bootloader_load_intf_drv(psp); 2923 if (ret) { 2924 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2925 return ret; 2926 } 2927 } 2928 2929 if ((is_psp_fw_valid(psp->dbg_drv)) && 2930 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2931 ret = psp_bootloader_load_dbg_drv(psp); 2932 if (ret) { 2933 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2934 return ret; 2935 } 2936 } 2937 2938 if ((is_psp_fw_valid(psp->ras_drv)) && 2939 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2940 ret = psp_bootloader_load_ras_drv(psp); 2941 if (ret) { 2942 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2943 return ret; 2944 } 2945 } 2946 2947 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2948 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2949 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2950 if (ret) { 2951 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2952 return ret; 2953 } 2954 } 2955 2956 if ((is_psp_fw_valid(psp->spdm_drv)) && 2957 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2958 ret = psp_bootloader_load_spdm_drv(psp); 2959 if (ret) { 2960 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2961 return ret; 2962 } 2963 } 2964 2965 if ((is_psp_fw_valid(psp->sos)) && 2966 (psp->funcs->bootloader_load_sos != NULL)) { 2967 ret = psp_bootloader_load_sos(psp); 2968 if (ret) { 2969 dev_err(adev->dev, "PSP load sos failed!\n"); 2970 return ret; 2971 } 2972 } 2973 } 2974 2975 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2976 if (ret) { 2977 dev_err(adev->dev, "PSP create ring failed!\n"); 2978 return ret; 2979 } 2980 2981 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2982 ret = psp_update_fw_reservation(psp); 2983 if (ret) { 2984 dev_err(adev->dev, "update fw reservation failed!\n"); 2985 return ret; 2986 } 2987 } 2988 2989 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2990 goto skip_pin_bo; 2991 2992 if (!psp->boot_time_tmr || psp->autoload_supported) { 2993 ret = psp_tmr_init(psp); 2994 if (ret) { 2995 dev_err(adev->dev, "PSP tmr init failed!\n"); 2996 return ret; 2997 } 2998 } 2999 3000 skip_pin_bo: 3001 /* 3002 * For ASICs with DF Cstate management centralized 3003 * to PMFW, TMR setup should be performed after PMFW 3004 * loaded and before other non-psp firmware loaded. 3005 */ 3006 if (psp->pmfw_centralized_cstate_management) { 3007 ret = psp_load_smu_fw(psp); 3008 if (ret) 3009 return ret; 3010 } 3011 3012 ret = psp_tmr_load(psp); 3013 if (ret) { 3014 dev_err(adev->dev, "PSP load tmr failed!\n"); 3015 return ret; 3016 } 3017 3018 return 0; 3019 } 3020 3021 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3022 enum psp_gfx_fw_type *type) 3023 { 3024 switch (ucode->ucode_id) { 3025 case AMDGPU_UCODE_ID_CAP: 3026 *type = GFX_FW_TYPE_CAP; 3027 break; 3028 case AMDGPU_UCODE_ID_SDMA0: 3029 *type = GFX_FW_TYPE_SDMA0; 3030 break; 3031 case AMDGPU_UCODE_ID_SDMA1: 3032 *type = GFX_FW_TYPE_SDMA1; 3033 break; 3034 case AMDGPU_UCODE_ID_SDMA2: 3035 *type = GFX_FW_TYPE_SDMA2; 3036 break; 3037 case AMDGPU_UCODE_ID_SDMA3: 3038 *type = GFX_FW_TYPE_SDMA3; 3039 break; 3040 case AMDGPU_UCODE_ID_SDMA4: 3041 *type = GFX_FW_TYPE_SDMA4; 3042 break; 3043 case AMDGPU_UCODE_ID_SDMA5: 3044 *type = GFX_FW_TYPE_SDMA5; 3045 break; 3046 case AMDGPU_UCODE_ID_SDMA6: 3047 *type = GFX_FW_TYPE_SDMA6; 3048 break; 3049 case AMDGPU_UCODE_ID_SDMA7: 3050 *type = GFX_FW_TYPE_SDMA7; 3051 break; 3052 case AMDGPU_UCODE_ID_CP_MES: 3053 *type = GFX_FW_TYPE_CP_MES; 3054 break; 3055 case AMDGPU_UCODE_ID_CP_MES_DATA: 3056 *type = GFX_FW_TYPE_MES_STACK; 3057 break; 3058 case AMDGPU_UCODE_ID_CP_MES1: 3059 *type = GFX_FW_TYPE_CP_MES_KIQ; 3060 break; 3061 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3062 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3063 break; 3064 case AMDGPU_UCODE_ID_CP_CE: 3065 *type = GFX_FW_TYPE_CP_CE; 3066 break; 3067 case AMDGPU_UCODE_ID_CP_PFP: 3068 *type = GFX_FW_TYPE_CP_PFP; 3069 break; 3070 case AMDGPU_UCODE_ID_CP_ME: 3071 *type = GFX_FW_TYPE_CP_ME; 3072 break; 3073 case AMDGPU_UCODE_ID_CP_MEC1: 3074 *type = GFX_FW_TYPE_CP_MEC; 3075 break; 3076 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3077 *type = GFX_FW_TYPE_CP_MEC_ME1; 3078 break; 3079 case AMDGPU_UCODE_ID_CP_MEC2: 3080 *type = GFX_FW_TYPE_CP_MEC; 3081 break; 3082 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3083 *type = GFX_FW_TYPE_CP_MEC_ME2; 3084 break; 3085 case AMDGPU_UCODE_ID_RLC_P: 3086 *type = GFX_FW_TYPE_RLC_P; 3087 break; 3088 case AMDGPU_UCODE_ID_RLC_V: 3089 *type = GFX_FW_TYPE_RLC_V; 3090 break; 3091 case AMDGPU_UCODE_ID_RLC_G: 3092 *type = GFX_FW_TYPE_RLC_G; 3093 break; 3094 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3095 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3096 break; 3097 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3098 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3099 break; 3100 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3101 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3102 break; 3103 case AMDGPU_UCODE_ID_RLC_IRAM: 3104 *type = GFX_FW_TYPE_RLC_IRAM; 3105 break; 3106 case AMDGPU_UCODE_ID_RLC_DRAM: 3107 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3108 break; 3109 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3110 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3111 break; 3112 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3113 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3114 break; 3115 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3116 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3117 break; 3118 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3119 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3120 break; 3121 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3122 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3123 break; 3124 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3125 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3126 break; 3127 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3128 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3129 break; 3130 case AMDGPU_UCODE_ID_SMC: 3131 *type = GFX_FW_TYPE_SMU; 3132 break; 3133 case AMDGPU_UCODE_ID_PPTABLE: 3134 *type = GFX_FW_TYPE_PPTABLE; 3135 break; 3136 case AMDGPU_UCODE_ID_UVD: 3137 *type = GFX_FW_TYPE_UVD; 3138 break; 3139 case AMDGPU_UCODE_ID_UVD1: 3140 *type = GFX_FW_TYPE_UVD1; 3141 break; 3142 case AMDGPU_UCODE_ID_VCE: 3143 *type = GFX_FW_TYPE_VCE; 3144 break; 3145 case AMDGPU_UCODE_ID_VCN: 3146 *type = GFX_FW_TYPE_VCN; 3147 break; 3148 case AMDGPU_UCODE_ID_VCN1: 3149 *type = GFX_FW_TYPE_VCN1; 3150 break; 3151 case AMDGPU_UCODE_ID_DMCU_ERAM: 3152 *type = GFX_FW_TYPE_DMCU_ERAM; 3153 break; 3154 case AMDGPU_UCODE_ID_DMCU_INTV: 3155 *type = GFX_FW_TYPE_DMCU_ISR; 3156 break; 3157 case AMDGPU_UCODE_ID_VCN0_RAM: 3158 *type = GFX_FW_TYPE_VCN0_RAM; 3159 break; 3160 case AMDGPU_UCODE_ID_VCN1_RAM: 3161 *type = GFX_FW_TYPE_VCN1_RAM; 3162 break; 3163 case AMDGPU_UCODE_ID_DMCUB: 3164 *type = GFX_FW_TYPE_DMUB; 3165 break; 3166 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3167 case AMDGPU_UCODE_ID_SDMA_RS64: 3168 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3169 break; 3170 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3171 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3172 break; 3173 case AMDGPU_UCODE_ID_IMU_I: 3174 *type = GFX_FW_TYPE_IMU_I; 3175 break; 3176 case AMDGPU_UCODE_ID_IMU_D: 3177 *type = GFX_FW_TYPE_IMU_D; 3178 break; 3179 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3180 *type = GFX_FW_TYPE_RS64_PFP; 3181 break; 3182 case AMDGPU_UCODE_ID_CP_RS64_ME: 3183 *type = GFX_FW_TYPE_RS64_ME; 3184 break; 3185 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3186 *type = GFX_FW_TYPE_RS64_MEC; 3187 break; 3188 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3189 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3190 break; 3191 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3192 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3193 break; 3194 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3195 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3196 break; 3197 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3198 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3199 break; 3200 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3201 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3202 break; 3203 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3204 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3205 break; 3206 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3207 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3208 break; 3209 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3210 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3211 break; 3212 case AMDGPU_UCODE_ID_VPE_CTX: 3213 *type = GFX_FW_TYPE_VPEC_FW1; 3214 break; 3215 case AMDGPU_UCODE_ID_VPE_CTL: 3216 *type = GFX_FW_TYPE_VPEC_FW2; 3217 break; 3218 case AMDGPU_UCODE_ID_VPE: 3219 *type = GFX_FW_TYPE_VPE; 3220 break; 3221 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3222 *type = GFX_FW_TYPE_UMSCH_UCODE; 3223 break; 3224 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3225 *type = GFX_FW_TYPE_UMSCH_DATA; 3226 break; 3227 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3228 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3229 break; 3230 case AMDGPU_UCODE_ID_P2S_TABLE: 3231 *type = GFX_FW_TYPE_P2S_TABLE; 3232 break; 3233 case AMDGPU_UCODE_ID_JPEG_RAM: 3234 *type = GFX_FW_TYPE_JPEG_RAM; 3235 break; 3236 case AMDGPU_UCODE_ID_ISP: 3237 *type = GFX_FW_TYPE_ISP; 3238 break; 3239 case AMDGPU_UCODE_ID_MAXIMUM: 3240 default: 3241 return -EINVAL; 3242 } 3243 3244 return 0; 3245 } 3246 3247 static void psp_print_fw_hdr(struct psp_context *psp, 3248 struct amdgpu_firmware_info *ucode) 3249 { 3250 struct amdgpu_device *adev = psp->adev; 3251 struct common_firmware_header *hdr; 3252 3253 switch (ucode->ucode_id) { 3254 case AMDGPU_UCODE_ID_SDMA0: 3255 case AMDGPU_UCODE_ID_SDMA1: 3256 case AMDGPU_UCODE_ID_SDMA2: 3257 case AMDGPU_UCODE_ID_SDMA3: 3258 case AMDGPU_UCODE_ID_SDMA4: 3259 case AMDGPU_UCODE_ID_SDMA5: 3260 case AMDGPU_UCODE_ID_SDMA6: 3261 case AMDGPU_UCODE_ID_SDMA7: 3262 hdr = (struct common_firmware_header *) 3263 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3264 amdgpu_ucode_print_sdma_hdr(hdr); 3265 break; 3266 case AMDGPU_UCODE_ID_CP_CE: 3267 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3268 amdgpu_ucode_print_gfx_hdr(hdr); 3269 break; 3270 case AMDGPU_UCODE_ID_CP_PFP: 3271 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3272 amdgpu_ucode_print_gfx_hdr(hdr); 3273 break; 3274 case AMDGPU_UCODE_ID_CP_ME: 3275 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3276 amdgpu_ucode_print_gfx_hdr(hdr); 3277 break; 3278 case AMDGPU_UCODE_ID_CP_MEC1: 3279 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3280 amdgpu_ucode_print_gfx_hdr(hdr); 3281 break; 3282 case AMDGPU_UCODE_ID_RLC_G: 3283 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3284 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3285 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3286 amdgpu_ucode_print_rlc_hdr(hdr); 3287 break; 3288 case AMDGPU_UCODE_ID_SMC: 3289 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3290 amdgpu_ucode_print_smc_hdr(hdr); 3291 break; 3292 default: 3293 break; 3294 } 3295 } 3296 3297 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3298 struct amdgpu_firmware_info *ucode, 3299 struct psp_gfx_cmd_resp *cmd) 3300 { 3301 int ret; 3302 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3303 3304 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3305 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3306 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3307 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3308 3309 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3310 if (ret) 3311 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3312 return ret; 3313 } 3314 3315 int psp_execute_ip_fw_load(struct psp_context *psp, 3316 struct amdgpu_firmware_info *ucode) 3317 { 3318 int ret = 0; 3319 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3320 3321 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3322 if (!ret) { 3323 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3324 psp->fence_buf_mc_addr); 3325 } 3326 3327 release_psp_cmd_buf(psp); 3328 3329 return ret; 3330 } 3331 3332 static int psp_load_p2s_table(struct psp_context *psp) 3333 { 3334 int ret; 3335 struct amdgpu_device *adev = psp->adev; 3336 struct amdgpu_firmware_info *ucode = 3337 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3338 3339 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3340 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3341 return 0; 3342 3343 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3344 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3345 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3346 0x0036003C; 3347 if (psp->sos.fw_version < supp_vers) 3348 return 0; 3349 } 3350 3351 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3352 return 0; 3353 3354 ret = psp_execute_ip_fw_load(psp, ucode); 3355 3356 return ret; 3357 } 3358 3359 static int psp_load_smu_fw(struct psp_context *psp) 3360 { 3361 int ret; 3362 struct amdgpu_device *adev = psp->adev; 3363 struct amdgpu_firmware_info *ucode = 3364 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3365 struct amdgpu_ras *ras = psp->ras_context.ras; 3366 3367 /* 3368 * Skip SMU FW reloading in case of using BACO for runpm only, 3369 * as SMU is always alive. 3370 */ 3371 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3372 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3373 return 0; 3374 3375 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3376 return 0; 3377 3378 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3379 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3380 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3381 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3382 if (ret) 3383 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3384 } 3385 3386 ret = psp_execute_ip_fw_load(psp, ucode); 3387 3388 if (ret) 3389 dev_err(adev->dev, "PSP load smu failed!\n"); 3390 3391 return ret; 3392 } 3393 3394 static bool fw_load_skip_check(struct psp_context *psp, 3395 struct amdgpu_firmware_info *ucode) 3396 { 3397 if (!ucode->fw || !ucode->ucode_size) 3398 return true; 3399 3400 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3401 return true; 3402 3403 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3404 (psp_smu_reload_quirk(psp) || 3405 psp->autoload_supported || 3406 psp->pmfw_centralized_cstate_management)) 3407 return true; 3408 3409 if (amdgpu_sriov_vf(psp->adev) && 3410 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3411 return true; 3412 3413 if (psp->autoload_supported && 3414 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3415 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3416 /* skip mec JT when autoload is enabled */ 3417 return true; 3418 3419 return false; 3420 } 3421 3422 int psp_load_fw_list(struct psp_context *psp, 3423 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3424 { 3425 int ret = 0, i; 3426 struct amdgpu_firmware_info *ucode; 3427 3428 for (i = 0; i < ucode_count; ++i) { 3429 ucode = ucode_list[i]; 3430 psp_print_fw_hdr(psp, ucode); 3431 ret = psp_execute_ip_fw_load(psp, ucode); 3432 if (ret) 3433 return ret; 3434 } 3435 return ret; 3436 } 3437 3438 static int psp_load_non_psp_fw(struct psp_context *psp) 3439 { 3440 int i, ret; 3441 struct amdgpu_firmware_info *ucode; 3442 struct amdgpu_device *adev = psp->adev; 3443 3444 if (psp->autoload_supported && 3445 !psp->pmfw_centralized_cstate_management) { 3446 ret = psp_load_smu_fw(psp); 3447 if (ret) 3448 return ret; 3449 } 3450 3451 /* Load P2S table first if it's available */ 3452 psp_load_p2s_table(psp); 3453 3454 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3455 ucode = &adev->firmware.ucode[i]; 3456 3457 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3458 !fw_load_skip_check(psp, ucode)) { 3459 ret = psp_load_smu_fw(psp); 3460 if (ret) 3461 return ret; 3462 continue; 3463 } 3464 3465 if (fw_load_skip_check(psp, ucode)) 3466 continue; 3467 3468 if (psp->autoload_supported && 3469 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3470 IP_VERSION(11, 0, 7) || 3471 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3472 IP_VERSION(11, 0, 11) || 3473 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3474 IP_VERSION(11, 0, 12) || 3475 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3476 IP_VERSION(15, 0, 0) || 3477 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3478 IP_VERSION(15, 0, 8)) && 3479 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3480 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3481 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3482 /* PSP only receive one SDMA fw for sienna_cichlid, 3483 * as all four sdma fw are same 3484 */ 3485 continue; 3486 3487 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3488 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3489 IP_VERSION(15, 0, 8) && 3490 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3491 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3492 continue; 3493 3494 psp_print_fw_hdr(psp, ucode); 3495 3496 ret = psp_execute_ip_fw_load(psp, ucode); 3497 if (ret) 3498 return ret; 3499 3500 /* Start rlc autoload after psp received all the gfx firmware */ 3501 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3502 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3503 ret = psp_rlc_autoload_start(psp); 3504 if (ret) { 3505 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3506 return ret; 3507 } 3508 } 3509 } 3510 3511 return 0; 3512 } 3513 3514 static int psp_load_fw(struct amdgpu_device *adev) 3515 { 3516 int ret; 3517 struct psp_context *psp = &adev->psp; 3518 3519 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3520 /* should not destroy ring, only stop */ 3521 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3522 } else { 3523 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3524 3525 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3526 if (ret) { 3527 dev_err(adev->dev, "PSP ring init failed!\n"); 3528 goto failed; 3529 } 3530 } 3531 3532 ret = psp_hw_start(psp); 3533 if (ret) 3534 goto failed; 3535 3536 ret = psp_load_non_psp_fw(psp); 3537 if (ret) 3538 goto failed1; 3539 3540 ret = psp_asd_initialize(psp); 3541 if (ret) { 3542 dev_err(adev->dev, "PSP load asd failed!\n"); 3543 goto failed1; 3544 } 3545 3546 ret = psp_rl_load(adev); 3547 if (ret) { 3548 dev_err(adev->dev, "PSP load RL failed!\n"); 3549 goto failed1; 3550 } 3551 3552 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3553 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3554 ret = psp_xgmi_initialize(psp, false, true); 3555 /* Warning the XGMI seesion initialize failure 3556 * Instead of stop driver initialization 3557 */ 3558 if (ret) 3559 dev_err(psp->adev->dev, 3560 "XGMI: Failed to initialize XGMI session\n"); 3561 } 3562 } 3563 3564 if (psp->ta_fw) { 3565 ret = psp_ras_initialize(psp); 3566 if (ret) 3567 dev_err(psp->adev->dev, 3568 "RAS: Failed to initialize RAS\n"); 3569 3570 ret = psp_hdcp_initialize(psp); 3571 if (ret) 3572 dev_err(psp->adev->dev, 3573 "HDCP: Failed to initialize HDCP\n"); 3574 3575 ret = psp_dtm_initialize(psp); 3576 if (ret) 3577 dev_err(psp->adev->dev, 3578 "DTM: Failed to initialize DTM\n"); 3579 3580 ret = psp_rap_initialize(psp); 3581 if (ret) 3582 dev_err(psp->adev->dev, 3583 "RAP: Failed to initialize RAP\n"); 3584 3585 ret = psp_securedisplay_initialize(psp); 3586 if (ret) 3587 dev_err(psp->adev->dev, 3588 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3589 } 3590 3591 return 0; 3592 3593 failed1: 3594 psp_free_shared_bufs(psp); 3595 failed: 3596 /* 3597 * all cleanup jobs (xgmi terminate, ras terminate, 3598 * ring destroy, cmd/fence/fw buffers destory, 3599 * psp->cmd destory) are delayed to psp_hw_fini 3600 */ 3601 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3602 return ret; 3603 } 3604 3605 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3606 { 3607 int ret; 3608 struct amdgpu_device *adev = ip_block->adev; 3609 3610 mutex_lock(&adev->firmware.mutex); 3611 3612 ret = amdgpu_ucode_init_bo(adev); 3613 if (ret) 3614 goto failed; 3615 3616 ret = psp_load_fw(adev); 3617 if (ret) { 3618 dev_err(adev->dev, "PSP firmware loading failed\n"); 3619 goto failed; 3620 } 3621 3622 mutex_unlock(&adev->firmware.mutex); 3623 return 0; 3624 3625 failed: 3626 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3627 mutex_unlock(&adev->firmware.mutex); 3628 return -EINVAL; 3629 } 3630 3631 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3632 { 3633 struct amdgpu_device *adev = ip_block->adev; 3634 struct psp_context *psp = &adev->psp; 3635 3636 if (psp->ta_fw) { 3637 psp_ras_terminate(psp); 3638 psp_securedisplay_terminate(psp); 3639 psp_rap_terminate(psp); 3640 psp_dtm_terminate(psp); 3641 psp_hdcp_terminate(psp); 3642 3643 if (adev->gmc.xgmi.num_physical_nodes > 1) 3644 psp_xgmi_terminate(psp); 3645 } 3646 3647 psp_asd_terminate(psp); 3648 psp_tmr_terminate(psp); 3649 3650 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3651 3652 return 0; 3653 } 3654 3655 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3656 { 3657 int ret = 0; 3658 struct amdgpu_device *adev = ip_block->adev; 3659 struct psp_context *psp = &adev->psp; 3660 3661 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3662 psp->xgmi_context.context.initialized) { 3663 ret = psp_xgmi_terminate(psp); 3664 if (ret) { 3665 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3666 goto out; 3667 } 3668 } 3669 3670 if (psp->ta_fw) { 3671 ret = psp_ras_terminate(psp); 3672 if (ret) { 3673 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3674 goto out; 3675 } 3676 ret = psp_hdcp_terminate(psp); 3677 if (ret) { 3678 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3679 goto out; 3680 } 3681 ret = psp_dtm_terminate(psp); 3682 if (ret) { 3683 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3684 goto out; 3685 } 3686 ret = psp_rap_terminate(psp); 3687 if (ret) { 3688 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3689 goto out; 3690 } 3691 ret = psp_securedisplay_terminate(psp); 3692 if (ret) { 3693 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3694 goto out; 3695 } 3696 } 3697 3698 ret = psp_asd_terminate(psp); 3699 if (ret) { 3700 dev_err(adev->dev, "Failed to terminate asd\n"); 3701 goto out; 3702 } 3703 3704 ret = psp_tmr_terminate(psp); 3705 if (ret) { 3706 dev_err(adev->dev, "Failed to terminate tmr\n"); 3707 goto out; 3708 } 3709 3710 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3711 if (ret) 3712 dev_err(adev->dev, "PSP ring stop failed\n"); 3713 3714 out: 3715 return ret; 3716 } 3717 3718 static int psp_resume(struct amdgpu_ip_block *ip_block) 3719 { 3720 int ret; 3721 struct amdgpu_device *adev = ip_block->adev; 3722 struct psp_context *psp = &adev->psp; 3723 3724 dev_info(adev->dev, "PSP is resuming...\n"); 3725 3726 if (psp->mem_train_ctx.enable_mem_training) { 3727 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3728 if (ret) { 3729 dev_err(adev->dev, "Failed to process memory training!\n"); 3730 return ret; 3731 } 3732 } 3733 3734 mutex_lock(&adev->firmware.mutex); 3735 3736 ret = amdgpu_ucode_init_bo(adev); 3737 if (ret) 3738 goto failed; 3739 3740 ret = psp_hw_start(psp); 3741 if (ret) 3742 goto failed; 3743 3744 ret = psp_load_non_psp_fw(psp); 3745 if (ret) 3746 goto failed; 3747 3748 ret = psp_asd_initialize(psp); 3749 if (ret) { 3750 dev_err(adev->dev, "PSP load asd failed!\n"); 3751 goto failed; 3752 } 3753 3754 ret = psp_rl_load(adev); 3755 if (ret) { 3756 dev_err(adev->dev, "PSP load RL failed!\n"); 3757 goto failed; 3758 } 3759 3760 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3761 ret = psp_xgmi_initialize(psp, false, true); 3762 /* Warning the XGMI seesion initialize failure 3763 * Instead of stop driver initialization 3764 */ 3765 if (ret) 3766 dev_err(psp->adev->dev, 3767 "XGMI: Failed to initialize XGMI session\n"); 3768 } 3769 3770 if (psp->ta_fw) { 3771 ret = psp_ras_initialize(psp); 3772 if (ret) 3773 dev_err(psp->adev->dev, 3774 "RAS: Failed to initialize RAS\n"); 3775 3776 ret = psp_hdcp_initialize(psp); 3777 if (ret) 3778 dev_err(psp->adev->dev, 3779 "HDCP: Failed to initialize HDCP\n"); 3780 3781 ret = psp_dtm_initialize(psp); 3782 if (ret) 3783 dev_err(psp->adev->dev, 3784 "DTM: Failed to initialize DTM\n"); 3785 3786 ret = psp_rap_initialize(psp); 3787 if (ret) 3788 dev_err(psp->adev->dev, 3789 "RAP: Failed to initialize RAP\n"); 3790 3791 ret = psp_securedisplay_initialize(psp); 3792 if (ret) 3793 dev_err(psp->adev->dev, 3794 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3795 } 3796 3797 mutex_unlock(&adev->firmware.mutex); 3798 3799 return 0; 3800 3801 failed: 3802 dev_err(adev->dev, "PSP resume failed\n"); 3803 mutex_unlock(&adev->firmware.mutex); 3804 return ret; 3805 } 3806 3807 int psp_gpu_reset(struct amdgpu_device *adev) 3808 { 3809 int ret; 3810 3811 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3812 return 0; 3813 3814 mutex_lock(&adev->psp.mutex); 3815 ret = psp_mode1_reset(&adev->psp); 3816 mutex_unlock(&adev->psp.mutex); 3817 3818 return ret; 3819 } 3820 3821 int psp_rlc_autoload_start(struct psp_context *psp) 3822 { 3823 int ret; 3824 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3825 3826 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3827 3828 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3829 psp->fence_buf_mc_addr); 3830 3831 release_psp_cmd_buf(psp); 3832 3833 return ret; 3834 } 3835 3836 int psp_ring_cmd_submit(struct psp_context *psp, 3837 uint64_t cmd_buf_mc_addr, 3838 uint64_t fence_mc_addr, 3839 int index) 3840 { 3841 unsigned int psp_write_ptr_reg = 0; 3842 struct psp_gfx_rb_frame *write_frame; 3843 struct psp_ring *ring = &psp->km_ring; 3844 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3845 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3846 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3847 struct amdgpu_device *adev = psp->adev; 3848 uint32_t ring_size_dw = ring->ring_size / 4; 3849 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3850 3851 /* KM (GPCOM) prepare write pointer */ 3852 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3853 3854 /* Update KM RB frame pointer to new frame */ 3855 /* write_frame ptr increments by size of rb_frame in bytes */ 3856 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3857 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3858 write_frame = ring_buffer_start; 3859 else 3860 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3861 /* Check invalid write_frame ptr address */ 3862 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3863 dev_err(adev->dev, 3864 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3865 ring_buffer_start, ring_buffer_end, write_frame); 3866 dev_err(adev->dev, 3867 "write_frame is pointing to address out of bounds\n"); 3868 return -EINVAL; 3869 } 3870 3871 /* Initialize KM RB frame */ 3872 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3873 3874 /* Update KM RB frame */ 3875 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3876 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3877 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3878 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3879 write_frame->fence_value = index; 3880 amdgpu_device_flush_hdp(adev, NULL); 3881 3882 /* Update the write Pointer in DWORDs */ 3883 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3884 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3885 return 0; 3886 } 3887 3888 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3889 { 3890 struct amdgpu_device *adev = psp->adev; 3891 const struct psp_firmware_header_v1_0 *asd_hdr; 3892 int err = 0; 3893 3894 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3895 "amdgpu/%s_asd.bin", chip_name); 3896 if (err) 3897 goto out; 3898 3899 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3900 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3901 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3902 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3903 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3904 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3905 return 0; 3906 out: 3907 amdgpu_ucode_release(&adev->psp.asd_fw); 3908 return err; 3909 } 3910 3911 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3912 { 3913 struct amdgpu_device *adev = psp->adev; 3914 const struct psp_firmware_header_v1_0 *toc_hdr; 3915 int err = 0; 3916 3917 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3918 adev->rev_id == 0) 3919 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3920 "amdgpu/%s_toc_1.bin", chip_name); 3921 else 3922 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3923 "amdgpu/%s_toc.bin", chip_name); 3924 if (err) 3925 goto out; 3926 3927 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3928 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3929 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3930 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3931 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3932 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3933 return 0; 3934 out: 3935 amdgpu_ucode_release(&adev->psp.toc_fw); 3936 return err; 3937 } 3938 3939 static int parse_sos_bin_descriptor(struct psp_context *psp, 3940 const struct psp_fw_bin_desc *desc, 3941 const struct psp_firmware_header_v2_0 *sos_hdr) 3942 { 3943 uint8_t *ucode_start_addr = NULL; 3944 3945 if (!psp || !desc || !sos_hdr) 3946 return -EINVAL; 3947 3948 ucode_start_addr = (uint8_t *)sos_hdr + 3949 le32_to_cpu(desc->offset_bytes) + 3950 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3951 3952 switch (desc->fw_type) { 3953 case PSP_FW_TYPE_PSP_SOS: 3954 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3955 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3956 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3957 psp->sos.start_addr = ucode_start_addr; 3958 break; 3959 case PSP_FW_TYPE_PSP_SYS_DRV: 3960 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3961 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3962 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3963 psp->sys.start_addr = ucode_start_addr; 3964 break; 3965 case PSP_FW_TYPE_PSP_KDB: 3966 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3967 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3968 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3969 psp->kdb.start_addr = ucode_start_addr; 3970 break; 3971 case PSP_FW_TYPE_PSP_TOC: 3972 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3973 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3974 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3975 psp->toc.start_addr = ucode_start_addr; 3976 break; 3977 case PSP_FW_TYPE_PSP_SPL: 3978 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3979 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3980 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3981 psp->spl.start_addr = ucode_start_addr; 3982 break; 3983 case PSP_FW_TYPE_PSP_RL: 3984 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3985 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3986 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3987 psp->rl.start_addr = ucode_start_addr; 3988 break; 3989 case PSP_FW_TYPE_PSP_SOC_DRV: 3990 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3991 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3992 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3993 psp->soc_drv.start_addr = ucode_start_addr; 3994 break; 3995 case PSP_FW_TYPE_PSP_INTF_DRV: 3996 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3997 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3998 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3999 psp->intf_drv.start_addr = ucode_start_addr; 4000 break; 4001 case PSP_FW_TYPE_PSP_DBG_DRV: 4002 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4003 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4004 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4005 psp->dbg_drv.start_addr = ucode_start_addr; 4006 break; 4007 case PSP_FW_TYPE_PSP_RAS_DRV: 4008 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4009 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4010 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4011 psp->ras_drv.start_addr = ucode_start_addr; 4012 break; 4013 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4014 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4015 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4016 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4017 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4018 break; 4019 case PSP_FW_TYPE_PSP_SPDM_DRV: 4020 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4021 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4022 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4023 psp->spdm_drv.start_addr = ucode_start_addr; 4024 break; 4025 default: 4026 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4027 break; 4028 } 4029 4030 return 0; 4031 } 4032 4033 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4034 { 4035 const struct psp_firmware_header_v1_0 *sos_hdr; 4036 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4037 uint8_t *ucode_array_start_addr; 4038 4039 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4040 ucode_array_start_addr = (uint8_t *)sos_hdr + 4041 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4042 4043 if (adev->gmc.xgmi.connected_to_cpu || 4044 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4045 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4046 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4047 4048 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4049 adev->psp.sys.start_addr = ucode_array_start_addr; 4050 4051 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4052 adev->psp.sos.start_addr = ucode_array_start_addr + 4053 le32_to_cpu(sos_hdr->sos.offset_bytes); 4054 } else { 4055 /* Load alternate PSP SOS FW */ 4056 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4057 4058 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4059 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4060 4061 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4062 adev->psp.sys.start_addr = ucode_array_start_addr + 4063 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4064 4065 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4066 adev->psp.sos.start_addr = ucode_array_start_addr + 4067 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4068 } 4069 4070 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4071 dev_warn(adev->dev, "PSP SOS FW not available"); 4072 return -EINVAL; 4073 } 4074 4075 return 0; 4076 } 4077 4078 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4079 { 4080 struct amdgpu_device *adev = psp->adev; 4081 const struct psp_firmware_header_v1_0 *sos_hdr; 4082 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4083 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4084 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4085 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4086 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4087 int fw_index, fw_bin_count, start_index = 0; 4088 const struct psp_fw_bin_desc *fw_bin; 4089 uint8_t *ucode_array_start_addr; 4090 int err = 0; 4091 4092 if (amdgpu_is_kicker_fw(adev)) 4093 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4094 "amdgpu/%s_sos_kicker.bin", chip_name); 4095 else 4096 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4097 "amdgpu/%s_sos.bin", chip_name); 4098 if (err) 4099 goto out; 4100 4101 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4102 ucode_array_start_addr = (uint8_t *)sos_hdr + 4103 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4104 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4105 4106 switch (sos_hdr->header.header_version_major) { 4107 case 1: 4108 err = psp_init_sos_base_fw(adev); 4109 if (err) 4110 goto out; 4111 4112 if (sos_hdr->header.header_version_minor == 1) { 4113 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4114 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4115 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4116 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4117 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4118 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4119 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4120 } 4121 if (sos_hdr->header.header_version_minor == 2) { 4122 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4123 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4124 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4125 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4126 } 4127 if (sos_hdr->header.header_version_minor == 3) { 4128 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4129 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4130 adev->psp.toc.start_addr = ucode_array_start_addr + 4131 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4132 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4133 adev->psp.kdb.start_addr = ucode_array_start_addr + 4134 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4135 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4136 adev->psp.spl.start_addr = ucode_array_start_addr + 4137 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4138 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4139 adev->psp.rl.start_addr = ucode_array_start_addr + 4140 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4141 } 4142 break; 4143 case 2: 4144 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4145 4146 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4147 4148 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4149 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4150 err = -EINVAL; 4151 goto out; 4152 } 4153 4154 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4155 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4156 4157 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4158 4159 if (psp_is_aux_sos_load_required(psp)) 4160 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4161 else 4162 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4163 4164 } else { 4165 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4166 } 4167 4168 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4169 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4170 sos_hdr_v2_0); 4171 if (err) 4172 goto out; 4173 } 4174 break; 4175 default: 4176 dev_err(adev->dev, 4177 "unsupported psp sos firmware\n"); 4178 err = -EINVAL; 4179 goto out; 4180 } 4181 4182 return 0; 4183 out: 4184 amdgpu_ucode_release(&adev->psp.sos_fw); 4185 4186 return err; 4187 } 4188 4189 static bool is_ta_fw_applicable(struct psp_context *psp, 4190 const struct psp_fw_bin_desc *desc) 4191 { 4192 struct amdgpu_device *adev = psp->adev; 4193 uint32_t fw_version; 4194 4195 switch (desc->fw_type) { 4196 case TA_FW_TYPE_PSP_XGMI: 4197 case TA_FW_TYPE_PSP_XGMI_AUX: 4198 /* for now, AUX TA only exists on 13.0.6 ta bin, 4199 * from v20.00.0x.14 4200 */ 4201 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4202 IP_VERSION(13, 0, 6)) { 4203 fw_version = le32_to_cpu(desc->fw_version); 4204 4205 if (adev->flags & AMD_IS_APU && 4206 (fw_version & 0xff) >= 0x14) 4207 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4208 else 4209 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4210 } 4211 break; 4212 default: 4213 break; 4214 } 4215 4216 return true; 4217 } 4218 4219 static int parse_ta_bin_descriptor(struct psp_context *psp, 4220 const struct psp_fw_bin_desc *desc, 4221 const struct ta_firmware_header_v2_0 *ta_hdr) 4222 { 4223 uint8_t *ucode_start_addr = NULL; 4224 4225 if (!psp || !desc || !ta_hdr) 4226 return -EINVAL; 4227 4228 if (!is_ta_fw_applicable(psp, desc)) 4229 return 0; 4230 4231 ucode_start_addr = (uint8_t *)ta_hdr + 4232 le32_to_cpu(desc->offset_bytes) + 4233 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4234 4235 switch (desc->fw_type) { 4236 case TA_FW_TYPE_PSP_ASD: 4237 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4238 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4239 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4240 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4241 break; 4242 case TA_FW_TYPE_PSP_XGMI: 4243 case TA_FW_TYPE_PSP_XGMI_AUX: 4244 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4245 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4246 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4247 break; 4248 case TA_FW_TYPE_PSP_RAS: 4249 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4250 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4251 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4252 break; 4253 case TA_FW_TYPE_PSP_HDCP: 4254 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4255 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4256 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4257 break; 4258 case TA_FW_TYPE_PSP_DTM: 4259 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4260 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4261 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4262 break; 4263 case TA_FW_TYPE_PSP_RAP: 4264 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4265 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4266 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4267 break; 4268 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4269 psp->securedisplay_context.context.bin_desc.fw_version = 4270 le32_to_cpu(desc->fw_version); 4271 psp->securedisplay_context.context.bin_desc.size_bytes = 4272 le32_to_cpu(desc->size_bytes); 4273 psp->securedisplay_context.context.bin_desc.start_addr = 4274 ucode_start_addr; 4275 break; 4276 default: 4277 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4278 break; 4279 } 4280 4281 return 0; 4282 } 4283 4284 static int parse_ta_v1_microcode(struct psp_context *psp) 4285 { 4286 const struct ta_firmware_header_v1_0 *ta_hdr; 4287 struct amdgpu_device *adev = psp->adev; 4288 4289 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4290 4291 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4292 return -EINVAL; 4293 4294 adev->psp.xgmi_context.context.bin_desc.fw_version = 4295 le32_to_cpu(ta_hdr->xgmi.fw_version); 4296 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4297 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4298 adev->psp.xgmi_context.context.bin_desc.start_addr = 4299 (uint8_t *)ta_hdr + 4300 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4301 4302 adev->psp.ras_context.context.bin_desc.fw_version = 4303 le32_to_cpu(ta_hdr->ras.fw_version); 4304 adev->psp.ras_context.context.bin_desc.size_bytes = 4305 le32_to_cpu(ta_hdr->ras.size_bytes); 4306 adev->psp.ras_context.context.bin_desc.start_addr = 4307 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4308 le32_to_cpu(ta_hdr->ras.offset_bytes); 4309 4310 adev->psp.hdcp_context.context.bin_desc.fw_version = 4311 le32_to_cpu(ta_hdr->hdcp.fw_version); 4312 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4313 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4314 adev->psp.hdcp_context.context.bin_desc.start_addr = 4315 (uint8_t *)ta_hdr + 4316 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4317 4318 adev->psp.dtm_context.context.bin_desc.fw_version = 4319 le32_to_cpu(ta_hdr->dtm.fw_version); 4320 adev->psp.dtm_context.context.bin_desc.size_bytes = 4321 le32_to_cpu(ta_hdr->dtm.size_bytes); 4322 adev->psp.dtm_context.context.bin_desc.start_addr = 4323 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4324 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4325 4326 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4327 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4328 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4329 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4330 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4331 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4332 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4333 4334 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4335 4336 return 0; 4337 } 4338 4339 static int parse_ta_v2_microcode(struct psp_context *psp) 4340 { 4341 const struct ta_firmware_header_v2_0 *ta_hdr; 4342 struct amdgpu_device *adev = psp->adev; 4343 int err = 0; 4344 int ta_index = 0; 4345 4346 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4347 4348 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4349 return -EINVAL; 4350 4351 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4352 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4353 return -EINVAL; 4354 } 4355 4356 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4357 err = parse_ta_bin_descriptor(psp, 4358 &ta_hdr->ta_fw_bin[ta_index], 4359 ta_hdr); 4360 if (err) 4361 return err; 4362 } 4363 4364 return 0; 4365 } 4366 4367 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4368 { 4369 const struct common_firmware_header *hdr; 4370 struct amdgpu_device *adev = psp->adev; 4371 int err; 4372 4373 if (amdgpu_is_kicker_fw(adev)) 4374 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4375 "amdgpu/%s_ta_kicker.bin", chip_name); 4376 else 4377 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4378 "amdgpu/%s_ta.bin", chip_name); 4379 if (err) 4380 return err; 4381 4382 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4383 switch (le16_to_cpu(hdr->header_version_major)) { 4384 case 1: 4385 err = parse_ta_v1_microcode(psp); 4386 break; 4387 case 2: 4388 err = parse_ta_v2_microcode(psp); 4389 break; 4390 default: 4391 dev_err(adev->dev, "unsupported TA header version\n"); 4392 err = -EINVAL; 4393 } 4394 4395 if (err) 4396 amdgpu_ucode_release(&adev->psp.ta_fw); 4397 4398 return err; 4399 } 4400 4401 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4402 { 4403 struct amdgpu_device *adev = psp->adev; 4404 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4405 struct amdgpu_firmware_info *info = NULL; 4406 int err = 0; 4407 4408 if (!amdgpu_sriov_vf(adev)) { 4409 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4410 return -EINVAL; 4411 } 4412 4413 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4414 "amdgpu/%s_cap.bin", chip_name); 4415 if (err) { 4416 if (err == -ENODEV) { 4417 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4418 err = 0; 4419 } else { 4420 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4421 } 4422 goto out; 4423 } 4424 4425 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4426 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4427 info->fw = adev->psp.cap_fw; 4428 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4429 adev->psp.cap_fw->data; 4430 adev->firmware.fw_size += ALIGN( 4431 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4432 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4433 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4434 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4435 4436 return 0; 4437 4438 out: 4439 amdgpu_ucode_release(&adev->psp.cap_fw); 4440 return err; 4441 } 4442 4443 int psp_config_sq_perfmon(struct psp_context *psp, 4444 uint32_t xcp_id, bool core_override_enable, 4445 bool reg_override_enable, bool perfmon_override_enable) 4446 { 4447 int ret; 4448 4449 if (amdgpu_sriov_vf(psp->adev)) 4450 return 0; 4451 4452 if (xcp_id > MAX_XCP) { 4453 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4454 return -EINVAL; 4455 } 4456 4457 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4458 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4459 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4460 return -EINVAL; 4461 } 4462 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4463 4464 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4465 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4466 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4467 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4468 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4469 4470 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4471 if (ret) 4472 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4473 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4474 4475 release_psp_cmd_buf(psp); 4476 return ret; 4477 } 4478 4479 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4480 enum amd_clockgating_state state) 4481 { 4482 return 0; 4483 } 4484 4485 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4486 enum amd_powergating_state state) 4487 { 4488 return 0; 4489 } 4490 4491 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4492 struct device_attribute *attr, 4493 char *buf) 4494 { 4495 struct drm_device *ddev = dev_get_drvdata(dev); 4496 struct amdgpu_device *adev = drm_to_adev(ddev); 4497 struct amdgpu_ip_block *ip_block; 4498 uint32_t fw_ver; 4499 int ret; 4500 4501 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4502 if (!ip_block || !ip_block->status.late_initialized) { 4503 dev_info(adev->dev, "PSP block is not ready yet\n."); 4504 return -EBUSY; 4505 } 4506 4507 mutex_lock(&adev->psp.mutex); 4508 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4509 mutex_unlock(&adev->psp.mutex); 4510 4511 if (ret) { 4512 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4513 return ret; 4514 } 4515 4516 return sysfs_emit(buf, "%x\n", fw_ver); 4517 } 4518 4519 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4520 struct device_attribute *attr, 4521 const char *buf, 4522 size_t count) 4523 { 4524 struct drm_device *ddev = dev_get_drvdata(dev); 4525 struct amdgpu_device *adev = drm_to_adev(ddev); 4526 int ret, idx; 4527 const struct firmware *usbc_pd_fw; 4528 struct amdgpu_bo *fw_buf_bo = NULL; 4529 uint64_t fw_pri_mc_addr; 4530 void *fw_pri_cpu_addr; 4531 struct amdgpu_ip_block *ip_block; 4532 4533 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4534 if (!ip_block || !ip_block->status.late_initialized) { 4535 dev_err(adev->dev, "PSP block is not ready yet."); 4536 return -EBUSY; 4537 } 4538 4539 if (!drm_dev_enter(ddev, &idx)) 4540 return -ENODEV; 4541 4542 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4543 "amdgpu/%s", buf); 4544 if (ret) 4545 goto fail; 4546 4547 /* LFB address which is aligned to 1MB boundary per PSP request */ 4548 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4549 AMDGPU_GEM_DOMAIN_VRAM | 4550 AMDGPU_GEM_DOMAIN_GTT, 4551 &fw_buf_bo, &fw_pri_mc_addr, 4552 &fw_pri_cpu_addr); 4553 if (ret) 4554 goto rel_buf; 4555 4556 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4557 4558 mutex_lock(&adev->psp.mutex); 4559 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4560 mutex_unlock(&adev->psp.mutex); 4561 4562 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4563 4564 rel_buf: 4565 amdgpu_ucode_release(&usbc_pd_fw); 4566 fail: 4567 if (ret) { 4568 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4569 count = ret; 4570 } 4571 4572 drm_dev_exit(idx); 4573 return count; 4574 } 4575 4576 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4577 { 4578 int idx; 4579 4580 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4581 return -ENODEV; 4582 4583 if (!bin_size || bin_size > PSP_1_MEG) { 4584 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 4585 drm_dev_exit(idx); 4586 return -EINVAL; 4587 } 4588 4589 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4590 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4591 4592 drm_dev_exit(idx); 4593 return 0; 4594 } 4595 4596 /** 4597 * DOC: usbc_pd_fw 4598 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4599 * this file will trigger the update process. 4600 */ 4601 static DEVICE_ATTR(usbc_pd_fw, 0644, 4602 psp_usbc_pd_fw_sysfs_read, 4603 psp_usbc_pd_fw_sysfs_write); 4604 /** 4605 * DOC: PTL sysfs attributes 4606 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4607 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4608 * formats for each GPU. 4609 */ 4610 static DEVICE_ATTR(ptl_enable, 0644, 4611 ptl_enable_show, ptl_enable_store); 4612 static DEVICE_ATTR(ptl_format, 0644, 4613 ptl_format_show, ptl_format_store); 4614 static DEVICE_ATTR(ptl_supported_formats, 0444, 4615 ptl_supported_formats_show, NULL); 4616 4617 static struct attribute *ptl_attrs[] = { 4618 &dev_attr_ptl_enable.attr, 4619 &dev_attr_ptl_format.attr, 4620 &dev_attr_ptl_supported_formats.attr, 4621 NULL, 4622 }; 4623 4624 const struct attribute_group amdgpu_ptl_attr_group = { 4625 .name = "ptl", 4626 .attrs = ptl_attrs, 4627 .is_visible = amdgpu_ptl_is_visible, 4628 }; 4629 4630 int is_psp_fw_valid(struct psp_bin_desc bin) 4631 { 4632 return bin.size_bytes; 4633 } 4634 4635 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4636 const struct bin_attribute *bin_attr, 4637 char *buffer, loff_t pos, size_t count) 4638 { 4639 struct device *dev = kobj_to_dev(kobj); 4640 struct drm_device *ddev = dev_get_drvdata(dev); 4641 struct amdgpu_device *adev = drm_to_adev(ddev); 4642 4643 adev->psp.vbflash_done = false; 4644 4645 /* Safeguard against memory drain */ 4646 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4647 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4648 kvfree(adev->psp.vbflash_tmp_buf); 4649 adev->psp.vbflash_tmp_buf = NULL; 4650 adev->psp.vbflash_image_size = 0; 4651 return -ENOMEM; 4652 } 4653 4654 mutex_lock(&adev->psp.mutex); 4655 4656 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4657 if (!adev->psp.vbflash_tmp_buf) { 4658 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4659 if (!adev->psp.vbflash_tmp_buf) { 4660 mutex_unlock(&adev->psp.mutex); 4661 return -ENOMEM; 4662 } 4663 } 4664 4665 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4666 adev->psp.vbflash_image_size += count; 4667 mutex_unlock(&adev->psp.mutex); 4668 4669 dev_dbg(adev->dev, "IFWI staged for update\n"); 4670 4671 return count; 4672 } 4673 4674 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4675 const struct bin_attribute *bin_attr, char *buffer, 4676 loff_t pos, size_t count) 4677 { 4678 struct device *dev = kobj_to_dev(kobj); 4679 struct drm_device *ddev = dev_get_drvdata(dev); 4680 struct amdgpu_device *adev = drm_to_adev(ddev); 4681 struct amdgpu_bo *fw_buf_bo = NULL; 4682 uint64_t fw_pri_mc_addr; 4683 void *fw_pri_cpu_addr; 4684 int ret; 4685 4686 if (adev->psp.vbflash_image_size == 0) 4687 return -EINVAL; 4688 4689 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4690 4691 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4692 AMDGPU_GPU_PAGE_SIZE, 4693 AMDGPU_GEM_DOMAIN_VRAM, 4694 &fw_buf_bo, 4695 &fw_pri_mc_addr, 4696 &fw_pri_cpu_addr); 4697 if (ret) 4698 goto rel_buf; 4699 4700 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4701 4702 mutex_lock(&adev->psp.mutex); 4703 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4704 mutex_unlock(&adev->psp.mutex); 4705 4706 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4707 4708 rel_buf: 4709 kvfree(adev->psp.vbflash_tmp_buf); 4710 adev->psp.vbflash_tmp_buf = NULL; 4711 adev->psp.vbflash_image_size = 0; 4712 4713 if (ret) { 4714 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4715 return ret; 4716 } 4717 4718 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4719 return 0; 4720 } 4721 4722 /** 4723 * DOC: psp_vbflash 4724 * Writing to this file will stage an IFWI for update. Reading from this file 4725 * will trigger the update process. 4726 */ 4727 static const struct bin_attribute psp_vbflash_bin_attr = { 4728 .attr = {.name = "psp_vbflash", .mode = 0660}, 4729 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 4730 .write = amdgpu_psp_vbflash_write, 4731 .read = amdgpu_psp_vbflash_read, 4732 }; 4733 4734 /** 4735 * DOC: psp_vbflash_status 4736 * The status of the flash process. 4737 * 0: IFWI flash not complete. 4738 * 1: IFWI flash complete. 4739 */ 4740 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4741 struct device_attribute *attr, 4742 char *buf) 4743 { 4744 struct drm_device *ddev = dev_get_drvdata(dev); 4745 struct amdgpu_device *adev = drm_to_adev(ddev); 4746 uint32_t vbflash_status; 4747 4748 vbflash_status = psp_vbflash_status(&adev->psp); 4749 if (!adev->psp.vbflash_done) 4750 vbflash_status = 0; 4751 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4752 vbflash_status = 1; 4753 4754 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4755 } 4756 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4757 4758 static const struct bin_attribute *const bin_flash_attrs[] = { 4759 &psp_vbflash_bin_attr, 4760 NULL 4761 }; 4762 4763 static struct attribute *flash_attrs[] = { 4764 &dev_attr_psp_vbflash_status.attr, 4765 &dev_attr_usbc_pd_fw.attr, 4766 NULL 4767 }; 4768 4769 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4770 { 4771 struct device *dev = kobj_to_dev(kobj); 4772 struct drm_device *ddev = dev_get_drvdata(dev); 4773 struct amdgpu_device *adev = drm_to_adev(ddev); 4774 4775 if (attr == &dev_attr_usbc_pd_fw.attr) 4776 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4777 4778 return adev->psp.sup_ifwi_up ? 0440 : 0; 4779 } 4780 4781 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4782 const struct bin_attribute *attr, 4783 int idx) 4784 { 4785 struct device *dev = kobj_to_dev(kobj); 4786 struct drm_device *ddev = dev_get_drvdata(dev); 4787 struct amdgpu_device *adev = drm_to_adev(ddev); 4788 4789 return adev->psp.sup_ifwi_up ? 0660 : 0; 4790 } 4791 4792 const struct attribute_group amdgpu_flash_attr_group = { 4793 .attrs = flash_attrs, 4794 .bin_attrs = bin_flash_attrs, 4795 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4796 .is_visible = amdgpu_flash_attr_is_visible, 4797 }; 4798 4799 #if defined(CONFIG_DEBUG_FS) 4800 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4801 { 4802 struct amdgpu_device *adev = filp->f_inode->i_private; 4803 struct spirom_bo *bo_triplet; 4804 int ret; 4805 4806 /* serialize the open() file calling */ 4807 if (!mutex_trylock(&adev->psp.mutex)) 4808 return -EBUSY; 4809 4810 /* 4811 * make sure only one userpace process is alive for dumping so that 4812 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4813 * let's say the case where one process try opening the file while 4814 * another one has proceeded to read or release. In this way, eliminate 4815 * the use of mutex for read() or release() callback as well. 4816 */ 4817 if (adev->psp.spirom_dump_trip) { 4818 mutex_unlock(&adev->psp.mutex); 4819 return -EBUSY; 4820 } 4821 4822 bo_triplet = kzalloc_obj(struct spirom_bo); 4823 if (!bo_triplet) { 4824 mutex_unlock(&adev->psp.mutex); 4825 return -ENOMEM; 4826 } 4827 4828 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4829 AMDGPU_GPU_PAGE_SIZE, 4830 AMDGPU_GEM_DOMAIN_GTT, 4831 &bo_triplet->bo, 4832 &bo_triplet->mc_addr, 4833 &bo_triplet->cpu_addr); 4834 if (ret) 4835 goto rel_trip; 4836 4837 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4838 if (ret) 4839 goto rel_bo; 4840 4841 adev->psp.spirom_dump_trip = bo_triplet; 4842 mutex_unlock(&adev->psp.mutex); 4843 return 0; 4844 rel_bo: 4845 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4846 &bo_triplet->cpu_addr); 4847 rel_trip: 4848 kfree(bo_triplet); 4849 mutex_unlock(&adev->psp.mutex); 4850 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4851 return ret; 4852 } 4853 4854 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4855 loff_t *pos) 4856 { 4857 struct amdgpu_device *adev = filp->f_inode->i_private; 4858 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4859 4860 if (!bo_triplet) 4861 return -EINVAL; 4862 4863 return simple_read_from_buffer(buf, 4864 size, 4865 pos, bo_triplet->cpu_addr, 4866 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4867 } 4868 4869 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4870 { 4871 struct amdgpu_device *adev = filp->f_inode->i_private; 4872 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4873 4874 if (bo_triplet) { 4875 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4876 &bo_triplet->cpu_addr); 4877 kfree(bo_triplet); 4878 } 4879 4880 adev->psp.spirom_dump_trip = NULL; 4881 return 0; 4882 } 4883 4884 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4885 .owner = THIS_MODULE, 4886 .open = psp_read_spirom_debugfs_open, 4887 .read = psp_read_spirom_debugfs_read, 4888 .release = psp_read_spirom_debugfs_release, 4889 .llseek = default_llseek, 4890 }; 4891 #endif 4892 4893 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4894 { 4895 #if defined(CONFIG_DEBUG_FS) 4896 struct drm_minor *minor = adev_to_drm(adev)->primary; 4897 4898 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4899 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4900 #endif 4901 } 4902 4903 const struct amd_ip_funcs psp_ip_funcs = { 4904 .name = "psp", 4905 .early_init = psp_early_init, 4906 .sw_init = psp_sw_init, 4907 .sw_fini = psp_sw_fini, 4908 .hw_init = psp_hw_init, 4909 .hw_fini = psp_hw_fini, 4910 .suspend = psp_suspend, 4911 .resume = psp_resume, 4912 .set_clockgating_state = psp_set_clockgating_state, 4913 .set_powergating_state = psp_set_powergating_state, 4914 }; 4915 4916 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4917 .type = AMD_IP_BLOCK_TYPE_PSP, 4918 .major = 3, 4919 .minor = 1, 4920 .rev = 0, 4921 .funcs = &psp_ip_funcs, 4922 }; 4923 4924 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4925 .type = AMD_IP_BLOCK_TYPE_PSP, 4926 .major = 10, 4927 .minor = 0, 4928 .rev = 0, 4929 .funcs = &psp_ip_funcs, 4930 }; 4931 4932 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4933 .type = AMD_IP_BLOCK_TYPE_PSP, 4934 .major = 11, 4935 .minor = 0, 4936 .rev = 0, 4937 .funcs = &psp_ip_funcs, 4938 }; 4939 4940 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4941 .type = AMD_IP_BLOCK_TYPE_PSP, 4942 .major = 11, 4943 .minor = 0, 4944 .rev = 8, 4945 .funcs = &psp_ip_funcs, 4946 }; 4947 4948 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4949 .type = AMD_IP_BLOCK_TYPE_PSP, 4950 .major = 12, 4951 .minor = 0, 4952 .rev = 0, 4953 .funcs = &psp_ip_funcs, 4954 }; 4955 4956 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4957 .type = AMD_IP_BLOCK_TYPE_PSP, 4958 .major = 13, 4959 .minor = 0, 4960 .rev = 0, 4961 .funcs = &psp_ip_funcs, 4962 }; 4963 4964 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4965 .type = AMD_IP_BLOCK_TYPE_PSP, 4966 .major = 13, 4967 .minor = 0, 4968 .rev = 4, 4969 .funcs = &psp_ip_funcs, 4970 }; 4971 4972 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4973 .type = AMD_IP_BLOCK_TYPE_PSP, 4974 .major = 14, 4975 .minor = 0, 4976 .rev = 0, 4977 .funcs = &psp_ip_funcs, 4978 }; 4979 4980 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 4981 .type = AMD_IP_BLOCK_TYPE_PSP, 4982 .major = 15, 4983 .minor = 0, 4984 .rev = 0, 4985 .funcs = &psp_ip_funcs, 4986 }; 4987 4988 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 4989 .type = AMD_IP_BLOCK_TYPE_PSP, 4990 .major = 15, 4991 .minor = 0, 4992 .rev = 8, 4993 .funcs = &psp_ip_funcs, 4994 }; 4995